Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor device comprises: sequentially forming a plurality of capacitors in the same layer, a plurality of first source-drain electrodes in the same layer, a plurality of first signal lines in the same layer and a plurality of second signal lines in the same layer above a substrate; the first source-drain electrode is correspondingly connected above the capacitor; each of the plurality of first signal lines extends along a first direction; each of the plurality of second signal lines extends along a second direction; a plurality of second through holes are formed; based on the second through holes, the first signal lines are laterally etched to form first grooves; a first gate insulating structure is formed in the first grooves; a semiconductor structure, a second gate insulating structure and a second gate electrode which sequentially cover and fill the second through holes are formed in the plurality of second through holes to form a plurality of transistors; and a third signal line is formed to connect the second gate electrodes of the plurality of transistors. The embodiments of the application can effectively improve the performance of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of semiconductor devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of semiconductor devices.

[0003] To minimize product costs, the goal is to fabricate as many semiconductor devices as possible on a substrate with limited area. Since the advent of Moore's Law, the industry has proposed various structural designs and process optimizations for semiconductor devices to meet current product demands. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device, its manufacturing method, and an electronic device, which can effectively improve the performance of the semiconductor device.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising:

[0006] Multiple capacitors, multiple first source / drain electrodes, multiple first signal lines, and multiple second signal lines are sequentially formed on a substrate. The first source / drain electrodes are connected to the ends of the capacitors that are away from the substrate. The first source / drain electrodes, the first signal lines, and the second signal lines are insulated from each other. The multiple first signal lines each extend along a first direction and are spaced apart along a second direction. The multiple second signal lines each extend along a second direction and are spaced apart along the first direction. The first direction and the second direction intersect and are both parallel to the substrate.

[0007] Multiple second vias are formed, with each second via penetrating the second signal line and the first signal line in sequence, exposing the corresponding first source and drain electrodes at the bottom; based on the second vias, the first signal line is etched laterally to form a first groove;

[0008] A first gate insulation structure is formed within the first groove;

[0009] A semiconductor structure, a second gate insulating structure, and a second gate are formed sequentially covering and filling the second vias to form a plurality of transistors. A first gate insulating structure is surrounded and connected to the outer periphery of the semiconductor structure. A third signal line is formed to connect the second gates of the plurality of transistors.

[0010] In some embodiments, a plurality of capacitors and a plurality of first source / drain electrodes are sequentially formed above the substrate, including:

[0011] A first dielectric layer is formed on a substrate, the first dielectric layer having a plurality of first vias arranged in an array;

[0012] A first electrode layer, a dielectric material layer, and a second electrode layer are sequentially deposited on the first dielectric layer and inside the first via to form an initial capacitor structure.

[0013] A first source / drain layer is deposited on the second electrode layer; the first source / drain layer and the initial capacitor structure are patterned to form multiple arrays of first source / drain electrodes and multiple arrays of capacitors; the capacitor includes a first electrode, a dielectric structure and a second electrode formed by the first electrode layer, the dielectric material layer and the second electrode layer respectively.

[0014] In some embodiments, a semiconductor structure, a second gate insulating structure, and a second gate are formed sequentially covering and filling the second vias to form a plurality of transistors, and a first gate insulating structure is surrounded and connected to the outer periphery of the semiconductor structure; a third signal line is formed to connect the second gates of the plurality of transistors, including:

[0015] A semiconductor material layer, a second gate insulating structure, and a second gate electrode are formed in the second via, sequentially covering the inner wall of the second via and the first source and drain electrodes.

[0016] A plurality of third signal lines are formed on the side of the semiconductor material layer, the second gate insulating structure, and the second gate facing away from the substrate. Each of the plurality of third signal lines extends along a first direction and is spaced apart along a second direction. A third signal line connects to the second gate in a plurality of second vias arranged along the first direction.

[0017] The portion of the semiconductor material layer near the third signal line is removed, so that the semiconductor material layer and the third signal line are spaced apart to form a semiconductor structure.

[0018] In some embodiments, a plurality of co-layered first signal lines and a plurality of co-layered second signal lines are sequentially formed above the substrate, including:

[0019] A second dielectric layer is formed covering the first source and drain electrodes;

[0020] A first metal layer is formed on the second dielectric layer, and the first metal layer is patterned to form a plurality of first word lines; the first signal line includes the first word lines.

[0021] A third dielectric layer is formed, covering the sidewalls and top surface of the first character line;

[0022] A second metal layer is formed on the third dielectric layer, and the second metal layer is patterned to form bit lines. The second signal line includes the bit lines.

[0023] In some embodiments, multiple second vias are formed, which sequentially penetrate the second signal line and the first signal line, exposing the corresponding first source and drain electrodes at their bottoms, including:

[0024] A fourth dielectric layer is formed to cover the sidewalls and top surface of the bit line;

[0025] A first mask structure is formed on the fourth dielectric layer, and the first mask structure has a plurality of third through holes corresponding to the first through holes;

[0026] Based on the first mask structure, etching is performed to form multiple second vias. The second vias sequentially penetrate the fourth dielectric layer, bit line, third dielectric layer, first word line, and second dielectric layer, exposing the first source and drain electrodes below.

[0027] In some embodiments, a first gate insulation structure is formed within the first groove, including:

[0028] A first gate insulating layer is formed in the first groove and the second through hole, and the first gate insulating layer covers the sidewall of the first groove;

[0029] The first gate insulating layer inside the second through hole is removed, and the first gate insulating layer inside the first groove forms the first gate insulating structure.

[0030] In some embodiments, a plurality of third signal lines are formed on the side of the semiconductor material layer, the second gate insulating structure, and the second gate away from the substrate, including:

[0031] A third metal layer is formed on a semiconductor material layer, a second gate insulating structure, a second gate, and a first mask structure; the third metal layer is patterned to form a second word line; the third signal line includes the second word line.

[0032] In addition, removing the portion of the semiconductor material layer near the third signal line includes:

[0033] Remove the first mask structure to expose the portion of the semiconductor material layer near the second word line;

[0034] The exposed semiconductor material layer is removed, and the remaining semiconductor material layer forms a semiconductor structure.

[0035] Secondly, embodiments of this application provide a semiconductor device, including:

[0036] Multiple capacitors are disposed on one side of the substrate in the same layer;

[0037] Multiple first source and drain electrodes are connected one-to-one to the ends of multiple capacitors that are away from the substrate.

[0038] Multiple transistors are connected one-to-one to multiple first source and drain electrodes. Each transistor includes: a first gate, a first gate insulating structure, a semiconductor structure, a second gate insulating structure, and a second gate. The second gate is columnar, and the second gate insulating structure and the semiconductor structure sequentially cover the sidewall and bottom wall of the second gate. The first gate insulating structure and the first gate sequentially surround a portion of the outer periphery of the semiconductor structure. The bottom of the semiconductor structure is connected to the first source and drain electrodes.

[0039] Multiple first signal lines are spaced apart along a second direction and each extends along a first direction. Each first signal line includes a first gate of multiple transistors arranged along the first direction. The first direction intersects the second direction and is parallel to the substrate.

[0040] Multiple second signal lines are located on the side of the first signal line away from the substrate, are spaced apart along a first direction, and each extends along a second direction. The second signal lines surround a portion of the outer periphery of the semiconductor structure of each transistor arranged along the second direction.

[0041] The third signal line is connected to the top of the second gate of multiple transistors.

[0042] In some embodiments, the first signal line includes a first word line surrounding the outer periphery of the first gate insulating structure of each transistor, with the portion near the first gate insulating structure forming a first gate.

[0043] The second signal line includes bit lines that surround a portion of the outer periphery of the semiconductor structure of each transistor;

[0044] The third signal line includes a second word line located on the side of the bit line away from the substrate, spaced apart along a second direction, each extending along a first direction, and connected to the top of the second gate of a plurality of transistors arranged along the first direction.

[0045] In some embodiments, the semiconductor device further includes: a landing pad;

[0046] Multiple capacitors are arranged in a honeycomb pattern; multiple transistors are arranged orthogonally.

[0047] The landing pad connects the capacitor and the transistor.

[0048] Thirdly, embodiments of this application provide an electronic device, including: a semiconductor device manufactured by any of the semiconductor device manufacturing methods provided in the first aspect above, or any of the semiconductor devices provided in the second aspect above.

[0049] The beneficial technical effects of the technical solutions provided in this application include:

[0050] In this embodiment, a capacitor, a first source / drain, a first signal line, and a second signal line are sequentially formed above a substrate. Then, a second via is formed penetrating the second signal line and the first signal line, so that the first source / drain is exposed from the bottom of the second via, and the first signal line is exposed from the sidewall of the second via. This allows the bottom of the semiconductor structure subsequently formed within the second via to be connected to the first source / drain, and then to the capacitor. The sidewall of the semiconductor structure is connected to the first signal line. A portion of the first signal line serves as the first gate of the transistor, surrounding the outer periphery of the semiconductor structure to form an outer ring gate. A second gate is formed inside the semiconductor structure, so that the semiconductor structure is ring-shaped around the second gate, forming a ring channel, thus obtaining a dual-gate transistor.

[0051] This application combines the manufacturing processes of vertical-ring gate transistors and vertical-ring channel transistors to obtain dual-gate transistors. The process is simple and easy to implement. Moreover, it can improve the gate control capability of the transistor, achieve more precise current regulation, effectively suppress short-channel effects, and ensure good device performance.

[0052] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0053] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0054] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application;

[0055] Figures 2-28 A schematic diagram of the film structure obtained in each step of a semiconductor device manufacturing method provided in this application embodiment;

[0056] Figure 29 A circuit diagram of a semiconductor device provided in an embodiment of this application.

[0057] Figure label:

[0058] 100 - Substrate; 110 - First dielectric layer; 111 - First via; 120 - Second mask structure; 121 - Fourth via; 130 - First insulating layer;

[0059] 200 - Capacitor; 210 - Initial capacitor structure; 211 - First electrode layer; 212 - Dielectric material layer; 213 - Second electrode layer; 220 - First electrode; 230 - Dielectric structure; 240 - Second electrode;

[0060] 300 - First source / drain electrode; 310 - First source / drain layer; 320 - Second dielectric layer;

[0061] 400 - First signal line; 410 - First word line; 420 - Third dielectric layer; 430 - First groove;

[0062] 500 - Second signal line; 510 - Bit line; 520 - Fourth dielectric layer; 530 - First mask structure; 531 - Third via;

[0063] 600 - Second through hole;

[0064] 700 - Transistor; 710 - First gate; 720 - First gate insulating structure; 730 - Semiconductor structure; 731 - Semiconductor material layer; 740 - Second gate insulating structure; 750 - Second gate;

[0065] 800 - Third signal line; 810 - Third metal layer; 820 - Second word line; 830 - Fifth dielectric layer. Detailed Implementation

[0066] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0067] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0068] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0069] The research and development concept of this application includes: the vertical all-around gate transistor is an advanced transistor structure and is considered an important direction for the future development of semiconductor technology.

[0070] However, vertical all-around gate transistors may have a complex manufacturing process. As transistor size shrinks, the control precision required for the doping depth of semiconductor materials and the width of the channel is extremely high. Any slight deviation may lead to a significant decrease in transistor device performance, making it difficult to ensure good device performance while controlling the complexity of the manufacturing process.

[0071] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.

[0072] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0073] This application provides a method for manufacturing a semiconductor device, and the flowchart of the method is shown below. Figure 1 As shown, the method includes steps S101-S104:

[0074] S101: Multiple capacitors 200, multiple first source / drain electrodes 300, multiple first signal lines 400, and multiple second signal lines 500 are sequentially formed on the substrate 100. The first source / drain electrodes 300 are connected to the end of the capacitors 200 away from the substrate 100. The first source / drain electrodes 300, the first signal lines 400, and the second signal lines 500 are insulated from each other. The multiple first signal lines 400 extend along a first direction and are spaced apart along a second direction. The multiple second signal lines 500 extend along a second direction and are spaced apart along the first direction. The first direction and the second direction intersect and are both parallel to the substrate 100.

[0075] S102: Form multiple second through holes 600, the second through holes 600 sequentially pass through the second signal line 500 and the first signal line 400, and expose the corresponding first source and drain electrodes 300 at the bottom; based on the second through holes 600, etch the first signal line 400 laterally to form a first groove 430.

[0076] S103: A first gate insulation structure 720 is formed in the first groove 430.

[0077] S104: A semiconductor structure 730, a second gate insulating structure 740, and a second gate 750 are formed in a plurality of second vias 600, which sequentially cover and fill the second vias 600, forming a plurality of transistors 700, and a first gate insulating structure 720 is connected around the outer periphery of the semiconductor structure 730; a third signal line 800 is formed to connect the second gate 750 of the plurality of transistors 700.

[0078] In this embodiment, a capacitor 200, a first source / drain 300, a first signal line 400, and a second signal line 500 are sequentially formed above the substrate 100. Then, a second via 600 is formed through the second signal line 500 and the first signal line 400, so that the first source / drain 300 is exposed from the bottom of the second via 600 and the first signal line 400 is exposed from the sidewall of the second via 600. This allows the bottom of the semiconductor structure 730 subsequently formed in the second via 600 to be connected to the first source / drain 300, and then to the capacitor 200. The sidewall of the semiconductor structure 730 is connected to the first signal line 400. A portion of the first signal line 400 serves as the first gate 710 of the transistor 700, surrounding the outer periphery of the semiconductor structure 730 to form an outer ring gate. A second gate 750 is formed inside the semiconductor structure 730, so that the semiconductor structure 730 is arranged in a ring around the second gate 750 to form a ring channel, thus obtaining a dual-gate transistor 700.

[0079] This application combines the manufacturing processes of vertical-ring gate transistors and vertical-ring channel transistors to obtain a dual-gate transistor 700. The process is simple and easy to implement. Moreover, it can improve the gate control capability of the transistor 700, achieve more precise current regulation, effectively suppress short-channel effects, and ensure good device performance of the transistor 700.

[0080] The specific steps of this application will be described in detail below with reference to the accompanying drawings.

[0081] This application provides a method for manufacturing a semiconductor device, which includes the following steps:

[0082] In some embodiments, the step S101 described above, in which a plurality of capacitors 200 and a plurality of first source / drain electrodes 300 are sequentially formed above the substrate 100, specifically includes the following steps:

[0083] like Figure 2 As shown, a first dielectric layer 110 is formed on the substrate 100. Figure 3 As shown, a second mask structure 120 is formed on the substrate 100, and the second mask structure 120 is etched to give the second mask structure 120 a plurality of fourth through holes 121. Figures 4-5 As shown, the first dielectric layer 110 is etched based on the second mask structure 120, so that the first dielectric layer 110 has a plurality of arrayed first vias 111.

[0084] like Figures 6-7 As shown, a first electrode layer 211, a dielectric material layer 212, and a second electrode layer 213 are sequentially deposited on the first dielectric layer 110 and in the first via 111 to form an initial capacitor structure 210.

[0085] like Figures 6-7 As shown, a first source / drain layer 310 is deposited on the second electrode layer 213.

[0086] like Figures 8-9 As shown, the patterned first source / drain layer 310 and the initial capacitor structure 210 each form a plurality of arrayed first source / drain electrodes 300 and a plurality of arrayed capacitors 200; the capacitor 200 includes a first electrode 220, a dielectric structure 230 and a second electrode 240 formed by the first electrode layer 211, the dielectric material layer 212 and the second electrode layer 213 respectively.

[0087] In this embodiment, a first electrode layer 211, a dielectric material layer 212, a second electrode layer 213, and a first source / drain layer 310 are sequentially formed. A capacitor 200 and a first source / drain electrode 300 electrically connected to the capacitor 200 can be formed simultaneously in a single etching operation. A transistor 700 is then formed above the first source / drain electrode 300. In this embodiment, the processes for the transistor 700 and the capacitor 200 are more easily integrated, reducing the manufacturing difficulty of semiconductor devices and improving manufacturing efficiency.

[0088] In some embodiments, step S101 above, in which a plurality of first signal lines and a plurality of second signal lines of the same layer are sequentially formed on the substrate, specifically includes the following steps:

[0089] like Figures 10-11 As shown, a first insulating layer 130 is formed on the second mask structure 120, filling the space between each of the first source and drain electrodes 300; as Figures 12-13 As shown, a second dielectric layer 320 is formed covering the top surface of the first source / drain electrode 300, a first metal layer is formed on the second dielectric layer 320, and the first metal layer is patterned to form a plurality of first word lines 410; the first signal line 400 includes the first word lines 410.

[0090] like Figures 14-15 As shown, a third dielectric layer 420 is formed covering the sidewalls and top surface of the first word line 410; a second metal layer is formed on the third dielectric layer 420, and the second metal layer is patterned to form a bit line 510, and the second signal line 500 includes the bit line 510.

[0091] In this embodiment, a first signal line 400 and a second signal line 500 are sequentially formed on the first source / drain 300. The orthographic projections of the first signal line 400 and the second signal line 500 intersect on the substrate 100, and the intersection point is exactly located on the orthographic projection of the first source / drain 300. This lays the foundation for the subsequent formation of the second via 600 and the semiconductor structure 730 within the second via 600, enabling the semiconductor structure 730 to simultaneously contact and connect with the first source / drain 300, the first signal line 400, and the second signal line 500.

[0092] In some embodiments, the formation of multiple second vias 600 in step S102 above, wherein the second vias 600 sequentially penetrate the second signal line 500 and the first signal line 400, and expose the corresponding first source / drain electrodes 300 at their bottom, includes:

[0093] like Figures 16-17 As shown, a fourth dielectric layer 520 is formed to cover the sidewalls and top surface of the bit line 510, and a first mask layer is formed on the fourth dielectric layer 520; the first mask layer is etched to obtain a first mask structure 530 having a plurality of third vias 531 corresponding to the first via 111.

[0094] like Figures 18-19 As shown, based on the first mask structure 530, etching is performed to form multiple second vias 600. The second vias 600 sequentially penetrate the fourth dielectric layer 520, bit line 510, third dielectric layer 420, first word line 410, and second dielectric layer 320, exposing the first source / drain electrode 300 below.

[0095] In this embodiment, the second via 600 obtained by etching a multilayer film structure in one step through the first mask structure 530 can penetrate the fourth dielectric layer 520, bit line 510, third dielectric layer 420, first word line 410 and second dielectric layer 320, exposing the first source and drain 300 below, so that the semiconductor structure 730 subsequently formed in the second via 600 can contact the first source and drain 300.

[0096] Next, as Figure 20 As shown, based on the second through-hole 600, the first signal line 400 is etched laterally to form a first groove 430. The sidewall of the first groove 430 is the first signal line 400.

[0097] In some embodiments, forming a first gate insulation structure 720 within the first groove 430 in step S103 above includes the following steps:

[0098] A first gate insulating layer is formed within the first groove 430 and the second through hole 600, covering the sidewall of the first groove 430. The first gate insulating layer within the second through hole 600 is then removed, leaving the first gate insulating layer within the first groove 430 to form a first gate insulating structure 720. A schematic diagram of the resulting film structure is shown below. Figure 21 As shown.

[0099] In some embodiments, step S104 above, which involves forming a semiconductor structure 730, a second gate insulating structure 740, and a second gate 750 sequentially covering and filling the second vias 600 to form a plurality of transistors 700, with the first gate insulating structure 720 surrounding and connected to the outer periphery of the semiconductor structure 730; and forming a third signal line 800 connecting the second gate 750 of the plurality of transistors 700, includes the following steps:

[0100] like Figure 22 and Figure 23 As shown, a semiconductor material layer 731, a second gate insulating structure 740, and a second gate 750 are formed in the second via 600, which sequentially cover the inner wall of the second via 600 and the first source / drain electrode 300.

[0101] like Figure 24 As shown, a plurality of third signal lines 800 are formed on the semiconductor material layer 731, the second gate insulating structure 740 and the second gate 750 (i.e. the side away from the substrate). Each of the plurality of third signal lines 800 extends along a first direction and is spaced apart along a second direction. A third signal line 800 connects to the second gate 750 in a plurality of second vias 600 arranged along the first direction.

[0102] Optionally, the steps for forming the third signal line 800 described above specifically include: such as Figure 23 As shown, a third metal layer 810 is formed on the semiconductor material layer 731, the second gate insulating structure 740, the second gate 750, and the first mask structure 530, as follows: Figure 24 As shown, a patterned third metal layer 810 forms a second word line 820; a third signal line 800 includes the second word line 820.

[0103] like Figures 25-27 As shown, the portion of the semiconductor material layer 731 near the third signal line 800 is removed, so that the semiconductor material layer 731 and the third signal line 800 are spaced apart to form a semiconductor structure 730.

[0104] Optionally, the step of removing the semiconductor material layer 731 described above specifically includes: as follows Figures 25-26 As shown, the first mask structure 530 is removed, exposing the portion of the semiconductor material layer 731 near the second word line 820.

[0105] like Figure 27 As shown, the exposed semiconductor material layer 731 is removed, and the remaining semiconductor material layer 731 forms a semiconductor structure 730.

[0106] Next, as Figure 28 As shown, a dielectric material is deposited in the window area and planarized to obtain the fifth dielectric layer 830, which exposes the top of the second letter line 820 for subsequent processing.

[0107] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned by a patterning process to manufacture each corresponding film layer.

[0108] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.

[0109] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film of a certain material manufactured on a substrate 100 using a deposition or coating process. If the thin film does not require a patterning process or photolithography process during the entire manufacturing process, the thin film can also be called a layer. If the thin film requires a patterning process or photolithography process during the entire manufacturing process, it can be called a thin film before the patterning process and a layer after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern".

[0110] Based on the same inventive concept, embodiments of this application provide a semiconductor device, such as... Figure 28 As shown, the semiconductor device includes: multiple capacitors 200, multiple first source-drain electrodes 300, multiple transistors 700, multiple first signal lines 400, multiple second signal lines 500, and a third signal line 800.

[0111] Multiple capacitors 200 are disposed on one side of substrate 100 in the same layer.

[0112] Multiple first source drains 300 are connected one-to-one above multiple capacitors 200 (i.e., the end away from the substrate).

[0113] Multiple transistors 700 are connected one-to-one to multiple first source-drain electrodes 300. Each transistor 700 includes: a first gate 710, a first gate insulating structure 720, a semiconductor structure 730, a second gate insulating structure 740, and a second gate 750. The second gate 750 is columnar, and the second gate insulating structure 740 and the semiconductor structure 730 sequentially cover the sidewalls and bottom wall of the second gate 750. The first gate insulating structure 720 and the first gate 710 sequentially surround a portion of the outer periphery of the semiconductor structure 730. The bottom of the semiconductor structure 730 is connected to the first source-drain electrodes 300.

[0114] Multiple first signal lines 400 are arranged at intervals along a second direction and each extends along a first direction. Each first signal line 400 includes a first gate 710 of multiple transistors 700 arranged along the first direction. The first direction intersects the second direction and is parallel to the substrate 100.

[0115] Multiple second signal lines 500 are located on the side of the first signal line 400 away from the substrate 100, are spaced apart along the first direction, and each extends along the second direction. The second signal lines surround a portion of the outer periphery of the semiconductor structure 730 of each transistor 700 arranged along the second direction.

[0116] The third signal line 800 is connected to the top of the second gate 750 of the plurality of transistors 700.

[0117] The transistor 700 in this embodiment has a first gate 710 (i.e., a ring gate) surrounding a semiconductor structure 730 and a semiconductor structure 730 (i.e., a ring channel) surrounding a second gate 750. By combining the structural features of a vertical ring gate transistor and a vertical ring channel transistor, a dual-gate transistor 700 is obtained, which has a simple process flow and is easy to implement. Furthermore, it can improve the gate control capability of the transistor 700, achieve more precise current regulation, effectively suppress short-channel effects, and ensure good device performance of the transistor 700.

[0118] In some embodiments, the relative positional relationship between capacitor 200 and transistor 700 is not limited, and capacitor 200 may also be located above transistor 700. The manufacturing method is similar and will not be described in detail here.

[0119] Optionally, the semiconductor structure 730 is made of a metal oxide semiconductor material. This metal oxide semiconductor material includes IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), IWO (Indium Wolfram Oxide), InGaO (Indium Gallium Oxide), ZnO (Zinc O), InO (Indium Oxide), InO (Indium Oxide), InWO (Indium Tungsten Oxide), SnO (Tin Oxide), TiO (Titanium Oxide), InSnO (Indium Tin Oxide), ZnON (Nitrogen-Doped Zinc Oxide), and Mg. ZnO (zinc magnesium oxide), InZnO (zinc indium oxide), InGaZnO (zinc indium gallium oxide), ZrInZnO (zinc zirconium oxide), HfInZnO (zinc hafnium oxide), SnInZnO (zinc tin oxide), AlZnO (zinc aluminum oxide), AlSnInZnO (zinc aluminum tin oxide), SiInZnO (zinc silicon oxide), ZnSnO (zinc tin oxide), AlZnSnO (zinc aluminum oxide), GaZnSnO (zinc gallium oxide), ZrZnSnO (zinc zirconium oxide), and InGaSiO (silicon indium gallium oxide), etc.

[0120] In some embodiments, the first signal line 400 includes a first word line 410 surrounding the outer periphery of the first gate insulating structure 720 of each transistor 700, with the portion near the first gate insulating structure 720 forming the first gate 710.

[0121] The second signal line 500 includes a bit line 510 that surrounds a portion of the outer periphery of the semiconductor structure 730 of each transistor 700.

[0122] The third signal line 800 includes a second word line 820 located on the side of the bit line 510 away from the substrate 100, arranged at intervals along the second direction, each extending along the first direction, and connected to the top of the second gate 750 of a plurality of transistors 700 arranged along the first direction.

[0123] In this embodiment, the first word line 410, the bit line 510, and the second word line 820 are arranged in a staggered pattern in pairs in a direction perpendicular to the substrate 100, and can be fabricated sequentially. The process is simple and easy to implement.

[0124] The following provides a detailed description of the access method when the semiconductor device structure provided in the embodiments of this application is used as a dynamic random access memory.

[0125] like Figure 28 and Figure 29 As shown, Figure 29 WL (Chinese WL) Figure 28 The second word line 820 is a word line connected to the second gate 750, which is the main gate. Figure 29 BG in Figure 28 The first word line 410 is the word line connected to the first gate 710, which is the back gate. Figure 29 BL refers to Figure 28 Bit line 510 in the memory. For the 1T1C (one transistor 700 and one capacitor 200) memory cell in the memory of this application embodiment, the presence or absence of stored charge in capacitor 200 is used to distinguish between two states, thereby representing the stored information "1" or "0".

[0126] like Figure 29 In the circuit shown, when the memory cell is not being read, the second word line WL and the first word line BG are at low potentials, transistor 700 is in the off state, and capacitor 200 maintains its charge state. When reading information, the target memory cell (with...) Figure 29 Taking the first memory cell as an example, when the second word line WL0 and the first word line BG0 are high, transistor 700 is turned on. If capacitor 200 stores "1", the charge on capacitor 200 discharges to the read amplifier through the connected bit line BL0, generating an output signal of "1". If capacitor 200 stores "0", there is no stored charge in the storage capacitor 200, no read current is generated, and therefore no output signal is generated, i.e., "0" is read. After the data is read, the read amplifier restores the stored data by adjusting the potential on capacitor 200 through bit line 510.

[0127] The write operation to a memory is the reverse of the read operation. For example... Figure 29 As shown, the target storage unit (in) Figure 29 Taking the first memory cell as an example, when transistor 700 is turned off, bit line BL0 is applied with a high potential, the second word line WL0 and the first word line BG0 are applied with a high potential, transistor 700 is turned on, capacitor 200 is fully charged, the second word line WL0 and the first word line BG0 are no longer charged, transistor 700 is turned off, and data '1' is written. When transistor 700 is turned off, bit line BL0 is grounded, the second word line WL0 and the first word line BG0 are applied with a high potential, transistor 700 is turned on, the charge in capacitor 200 is completely drained, the second word line WL0 and the first word line BG0 are no longer charged, transistor 700 is turned off, and data '0' is written.

[0128] In some embodiments, the semiconductor device further includes a landing pad.

[0129] Multiple capacitors 200 are arranged in a honeycomb pattern; multiple transistors 700 are arranged in an orthogonal pattern.

[0130] The landing pad is connected between capacitor 200 and transistor 700.

[0131] In this embodiment, the capacitors 200 and transistors 700 are arranged differently in the direction parallel to the substrate 100. The capacitors 200 can be arranged in a honeycomb hexagonal pattern, which can increase the arrangement density of the capacitors 200. The transistors 700 are arranged orthogonally, which can reduce the manufacturing difficulty. A landing pad can be provided between the first source / drain 300 and the transistors 700 to achieve a one-to-one electrical connection between the capacitors 200 and the transistors 700.

[0132] Based on the same inventive concept, this application provides an electronic device, including: a semiconductor device manufactured according to the manufacturing method of any of the semiconductor devices provided in the foregoing embodiments, or any of the semiconductor devices provided in the foregoing embodiments.

[0133] In this embodiment, since the electronic device uses any of the semiconductor devices provided in the foregoing embodiments, the principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0134] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or power bank.

[0135] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the semiconductor devices provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.

[0136] Those skilled in the art will understand that the electronic devices provided in the embodiments of this application can be specifically designed and manufactured for a desired purpose, or may include known devices in general-purpose computers. These devices have any of the semiconductor devices provided in the various embodiments described above.

[0137] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0138] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0139] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0140] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Multiple capacitors, multiple first source and drain electrodes, multiple first signal lines, and multiple second signal lines are sequentially formed on the substrate; The first source and drain are connected to the end of the capacitor that is away from the substrate; the first source and drain, the first signal line and the second signal line are insulated from each other; a plurality of the first signal lines each extend along a first direction and are spaced apart along a second direction. Each of the second signal lines extends along a second direction and is spaced apart along a first direction; the first direction intersects the second direction and is parallel to the substrate. Multiple second vias are formed, each via passing through the second signal line and the first signal line in sequence, with the corresponding first source and drain electrodes exposed at the bottom; based on the second vias, the first signal line is etched laterally to form a first groove; A first gate insulation structure is formed within the first groove; A semiconductor structure, a second gate insulating structure, and a second gate are formed within a plurality of second vias, sequentially covering and filling the second vias, to form a plurality of transistors, wherein the first gate insulating structure surrounds and is connected to the outer periphery of the semiconductor structure; A third signal line is formed, connecting the second gates of the plurality of transistors.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Multiple capacitors and multiple first source / drain electrodes are sequentially formed above the substrate, including: A first dielectric layer is formed on the substrate, the first dielectric layer having a plurality of first vias arranged in an array; A first electrode layer, a dielectric material layer, and a second electrode layer are sequentially deposited on the first dielectric layer and inside the first via to form an initial capacitor structure. A first source / drain layer is deposited on the second electrode layer; the first source / drain layer and the initial capacitor structure are patterned to form multiple arrays of first source / drain electrodes and multiple arrays of capacitors; the capacitor includes a first electrode, a dielectric structure and a second electrode formed by the first electrode layer, the dielectric material layer and the second electrode layer respectively.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, A semiconductor structure, a second gate insulating structure, and a second gate are formed within a plurality of second vias, sequentially covering and filling the second vias, to form a plurality of transistors, wherein the first gate insulating structure surrounds and is connected to the outer periphery of the semiconductor structure; Forming a third signal line to connect the second gates of the plurality of transistors, including: A semiconductor material layer, a second gate insulating structure, and a second gate are formed within the second via, sequentially covering the inner wall of the second via and the first source / drain electrode; A plurality of third signal lines are formed on the side of the semiconductor material layer, the second gate insulating structure, and the second gate facing away from the substrate. Each of the plurality of third signal lines extends along the first direction and is spaced apart along the second direction. One of the third signal lines connects to the second gate in a plurality of second vias arranged along the first direction. The portion of the semiconductor material layer near the third signal line is removed, so that the semiconductor material layer and the third signal line are spaced apart, thus forming the semiconductor structure.

4. The method for manufacturing a semiconductor device according to claim 2, characterized in that, Multiple first signal lines and multiple second signal lines of the same layer are sequentially formed above the substrate, including: A second dielectric layer is formed covering the first source and drain electrodes; A first metal layer is formed on the second dielectric layer, and the first metal layer is patterned to form a plurality of first word lines; the first signal line includes the first word lines. A third dielectric layer is formed covering the sidewalls and top surface of the first character line; A second metal layer is formed on the third dielectric layer, and the second metal layer is patterned to form a bit line, the second signal line including the bit line.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, Multiple second vias are formed, each second via sequentially penetrating the second signal line and the first signal line, with the corresponding first source / drain electrodes exposed at the bottom, including: A fourth dielectric layer is formed covering the sidewalls and top surface of the bit line; A first mask structure is formed on the fourth dielectric layer, and the first mask structure has a plurality of third through holes corresponding to the first through holes; Based on the first mask structure, etching is performed to form multiple second vias. The second vias sequentially penetrate the fourth dielectric layer, the bit line, the third dielectric layer, the first word line, and the second dielectric layer, exposing the first source and drain electrodes below.

6. The method for manufacturing a semiconductor device according to claim 2, characterized in that, A first gate insulation structure is formed within the first groove, including: A first gate insulating layer is formed in the first groove and the second through hole, and the first gate insulating layer covers the sidewall of the first groove; The first gate insulating layer in the second through hole is removed, and the first gate insulating layer in the first groove forms the first gate insulating structure.

7. The method for manufacturing a semiconductor device according to claim 5, characterized in that, A plurality of third signal lines are formed on the side of the semiconductor material layer, the second gate insulating structure, and the second gate away from the substrate, including: A third metal layer is formed on the semiconductor material layer, the second gate insulating structure, the second gate, and the first mask structure, and the third metal layer is patterned to form a second word line; the third signal line includes the second word line. And, removing the portion of the semiconductor material layer near one end of the third signal line, including: Remove the first mask structure to expose the portion of the semiconductor material layer near the second word line; The exposed semiconductor material layer is removed, and the remaining semiconductor material layer forms a semiconductor structure.

8. A semiconductor device, characterized in that, include: Multiple capacitors are disposed on one side of the substrate in the same layer; Multiple first source and drain electrodes are connected one-to-one to the ends of the multiple capacitors that are away from the substrate; Multiple transistors are connected one-to-one to multiple first source and drain electrodes. Each transistor includes: a first gate, a first gate insulating structure, a semiconductor structure, a second gate insulating structure, and a second gate. The second gate is columnar, and the second gate insulating structure and the semiconductor structure sequentially cover the sidewall and bottom wall of the second gate. The first gate insulating structure and the first gate sequentially surround a portion of the outer periphery of the semiconductor structure. The bottom of the semiconductor structure is connected to the first source and drain electrode. Multiple first signal lines are spaced apart along a second direction and each extends along a first direction. Each first signal line includes a first gate of multiple transistors arranged along the first direction. The first direction intersects the second direction and is parallel to the substrate. A plurality of second signal lines are located on the side of the first signal line away from the substrate, are spaced apart along the first direction, and each extends along the second direction, the second signal lines surrounding a portion of the outer periphery of the semiconductor structure of each transistor arranged along the second direction; The third signal line is connected to the top of the second gate of the plurality of transistors.

9. The semiconductor device according to claim 8, characterized in that, The first signal line includes a first word line, which surrounds the outer periphery of the first gate insulating structure of each transistor, and the portion close to the first gate insulating structure forms the first gate. The second signal line includes a bit line that surrounds a portion of the outer periphery of the semiconductor structure of each of the transistors; The third signal line includes a second word line located on the side of the bit line away from the substrate, spaced apart along the second direction, each extending along the first direction, and connected to the top of the second gate of the plurality of transistors arranged along the first direction.

10. The semiconductor device according to claim 8, characterized in that, Also includes: Landing mat; The capacitors are arranged in a honeycomb pattern; the transistors are arranged orthogonally. The landing pad is connected between the capacitor and the transistor.

11. An electronic device, characterized in that, include: Semiconductor devices manufactured by any of the manufacturing methods described in claims 1-7 above, or semiconductor devices described in any of claims 8-10 above.

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