Memory device including a trench structure

Abstract

The present disclosure relates to a memory device including a channel structure. The memory device can include a channel structure including a first end and a second end opposite the first end in a vertical direction, a data storage pattern connected to the first end of the channel structure, a bit line contacting the second end of the channel structure, a bonding insulating layer disposed above the bit line, a first substrate disposed above the bonding insulating layer and including a first surface facing the bit line and a second surface opposite the first surface in the vertical direction, and a first transistor disposed on the second surface of the first substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0042013, filed on April 1, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a storage device. Background Technology

[0004] Storage devices are receiving increasing attention as crucial components in the electronics industry due to their miniaturization, multifunctionality, and / or low manufacturing costs. With the rapid development of the electronics industry, the integration level of storage devices is also increasing.

[0005] In two-dimensional or planar semiconductor memory devices, the integration density depends primarily on the area occupied by a single memory cell, and is therefore greatly influenced by the level of fine patterning technology. However, due to the extremely expensive equipment required for fine patterning, the integration density of two-dimensional semiconductor memory devices has approached its limit. Therefore, semiconductor memory devices incorporating vertical channel transistors (where the channel extends in a vertical direction) have been proposed. Summary of the Invention

[0006] Embodiments of this disclosure are intended to provide a storage device that simplifies the process of forming wiring.

[0007] The purposes of the embodiments disclosed herein are not limited to those set forth herein, and other purposes not mentioned will be apparent to those skilled in the art from the following description.

[0008] In one embodiment, the memory device may include: a channel structure including a first end and a second end opposite to the first end in a vertical direction; a data storage pattern connected to the first end of the channel structure; a bit line contacting the second end of the channel structure; a bonding insulating layer disposed on the bit line; a first substrate disposed on the bonding insulating layer, the first substrate including a first surface facing the bit line and a second surface opposite to the first surface in a vertical direction; and a first transistor disposed on the second surface of the first substrate.

[0009] In one embodiment, the memory device may include: a first semiconductor structure including a channel structure, a bit line contacting the upper surface of the channel structure, and a first bonding insulating layer above the bit line; a second semiconductor structure including a second bonding insulating layer bonded to the first bonding insulating layer, a first substrate disposed above the second bonding insulating layer, and a first transistor disposed on the first substrate; and a plurality of contact plugs including a first contact plug, a second contact plug, and a third contact plug spaced apart from each other, which connect the first semiconductor structure and the second semiconductor structure by passing through the first substrate, the first bonding insulating layer, and the second bonding insulating layer.

[0010] In one embodiment, the storage device may include: a channel structure including a first end and a second end opposite to the first end in a vertical direction; a data storage pattern connected to the first end of the channel structure; a bit line contacting the second end of the channel structure; a bonding insulating layer above the bit line; a first substrate above the bonding insulating layer; a plurality of wirings above the first substrate; and a plurality of contact plugs, each directly connected to the plurality of wirings and penetrating the bonding insulating layer and the first substrate.

[0011] According to embodiments of this disclosure, a storage device that simplifies the wiring process can be provided.

[0012] The effects of this disclosure are not limited to the foregoing objectives, and other effects will become apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0013] This disclosure will be more fully understood from the following detailed description and accompanying drawings; however, these detailed descriptions and accompanying drawings are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0014] Figure 1 This is a diagram illustrating an example of the cross-sectional structure of a storage device according to an embodiment of the present disclosure.

[0015] Figures 2 to 11 This is a diagram illustrating an example of a method for manufacturing a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0016] Embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In the following description, although the same elements appear in different drawings, they will be referred to by the same reference numerals. Furthermore, in the following description of this disclosure, detailed descriptions of known functions and configurations incorporated herein will be omitted if such detailed descriptions would make the subject matter of this disclosure more unclear. It should be noted that, unless expressly stated otherwise, terms such as “comprising,” “having,” “including,” etc., as used in the specification and claims should not be construed as limited to the means listed thereafter. When indefinite or definite articles are used to refer to singular nouns, such as “a,” “an,” and “the,” this may include the plural form of the noun unless expressly stated otherwise.

[0017] Furthermore, in describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are used only to distinguish one component from another and do not limit the substance, order, sequence, or quantity of the components.

[0018] When referring to a second element as "connected or coupled," "in contact with," or "overlapping" the first element, it should be understood that the first element can not only be "directly connected or coupled" or "directly contact or overlap" the second element, but also that a third element can be "intermediate" between the first and second elements, or that the first and second elements can be "connected or coupled," "in contact with," or "overlapping" with each other through a fourth element. Here, at least one of the at least two elements that are "connected," "coupled," or "linked" to each other may include the other element.

[0019] When describing the temporal flow relationships of components in an operational or manufacturing method, non-continuous situations may be included when describing temporal or procedural relationships, such as using "after," "immediately following," "next," or "before," unless "immediately after" or "directly" is used.

[0020] When referring to a value of a component or its corresponding information (e.g., hierarchy), even without a separate explicit description, the value or its corresponding information can be interpreted as including the range of errors that may be caused by various factors (e.g., process variables, internal or external shocks, noise, etc.).

[0021] In the accompanying drawings, two directions parallel to the upper surface of the first substrate are defined as the first direction FD and the second direction SD, respectively, and a direction projecting perpendicularly to the upper surface of the first substrate is defined as the third direction VD. The first direction FD and the second direction SD may be substantially perpendicular to each other. The third direction VD is a direction perpendicular to the first direction FD and the second direction SD. In the following description, the terms "perpendicular" or "perpendicular direction" have substantially the same meaning as the third direction VD. In the accompanying drawings, the direction indicated by the arrow and its opposite direction represent the same direction.

[0022] Figure 1 This is a diagram illustrating an example of the cross-sectional structure of a storage device according to an embodiment of the present disclosure.

[0023] refer to Figure 1 The storage device according to embodiments of this disclosure may include a first semiconductor structure CS1, a second semiconductor structure CS2, and a contact plug 110. The first semiconductor structure CS1 may include a storage cell. The second semiconductor structure CS2 may include peripheral circuitry connected to the storage cell.

[0024] The first semiconductor structure CS1 may include a first insulating pattern 21, a first gate insulating layer 22, a back gate electrode BG, a second insulating pattern 24, a channel structure 25, a third insulating pattern 26, a second gate insulating layer 27, a word line WL, a fourth insulating pattern 29, a first interlayer insulating layer 30, a storage node contact 31, a second interlayer insulating layer 32, a landing pad 33, a conductive pad 34, a data storage pattern 40, a first insulating layer 44, a bit line 50, a second insulating layer 60, and a first bonding insulating layer 71.

[0025] The second semiconductor structure CS2 may include a first substrate 101, a first transistor TR1, a gate capping layer 106, a spacer 107, a third insulating layer 108, a second bonding insulating layer 109, a contact plug 110, a source contact 114, a drain contact 115, a gate contact 116, a fourth insulating layer 117, wiring 120, source wiring 124, and gate wiring 125. The contact plug 110 may include a first contact plug 111, a second contact plug 112, and a third contact plug 113.

[0026] The data storage pattern 40 may include a first electrode 41, a dielectric layer 42, and a second electrode 43. The first transistor TR1 may include a source region 102, a drain region 103, a third gate insulating layer 104, and a first gate electrode 105. The wiring 120 may include a first wiring 121, a second wiring 122, and a third wiring 123.

[0027] The first semiconductor structure CS1 may include a cell region CR and a connection region CNR. The cell region CR may refer to the region where memory cells are disposed. The connection region CNR may refer to the region where various contacts for connecting memory cells to peripheral circuitry are disposed. Alternatively, the connection region CNR may be the region where electrodes for connecting one semiconductor chip to another semiconductor chip are disposed.

[0028] The first gate insulating layer 22 may be disposed on two sides of the first insulating pattern 21, the back gate electrode BG, and the second insulating pattern 24. The first gate insulating layer 22 may be disposed on two sides of the back gate electrode BG. The first gate insulating layer 22 can electrically insulate the back gate electrode BG from the channel structure 25.

[0029] The channel structure 25 may be disposed on a side surface of the first gate insulating layer 22. The channel structure 25 may include a first end 25a and a second end 25b, which are opposite to each other in the vertical direction. The first end 25a may refer to the lower surface of the channel structure 25. The second end 25b may refer to the upper surface of the channel structure 25. Hereinafter, the first end 25a of the channel structure 25 may be referred to as the lower surface of the channel structure 25. Similarly, the second end 25b of the channel structure 25 may be referred to as the upper surface of the channel structure 25.

[0030] The channel structure 25 may include a source region, a channel region, and a drain region. In one embodiment, the channel region may be located between the source region and the drain region in the vertical direction. The source region may be disposed in a region adjacent to or close to the second end 25b of the channel structure 25. The drain region may be disposed in a region adjacent to or close to the first end 25a of the channel structure 25. Alternatively, the positions of the source region and the drain region may be interchanged. The channel structure 25 may be located between a word line WL and a back gate electrode BG.

[0031] The third insulating pattern 26, the second gate insulating layer 27, and the fourth insulating pattern 29 may be disposed on the side surface of the channel structure 25. The second gate insulating layer 27 may be disposed between the word line WL and the channel structure 25. The second gate insulating layer 27 may electrically insulate the word line WL and the channel structure 25 from each other. In one embodiment, the first gate insulating layer 22 and the second gate insulating layer 27 may contact at least a portion of the side surface of the channel structure 25.

[0032] The first interlayer insulating layer 30 may be disposed beneath the channel structure 25, the first gate insulating layer 22, the second gate insulating layer 27, the first insulating pattern 21, and the third insulating pattern 26. The memory node contact 31 may penetrate the first interlayer insulating layer 30 and be directly connected to the channel structure 25. For example, one surface (e.g., the upper surface) of the memory node contact 31 may contact the first end 25a of the channel structure 25.

[0033] The second interlayer insulating layer 32 may be disposed below the first interlayer insulating layer 30. The landing pad 33 can be connected to the storage node contact 31 by penetrating the second interlayer insulating layer 32. In the connection region CNR, a conductive pad 34 may be disposed within the second interlayer insulating layer 32. The conductive pad 34 may be disposed on the same layer as the landing pad 33. The conductive pad 34 can contact a surface (e.g., the lower surface) of the first interlayer insulating layer 30 by penetrating the second interlayer insulating layer 32.

[0034] The data storage pattern 40 may be disposed beneath the landing pad 33 and the second interlayer insulation layer 32. In one embodiment, the data storage pattern 40 may be a capacitor. The data storage pattern 40 may be electrically connected to the first end 25a of the channel structure 25 via the storage node contact 31 and the landing pad 33.

[0035] The first electrode 41 of the data storage pattern 40 may contact a surface (e.g., the lower surface) of the landing pad 33. The first electrode 41 is shown as having a columnar shape, but the shape of the first electrode 41 is not limited thereto. A dielectric layer 42 may be disposed to cover the surface of the first electrode 41. The dielectric layer 42 is shown as contacting a surface (e.g., the lower surface) of the second interlayer insulating layer 32, but the embodiment is not limited thereto. For example, an etch stop layer may be further disposed between the dielectric layer 42 and the second interlayer insulating layer 32. A second electrode 43 may surround the first electrode 41 and the dielectric layer 42. At least a portion of the dielectric layer 42 and the second electrode 43 may also be disposed in the connection region CNR. A first insulating layer 44 may be disposed to cover the second electrode 43.

[0036] Bit line 50 may be connected to a second end 25b of channel structure 25. For example, one surface of bit line 50 (e.g., the lower surface) may contact the second end 25b of channel structure 25. Bit line 50 may extend along a first direction FD.

[0037] The second insulating layer 60 may be configured to cover the bit line 50. The first bonding insulating layer 71 may be disposed on the second insulating layer 60. One surface (e.g., the upper surface) of the first bonding insulating layer 71 may be used as the surface (e.g., the upper surface) of the first semiconductor structure CS1.

[0038] The second semiconductor structure CS2 is bonded to the first semiconductor structure CS1. One surface (e.g., the lower surface) of the second semiconductor structure CS2 may contact the surface (e.g., the upper surface) of the first bonding insulating layer 71.

[0039] The first substrate 101 of the second semiconductor structure CS2 may include a first surface 101a and a second surface 101b. The second surface 101b is opposite to the first surface 101a in the vertical direction. The first surface 101a is the surface facing the bit line 50 and may refer to the lower surface of the first substrate 101. The second surface 101b may refer to the upper surface of the first substrate 101. In one embodiment, the first surface 101a of the first substrate 101 may contact the second bonding insulating layer 109. Hereinafter, the first surface 101a of the first substrate 101 may be referred to as the lower surface of the first substrate 101. Similarly, the second surface 101b of the first substrate 101 may be referred to as the upper surface of the first substrate 101.

[0040] The first transistor TR1 may be disposed on the second surface 101b of the first substrate 101. The first transistor TR1 may be a transistor that transmits various voltages or signals to the memory cell. Although Figure 1 Only one first transistor TR1 is shown, but the first transistor TR1 can refer to any transistor included in the peripheral circuitry, such as a sensing transistor, a transmitting transistor, or a driving transistor. The first transistor TR1 may be located in the region surrounded by the wiring 120 and the first surface 101a of the first substrate 101.

[0041] The source region 102 and drain region 103 of the first transistor TR1 can be disposed in the first substrate 101. A third gate insulating layer 104 can be disposed on the first substrate 101 between the source region 102 and the drain region 103. A first gate electrode 105 and a gate capping layer 106 can be disposed sequentially on the third gate insulating layer 104. Spacers 107 can be disposed on the sides of the third gate insulating layer 104, the first gate electrode 105, and the gate capping layer 106.

[0042] The third gate insulating layer 104, the first gate electrode 105, and the gate capping layer 106 may be disposed on the second surface 101b of the first substrate 101. Viewed from the first substrate 101, the third gate insulating layer 104, the first gate electrode 105, and the gate capping layer 106 may be located opposite to the second bonding insulating layer 109.

[0043] The third insulating layer 108 may be disposed on the first substrate 101 and the first transistor TR1. The source contact 114 and the drain contact 115 may be connected to the source region 102 and the drain region 103 respectively through the third insulating layer 108. The gate contact 116 may be contacted with the upper surface of the first gate electrode 105 through the third insulating layer 108 and the gate capping layer 106.

[0044] A fourth insulating layer 117 may be disposed on the third insulating layer 108, the source contact 114, the drain contact 115, and the gate contact 116. Wiring 120, source wiring 124, and gate wiring 125 may penetrate the fourth insulating layer 117. Wiring 120 may be disposed in the same layer and spaced apart from each other. For example, first wiring 121, second wiring 122, third wiring 123, source wiring 124, and gate wiring 125 may be spaced apart from each other in the first direction FD. First wiring 121 may be connected to the drain contact 115. First wiring 121 may also be referred to as the drain wiring. Source wiring 124 may be connected to the source contact 114. Gate wiring 125 may be connected to the gate contact 116.

[0045] The first contact plug 111 can connect the first semiconductor structure CS1 and the second semiconductor structure CS2 through the third insulating layer 108, the first substrate 101, the bonding insulating layer 80 including the first bonding insulating layer 71 and the second bonding insulating layer 109, and the second insulating layer 60. For example, the first contact plug 111 can connect the first wiring 121 and the bit line 50 to each other. For example, one end of the first contact plug 111 can contact one surface (e.g., the lower surface) of the first wiring 121, while the other end of the first contact plug 111 can contact another surface (e.g., the upper surface) of the bit line 50. The first transistor TR1 can be connected to the bit line 50 through the drain contact 115, the first wiring 121, and the first contact plug 111.

[0046] The second contact plug 112 can connect the first semiconductor structure CS1 and the second semiconductor structure CS2 through the third insulating layer 108, the first substrate 101, the bonding insulating layer 80, the second insulating layer 60, the fourth insulating pattern 29, the third insulating pattern 26, the first interlayer insulating layer 30, the second interlayer insulating layer 32, and the dielectric layer 42. For example, the second contact plug 112 can interconnect the second wiring 122 and the data storage pattern 40. For example, one end of the second contact plug 112 can contact a surface (e.g., the lower surface) of the second wiring 122, while the other end of the second contact plug 112 can contact a surface (e.g., the upper surface) of the second electrode 43 of the data storage pattern 40.

[0047] The third contact plug 113 can connect the first semiconductor structure CS1 and the second semiconductor structure CS2 by penetrating the third insulating layer 108, the first substrate 101, the bonding insulating layer 80, the second insulating layer 60, the fourth insulating pattern 29, the third insulating pattern 26, and the first interlayer insulating layer 30. For example, the third contact plug 113 can interconnect the third wiring 123 and the conductive pad 34. For example, one end of the third contact plug 113 can contact a surface (e.g., the lower surface) of the third wiring 123, while the other end of the third contact plug 113 can contact a surface (e.g., the upper surface) of the conductive pad 34. The third contact plug 113 can also be referred to as a through electrode. In some embodiments, an additional contact penetrating the first insulating layer 44 can be provided below the conductive pad 34. In one embodiment, the third contact plug 113 can be used to electrically connect a semiconductor device to the outside of the semiconductor device.

[0048] Figures 2 to 11 A diagram illustrating an example of a method for manufacturing a storage device according to an embodiment of the present disclosure.

[0049] refer to Figure 2 A first semiconductor structure CS1 is fabricated, including a second substrate 11. The second substrate 11 may comprise a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The second substrate 11 may comprise a III-V group semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The second substrate 11 may comprise monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or a combination thereof.

[0050] A fifth insulating layer 12 is formed on the second substrate 11. In the cell region CR, a first insulating pattern 21, a back gate electrode BG, and a second insulating pattern 24 may be formed on the fifth insulating layer 12. A first gate insulating layer 22 may be disposed on two side surfaces of the first insulating pattern 21, the back gate electrode BG, and the second insulating pattern 24, respectively.

[0051] The fifth insulating layer 12, the first insulating pattern 21, the second insulating pattern 24, and the first gate insulating layer 22 may comprise silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0052] A channel structure 25 is disposed on the side of the first gate insulating layer 22. The channel structure 25 may comprise monocrystalline silicon, polycrystalline silicon, doped polycrystalline silicon, or a combination thereof. A source region, a channel region, and a drain region may be formed in the channel structure 25. In one embodiment, the channel region may be formed vertically between the source region and the drain region.

[0053] A third insulating pattern 26, a second gate insulating layer 27, a word line WL, and a fourth insulating pattern 29 may be formed on the side of the channel structure 25. The second gate insulating layer 27 provides electrical insulation between the word line WL and the channel structure 25.

[0054] The third insulating pattern 26, the second gate insulating layer 27, and the fourth insulating pattern 29 may comprise silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, high-k dielectric material, or combinations thereof. The word line WL may comprise a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or combinations thereof.

[0055] refer to Figure 3 A first interlayer insulating layer 30 may be formed on the first insulating pattern 21, the third insulating pattern 26, the first gate insulating layer 22, the second gate insulating layer 27, and the channel structure 25. A memory node contact 31 may be formed in the first interlayer insulating layer 30. The memory node contact 31 may be connected to the corresponding channel structure 25.

[0056] A second interlayer insulating layer 32 may be formed on the first interlayer insulating layer 30 and the storage node contact 31. In the cell region CR, a landing pad 33 may be formed in the second interlayer insulating layer 32. The landing pad 33 may be connected to the corresponding storage node contact 31. In the connection region CNR, a conductive pad 34 may be formed in the second interlayer insulating layer 32. The upper surface of the conductive pad 34 may be substantially coplanar with the upper surface of the landing pad 33.

[0057] The first interlayer insulating layer 30 and the second interlayer insulating layer 32 may comprise silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof. The storage node contact 31, landing pad 33, and conductive pad 34 may comprise conductive materials, such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or combinations thereof.

[0058] refer to Figure 4 A data storage pattern 40 may be formed on the second interlayer insulating layer 32 and the landing pad 33. In one embodiment, the data storage pattern 40 may be a capacitor. A first electrode 41 of the data storage pattern 40 may be formed to connect to a corresponding landing pad 33. In some embodiments, a support layer for supporting the first electrode 41 may be further formed on the side of the first electrode 41. A dielectric layer 42 may be formed on the surface of the first electrode 41. The dielectric layer 42 may also be partially formed within the connection region CNR. A second electrode 43 may be formed on the dielectric layer 42. The second electrode 43 may cover the entire upper surface of the dielectric layer 42. A first insulating layer 44 may be formed on the second electrode 43.

[0059] The first electrode 41 and the second electrode 43 may comprise conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof. The dielectric layer 42 may comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, or combinations thereof. The first insulating layer 44 may comprise silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, high-k dielectric materials, or combinations thereof.

[0060] refer to Figure 5 It can remove Figure 4 The second substrate 11 and the fifth insulating layer 12 are present. In one embodiment, the process for removing the second substrate 11 may include a laser lift-off (LLO) process. In one embodiment, the process for removing the fifth insulating layer 12 may include an etching process.

[0061] When the second substrate 11 and the fifth insulating layer 12 are removed, the upper surfaces of the second insulating pattern 24, the first gate insulating layer 22, the second gate insulating layer 27, the fourth insulating pattern 29, and the channel structure 25 are exposed.

[0062] refer to Figure 6 In the cell region CR, bit lines 50 may be formed on the upper surfaces of the second insulating pattern 24, the first gate insulating layer 22, the second gate insulating layer 27, the fourth insulating pattern 29, and the channel structure 25. Bit lines 50 may contact the upper surface of the channel structure 25. Bit lines 50 may comprise conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0063] A second insulating layer 60 may be disposed on bit line 50. The second insulating layer 60 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a high-k dielectric material, or a combination thereof. The upper surface of the second insulating layer 60 may be planarized by a chemical mechanical polishing (CMP) process.

[0064] A first bonding insulating layer 71 may be formed on the second insulating layer 60. The first bonding insulating layer 71 may comprise silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

[0065] refer to Figure 7 A second semiconductor structure CS2 is fabricated, comprising a first substrate 101. The first substrate 101 may comprise a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The first substrate 101 may comprise a III-V group semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The first substrate 101 may comprise monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or a combination thereof.

[0066] A source region 102, a drain region 103, a third gate insulating layer 104, a first gate electrode 105, a gate capping layer 106, and a spacer 107 may be formed in and above a first substrate 101. The source region 102 and drain region 103 may be formed in the first substrate 101. In one embodiment, the source region 102 and drain region 103 may be regions doped with N-type impurities (e.g., phosphorus (P), arsenic (As), or combinations thereof). The third gate insulating layer 104, gate capping layer 106, and spacer 107 may comprise silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof. The first gate electrode 105 may comprise a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or combinations thereof.

[0067] refer to Figure 7 and Figure 8 A third insulating layer 108 may be formed on one surface (e.g., the upper surface) of the first substrate 101. The third insulating layer 108 may cover the source region 102, the drain region 103, the spacer 107, and the gate capping layer 106. The third insulating layer 108 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a high-k dielectric material, or a combination thereof.

[0068] A second bonding insulating layer 109 may be formed on another surface (e.g., the lower surface) of the first substrate 101. Viewed from the first substrate 101, the second bonding insulating layer 109 may be formed at the opposite position to the third insulating layer 108. In one embodiment, a process for removing a portion of the first substrate 101 may be performed prior to the formation of the second bonding insulating layer 109. The process for removing a portion of the first substrate 101 may include polishing the other surface (e.g., the lower surface) of the first substrate 101 using a chemical mechanical polishing process. The second bonding insulating layer 109 may comprise silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

[0069] refer to Figure 9 The second semiconductor structure CS2 can be bonded to the first semiconductor structure CS1. In one embodiment, the second semiconductor structure CS2 can be bonded to the first semiconductor structure CS1 via a melt bonding process. For example, bonding the second semiconductor structure CS2 to the first semiconductor structure CS1 may include a process of bonding a second bonding insulating layer 109 to a first bonding insulating layer 71. One surface of the second bonding insulating layer 109 may contact a surface of the first bonding insulating layer 71. After the second bonding insulating layer 109 and the first bonding insulating layer 71 come into contact with each other, heat may be applied.

[0070] refer to Figure 10 Through-holes THR1, THR2, THR3, THR4, THR5 and THR6 can be formed in the first semiconductor structure CS1 and the second semiconductor structure CS2. Figure 10The diagram shows six vias: THR1, THR2, THR3, THR4, THR5, and THR6. However, this is for illustrative purposes only, and the number of vias contained in a semiconductor device is not limited to this.

[0071] Through-holes THR1, THR2, THR3, THR4, THR5, and THR6 can be formed in the same manufacturing stage. The process for forming through-holes THR1, THR2, THR3, THR4, THR5, and THR6 may include an etching process.

[0072] The first via THR1 can expose the upper surface of the bit line 50 by penetrating the third insulating layer 108, the first substrate 101, the bonding insulating layer 80, and the second insulating layer 60. In some embodiments, the first via THR1 may be formed in the connection region CNR and the cell region CR.

[0073] The second via THR2 can expose the second electrode 43 by penetrating the third insulating layer 108, the first substrate 101, the bonding insulating layer 80, the second insulating layer 60, the fourth insulating pattern 29, the third insulating pattern 26, the first interlayer insulating layer 30, the second interlayer insulating layer 32, and the dielectric layer 42. In some embodiments, the lower end of the second via THR2 can penetrate a portion of the second electrode 43, and its position is below the uppermost surface of the second electrode 43.

[0074] The third via THR3 can expose the upper surface of the conductive pad 34 by penetrating the third insulating layer 108, the first substrate 101, the bonding insulating layer 80, the second insulating layer 60, the fourth insulating pattern 29, the third insulating pattern 26, and the first interlayer insulating layer 30. In one embodiment, the width of the third via THR3 may be greater than the width of the first via THR1 and the width of the second via THR2.

[0075] The fourth via THR4 and the fifth via THR5 can expose the upper surfaces of the source region 102 and the drain region 103, respectively, by penetrating the third insulating layer 108. The sixth via THR6 can expose the upper surface of the first gate 105 by penetrating the third insulating layer 108 and the gate capping layer 106.

[0076] refer to Figure 10 and Figure 11 Conductive material is used to fill through-holes THR1, THR2, THR3, THR4, THR5 and THR6 to form a first contact plug 111, a second contact plug 112, a third contact plug 113, a source contact 114, a drain contact 115 and a gate contact 116, respectively.

[0077] The lower surface of the first contact plug 111 can contact the upper surface of the bit line 50. The lower surface of the second contact plug 112 can contact the upper surface of the second electrode 43. The lower surface of the third contact plug 113 can contact the upper surface of the conductive pad 34. The lower surfaces of the source contact 114 and the drain contact 115 can contact the upper surfaces of the source region 102 and the drain region 103, respectively. The lower surface of the gate contact 116 can contact the upper surface of the first gate electrode 105.

[0078] The upper surfaces of the first contact plug 111, the second contact plug 112, the third contact plug 113, the source contact 114, the drain contact 115, and the gate contact 116 can be substantially located on the same plane.

[0079] The first contact plug 111, the second contact plug 112, the third contact plug 113, the source contact 114, the drain contact 115, and the gate contact 116 may comprise conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. In one embodiment, the first contact plug 111, the second contact plug 112, the source contact 114, the drain contact 115, and the gate contact 116 may comprise tungsten (W), tungsten nitride, or combinations thereof. In one embodiment, the third contact plug 113 may comprise copper (Cu), tantalum (Ta), tantalum nitride, or combinations thereof.

[0080] Refer again Figure 1 A fourth insulating layer 117 is formed on the first contact plug 111, the second contact plug 112, the third contact plug 113, the source contact 114, the drain contact 115, and the gate contact 116. The fourth insulating layer 117 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a high-k dielectric material, or a combination thereof.

[0081] A first wiring 121, a second wiring 122, a third wiring 123, a source wiring 124, and a gate wiring 125 may be formed in the fourth insulating layer 117. The first wiring 121 may be connected to a first contact plug 111 and a drain contact 115. The second wiring 122 may be connected to a second contact plug 112. The third wiring 123 may be connected to a third contact plug 113. The source wiring 124 may be connected to a source contact 114. The gate wiring 125 may be connected to a gate contact 116.

[0082] The first wiring 121, the second wiring 122, the third wiring 123, the source wiring 124, and the gate wiring 125 may be spaced apart from each other. The upper surfaces of the first wiring 121, the second wiring 122, the third wiring 123, the source wiring 124, and the gate wiring 125 may be substantially located on the same plane.

[0083] According to embodiments of this disclosure, a second semiconductor structure CS2, including a first transistor TR1, can be bonded to the first semiconductor structure CS1, which includes a memory cell. The first transistor TR1 can be disposed on a second surface 101b of a first substrate 101.

[0084] Because the first transistor TR1 is located on the upper part of the semiconductor device, connecting the outside of the semiconductor device to the first transistor TR1 is easier. For example, the vertical distance between the external device located on the semiconductor device and the first transistor TR1 can be less than the distance between the external device and the first transistor TR1 when the first transistor TR1 is located on the lower part of the first semiconductor structure CS1. Therefore, when the first transistor TR1 is located on the upper part of the semiconductor device, the number of wirings or contacts required to connect the outside of the semiconductor device to the first transistor TR1 can be reduced, and the length of the contacts for connecting wiring can also be shortened. Thus, the wiring formation process in the semiconductor device can be simplified.

[0085] The above description is intended to enable those skilled in the art to make, use, and practice the technical features of this disclosure, and is provided as an example in conjunction with specific applications and their requirements. Those skilled in the art will be able to readily make various modifications, additions, and substitutions to the described embodiments, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. Therefore, the embodiments and drawings disclosed above should be considered descriptive only and not intended to limit the scope of the technology. The technical scope of this disclosure is not limited to the embodiments and drawings.

Claims

1. A storage device, comprising: A channel structure, comprising a first end and a second end that is perpendicular to the first end in a vertical direction; A data storage pattern, which is connected to the first end of the channel structure; The bit line contacts the second end of the channel structure; A bonding insulating layer is disposed on the bit line; A first substrate is disposed on the bonding insulating layer and includes a first surface facing the bit line and a second surface opposite to the first surface in the vertical direction; as well as A first transistor is disposed on the second surface of the first substrate.

2. The storage device according to claim 1, further comprising: Multiple wirings are located on the first substrate and include a first wiring, a second wiring, and a third wiring spaced apart from each other in the same layer; as well as A first contact plug connects the first wiring and the bit line by penetrating the first substrate and the bonding insulating layer.

3. The storage device according to claim 2, wherein, The first transistor is located along the vertical direction between at least one of the plurality of wirings and the first surface of the first substrate.

4. The storage device according to claim 2, wherein, The first transistor is connected to the first wiring.

5. The storage device according to claim 2, further comprising: A second contact plug extends through the first substrate and the bonding insulating layer to connect the second wiring and the data storage pattern.

6. The storage device according to claim 5, wherein, The data storage pattern includes: First electrode; A second electrode, which surrounds the first electrode; and A dielectric layer is located between the first electrode and the second electrode. The second contact plug is connected to the second electrode.

7. The storage device according to claim 2, further comprising: A through electrode that penetrates the first substrate and the bonding insulating layer and is connected to the third wiring.

8. The storage device according to claim 7, further comprising: A landing pad is disposed between the data storage pattern and the channel structure; as well as The conductive pads are disposed on the same layer as the landing pads. The through electrode is connected to the conductive pad.

9. A storage device, comprising: A first semiconductor structure includes a channel structure, a bit line in contact with the upper surface of the channel structure, and a first bonding insulating layer located above the bit line. A second semiconductor structure includes: a second bonding insulating layer bonded to the first bonding insulating layer; a first substrate disposed on the second bonding insulating layer; and a first transistor disposed on the first substrate; and Multiple contact plugs, including a first contact plug, a second contact plug and a third contact plug spaced apart from each other, connect the first semiconductor structure and the second semiconductor structure by passing through the first substrate, the first bonding insulating layer and the second bonding insulating layer.

10. The storage device according to claim 9, wherein The second semiconductor structure also includes a plurality of wirings located on the first substrate, and Each of the plurality of contact plugs is connected to one of the plurality of wirings.

11. The storage device according to claim 10, wherein, The first transistor is disposed between at least one of the plurality of wirings and the second bonding insulating layer.

12. The storage device according to claim 10, wherein The plurality of wirings includes a first wiring, a second wiring, and a third wiring spaced apart from each other on the same layer, and The first contact plug connects the first wiring and the bit line.

13. The storage device according to claim 12, wherein, The first transistor is connected to the first wiring.

14. The storage device of claim 10, wherein The first semiconductor structure also includes a data storage pattern connected to the lower surface of the channel structure. The plurality of wirings includes a first wiring, a second wiring, and a third wiring spaced apart from each other on the same layer, and The second contact plug connects the second wiring and the data storage pattern.

15. The storage device according to claim 14, wherein, The data storage pattern includes: First electrode; A second electrode, which surrounds the first electrode; and A dielectric layer is located between the first electrode and the second electrode. The second contact plug is connected to the second electrode.

16. The storage device of claim 10, wherein The plurality of wirings includes a first wiring, a second wiring, and a third wiring spaced apart from each other on the same layer, and The third contact plug is connected to the third wiring.

17. The storage device according to claim 16, wherein, The first semiconductor structure further includes: Landing pads, which are connected to the lower surface of the channel structure; and The conductive pads are disposed on the same layer as the landing pads. The third contact plug is connected to the conductive pad.

18. A storage device comprising: A channel structure, comprising a first end and a second end that is perpendicular to the first end in a vertical direction; A data storage pattern, which is connected to the first end of the channel structure; The bit line contacts the second end of the channel structure; A bonding insulating layer is located above the bit line; A first substrate is located on the bonding insulating layer; Multiple wirings are located on the first substrate; as well as Multiple contact plugs are respectively directly connected to the multiple wirings and penetrate the bonding insulation layer and the first substrate.

19. The storage device of claim 18, further comprising: A first transistor is disposed on the first substrate. in, The first transistor is connected to at least one of the plurality of wirings.

20. The storage device according to claim 18, wherein, At least one of the plurality of contact plugs connects to any one of the plurality of wirings and the bit line.

Images