Semiconductor device

Abstract

The present disclosure relates to a semiconductor device, and the semiconductor device includes: a peripheral circuit structure including a substrate having a first surface and a second surface facing each other, a peripheral circuit, and a first peripheral buffer layer, the substrate including a first impurity region and a second impurity region between the first impurity region, the peripheral circuit being located on the first surface of the substrate, the first peripheral buffer layer being located on the second surface of the substrate; a cell structure overlapping the peripheral circuit structure; and a charge shielding layer between the substrate and the first peripheral buffer layer, wherein the cell structure includes: a plurality of memory cells including a memory transistor and a capacitor; and a word line and a bit line connected to the memory transistor.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] There is a need for technologies to improve the integration density of semiconductor devices. For two-dimensional semiconductor devices, the integration density is mainly determined by the area occupied by a unit memory cell, and this aspect of the integration density may be affected by the level of fine patterning technology.

[0003] However, the integration density of two-dimensional semiconductor devices is increasing, but still limited, due to the need for expensive equipment for fine patterning techniques. Therefore, three-dimensional semiconductor memory devices with memory cells arranged in three dimensions are being proposed. Summary of the Invention

[0004] The embodiments are intended to provide a semiconductor device with improved electrical characteristics.

[0005] According to an embodiment, a semiconductor device includes: a peripheral circuit structure comprising a substrate, a peripheral circuit, and a first peripheral buffer layer; the substrate having a first surface and a second surface facing each other; the substrate including a first impurity region and a second impurity region located between the first impurity regions; the peripheral circuit located on the first surface of the substrate; and the first peripheral buffer layer located on the second surface of the substrate; a cell structure overlapping the peripheral circuit structure; and a charge shielding layer located between the substrate and the first peripheral buffer layer; wherein the cell structure includes: a plurality of memory cells, the plurality of memory cells including a memory transistor and a capacitor; and word lines and bit lines connected to the memory transistor.

[0006] According to an embodiment, a semiconductor device includes: a first substrate and a cell structure, the cell structure being located on the first substrate and including a plurality of memory cells; a peripheral circuit structure, the peripheral circuit structure including a second substrate having a first impurity region and a second impurity region located between the first impurity region, peripheral circuitry located on the second substrate, and a first peripheral buffer layer located below the second substrate, the peripheral circuit structure overlapping the cell structure; and a charge shielding layer located between the first substrate and the second substrate, wherein the cell structure includes: a gate stack structure in which a plurality of word lines and a plurality of interlayer insulating layers are alternately stacked; a plurality of channel patterns arranged at intervals along a direction perpendicular to the first substrate; bit lines extending in a direction perpendicular to the first substrate and connected to one end of a corresponding channel pattern; and a capacitor connected to the other end of the corresponding channel pattern.

[0007] According to an embodiment, a semiconductor device includes: a first substrate and a cell structure, the cell structure being located on the first substrate and including a plurality of memory cells; a peripheral circuit structure, the peripheral circuit structure being located on the cell structure and including a second substrate having a first impurity region and a second impurity region located between the first impurity region, a peripheral circuit located on the second substrate, and a peripheral buffer layer located below the second substrate; and a charge shielding layer, the charge shielding layer covering the bottom surface of the second impurity region located in the second substrate.

[0008] According to an embodiment, a method of manufacturing a semiconductor device includes: forming a cell structure including a first substrate and a plurality of memory cells disposed on a front surface of the first substrate; forming peripheral circuitry on a front surface of a second substrate; performing a wafer thinning process on a rear surface of the second substrate until an insulating pattern located inside the second substrate is exposed; forming a charge shielding layer on the rear surface of the second substrate; forming a first peripheral buffer layer covering the charge shielding layer; bonding the first peripheral buffer layer to the cell structure; and forming a peripheral wiring structure covering the second substrate, the insulating pattern, and the peripheral circuitry.

[0009] In the method of manufacturing a semiconductor device according to an embodiment, the first peripheral buffer layer may have a positive charge.

[0010] In a method for manufacturing a semiconductor device according to an embodiment, the step of forming the charge shielding layer may include: forming the charge shielding layer using a low-pressure chemical vapor deposition (LPCVD) process, a chemical vapor deposition (CVD) process, or a selective epitaxial growth (SEG) process.

[0011] In a method of manufacturing a semiconductor device according to an embodiment, the step of forming the charge shielding layer may include forming the charge shielding layer as a portion covering the back surface of the second substrate.

[0012] In a method of manufacturing a semiconductor device according to an embodiment, the step of forming the charge shielding layer may include forming the charge shielding layer to cover the entire back surface of the second substrate.

[0013] In a method for manufacturing a semiconductor device according to an embodiment, the step of forming the charge shielding layer may include performing an impurity activation process on the charge shielding layer.

[0014] In the method of manufacturing a semiconductor device according to an embodiment, the impurity activation process may include a laser annealing process.

[0015] In the method of manufacturing a semiconductor device according to an embodiment, the charge shielding layer may include monocrystalline silicon, polycrystalline silicon, or amorphous silicon.

[0016] In a method of manufacturing a semiconductor device according to an embodiment, the charge shielding layer may include B-doped Si or B-doped SiGe.

[0017] In the method of manufacturing a semiconductor device according to an embodiment, the method may further include: forming a second peripheral buffer layer having a negative charge between the second substrate and the first peripheral buffer layer, and the charge shielding layer may include P-doped Si, P-doped SiGe, As-doped Si, or As-doped SiGe. Attached Figure Description

[0018] Figure 1 This is a schematic top view of a portion of a semiconductor device according to an embodiment.

[0019] Figure 2 This is a circuit diagram of a memory cell array of a semiconductor device according to an embodiment.

[0020] Figure 3 This is a perspective view of the memory cell layer of a semiconductor device according to an embodiment.

[0021] Figure 4 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0022] Figure 5 and Figure 6 According to some embodiments Figure 4 A magnified view of region M.

[0023] Figure 7 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0024] Figure 8 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0025] Figure 9 and Figure 10 According to some embodiments Figure 8 A magnified view of region N.

[0026] Figure 11 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0027] Figures 12 to 18 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0028] In the following description, various embodiments of the invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the invention. The invention may be embodied in many different forms and is not limited to the embodiments described herein.

[0029] To clearly illustrate the invention, parts irrelevant to the description have been omitted, and the same reference numerals are used for the same or similar parts throughout the specification.

[0030] Furthermore, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrary for ease of illustration, and the invention is not necessarily limited to what is shown. Thicknesses are enlarged and shown to clearly illustrate the various layers and regions in the drawings. In the drawings, the thicknesses of some layers and regions are exaggerated for ease of illustration.

[0031] Furthermore, when we say that a part of a layer, membrane, region, or plate is "above" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there are other parts in between. Conversely, when we say that a part is "directly above" another part, we mean that there are no other parts in between. Also, "above" or "on" a reference part means above or below the reference part, and does not necessarily mean "above" or "on" in the opposite direction of gravity.

[0032] Furthermore, throughout the specification, unless otherwise specifically stated, whenever a part is referred to as "including" a component, this does not mean that it excludes other components, but rather that it may include other components.

[0033] Additionally, throughout the instruction manual, when we say "in a plane," we mean when viewing the target portion from above, and when we say "in a cross-section," we mean when viewing the target portion from one side of a vertically cut cross-section.

[0034] Furthermore, throughout the specification, two directions parallel to and intersecting the upper surfaces of the first and second substrates are defined as the first direction X and the second direction Y, respectively, and a direction perpendicular to the upper surfaces of the first and second substrates is described as the third direction Z. For example, the first direction X and the second direction Y can be orthogonal to each other.

[0035] Figure 1 This is a schematic top view of a portion of a semiconductor device according to an embodiment. Figure 2 This is a circuit diagram of a memory cell array of a semiconductor device according to an embodiment. Figure 3 This is a perspective view of the memory cell layer of a semiconductor device according to an embodiment. Figure 4 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0036] refer to Figures 1 to 4 The semiconductor device 10 according to the embodiment may include a cell structure CS and a peripheral circuit structure PS that overlap each other in the vertical direction.

[0037] According to an embodiment, the cell structure CS and the peripheral circuit structure PS can be stacked sequentially. In other words, the peripheral circuit structure PS can be located on top of the cell structure CS. However, this is not limited to this, and the stacking relationship between the cell structure CS and the peripheral circuit structure PS can be changed in various ways. For example, contrary to what is shown, the cell structure CS can be located on top of the peripheral circuit structure PS.

[0038] According to an embodiment, the cell structure CS may include: a plurality of memory cells MC, and a memory cell array MCA including the memory cells. The plurality of memory cells MC and the memory cell array MCA including the memory cells may be located in the memory cell layer MSL of the cell structure CS described below.

[0039] According to an embodiment, a storage cell array (MCA) may have multiple storage cells (MCs) arranged in the row and column directions to store data. The MCA can output data from storage cell MCs specified by row and column addresses, or write data to storage cell MCs specified by row and column addresses.

[0040] Specifically, such as Figure 2 As shown, a memory cell array MCA may include bit lines BL, word lines WL, and memory cells MC connected to them.

[0041] According to an embodiment, the memory cell MC may include a memory transistor TR and a capacitor CP. The capacitor CP can be used as a memory element by forming two distinguishable logic states depending on whether charge is stored.

[0042] According to an embodiment, the gate electrode of the storage transistor TR can be connected to the word line WL. The first source / drain electrode of the storage transistor TR can be connected to one end of the capacitor CP, and the second source / drain electrode of the storage transistor TR can be connected to the bit line BL. The other end of the capacitor CP can be connected to the board line PL. For example, the board line PL can be a wiring that applies a bias voltage to the capacitor CP when the memory cell MC is operating.

[0043] Although not shown, the peripheral circuit structure PS may include a core region and a peripheral region. The core region and the peripheral region may be collectively referred to as the logic region or the peripheral circuit region.

[0044] According to an embodiment, the core region may include a core bank, and the core bank may include core circuitry such as word line drivers, sense amplifiers, row decoders, column decoders, and read / write circuitry.

[0045] According to an embodiment, the peripheral area may include peripheral circuitry, such as a timing register, an address register, a data input register, a data output register, and data input / output terminals.

[0046] According to an embodiment, the peripheral circuit structure PS may include peripheral circuitry PC for driving components located in the unit structure CS. For example, the peripheral circuitry PC may include the core circuitry and / or peripheral circuitry described above.

[0047] According to an embodiment, the cell structure CS may include a first substrate 100 and a plurality of memory cells MC located on the first substrate 100.

[0048] According to an embodiment, the first substrate 100 may have a first surface 100S1 and a second surface 100S2. For example, the first surface 100S1 of the first substrate 100 may correspond to the upper surface, and the second surface 100S2 may correspond to the lower surface. In this disclosure, two directions parallel to and intersecting each other with the first surface 100S1 of the first substrate 100 are defined as a first direction X and a second direction Y, respectively, and a direction perpendicular to the first surface 100S1 of the first substrate 100 is defined as a third direction Z. The first direction X and the second direction Y may be orthogonal to each other.

[0049] According to an embodiment, the first substrate 100 may include a semiconductor material. For example, the first substrate 100 may be a semiconductor substrate comprising a semiconductor material, such as a single-crystal Si substrate, a silicon-germanium (Si-Ge) substrate, or an SOI (Si-on-insulator) substrate. As another example, the first substrate 100 may be a semiconductor epitaxial layer comprising a semiconductor material. However, the type of the first substrate 100 is not limited thereto and can be varied in various ways.

[0050] According to an embodiment, multiple memory cells MC can be arranged in a first direction X and a second direction Y. Multiple memory cells MC can be stacked in a third direction Z perpendicular to the first surface 100S1 of the first substrate 100. The multiple memory cells MC can have a three-dimensional array structure. The multiple memory cells MC can be referred to as a memory cell array MCA.

[0051] According to an embodiment, the cell structure CS may include a gate stack structure 120 in which word lines WL and interlayer dielectric layers ILD (also referred to as interlayer insulating layers) are alternately stacked in a third direction Z perpendicular to a first surface 100S1 of the first substrate 100. The word lines WL and interlayer dielectric layers ILD may extend in a direction parallel to the first surface 100S1 of the first substrate 100 (e.g., in a first direction (X)). The word lines WL and interlayer dielectric layers ILD may have a longer length extending in the first direction X as they are closer to the first substrate 100. Therefore, the gate stack structure 120 may have a stepped structure in cross-section. In other words, the ends of the multiple word lines WL and the ends of the multiple interlayer dielectric layers ILD may have steps.

[0052] According to an embodiment, the memory cell layer MSL of the cell structure CS may include multiple bit lines BL located outside the gate stack structure 120. The multiple bit lines BL are spaced apart in a direction parallel to the first surface 100S1 of the first substrate 100 (e.g., a first direction (X)). Each of the multiple bit lines BL may extend in a third direction Z perpendicular to the first surface 100S1 of the first substrate 100.

[0053] According to an embodiment, each of the plurality of memory cells MC can be connected to a bit line BL and a word line WL. When a voltage is applied to the word line WL and the bit line BL, a read or write operation can be performed on the memory cell MC. The word line WL can be referred to as the gate electrode.

[0054] According to an embodiment, each of the plurality of memory cells MC may include a semiconductor pattern SP. The semiconductor pattern SP may be spaced apart along a third direction Z and extend in a second direction Y.

[0055] According to an embodiment, each of the plurality of semiconductor patterns SP may include a first impurity pattern SD1 located on one side of the word line WL, a second impurity pattern SD2 located on the other side of the word line WL, and a channel pattern CH located between the first impurity pattern SD1 and the second impurity pattern SD2.

[0056] According to an embodiment, both the first impurity pattern SD1 and the second impurity pattern SD2 can be regions doped with impurities (e.g., n-type or p-type impurities). The first impurity pattern SD1 and the second impurity pattern SD2 of the semiconductor pattern SP can form the storage transistor of the storage cell MC (e.g., Figure 2 The source / drain regions of a storage transistor (TR). The channel pattern CH of the semiconductor pattern SP can be surrounded by word lines WL.

[0057] According to an embodiment, a semiconductor pattern SP can penetrate a word line WL in the second direction Y. One end of the semiconductor pattern SP along the second direction Y can be connected to a bit line BL, and the other end of the semiconductor pattern SP along the second direction Y can be connected to a capacitor CP. One end of the channel pattern CH along the second direction Y can contact the bit line BL, and the other end of the channel pattern CH along the second direction Y can contact the capacitor. A first impurity pattern SD1 of the semiconductor pattern SP can be connected to the bit line BL, and a second impurity pattern SD2 can be connected to the capacitor CP.

[0058] According to an embodiment, the channel pattern CH can penetrate the word line WL in the second direction Y, and the word line WL can have a structure that completely surrounds the side surface of the channel pattern CH of the semiconductor pattern SP (in other words, a gate all around (GAA) structure).

[0059] According to an embodiment, the first impurity pattern SD1 of the semiconductor pattern SP can be connected to the bit line BL and used as a first source / drain region, and the second impurity pattern SD2 can be connected to the capacitor CP and used as a second source / drain region. The channel pattern CH located between the first impurity pattern SD1 and the second impurity pattern SD2 can be used as the channel region of the storage transistor TR.

[0060] The semiconductor device 10 according to the embodiment may further include a gate insulating film GI located between the channel pattern CH and the word line WL.

[0061] In one embodiment, the gate insulating film GI may surround the channel pattern CH. The channel pattern CH may be separated from the word line WL by the gate insulating film GI. The gate insulating film GI may not contact the first impurity pattern SD1 and the second impurity pattern SD2 of the semiconductor pattern SP. However, this is not a limitation, and the channel pattern CH may extend in the second direction Y on one side of the word line WL, and the gate insulating film GI may be located between one side of the word line WL and the channel pattern CH.

[0062] In the embodiments described above, the semiconductor device is described as a vertically stacked dynamic random access memory (VSDRAM) in which multiple memory cells MC are stacked vertically, but it is not limited thereto. For example, the semiconductor device can be changed to various memory devices, such as DRAM including vertical channel transistors (VCT) or buried channel array transistors (BCAT), vertical NAND flash memory, 3D FeFET (ferroelectric FET), 3D monolithic, etc.

[0063] The semiconductor device 10 according to an embodiment includes a memory cell layer MSL and may also include a first cell insulating layer 130 covering the gate stack structure 120.

[0064] According to an embodiment, the first unit insulating layer 130 may cover the upper surface and side surface of the gate stack structure 120. In other words, the first unit insulating layer 130 may cover the upper surface of the word line WL located at the top of the gate stack structure 120 and the side surface of the word line WL and the interlayer dielectric layer (interlayer insulating layer) ILD that constitute the side surface of the gate stack structure 120.

[0065] According to an embodiment, the cell structure CS may further include: a second cell insulating layer 150 located above the storage cell layer MSL, and a first cell wiring layer 141, a second cell wiring layer 143, and a first cell path 142 located within the second cell insulating layer 150.

[0066] According to an embodiment, the first unit wiring layer 141 and the second unit wiring layer 143 may be located at different heights within the second unit insulating layer 150. The first unit wiring layer 141 and the second unit wiring layer 143 may be connected to each other via the first unit passage 142.

[0067] exist Figure 4 In the diagram, the cell structure CS is shown to include a first cell wiring layer 141, a second cell wiring layer 143, and a first cell path 142 connecting them, but the number of cell wiring layers and cell paths included in the cell structure CS and / or their connection relationships may vary.

[0068] According to an embodiment, the cell structure CS may include a word line contact WLC connecting the word line WL and the first cell wiring layer 141. The word line contact WLC can be connected to the word line WL by penetrating the first cell insulating layer 130. The word line contact WLC may be surrounded by the first cell insulating layer 130.

[0069] In an embodiment, the word line contact (WLC) may extend in the third direction (Z). The word line contact (WLC) may have a cylindrical shape in cross-section. For example, the word line contact (WLC) may have sloping side surfaces such that, depending on the aspect ratio in the cross-section, its width becomes narrower as it approaches the first substrate 100. However, the cross-sectional shape of the word line contact (WLC) is not limited to this and can be varied in various ways.

[0070] Although not shown, the cell structure CS may also include bit line contacts (not shown) that penetrate the first cell insulating layer 130 and connect multiple bit lines BL located outside the gate stack structure 120 to the first cell wiring layer 141.

[0071] According to an embodiment, one end of the word line contact WLC along the third direction Z can be connected to the word line WL, and the other end of the word line contact WLC along the third direction Z can be connected to the first unit wiring layer 141.

[0072] According to an embodiment, each of the bit line BL, word line WL, word line contact WLC, first unit wiring layer 141, second unit wiring layer 143, and first unit passage 142 may include, for example, at least one of doped polysilicon, metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicide, or conductive metal oxide (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), but is not limited thereto and may be varied.

[0073] According to embodiments, the channel pattern CH may include at least one of a single-crystal semiconductor, a polycrystalline semiconductor, an oxide semiconductor, and a two-dimensional material. For example, the single-crystal semiconductor may be single-crystal silicon. As another example, the polycrystalline semiconductor may be polycrystalline silicon. As another example, the oxide semiconductor may be indium gallium zinc oxide (IGZO). As another example, the two-dimensional material may be MoS2, WS2, MoSe2, or WSe2. However, the materials included in the channel pattern CH are not limited to these and may be varied in various ways.

[0074] According to an embodiment, each of the interlayer dielectric layer (ILD), the gate insulating film (GI), the first unit insulating layer 130, and the second unit insulating layer 150 may include an insulating material. For example, the insulating material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., and may vary in various ways.

[0075] According to an embodiment, the peripheral circuit structure PS may include a second substrate 200 and a peripheral circuit PC located above the second substrate 200.

[0076] According to an embodiment, the second substrate 200 may include a third surface 200S1 and a fourth surface 200S2 facing each other. A peripheral circuit PC may be located on the third surface 200S1 of the second substrate 200. A peripheral circuit structure PS may be located on the unit structure CS, such that the fourth surface 200S2 of the second substrate 200 faces the first surface 100S1 of the first substrate 100 of the unit structure CS in the third direction Z.

[0077] According to an embodiment, the second substrate 200 may include a semiconductor material. For example, the second substrate 200 may include group IV semiconductors, group III-V compound semiconductors, group II-VI compound semiconductors, etc. For example, the second substrate 200 may include semiconductors such as Si and Ge, or compound semiconductors such as SiGe, SiC, GaAs, InAs, or InP. For example, the second substrate 200 may be a single-crystal epitaxial layer grown on a single-crystal silicon substrate. However, the material of the second substrate 200 is not limited to these and can be changed in various ways.

[0078] According to an embodiment, the second substrate 200 may include a first impurity region as described below and a second impurity region located between the first impurity regions. For example, the first and second impurities may be of different types. See later. Figure 5 and Figure 6 Describe the specific details related to this.

[0079] According to an embodiment, the peripheral circuit PC is a circuit that performs logic operations and may be composed of a combination of circuit elements such as transistors. The peripheral circuit PC may include circuitry that controls a plurality of memory cells MC located in a cell structure CS. For example, the peripheral circuit PC may include, but is not limited to, a row decoder that selects rows of the memory cell array based on address signals, a column decoder that selects columns of the memory cell array based on address signals, a readout amplifier that senses and amplifies data in the memory cells, and a word line driver that activates the word line of the selected row.

[0080] According to an embodiment, the peripheral circuit PC may have a GAA (gate all around) structure and an MBCFET. TM (Multi-bridge channel field-effect transistor) structure, etc., in which the four sides of the channel are surrounded by gate electrodes. However, this is not limited to this, and the peripheral circuit PC can have FinFET (Fin Field-Effect Transistor) structure, 3DSFET (3D Stacked Field-Effect Transistor) structure using next-generation technology, CFET (Complementary Field-Effect Transistor) structure, etc.

[0081] According to an embodiment, the peripheral circuit structure PS may further include: a first peripheral insulating layer 230 and a second peripheral insulating layer 250 sequentially stacked on the third surface 200S1 of the second substrate 200, a first peripheral wiring layer 241, a second peripheral wiring layer 243, a first peripheral path 242, a second peripheral path 244 and a third peripheral path 246 located within the first peripheral insulating layer 230, and a third peripheral wiring layer 260 located within the second peripheral insulating layer 250.

[0082] exist Figure 4 In the diagram, the peripheral circuit structure PS is shown to include a first peripheral wiring layer 241, a second peripheral wiring layer 243 and a third peripheral wiring layer 260, and a first peripheral path 242, a second peripheral path 244 and a third peripheral path 246 connecting them. However, the number of peripheral wiring layers and peripheral paths included in the peripheral circuit structure PS and / or their connection relationships may vary.

[0083] According to an embodiment, the first peripheral wiring layer 241 and the second peripheral wiring layer 243 may be located at different heights within the first peripheral insulating layer 230. The first peripheral wiring layer 241 is connected to at least one of the source or drain regions of the peripheral circuit PC via a first peripheral passage 242, and the first peripheral wiring layer 241 and the second peripheral wiring layer 243 may be connected to each other via a second peripheral passage 244. The first peripheral wiring layer 241 and the second peripheral wiring layer 243, as well as the first peripheral passage 242 and the second peripheral passage 244, may be surrounded by the first peripheral insulating layer 230.

[0084] According to an embodiment, the third peripheral wiring layer 260 may be located within the second peripheral insulating layer 250. The third peripheral wiring layer 260 may be located on the upper surface of the first peripheral insulating layer 230. The third peripheral wiring layer 260 may be connected to the second peripheral wiring layer 243 via a third peripheral path 246 located within the first peripheral insulating layer 230. The third peripheral wiring layer 260 may be, for example, an input / output pad for connecting the semiconductor device 10 to the outside. However, this is just an example, and the function of the third peripheral wiring layer 260 may be varied in various ways.

[0085] According to an embodiment, each of the first peripheral wiring layer 241, the second peripheral wiring layer 243, and the third peripheral wiring layer 260, as well as the first peripheral path 242, the second peripheral path 244, and the third peripheral path 246, may include a conductive material. For example, each of the first peripheral wiring layer 241, the second peripheral wiring layer 243, and the third peripheral wiring layer 260, as well as the first peripheral path 242, the second peripheral path 244, and the third peripheral path 246, may include the same conductive material as the first unit wiring layer 141, the second unit wiring layer 143, and the first unit path 142. However, this is exemplary, and the materials included in the first peripheral wiring layer 241, the second peripheral wiring layer 243, and the third peripheral wiring layer 260, as well as the first peripheral path 242, the second peripheral path 244, and the third peripheral path 246, may be varied.

[0086] According to an embodiment, the first peripheral insulating layer 230 and the second peripheral insulating layer 250 may include insulating materials. For example, the insulating material may include, but is not limited to, silicon oxide, and may vary in various ways.

[0087] The cell structure CS of the semiconductor device 10 according to the embodiment may further include a cell buffer layer 170 located on the second cell insulating layer 150, and the peripheral circuit structure PS may further include a first peripheral buffer layer 270 located below the fourth surface 200S2 of the second substrate 200.

[0088] According to an embodiment, the unit buffer layer 170 may include an insulating material. For example, the insulating material may include, but is not limited to, silicon oxide, and may vary in various ways.

[0089] According to an embodiment, the first peripheral buffer layer 270 may include an insulating material. According to an embodiment, the first peripheral buffer layer 270 may have unique charge characteristics depending on the formation process and thermal conditions.

[0090] According to an embodiment, the first peripheral buffer layer 270 may include a positively charged material. For example, the first peripheral buffer layer 270 may include tetraethyl orthosilicate (TEOS). However, this is not limited to this, and the first peripheral buffer layer 270 may include various positively charged materials.

[0091] More specifically, due to defects or imperfect bonding structures within the film, the first peripheral buffer layer 270 can trap holes or have a fixed positive charge. When the first peripheral buffer layer 270 comes into contact with the second substrate 200, if the first peripheral buffer layer 270 becomes positively charged, a negative charge can be induced in the second substrate 200 in response. This charge distribution can cause leakage current by forming unintended current paths within the second substrate 200.

[0092] The semiconductor device 10 according to an embodiment may include a first charge shielding layer 510 located between a fourth surface 200S2 of a second substrate 200 and a first peripheral buffer layer 270. For example, the semiconductor device 10 according to an embodiment may include the first charge shielding layer 510 to suppress the phenomenon of negative charge being induced in the second substrate 200 due to positive charge induced in the first peripheral buffer layer 270.

[0093] According to an embodiment, the first charge shielding layer 510 may be located between the first substrate 100 of the cell structure CS and the second substrate 200 of the peripheral circuit structure PS. The first charge shielding layer 510 may be located between the first surface 100S1 of the first substrate 100 and the fourth surface 200S2 of the second substrate 200. For example, the first charge shielding layer 510 may be located between the memory cell layer MSL of the cell structure CS and the fourth surface 200S2 of the second substrate 200 of the peripheral circuit structure PS.

[0094] According to an embodiment, the first charge shielding layer 510 may be located in the peripheral circuit structure PS. The first charge shielding layer 510 may be located between the second substrate 200 and the first peripheral buffer layer 270. Alternatively, the first charge shielding layer 510 may be described as being located within the first peripheral buffer layer 270.

[0095] According to an embodiment, the first charge shielding layer 510 covers at least a portion of the fourth surface 200S2 of the second substrate 200 and may be in contact with the fourth surface 200S2 of the second substrate 200. However, this is not limited to this, and additional layers may be located between the fourth surface 200S2 of the second substrate 200 and the first charge shielding layer 510, and between the first peripheral buffer layer 270 and the first charge shielding layer 510.

[0096] According to an embodiment, the thickness of the first charge shielding layer 510 may be thinner than the thickness of the unit buffer layer 170, the thickness of the second substrate 200, and the thickness of the first peripheral buffer layer 270. However, this is just an example, and the position and / or thickness of the first charge shielding layer 510 may be varied in various ways.

[0097] According to an embodiment, the first charge shielding layer 510 may include at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. Reference will be made later. Figure 5 and Figure 6 The specific details related to the first charge shielding layer 510 are described in detail.

[0098] The semiconductor device 10 according to the embodiment may further include a first bonding layer 175 located above the unit buffer layer 170 and a second bonding layer 275 located below the first peripheral buffer layer 270.

[0099] According to an embodiment, the first bonding layer 175 and the second bonding layer 275 can be in contact with each other. The first bonding layer 175 and the second bonding layer 275 can be in contact with each other to form a boundary surface BS. The unit structure CS and the peripheral circuit structure PS can be bonded to each other through the first bonding layer 175 and the second bonding layer 275. Figure 4 In the diagram, semiconductor device 10 is shown to include a unit buffer layer 170, a first bonding layer 175, a second bonding layer 275, and a first peripheral buffer layer 270 stacked sequentially, but the number and / or order of the buffer layers and bonding layers included in semiconductor device 10 may vary.

[0100] The semiconductor device 10 according to the embodiment may further include a through-path 400 connecting the peripheral circuit structure PS and the unit structure CS, and a first insulating pattern 410 surrounding the through-path.

[0101] According to an embodiment, the through-path 400 can extend along a third direction Z from the peripheral circuit structure PS to the cell structure CS. Some through-paths 400 can be a single through-path, partly located in the cell structure CS and other parts located in the peripheral circuit structure PS. In other words, a single through-path 400 can penetrate at least a portion of the first peripheral insulating layer 230, the first insulating pattern 410, the first peripheral buffer layer 270, the cell buffer layer 170, and at least a portion of the second cell insulating layer 150.

[0102] According to an embodiment, the through path 400 can connect a cell routing layer connected to a plurality of memory cells MC in a cell structure CS and a peripheral routing layer connected to a peripheral circuit PC in a peripheral circuit structure PS. For example, the through path 400 can connect a second cell routing layer 143 in the cell structure CS and a second peripheral routing layer 243 in the peripheral circuit structure PS.

[0103] exist Figure 4 In this diagram, one end of the through-path 400 is shown connected to the second cell wiring layer 143 and the other end is shown connected to the second peripheral wiring layer 243. However, the connection relationship between the through-path 400, the cell wiring layer, and the peripheral wiring layer is not limited to this and can be changed in various ways. For example, one end of the through-path 400 may be connected to a plurality of first cell wiring layers 141 located in the cell structure CS, and the other end may be connected to a first peripheral wiring layer 241 located in the peripheral circuit structure PS. As another example, the through-path 400 may consist of multiple paths to connect the cell structure CS and the peripheral circuit structure PS.

[0104] In an embodiment, the through-path 400 may have a columnar shape in cross-section. For example, the through-path 400 may have sloping side surfaces such that its width becomes narrower as it approaches the first substrate 100, depending on the aspect ratio in the cross-section. However, the cross-sectional shape of the through-path 400 is not limited to this and can be varied in various ways.

[0105] According to an embodiment, a first insulating pattern 410 may be located within a second substrate 200. The first insulating pattern 410 is located between the through-path 400 and the second substrate 200, and may surround the side of the through-path 400 that penetrates the second substrate 200. The through-path 400 and the second substrate 200 may be insulated by the first insulating pattern 410.

[0106] According to an embodiment, the first insulating pattern 410 may have a shape that penetrates the second substrate 200. The first insulating pattern 410 can be formed by filling an insulating material into a trench deeper than the isolation pattern 412 described later. The height of the first insulating pattern 410 along the third direction Z may be the same as the thickness of the second substrate 200 along the third direction Z. In other words, the upper surface of the first insulating pattern 410 may be located at substantially the same height as the third surface 200S1 of the second substrate 200, and the lower surface of the first insulating pattern 410 may be located at substantially the same height as the fourth surface 200S2 of the second substrate 200. The first insulating pattern 410 may have a shape in which the width becomes narrower from the third surface 200S1 to the fourth surface 200S2 of the second substrate 200. In other words, the first insulating pattern 410 may have a maximum width at the upper surface and a minimum width at the lower surface.

[0107] In an embodiment, the through-path 400 may include a conductive material. For example, the through-path 400 may include the same conductive material as the first unit path 142 and the first peripheral path 242, the second peripheral path 244 and the third peripheral path 246 described above.

[0108] According to an embodiment, the first insulating pattern 410 may include an insulating material. For example, the first insulating pattern 410 may include silicon oxide. However, this is not limited to this, and the material included in the first insulating pattern 410 may be varied in various ways.

[0109] According to an embodiment, the isolation pattern 412 may be located within the second substrate 200. The isolation pattern 412 can be formed by filling an insulating material into a trench having a predetermined depth from the upper surface of the second substrate 200. The isolation pattern 412 may include, for example, silicon oxide, but is not limited thereto. The insulating material included in the isolation pattern 412 may vary in various ways.

[0110] According to an embodiment, the isolation pattern 412 may have a shallower depth from the upper surface of the second substrate 200 compared to the first insulating pattern 410. The lower surface of the isolation pattern 412 may be located at a higher height than the lower surface of the second substrate 200.

[0111] According to an embodiment, the active region of the second substrate 200 may be defined by isolation patterns 412. Multiple isolation patterns 412 may be spaced apart in a parallel direction on the upper surface of the second substrate 200. The region of the second substrate 200 located between the multiple isolation patterns 412 may be defined as the active region. Peripheral circuitry PC may be formed in the active region of the second substrate 200.

[0112] In the following text, reference will be made to Figure 5 and Figure 6 Semiconductor devices according to various embodiments are described. In the following embodiments, the same components as those previously described are indicated by the same reference numerals, and redundant descriptions may be omitted or simplified.

[0113] Figure 5 and Figure 6 According to some embodiments Figure 4 A magnified view of region M.

[0114] refer to Figure 5 The second substrate 200 may include first impurity regions 210 and 230 and a second impurity region 220 located between the first impurity regions 210 and 230. In other words, the first impurity regions 210 and 230 may be located on both sides of the second impurity region 220.

[0115] According to an embodiment, the first impurity regions 210 and 230 and the second impurity region 220 may include different impurities. For example, the first impurity included in the first impurity regions 210 and 230 may be n-type, and the second impurity included in the second impurity region 220 may be p-type. In other words, the first impurity regions 210 and 230 may be regions doped with n-type impurities, and the second impurity region 220 may be a region doped with p-type impurities. The first impurity regions 210 and 230 may include P, Sb, As, or combinations thereof. The second impurity region 220 may include B, V, In, Ga, Al, or combinations thereof.

[0116] According to an embodiment, the first peripheral buffer layer 270 located beneath the second substrate 200 may comprise a positively charged material. For example, the first peripheral buffer layer 270 may comprise tetraethyl orthosilicate (TEOS). However, this is not limited to this, and the first peripheral buffer layer 270 may comprise various positively charged materials.

[0117] More specifically, due to defects or imperfect bonding structures within the film, the first peripheral buffer layer 270 can trap holes or have a fixed positive charge. When the first peripheral buffer layer 270 comes into contact with the second substrate 200, if the first peripheral buffer layer 270 becomes positively charged, a negative charge can be induced in the second substrate 200 in response.

[0118] Specifically, since the first peripheral buffer layer 270 adjacent to the second substrate 200 has a positive charge, the region of the second substrate 200 adjacent to the first peripheral buffer layer 270 can have a negative charge. This charge distribution can cause leakage current by forming unintended current paths within the second substrate 200.

[0119] The semiconductor device 10 according to an embodiment may include a first charge shielding layer 510 to suppress the phenomenon of negative charge being induced in the second substrate 200 due to positive charge induced in the first peripheral buffer layer 270.

[0120] According to an embodiment, the first charge shielding layer 510 may be located on the fourth surface 200S2 of the second substrate 200. According to an embodiment, the first charge shielding layer 510 may overlap with the second impurity region 220 in the third direction Z. In this case, the first charge shielding layer 510 may not overlap with the first impurity regions 210 and 230 in the third direction Z. However, the first charge shielding layer 510 is not necessarily not required to not overlap with the first impurity regions (210, 230) in the third direction Z, and the first charge shielding layer 510 may overlap with at least a portion of the first impurity regions 210 and 230 in the third direction Z.

[0121] According to an embodiment, the first charge shielding layer 510 may be in contact with the fourth surface 200S2 of the second substrate 200. According to an embodiment, the first charge shielding layer 510 may cover the second impurity region 220 located between the first impurity regions 210 and 230. For example, the first charge shielding layer 510 may only cover the second impurity region 220, or it may cover a portion of the region adjacent to the second impurity region 220.

[0122] According to an embodiment, the first charge shielding layer 510 may include at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. According to an embodiment, the first charge shielding layer 510 may include p-type impurities. For example, the first charge shielding layer 510 may include boron (B)-doped Si or boron (B)-doped SiGe.

[0123] refer to Figure 6The semiconductor device according to an embodiment may include eleventh impurity regions 211 and 231 and a twenty-first impurity region 221 located between the eleventh impurity regions 211 and 231. According to an embodiment, the semiconductor device may further include a third impurity region 240 located below the eleventh impurity regions 211 and 231 and the twenty-first impurity region 221. According to an embodiment, the third impurity region 240 may include impurities of the same type as the eleventh impurity regions 211 and 231 and impurities of a different type than the twenty-first impurity region 221. For example, the eleventh impurity regions 211 and 231 and the third impurity region 240 may include n-type impurities, and the twenty-first impurity region 221 may include p-type impurities. In other words, the eleventh impurity included in the eleventh impurity regions 211 and 231 and the third impurity included in the third impurity region 240 may be n-type, and the twenty-first impurity included in the twenty-first impurity region 221 may be p-type.

[0124] According to an embodiment, the third impurity region 240 may completely cover the eleventh impurity regions 211 and 231 and the twenty-first impurity region 221. However, this is not limited to this, and may also cover at least a portion of the eleventh impurity regions 211 and 231 and / or at least a portion of the twenty-first impurity region 221.

[0125] According to an embodiment, the first charge shielding layer 510 may be located on the fourth surface 200S2 of the second substrate 200. According to an embodiment, the first charge shielding layer 510 may overlap with the twenty-first impurity region 221 in the third direction Z. In this case, the first charge shielding layer 510 may not overlap with the eleventh impurity regions 211 and 231.

[0126] According to an embodiment, the first charge shielding layer 510 may contact the fourth surface 200S2 of the second substrate 200. According to an embodiment, the first charge shielding layer 510 may cover the third impurity region 240 that overlaps with the twenty-first impurity region 221.

[0127] According to an embodiment, the first charge shielding layer 510 may include at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. For example, the first charge shielding layer 510 may include boron (B)-doped Si or boron (B)-doped SiGe.

[0128] As described above, the semiconductor device according to this disclosure can reduce leakage current by including a boron (B) doped silicon layer as a first charge shielding layer 510 to suppress the phenomenon of negative charge induced in the second substrate 200 due to positive charge induced in the first peripheral buffer layer 270.

[0129] In other words, the boron-doped silicon layer (a group 3 impurity) can suppress charge induction caused by the positive charge of the first peripheral buffer layer 270 and prevent the generation of leakage paths by forming a potential barrier on the band structure.

[0130] Furthermore, as described above, the first charge shielding layer 510 of the semiconductor device according to this disclosure can reduce the occurrence of leakage current in the second substrate 200 by suppressing the influence of the electric field induced by the fixed charge caused by the first peripheral buffer layer 270 with positive charge.

[0131] In addition, as described above, the first charge shielding layer 510 of the semiconductor device according to this disclosure can prevent the formation of unintended current paths inside the second substrate 200 by shielding the positive charge effect generated from the first peripheral buffer layer 270.

[0132] In addition, as described above, the first charge shielding layer 510 can prevent the accumulation of opposite polarity charges (electrons) induced by the fixed charge of the first peripheral buffer layer 270, thereby reducing the potential imbalance in the second substrate 200.

[0133] Figure 7 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0134] Figure 7 The semiconductor device shown may include reference Figures 1 to 6 The semiconductor device described is similar to or the same as the component described. However, with Figures 1 to 6 Unlike the semiconductor devices shown, the semiconductor device in this embodiment has a structure in which the first charge shielding layer 510 is entirely located on the second substrate 200. Here, any overlapping content from the foregoing will be briefly described or omitted, and the differences will be the main focus.

[0135] refer to Figure 7 The semiconductor device according to an embodiment may include a first peripheral buffer layer 270 located beneath a second substrate 200. According to an embodiment, the first peripheral buffer layer 270 may include a positively charged material. For example, the first peripheral buffer layer 270 may include tetraethyl orthosilicate (TEOS). However, this is not limited to this, and the first peripheral buffer layer 270 may include various positively charged materials.

[0136] According to an embodiment, the first charge shielding layer 510 may be located on the fourth surface 200S2 of the second substrate 200. According to an embodiment, the first charge shielding layer 510 may be completely located on the fourth surface 200S2 of the second substrate 200. Specifically, the first charge shielding layer 510 may be in complete contact with the fourth surface 200S2 of the second substrate 200. According to an embodiment, the first charge shielding layer 510 may cover... Figure 5The first impurity regions 210 and 230 and the second impurity region 220 are shown. According to an embodiment, the first charge shielding layer 510 can cover... Figure 6 The third impurity region 240 is formed by the overlap of the eleventh impurity regions 211 and 231 and the twenty-first impurity region 221.

[0137] According to an embodiment, the first charge shielding layer 510 may include at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. For example, the first charge shielding layer 510 may include boron (B)-doped Si or boron (B)-doped SiGe.

[0138] According to an embodiment, the semiconductor device may further include a second insulating pattern 411 located between the first charge shielding layer 510 and the through-path 400.

[0139] According to an embodiment, the second insulating pattern 411 is located between the through-path 400 and the first charge shielding layer 510 and may surround the side surface of the through-path 400 that penetrates the first charge shielding layer 510. The through-path 400 and the first charge shielding layer 510 may be insulated by the second insulating pattern 411.

[0140] According to an embodiment, the second insulating pattern 411 may have a shape that penetrates the first charge shielding layer 510. The height of the second insulating pattern 411 along the third direction Z may be the same as the thickness of the first charge shielding layer 510 along the third direction Z. In other words, the upper surface of the second insulating pattern 411 may be located at substantially the same height as the upper surface of the first charge shielding layer 510, and the lower surface of the second insulating pattern 411 may be located at substantially the same height as the lower surface of the first charge shielding layer 510.

[0141] According to an embodiment, the second insulating pattern 411 may have a shape in which the width becomes narrower from the upper surface to the lower surface of the first charge shielding layer 510. In other words, the second insulating pattern 411 may have a maximum width at the upper surface and a minimum width at the lower surface. However, this is not limited to this, and the shape of the second insulating pattern 411 may be changed in various ways.

[0142] According to an embodiment, the second insulating pattern 411 may include an insulating material. For example, the second insulating pattern 411 may include silicon oxide. However, this is not limited to this, and the material included in the second insulating pattern 411 may be varied in various ways.

[0143] Figure 8 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0144] Figure 8 The semiconductor device 10 shown may include reference Figures 1 to 7The semiconductor device described is similar to or the same as the component described. However, with Figures 1 to 7 Unlike the semiconductor device shown, the semiconductor device in this embodiment also includes a second peripheral buffer layer 280 located above the first peripheral buffer layer 270 and a second charge shielding layer 520 located between the second peripheral buffer layer 280 and the second substrate 200. Here, any overlapping content from the above will be briefly described or omitted, and the differences will be mainly explained.

[0145] According to an embodiment, the cell structure CS of the semiconductor device 10 may further include a cell buffer layer 170 located on the second cell insulating layer 150, and the peripheral circuit structure PS may include a first peripheral buffer layer 270 and a second peripheral buffer layer 280 located below the fourth surface 200S2 of the second substrate 200.

[0146] According to an embodiment, the first peripheral buffer layer 270 may include an insulating material. According to an embodiment, the first peripheral buffer layer 270 may have unique charge characteristics depending on the formation process and thermal conditions.

[0147] According to an embodiment, the first peripheral buffer layer 270 may include a positively charged material. For example, the first peripheral buffer layer 270 may include tetraethyl orthosilicate (TEOS). However, this is not limited to this, and the first peripheral buffer layer 270 may include various positively charged materials.

[0148] According to an embodiment, the second peripheral buffer layer 280 may be located between the fourth surface 200S2 of the second substrate 200 and the first peripheral buffer layer 270. One side of the second peripheral buffer layer 280 may contact the fourth surface 200S2 of the second substrate 200, and the other side of the second peripheral buffer layer 280 may contact the first peripheral buffer layer 270.

[0149] According to an embodiment, the second peripheral buffer layer 280 may include an insulating material. According to an embodiment, the second peripheral buffer layer 280 may have unique charge characteristics depending on the formation process and thermal conditions.

[0150] According to an embodiment, the second peripheral buffer layer 280 may include a material with a negative charge. This negative charge may be due to a fixed charge within the film or the nature of the bonding structure. For example, the second peripheral buffer layer 280 may include aluminum oxide (AlxOy). However, this is not limited to this, and the second peripheral buffer layer 280 may include various materials with a negative charge.

[0151] In this way, when the second peripheral buffer layer 280 is negatively charged, a positive charge can be induced in the second substrate 200, which can cause leakage current by forming an unexpected current path.

[0152] Specifically, since the second peripheral buffer layer 280 adjacent to the second substrate 200 has a negative charge, the second substrate 200 adjacent to the second peripheral buffer layer 280 can have a positive charge. This charge distribution can cause leakage current by forming unintended current paths within the second substrate 200.

[0153] The semiconductor device 10 according to the embodiment may further include a second charge shielding layer 520 located between the fourth surface 200S2 of the second substrate 200 and the second peripheral buffer layer 280.

[0154] According to an embodiment, the second charge shielding layer 520 may be located between the first substrate 100 of the cell structure CS and the second substrate 200 of the peripheral circuit structure PS. The second charge shielding layer 520 may also be located between the first surface 100S1 of the first substrate 100 and the fourth surface 200S2 of the second substrate 200. For example, the second charge shielding layer 520 may be located between the memory cell layer MSL of the cell structure CS and the fourth surface 200S2 of the second substrate 200 of the peripheral circuit structure PS.

[0155] According to an embodiment, the second charge shielding layer 520 may be located in the peripheral circuit structure PS. The second charge shielding layer 520 may be located between the second substrate 200 and the second peripheral buffer layer 280. Alternatively, the second charge shielding layer 520 may be described as being located within the second peripheral buffer layer 280.

[0156] According to an embodiment, the second charge shielding layer 520 covers at least a portion of the fourth surface 200S2 of the second substrate 200 and may be in contact with the fourth surface 200S2 of the second substrate 200. However, this is not limited to this, and an additional layer may be positioned between the fourth surface 200S2 of the second substrate 200 and the second charge shielding layer 520, and between the second peripheral buffer layer 280 and the second charge shielding layer 520.

[0157] In this embodiment, the thickness of the second charge shielding layer 520 may be thinner than the thickness of the unit buffer layer 170, the thickness of the second substrate 200, and the thickness of the second peripheral buffer layer 280. However, this is just an example, and the position and / or thickness of the second charge shielding layer 520 may be varied in various ways.

[0158] According to an embodiment, the second charge shielding layer 520 may include at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. Reference will be made later. Figure 9 and Figure 10 The specific details related to the second charge shielding layer 520 are described in detail.

[0159] In the following text, reference will be made to Figure 9 and Figure 10Semiconductor devices according to various embodiments are described. In the following embodiments, the same components as those previously described are indicated by the same reference numerals, and redundant descriptions may be omitted or simplified.

[0160] Figure 9 and Figure 10 According to some embodiments Figure 8 A magnified view of region N.

[0161] refer to Figure 9 The second substrate 200 may include fourth impurity regions 310 and 330 and a fifth impurity region 320 located between the fourth impurity regions 310 and 330. In other words, the fourth impurity regions 310 and 330 may be located on both sides of the fifth impurity region 320.

[0162] According to an embodiment, the fourth impurity regions 310 and 330 and the fifth impurity region 320 may include different impurities. For example, the fourth impurity may be p-type and the fifth impurity may be n-type. In other words, the fourth impurity regions 310 and 330 may be regions doped with p-type impurities, and the fifth impurity region 320 may be a region doped with n-type impurities. The fourth impurity regions 310 and 330 may include B, V, In, Ga, Al, or combinations thereof. The fifth impurity region 320 may include P, Sb, As, or combinations thereof.

[0163] According to an embodiment, the second peripheral buffer layer 280 located below the second substrate 200 may include a material with a negative charge. For example, the second peripheral buffer layer 280 may include aluminum oxide (AlxOy). However, this is not limited to this, and the second peripheral buffer layer 280 may include various materials with a negative charge.

[0164] According to an embodiment, when the second peripheral buffer layer 280 comes into contact with the second substrate 200, if the second peripheral buffer layer 280 becomes negatively charged, a positive charge can be induced in the second substrate 200 in response to this.

[0165] Specifically, since the second peripheral buffer layer 280 adjacent to the second substrate 200 has a negative charge, the region of the second substrate 200 adjacent to the second peripheral buffer layer 280 can have a positive charge. This charge distribution can cause leakage current by forming unintended current paths within the second substrate 200.

[0166] The semiconductor device 10 according to an embodiment may include a second charge shielding layer 520 to suppress the phenomenon of positive charge being induced in the second substrate 200 due to negative charge induced in the second peripheral buffer layer 280.

[0167] According to an embodiment, the second charge shielding layer 520 may be located on the fourth surface 200S2 of the second substrate 200. According to an embodiment, the second charge shielding layer 520 may overlap with the fifth impurity region 320 in the third direction Z. In this case, the second charge shielding layer 520 may not overlap with the fourth impurity regions 310 and 330 in the third direction Z. However, the second charge shielding layer 520 is not necessarily not required to avoid overlapping with the fourth impurity regions 310 and 330 in the third direction Z, and the second charge shielding layer 520 may overlap with at least a portion of the fourth impurity regions 310 and 330 in the third direction Z.

[0168] According to an embodiment, the second charge shielding layer 520 may be in contact with the fourth surface 200S2 of the second substrate 200. According to an embodiment, the second charge shielding layer 520 may cover the fifth impurity region 320 located between the fourth impurity regions 310 and 330. For example, the second charge shielding layer 520 may only cover the fifth impurity region 320, or it may cover a portion of the region adjacent to the fifth impurity region 320.

[0169] According to an embodiment, the second charge shielding layer 520 may include at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. According to an embodiment, the second charge shielding layer 520 may include n-type impurities. For example, the second charge shielding layer 520 may include phosphorus (P)-doped Si, phosphorus (P)-doped SiGe, arsenic (As)-doped Si, or arsenic (As)-doped SiGe.

[0170] refer to Figure 10 The semiconductor device according to an embodiment may include a forty-first impurity region 311 and 331 and a fifty-first impurity region 321 located between the forty-first impurity regions 311 and 331. According to an embodiment, the semiconductor device may also include a sixth impurity region 340 located below the forty-first impurity regions 311 and 331 and the fifty-first impurity region 321. According to an embodiment, the sixth impurity region 340 may include impurities of the same type as the forty-first impurity regions 311 and 331 and may include impurities of a different type than the fifty-first impurity region 321. For example, the forty-first impurity regions 311 and 331 and the sixth impurity region 340 may include p-type impurities, and the fifty-first impurity region 321 may include n-type impurities. In other words, the forty-first impurity included in the forty-first impurity regions 311 and 331 and the sixth impurity included in the sixth impurity region 340 may be p-type, and the fifty-first impurity included in the fifty-first impurity region 321 may be n-type.

[0171] According to an embodiment, the sixth impurity region 340 can completely cover the forty-first impurity regions 311 and 331 and the fifty-first impurity region 321. However, this is not limited to this, and it can also cover at least a portion of the forty-first impurity regions 311 and 331 and / or at least a portion of the fifty-first impurity region 321.

[0172] According to an embodiment, the second charge shielding layer 520 may be located on the fourth surface 200S2 of the second substrate 200. According to an embodiment, the second charge shielding layer 520 may overlap with the fifty-first impurity region 321 in the third direction Z. In this case, the second charge shielding layer 520 may not overlap with the forty-first impurity regions 311 and 331.

[0173] According to an embodiment, the second charge shielding layer 520 may contact the fourth surface 200S2 of the second substrate 200. In another embodiment, the second charge shielding layer 520 may cover the sixth impurity region 340 that overlaps with the fifty-first impurity region 321.

[0174] According to an embodiment, the second charge shielding layer 520 may include at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. For example, the second charge shielding layer 520 may include phosphorus (P)-doped Si, phosphorus (P)-doped SiGe, arsenic (As)-doped Si, or arsenic (As)-doped SiGe.

[0175] As described above, the semiconductor device according to this disclosure can reduce leakage current by including a silicon layer doped with phosphorus or arsenic (As) as a second charge shielding layer 520 to suppress the phenomenon of positive charge induced in the second substrate 200 due to negative charge induced in the second peripheral buffer layer 280.

[0176] In other words, a silicon layer doped with phosphorus or arsenic (which are group 5 impurities) can suppress the inflow of holes induced by the negative charge of the second peripheral buffer layer 280 and prevent the generation of leakage paths by forming a barrier on the band structure.

[0177] Furthermore, as described above, the second charge shielding layer 520 of the semiconductor device according to this disclosure can reduce the occurrence of leakage current in the second substrate 200 by suppressing the influence of the electric field induced by the fixed charge caused by the negatively charged second peripheral buffer layer 280.

[0178] In addition, as described above, the second charge shielding layer 520 of the semiconductor device according to this disclosure can prevent the formation of unintended current paths inside the second substrate 200 by shielding the influence of negative charges generated from the second peripheral buffer layer 280.

[0179] In addition, as described above, the second charge shielding layer 520 can prevent the accumulation of opposite polarity charges (holes) induced by the fixed charge of the second peripheral buffer layer 280, thereby reducing the potential imbalance in the second substrate 200.

[0180] Figure 11 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0181] Figure 11 The semiconductor device shown may include reference Figures 8 to 10 The semiconductor device described is similar to or the same as the component described. However, with Figures 8 to 10 Unlike the semiconductor devices shown, the semiconductor device in this embodiment has a structure in which the second charge shielding layer 520 is entirely located on the second substrate 200. Here, any overlapping content from the foregoing will be briefly described or omitted, and the differences will be the main focus.

[0182] refer to Figure 11 The semiconductor device according to an embodiment may include a second peripheral buffer layer 280 located beneath a second substrate 200. According to an embodiment, the second peripheral buffer layer 280 may include a material having a negative charge. For example, the second peripheral buffer layer 280 may include aluminum oxide (AlxOy). However, this is not limited to this, and the second peripheral buffer layer 280 may include various materials having a negative charge.

[0183] According to an embodiment, the second charge shielding layer 520 may be located on the fourth surface 200S2 of the second substrate 200. According to an embodiment, the second charge shielding layer 520 may be completely located on the fourth surface 200S2 of the second substrate 200. Specifically, the second charge shielding layer 520 may be in complete contact with the fourth surface 200S2 of the second substrate 200. According to an embodiment, the second charge shielding layer 520 may cover... Figure 9 The fourth impurity regions 310 and 330 and the fifth impurity region 320 are shown. According to an embodiment, the second charge shielding layer 520 can cover... Figure 10 The sixth impurity region 340 is the overlap of the forty-first impurity regions 311 and 331 and the fifty-first impurity region 321 shown.

[0184] According to an embodiment, the second charge shielding layer 520 may include at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. For example, the second charge shielding layer 520 may include phosphorus (P)-doped Si, phosphorus (P)-doped SiGe, arsenic (As)-doped Si, or arsenic (As)-doped SiGe.

[0185] According to an embodiment, the semiconductor device may further include a second insulating pattern 411 located between the second charge shielding layer 520 and the through-path 400.

[0186] According to an embodiment, the second insulating pattern 411 is located between the through-path 400 and the second charge shielding layer 520 and may surround the side surface of the through-path 400 that penetrates the second charge shielding layer 520. The through-path 400 and the second charge shielding layer 520 may be insulated by the second insulating pattern 411.

[0187] According to an embodiment, the second insulating pattern 411 may have a shape that penetrates the second charge shielding layer 520. The height of the second insulating pattern 411 along the third direction Z may be the same as the thickness of the second charge shielding layer 520 along the third direction Z. In other words, the upper surface of the second insulating pattern 411 may be located at substantially the same height as the upper surface of the second charge shielding layer 520, and the lower surface of the second insulating pattern 411 may be located at substantially the same height as the lower surface of the second charge shielding layer 520.

[0188] According to an embodiment, the second insulating pattern 411 may have a shape in which the width becomes narrower from the upper surface to the lower surface of the second charge shielding layer 520. In other words, the second insulating pattern 411 may have a maximum width at the upper surface and a minimum width at the lower surface. However, this is not limited to this, and the shape of the second insulating pattern 411 may be changed in various ways.

[0189] According to an embodiment, the second insulating pattern 411 may include an insulating material. For example, the second insulating pattern 411 may include silicon oxide. However, this is not limited to this, and the material included in the second insulating pattern 411 may be varied in various ways.

[0190] In the following text, reference will be made to Figures 12 to 18 Description for manufacturing Figure 4 Methods for developing semiconductor devices.

[0191] Figures 12 to 18 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to an embodiment.

[0192] refer to Figure 12 This can form a unit structure CS.

[0193] According to an embodiment, a memory cell layer MSL can be stacked on a first surface 100S1 of a first substrate 100 to form a cell structure CS. The memory cell layer MSL may include a plurality of memory cells MC and bit lines connected to the plurality of memory cells MC (e.g., Figure 3 The bit line BL and word line WL, and contacts (e.g., bit line contact (not shown) and word line contact WLC) connecting the bit line BL and word line WL to the first unit wiring layer 141. It can be assumed that... Figure 12 The storage unit layer MSL includes multiple storage units MC and Figure 2 and Figure 4 In the embodiments, multiple storage units (MCs) are identical. Therefore, the above reference... Figure 2 and Figure 4 The description can be applied equally to multiple memory cells (MCs).

[0194] According to an embodiment, a first cell wiring layer 141 and a second cell wiring layer 143 can be formed on a memory cell layer MSL. For example, a metal layer can be formed on the memory cell layer MSL, and the metal layer can be patterned to form the first cell wiring layer 141 and the second cell wiring layer 143. An insulating material layer can be formed covering the first cell wiring layer 141 and the second cell wiring layer 143, and a first cell path 142 connected to the first cell wiring layer 141 can be formed by penetrating the insulating material layer in a third direction Z perpendicular to the first surface 100S1 of the first substrate 100. Through the process described above, a first cell wiring layer 141 and a second cell wiring layer 143 including multiple wiring layers, a first cell path 142 connecting the multiple wiring layers in a third direction Z, and a second cell insulating layer 150 surrounding the first cell wiring layer 141, the second cell wiring layer 143, and the first cell path 142 can be formed.

[0195] According to an embodiment, a unit buffer layer 170 may be formed covering the second unit insulating layer 150. According to an embodiment, the unit buffer layer 170 may include an insulating material. For example, the insulating material may include, but is not limited to, silicon oxide, and may vary in various ways.

[0196] refer to Figure 13 A peripheral circuit PC can be formed on the third surface 200S1 of the second substrate 200. The peripheral circuit PC is a circuit that performs logic operations and can be composed of a combination of circuit elements such as transistors.

[0197] In an embodiment, the peripheral circuit PC may include circuitry for controlling multiple memory cells. For example, the peripheral circuit PC may include, but is not limited to, a row decoder for selecting rows of the memory cell array based on address signals, a column decoder for selecting columns of the memory cell array based on address signals, a readout amplifier for sensing and amplifying data in the memory cells, and a word line driver for activating the word line of the selected row.

[0198] In an embodiment, the peripheral circuit PC may include at least one of an arithmetic circuit that performs arithmetic using data stored in multiple memory cells and a buffer that temporarily stores the data used in the arithmetic circuit. For example, the computing circuit may be an NPU, and the buffer may be a cache memory of the NPU, but is not limited thereto.

[0199] According to an embodiment, a first insulating pattern 410 may be formed inside the second substrate 200. For example, a recessed trench may be formed from the third surface 200S1 of the second substrate 200 toward the fourth surface 200S2, and the trench may be filled with an insulating material to form the first insulating pattern 410.

[0200] According to an embodiment, the first insulating pattern 410 may have a shape in which the width becomes narrower from the third surface 200S1 of the second substrate 200 towards the fourth surface 200S2. The first insulating pattern 410 may include a side located at substantially the same height as the third surface 200S1 of the second substrate 200 and another side facing that side. The surface of the other side may be located at a height between the third surface 200S1 and the fourth surface 200S2 of the second substrate 200.

[0201] According to an embodiment, an isolation pattern 412 can be formed inside the second substrate 200. For example, a recessed trench can be formed from the third surface 200S1 of the second substrate 200 toward the fourth surface 200S2, and the trench can be filled with an insulating material to form the isolation pattern 412.

[0202] According to an embodiment, the isolation pattern 412 may have a shape in which the width narrows from the third surface 200S1 of the second substrate 200 towards the fourth surface 200S2. The isolation pattern 412 may include one side located at substantially the same height as the third surface 200S1 of the second substrate 200 and another side facing that side. The surface of the other side may be located at a height between the third surface 200S1 and the fourth surface 200S2 of the second substrate 200.

[0203] refer to Figure 14 A wafer thinning process can be performed on the fourth surface 200S2 of the second substrate 200 to reduce the thickness of the second substrate 200. A first insulating pattern 410 located inside the second substrate 200 can be used as a stop layer to perform the wafer thinning process. The wafer thinning process can be terminated when the first insulating pattern 410 is exposed.

[0204] According to an embodiment, through a wafer thinning process, the fourth surface 200S2 of the second substrate 200 can be located at substantially the same height as one side of the first insulating pattern 410. One side of the first insulating pattern 410 can be located at substantially the same height as the third surface 200S1 of the second substrate 200, and the other side facing that side can be located at substantially the same height as the fourth surface 200S2 of the second substrate 200. The first insulating pattern 410 can penetrate the second substrate 200 in a third direction Z perpendicular to the third surface 200S1 and the fourth surface 200S2 of the second substrate 200.

[0205] refer to Figure 15A first charge shielding layer 510 can be formed on the fourth surface 200S2 of the second substrate 200.

[0206] According to an embodiment, a mask pattern can be formed on a fourth surface 200S2 of the second substrate 200, excluding the area where the first charge shielding layer 510 is to be formed.

[0207] Next, a first charge shielding layer 510 can be formed on the area where the mask pattern is not formed. For example, to form the first charge shielding layer 510, a low-pressure chemical vapor deposition (LPCVD), chemical vapor deposition (CVD), or selective epitaxial growth (SEG) process can be performed using raw materials including elemental semiconductor precursors. The aforementioned elemental semiconductor precursors may include elements such as Si, Ge, etc.

[0208] According to embodiments, an impurity activation process can be performed on the first charge shielding layer 510. As the impurity activation process is performed, impurities in the first charge shielding layer 510 can be activated. According to some embodiments, the impurity activation process may include a laser annealing process. For example, the laser annealing process may include nanosecond laser annealing, microsecond laser annealing, or millisecond laser annealing.

[0209] In the method for manufacturing a semiconductor device according to this disclosure, by applying a laser annealing process for activating impurities, energy can be locally irradiated onto the doped region to selectively heat the doped region, thereby minimizing stress due to heat. Therefore, debonding defects that may occur at the bonding surface between the thin film and the substrate can be effectively prevented. Furthermore, high-efficiency impurity activation can be achieved while maintaining the thermal stability of the first charge shielding layer 510, thereby contributing to improved device reliability and manufacturing yield.

[0210] In an embodiment, as the impurity activation process is performed, the first charge shielding layer 510 may include boron (B) doped Si or boron (B) doped SiGe.

[0211] In addition, in manufacturing Figures 8 to 11 In the manufacturing method of semiconductor devices, as the impurity activation process is performed, a second charge shielding layer can be formed, including phosphorus (P)-doped Si, phosphorus (P)-doped SiGe, arsenic (As)-doped Si, or arsenic (As)-doped SiGe (e.g., Figures 8 to 11 The second charge shielding layer 520).

[0212] refer to Figure 16 A first peripheral buffer layer 270 can be formed to cover the second substrate 200 and the first charge shielding layer 510. For example, the first peripheral buffer layer 270 can be formed to cover the fourth surface 200S2 of the second substrate 200 and the first charge shielding layer 510.

[0213] According to an embodiment, the first peripheral buffer layer 270 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes.

[0214] According to an embodiment, the first peripheral buffer layer 270 may include an insulating material. According to an embodiment, the first peripheral buffer layer 270 may have unique charge characteristics depending on the formation process and thermal conditions.

[0215] According to an embodiment, the first peripheral buffer layer 270 may include a positively charged material. For example, the first peripheral buffer layer 270 may include tetraethyl orthosilicate (TEOS). However, this is not limited to this, and the first peripheral buffer layer 270 may include various positively charged materials.

[0216] refer to Figure 17 The first peripheral buffer layer 270 can be adhered to the unit structure CS.

[0217] According to an embodiment, a first bonding layer 175 may be formed on the unit buffer layer 170. Figure 17 In the diagram, the first bonding layer 175 is shown to cover the entire unit buffer layer 170, but unlike what is shown, the position and / or shape of the first bonding layer 175 may be changed.

[0218] According to an embodiment, a second bonding layer 275 may be formed below the first peripheral buffer layer 270. Figure 17 In the diagram, the second bonding layer 275 is shown to cover the entire first peripheral buffer layer 270, but unlike what is shown, the position and / or shape of the second bonding layer 275 may vary.

[0219] According to an embodiment, a bonding process can be performed to adhere the first peripheral buffer layer 270 to the unit structure CS. For example, the first bonding layer 175 and the second bonding layer 275 can be aligned in a third direction Z. The first bonding layer 175 and the second bonding layer 275 can then be bonded by applying pressure and / or heat.

[0220] refer to Figure 18 A first peripheral wiring layer 241 can be formed on the peripheral circuit PC.

[0221] According to an embodiment, an insulating material layer can be formed to cover the second substrate 200, the first insulating pattern 410, and the peripheral circuit PC, and a first peripheral passage 242 can be formed to penetrate the insulating material layer in a third direction Z perpendicular to the third surface 200S1 of the second substrate 200. The first peripheral passage 242 may include contacts connecting the first peripheral wiring layer 241 and the circuit elements constituting the peripheral circuit PC. A metal layer can be formed to cover the insulating material layer and the contacts, and the metal layer can be patterned to form the first peripheral wiring layer 241. Through the process described above, the first peripheral wiring layer 241 and the second peripheral wiring layer 243, the first peripheral passage 242, the second peripheral passage 244, and the third peripheral passage 246 connecting multiple wiring layers in the third direction Z, and a first peripheral insulating layer 230 surrounding the first peripheral wiring layer 241 and the second peripheral wiring layer 243, as well as the first peripheral passage 242, the second peripheral passage 244, and the third peripheral passage 246 can be formed.

[0222] In this embodiment, the through passage 400 can be formed simultaneously with the formation of the first peripheral passage 242, the second peripheral passage 244, and the third peripheral passage 246. For example, the processes for forming the through passage 400 and the second peripheral passage 244 can be performed sequentially, and the order can be changed in various ways. However, this is not limited to the above, and the through passage 400 and the second peripheral passage 244 can be formed together.

[0223] According to an embodiment, a first trench can be formed to form a through passage 400. For example, a seed metal layer can be deposited covering the inner wall and bottom surface of the first trench, and an electroplating process can be performed to fill the interior of the first trench with a metallic material to form the through passage 400. However, the method of forming the through passage 400 is not limited to this, and the through passage 400 can be formed in various ways.

[0224] exist Figure 18 In the diagram, the through path 400 is shown as connecting to a second peripheral wiring layer 243 and a second unit wiring layer 143 among a plurality of wiring layers, but is not limited thereto. The through path 400 is sufficient to connect to any of the plurality of wiring layers included in the peripheral circuit structure PS and any of the plurality of wiring layers included in the unit structure CS.

[0225] Next, a second peripheral insulation layer 250 covering the first peripheral insulation layer 230 and a third peripheral wiring layer 260 located within the second peripheral insulation layer 250 can be formed.

[0226] Although embodiments of the invention have been described in detail above, the scope of the invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the invention as defined in the appended claims also fall within the scope of the invention.

Claims

1. A semiconductor device, the semiconductor device comprising: An external circuit structure includes a substrate, an external circuit, and a first external buffer layer. The substrate has a first surface and a second surface facing each other. The substrate includes a first impurity region and a second impurity region located between the first impurity regions. The external circuit is located on the first surface of the substrate, and the first external buffer layer is located on the second surface of the substrate. The unit structure overlaps with the peripheral circuit structure; as well as A charge shielding layer is located between the substrate and the first peripheral buffer layer. The unit structure includes: Multiple memory cells, each including a storage transistor and a capacitor; and Word lines and bit lines are connected to the memory transistor.

2. The semiconductor device according to claim 1, wherein, The charge shielding layer is located between the second surface of the substrate and the unit structure.

3. The semiconductor device according to claim 1, wherein, The charge shielding layer overlaps with the second impurity region.

4. The semiconductor device according to claim 1, wherein, The charge shielding layer is located entirely on the second surface of the substrate.

5. The semiconductor device according to claim 1, wherein, The charge shielding layer includes monocrystalline silicon, polycrystalline silicon, or amorphous silicon.

6. The semiconductor device according to claim 1, wherein, The first impurity region includes a first impurity, the second impurity region includes a second impurity, the first impurity is n-type, the second impurity is p-type, the first peripheral buffer layer has a positive charge, and the charge shielding layer includes p-type impurities.

7. The semiconductor device according to claim 6, wherein, The charge shielding layer comprises B-doped Si or B-doped SiGe.

8. The semiconductor device of claim 7, further comprising a third impurity region located below the first impurity region and the second impurity region. in, The third impurity region includes a third impurity, which is of type n, and the charge shielding layer covers the third impurity region.

9. The semiconductor device of claim 1, further comprising a second peripheral buffer layer located between the first peripheral buffer layer and the second surface of the substrate. in, The first impurity region includes a first impurity, the second impurity region includes a second impurity, the first impurity is p-type, the second impurity is n-type, the second peripheral buffer layer has a negative charge, and the charge shielding layer includes n-type impurities.

10. The semiconductor device according to claim 9, wherein, The charge shielding layer includes P-doped Si, P-doped SiGe, As-doped Si, or As-doped SiGe.

11. The semiconductor device of claim 10, further comprising a third impurity region located below the first impurity region and the second impurity region. in, The third impurity region includes a third impurity, which is p-type, and the charge shielding layer covers the third impurity region.

12. A semiconductor device, the semiconductor device comprising: A first substrate and a cell structure, the cell structure being located on the first substrate and including a plurality of memory cells; The peripheral circuit structure includes: a second substrate having a first impurity region and a second impurity region located between the first impurity region; a peripheral circuit located on the second substrate; and a first peripheral buffer layer located below the second substrate, wherein the peripheral circuit structure overlaps with the unit structure; and A charge shielding layer is located between the first substrate and the second substrate. The unit structure includes: A gate stack structure in which multiple word lines and multiple interlayer insulating layers are alternately stacked; Multiple channel patterns are arranged at intervals along a direction perpendicular to the first substrate; Bit lines, which extend in a direction perpendicular to the first substrate and connect to one end of a corresponding channel pattern; and A capacitor, which is connected to the other end of the corresponding channel pattern.

13. The semiconductor device according to claim 12, wherein, The second substrate includes a first surface and a second surface opposite to the first surface, wherein the peripheral circuit is located on the first surface, and the charge shielding layer is located between the second surface of the second substrate and the unit structure.

14. The semiconductor device according to claim 12, wherein, The charge shielding layer overlaps with the second impurity region.

15. The semiconductor device according to claim 12, wherein, The charge shielding layer is located entirely on the second substrate.

16. The semiconductor device according to claim 12, wherein, The first impurity region includes a first impurity, the second impurity region includes a second impurity, the first impurity is n-type, the second impurity is p-type, the first peripheral buffer layer has a positive charge, and the charge shielding layer includes p-type impurities.

17. The semiconductor device according to claim 16, wherein, The charge shielding layer comprises B-doped Si or B-doped SiGe.

18. The semiconductor device of claim 12, further comprising a second peripheral buffer layer located between the first peripheral buffer layer and the second substrate, wherein, The first impurity region includes a first impurity, the second impurity region includes a second impurity, the first impurity is p-type, the second impurity is n-type, the second peripheral buffer layer has a negative charge, and the charge shielding layer includes n-type impurities.

19. The semiconductor device according to claim 18, wherein, The charge shielding layer includes P-doped Si, P-doped SiGe, As-doped Si, or As-doped SiGe.

20. A semiconductor device, the semiconductor device comprising: A first substrate and a cell structure, the cell structure being located on the first substrate and comprising a plurality of memory cells; A peripheral circuit structure is located on the unit structure and includes: a second substrate having a first impurity region and a second impurity region located between the first impurity region, a peripheral circuit located on the second substrate, and a peripheral buffer layer located below the second substrate; as well as A charge shielding layer that covers the bottom surface of the second impurity region located in the second substrate.

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