Semiconductor device

Abstract

A semiconductor device includes a peripheral circuit region and a cell array region arranged on the peripheral circuit region, wherein the cell array region includes: bit lines extending in a first horizontal direction; active patterns extending in a vertical direction on the bit lines and each including a first sidewall and a second sidewall opposite to the first sidewall; and word lines extending in a second horizontal direction on the bit lines and including a first conductive layer arranged on the first sidewall of each of the active patterns and extending in the second horizontal direction, and a second conductive layer including a first portion arranged on the second sidewall of each of the active patterns and including a second portion arranged on a sidewall of the first conductive layer; and cell capacitors arranged on the active patterns, respectively.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0045623, filed on April 8, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device including a vertical channel transistor. Background Technology

[0003] As the size of semiconductor devices shrinks, the size of DRAM devices has also decreased. In a DRAM device with a 1T-1C structure where one capacitor is connected to a transistor, the leakage current through the channel region can become increasingly larger as the DRAM device becomes smaller. To reduce leakage current, vertical channel transistors that include a channel region extending in a vertical direction have been proposed. Summary of the Invention

[0004] The present invention proposes a semiconductor device with superior electrical performance.

[0005] According to various aspects of the present invention, a semiconductor device is provided, comprising: a peripheral circuit region and a cell array region disposed on the peripheral circuit region, wherein the cell array region includes: a plurality of bit lines extending in a first horizontal direction; a plurality of active patterns extending in a vertical direction on the plurality of bit lines, each including a first sidewall and a second sidewall opposite to the first sidewall; word lines extending in a second horizontal direction intersecting the first horizontal direction on the plurality of bit lines, and including a first conductive layer and a second conductive layer, the first conductive layer being disposed on a first sidewall of each of the plurality of active patterns and extending in the second horizontal direction, the second conductive layer including a first portion disposed on a second sidewall of each of the plurality of active patterns and including a second portion disposed on a sidewall of the first conductive layer; and a plurality of cell capacitors disposed on the plurality of active patterns.

[0006] According to various aspects of the present invention, a semiconductor device is provided, comprising: a plurality of bit lines disposed on a substrate and extending in a first horizontal direction; a plurality of active patterns extending in a vertical direction on the plurality of bit lines, each including a first sidewall and a second sidewall opposite to each other, and a third sidewall and a fourth sidewall opposite to each other; word lines extending on the plurality of bit lines in a second horizontal direction intersecting the first horizontal direction, and including a first conductive layer and a second conductive layer, the first conductive layer being disposed on a first sidewall of each of the plurality of active patterns and extending in the second horizontal direction, the second conductive layer including a first portion disposed on a second sidewall, a third sidewall, and a fourth sidewall of each of the plurality of active patterns and extending in the second horizontal direction; and a unit capacitor disposed on each of the plurality of active patterns.

[0007] According to various aspects of the present invention, a semiconductor device is provided, comprising: a peripheral circuit region and a cell array region disposed on the peripheral circuit region, wherein the cell array region includes: a plurality of bit lines extending in a first horizontal direction; a plurality of active patterns extending in a vertical direction on the plurality of bit lines, each including a first sidewall and a second sidewall opposite to the first sidewall; word lines extending in a second horizontal direction intersecting the first horizontal direction on the plurality of bit lines, and including a first conductive layer and a second conductive layer, the first conductive layer being disposed on the first sidewall of each of the plurality of active patterns and extending in the second horizontal direction, the second... The conductive layer includes a first portion disposed on a second sidewall of each of the plurality of active patterns and a second portion disposed on a sidewall of a first conductive layer, the second conductive layer extending in a second horizontal direction; a plurality of gate insulating layer structures disposed between word lines and each of the plurality of active patterns, and including a first gate insulating layer and a second gate insulating layer, the first gate insulating layer being disposed between a first sidewall of each of the plurality of active patterns and the first conductive layer, the second gate insulating layer being disposed between a second sidewall of each of the plurality of active patterns and a first portion of the second conductive layer; and a plurality of unit capacitors, respectively disposed on the plurality of active patterns.

[0008] According to various aspects of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a plurality of bit lines extending in a first horizontal direction on a substrate; forming a first conductive layer extending in a second horizontal direction on the plurality of bit lines; forming a plurality of active patterns extending in a vertical direction and spaced apart from each other in the second horizontal direction on the sidewalls of the first conductive layer, each of the plurality of active patterns including a first sidewall facing the sidewall of the first conductive layer and a second sidewall opposite to the first sidewall; forming a second conductive layer on the sidewall of the first conductive layer and the second sidewall of each of the plurality of active patterns; and forming a plurality of unit capacitors on the plurality of active patterns respectively.

[0009] In some embodiments, the second conductive layer may include a first portion disposed on a second sidewall of each of a plurality of active patterns and a second portion disposed on a sidewall of the first conductive layer.

[0010] In some embodiments, the method may further include: forming a first gate insulating layer between a sidewall of a first conductive layer and a first sidewall of each of a plurality of active patterns; and forming a second gate insulating layer between a first portion of a second conductive layer and a second sidewall of each of a plurality of active patterns.

[0011] In some embodiments, each of the plurality of active patterns may further include a third sidewall connected to the first sidewall and the second sidewall and a fourth sidewall connected to the first sidewall and the second sidewall and opposite to the third sidewall, and forming the second gate insulating layer may include forming the second gate insulating layer on the second sidewall, the third sidewall and the fourth sidewall of each of the plurality of active patterns.

[0012] In some embodiments, the second gate insulating layer may contact the first gate insulating layer, and in a plan view, the first gate insulating layer and the second gate insulating layer may together surround each of a plurality of active patterns.

[0013] In some embodiments, a plurality of active patterns may extend in a vertical direction and each may include a vertically extending portion having a first sidewall and a second sidewall and a horizontally extending portion connected to the bottom of the vertically extending portion and extending in a first horizontal direction. A first gate insulating layer may be disposed between the first sidewall of the vertically extending portion and a first conductive layer, and a second gate insulating layer may be disposed between the second sidewall of the vertically extending portion and a first portion of the second conductive layer and may extend to the top surface of the horizontally extending portion.

[0014] In some embodiments, the first conductive layer may have a first thickness in a first horizontal direction, the second conductive layer may have a second thickness in the first horizontal direction, and the second thickness may be less than the first thickness.

[0015] In some embodiments, the method may further include: forming a lower molding layer extending in a second horizontal direction on a plurality of bit lines and having a top surface in contact with the bottom surface of the first conductive layer; and forming an upper molding layer disposed on the top surface of the first conductive layer and extending in the second horizontal direction.

[0016] In some embodiments, each of the plurality of active patterns may include: a vertical extension disposed on the sidewall of the lower molding layer, the sidewall of the first conductive layer, and the sidewall of the upper molding layer; and a horizontal extension connected to the bottom of the vertical extension, extending in a first horizontal direction, and disposed on a plurality of bit lines.

[0017] In some embodiments, the method may further include forming a first gate insulating layer between a vertically extending portion of each of the plurality of active patterns and a sidewall of a lower molding layer, a sidewall of a first conductive layer, and a sidewall of an upper molding layer. Attached Figure Description

[0018] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic diagram illustrating a semiconductor device according to some embodiments; Figure 2 It is shown schematically. Figure 1 A perspective view of the partial structure; Figure 3 yes Figure 1 Layout diagram of Part II; Figure 4 It is along Figure 3 A sectional view taken by line A1-A1'; Figure 5 It is along Figure 3 A sectional view taken by line A2-A2'; Figure 6 It is along Figure 3 A sectional view taken by line A3-A3'; Figure 7 yes Figure 4 A magnified view of part of EN1; Figure 8 Is Figure 7 Plan view at the first vertical horizontal position; Figure 9 and Figure 10 This is a cross-sectional view showing a semiconductor device according to some embodiments; Figure 11 yes Figure 9 A magnified view of part of EN1; Figure 12 and Figure 13 This is a cross-sectional view showing a semiconductor device according to some embodiments; Figure 14 yes Figure 12 A magnified view of part of EN1; Figure 15 This is a cross-sectional view showing a semiconductor device according to some embodiments; Figure 16 This is a plan view illustrating a semiconductor device according to some embodiments; Figures 17 to 33 This is a schematic diagram illustrating a method of manufacturing a semiconductor device according to some embodiments; Figure 18A , Figure 19A , Figure 20 , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 31 , Figure 32 and Figure 33 It is along Figure 3 A sectional view taken by line A1-A1'; Figure 26B and Figure 27B It is along Figure 3 A sectional view taken by line A2-A2'; Figure 17 , Figure 18B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 29B and Figure 30 It is along Figure 3 A sectional view taken by line A3-A3'; and Figure 19B , Figure 21B , Figure 23C , Figure 24C , Figure 25C and Figure 28B Each is Figure 19A Plan view of the first vertical horizontal position. Detailed Implementation

[0019] Figure 1 This is a schematic diagram illustrating a semiconductor device 100 according to some embodiments. Figure 2 It is shown schematically. Figure 1 A perspective view of a partial structure. Figure 3 yes Figure 1 The layout diagram of Part II. Figure 4 It is along Figure 3 The sectional view taken by line A1-A1'. Figure 5 It is along Figure 3 The sectional view taken by line A2-A2'. Figure 6 It is along Figure 3 The sectional view taken by line A3-A3'. Figure 7 yes Figure 4 A magnified view of part of EN1. Figure 8 Is Figure 7 Plan view at the first vertical horizontal LV1.

[0020] Reference Figures 1 to 8 The semiconductor device 100 may include a cell array region MCA and a peripheral circuit region PCA arranged at different vertical horizontal positions. The peripheral circuit region PCA and the cell array region MCA may overlap each other in the vertical direction. For example, as Figure 1As shown, the cell array region MCA may be arranged on the peripheral circuit region PCA, and the semiconductor device 100 may have a cell-on-periphery (COP) structure. An interface region IA may be arranged on at least one side of the cell array region MCA. In some embodiments, in a plan view, the cell array region MCA may be surrounded by the interface region IA.

[0021] In some embodiments, the cell array region MCA may be a memory cell region of a DRAM device, and the peripheral circuit region PCA may be a core region or a peripheral circuit region of the DRAM device. For example, the peripheral circuit region PCA may include peripheral circuit transistors PTRs for transmitting signals and / or power to the memory cell array included in the cell array region MCA (see...). Figure 4 In some embodiments, the peripheral circuit transistor (PTR) may include various circuits such as a command decoder, control logic, address buffer, row decoder, column decoder, sense amplifier, and data input / output circuitry.

[0022] like Figure 2 and Figure 3 As shown, multiple word lines WL can extend in the cell array region MCA along the first horizontal direction X. Additionally, multiple bit lines BL can extend in the second horizontal direction Y. Multiple cell transistors CTR can be arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. Multiple cell capacitors CAP can be arranged on the multiple cell transistors CTR respectively.

[0023] Multiple word lines WL may include first word lines WL1 and second word lines WL2 alternately arranged in the second horizontal direction Y, and multiple unit transistors CTR may include first unit transistors CTR1 and second unit transistors CTR2 alternately arranged in the second horizontal direction Y. First unit transistors CTR1 may be arranged adjacent to the first word line WL1, and second unit transistors CTR2 may be arranged adjacent to the second word line WL2. First unit transistors CTR1 and second unit transistors CTR2 may be mirror-symmetrical to each other. For example, first unit transistors CTR1 and second unit transistors CTR2 may be mirror-symmetrical about a center line extending in the first horizontal direction X and arranged between first unit transistors CTR1 and second unit transistors CTR2.

[0024] The interface area IA can be the region where contacts, through-holes, wiring, etc., are formed for the electrical connection between the memory cell array included in the cell array area MCA and the peripheral circuit transistors PTR included in the peripheral circuit area PCA. For example, a word line WL can extend from the cell array area MCA to the interface area IA, and a word line contact WLC can be arranged in the interface area IA and connected to the word line WL.

[0025] In some embodiments, the peripheral circuit region PCA may include a substrate 110 and a peripheral circuit transistor PTR disposed on the substrate 110.

[0026] In some embodiments, substrate 110 may include silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. An active region AC may be defined in substrate 110.

[0027] In some embodiments, the peripheral circuit transistor PTR may be disposed on the active region AC of the substrate 110. The peripheral circuit transistor PTR may include at least one of a planar transistor, a FinFET transistor, a multi-bridge channel transistor, and a buried channel array transistor. In some embodiments, the peripheral circuit transistor PTR may include a gate electrode PTG and a gate insulating layer PTI. The source region and drain region of the peripheral circuit transistor PTR may be disposed on the upper part of the substrate on both sides of the gate electrode PTG.

[0028] The peripheral circuit transistor PTR can be configured to apply a drive signal or drive voltage to at least one of the bit line BL and word line WL arranged in the cell array region MCA that is vertically overlapping with the peripheral circuit region PCA.

[0029] Peripheral circuit wiring structure 120 may be disposed on substrate 110. Peripheral circuit wiring structure 120 may include peripheral circuit wiring 122, peripheral circuit contacts 124, and peripheral circuit insulating layer 126. Peripheral circuit wiring 122 and peripheral circuit contacts 124 may be electrically connected to peripheral circuit transistor PTR and / or substrate 110, and peripheral circuit insulating layer 126 may cover peripheral circuit transistor PTR, peripheral circuit wiring 122, and peripheral circuit contacts 124 on substrate 110. Peripheral circuit insulating layer 126 may include oxide film, nitride film, low dielectric film, or combinations thereof, and may be formed as a stacked structure having multiple insulating layers.

[0030] The cell array region MCA can be arranged on the peripheral circuit wiring structure 120. In the cell array region MCA, multiple bit lines BL, multiple cell transistors CTR, and cell capacitors CAP can be arranged sequentially in the vertical direction Z. For example, multiple bit lines BL can be arranged on the peripheral circuit wiring structure 120, cell transistors CTR can be arranged on multiple bit lines BL, and cell capacitors CAP can be arranged on cell transistors CTR. In some embodiments, the bit lines BL can be arranged closer to the top surface of the substrate 110 than the cell transistors CTR or cell capacitors CAP. Therefore, the vertical distance between the bit lines BL and the peripheral circuit transistors PTR can be smaller than the vertical distance between the cell capacitors CAP and the peripheral circuit transistors PTR.

[0031] In some embodiments, multiple bit lines BL may extend in a second horizontal direction Y. The bit lines BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or combinations thereof. A first insulating layer 132 may be disposed between the multiple bit lines BL. The first insulating layer 132 may fill the space between the multiple bit lines BL and may have multiple line pattern shapes extending in the second horizontal direction Y between the multiple bit lines BL.

[0032] In some embodiments, the bit line contact BLC may be disposed between the bottom surface of the bit line BL and the peripheral circuit wiring 122. The bit line BL can be electrically connected to the peripheral circuit transistor PTR through the bit line contact BLC.

[0033] Multiple cell transistors (CTRs) can be arranged on multiple bit lines (BLs). Multiple cell transistors (CTRs) may include multiple active patterns (APs), multiple gate insulating layer structures (150s), and multiple word lines (WLs). Multiple cell transistors (CTRs) may include gate all-around (GAA) transistors.

[0034] In some embodiments, a plurality of active patterns AP may be spaced apart from each other in a first horizontal direction X and a second horizontal direction Y, and may be arranged in a matrix form. Each of the plurality of active patterns AP may include a vertical extension AP_V and a horizontal extension AP_P. The horizontal extension AP_P of each of the plurality of active patterns AP may be arranged on the top surface of the bit line BL.

[0035] In some embodiments, each of the plurality of active pattern APs may have a U-shaped vertical cross-section. For example, each of the plurality of active pattern APs may have a shape in which the bottoms of two vertical extensions AP_V are respectively connected to opposite ends of a horizontal extension AP_P disposed between them. One of the two vertical extensions AP_V may be the channel region of a first unit transistor CTR1, and the other of the two vertical extensions AP_V may be the channel region of a second unit transistor CTR2.

[0036] In some embodiments, multiple active patterned APs may include zinc tin oxide (ZnO2) x Sn y O), indium zinc oxide (In x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In x Ga ySi z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxynitride (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), magnesium aluminum zinc oxide (Mg x Al y Zn z O), zirconium indium zinc oxide (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc oxide (Al) x Sn y In z Zn a O), silicon indium zinc oxide (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of O and silicon.

[0037] like Figure 8 As shown, the vertical extension AP_V of each of the plurality of active patterns AP may include a first sidewall SW1, a second sidewall SW2, a third sidewall SW3, and a fourth sidewall SW4. The first sidewall SW1 and the second sidewall SW2 may be arranged opposite to each other and may extend in a first horizontal direction X. The third sidewall SW3 may be arranged to connect with or adjoin the first sidewall SW1 and the second sidewall SW2, and may extend in a second horizontal direction Y. The fourth sidewall SW4 may be arranged to connect with or adjoin the first sidewall SW1 and the second sidewall SW2, and may be arranged opposite to the third sidewall SW3.

[0038] In some embodiments, such as Figure 8 As shown, the third sidewall SW3 and the fourth sidewall SW4 may have flat sidewall profiles and may be arranged orthogonally to the first sidewall SW1 and the second sidewall SW2. However, in some embodiments, due to tolerances in the manufacturing process, at least one of the third sidewall SW3 and the fourth sidewall SW4 may have a circular profile and may be connected to at least one of the first sidewall SW1 and the second sidewall SW2 at an oblique angle.

[0039] A gate insulating layer structure 150 may be disposed on the sidewall of each of a plurality of active pattern APs. The gate insulating layer structure 150 may include a first gate insulating layer 152 and a second gate insulating layer 154. The first gate insulating layer 152 may be disposed on a first sidewall SW1 of the vertical extension portion AP_V of each of the plurality of active pattern APs and may extend in the vertical direction Z. The second gate insulating layer 154 may be disposed on the second sidewalls SW2, third sidewalls SW3, and fourth sidewalls SW4 of the vertical extension portion AP_V of each of the plurality of active pattern APs and may extend in the vertical direction Z. A portion of the second gate insulating layer 154 may be disposed on the horizontal extension portion AP_P of each of the plurality of active pattern APs.

[0040] The width of the first gate insulating layer 152 in the first horizontal direction X may be substantially equal to the width of the vertical extension portion AP_V of each of the plurality of active patterns AP in the first horizontal direction X. A second gate insulating layer 154 may be disposed on the second sidewall SW2, the third sidewall SW3, and the fourth sidewall SW4 of the vertical extension portion AP_V, and may contact the opposite side surface of the first gate insulating layer 152. Therefore, as Figure 8 As shown in the plan view, the first gate insulating layer 152 and the second gate insulating layer 154 can together surround the vertically extending portion AP_V.

[0041] In some embodiments, the first gate insulating layer 152 and the second gate insulating layer 154 may include at least one of silicon oxide, silicon nitride, and high-k metal oxide.

[0042] In some embodiments, the first gate insulating layer 152 and the second gate insulating layer 154 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconium titanate (PbZrTiO), strontium tantalum bismuth oxide (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0043] In some embodiments, multiple word lines WL may surround a vertical extension AP_V of each of a plurality of active patterns AP and may extend in a first horizontal direction X. Each of the vertical extensions AP_V may be surrounded by a gate insulating layer structure 150, such that the gate insulating layer structure 150 is disposed between the word line WL and each of the vertical extensions AP_V.

[0044] In some embodiments, each of the plurality of word lines WL may include a first conductive layer 162 and a second conductive layer 164.

[0045] In some embodiments, the first conductive layer 162 may have a line pattern shape extending in a first horizontal direction X. The first conductive layer 162 may have sidewalls extending straight in the first horizontal direction X. In some embodiments, the first sidewall SW1 of the vertical extension portion AP_V of each of the plurality of active patterns AP may be disposed on the sidewall of the first conductive layer 162, and the first gate insulating layer 152 may be disposed between the sidewall of the first conductive layer 162 and the first sidewall SW1 of the vertical extension portion AP_V.

[0046] In some embodiments, the second conductive layer 164 may include a first portion P1 and a second portion P2, and may extend in a first horizontal direction X. The first portion P1 of the second conductive layer 164 may be disposed on the second sidewall SW2, third sidewall SW3, and fourth sidewall SW4 of the vertical extension portion AP_V of each of the plurality of active patterns AP. The vertical extension portion AP_V of each of the plurality of active patterns AP may be disposed between the first portion P1 of the second conductive layer 164 and the first conductive layer 162. The second portion P2 of the second conductive layer 164 may be disposed on the sidewall of the first conductive layer 162. The second portion P2 of the second conductive layer 164 may be in direct contact with the sidewall of the first conductive layer 162.

[0047] In some embodiments, a first gate insulating layer 152 may be disposed between a first conductive layer 162 and a first sidewall SW1 of a vertical extension portion AP_V of each of the plurality of active patterns AP, and a second gate insulating layer 154 may be disposed between a first portion P1 of the second conductive layer 164 and a second sidewall SW2, a third sidewall SW3 and a fourth sidewall SW4 of a vertical extension portion AP_V of each of the plurality of active patterns AP.

[0048] In some embodiments, in a plan view, the word line WL may surround the vertical extension portion AP_V of each of the plurality of active patterns AP and may extend in a first horizontal direction X. Since the first conductive layer 162 and the second conductive layer 164 are arranged to surround the first sidewall SW1, the second sidewall SW2, the third sidewall SW3 and the fourth sidewall SW4 of the vertical extension portion AP_V of each of the plurality of active patterns AP, the word line WL may be a GAA type gate electrode.

[0049] In some embodiments, the top surface of the first conductive layer 162 may be disposed at a second vertical horizontal level LV2, and the top surface of the second conductive layer 164 may be disposed at a second vertical horizontal level LV2. In other words, the top surface of the first conductive layer 162 may be coplanar with the top surface of the second conductive layer 164. In some embodiments, the top surfaces of the first conductive layer 162 and the second conductive layer 164 may be disposed at a vertical horizontal level below the top surface of the gate insulating layer structure 150.

[0050] In some embodiments, such as Figure 8 As shown, the first conductive layer 162 may have a first thickness t1 in the second horizontal direction Y, and the second conductive layer 164 may have a second thickness t2 in the second horizontal direction Y. In some embodiments, the second thickness t2 may be different from the first thickness t1. For example, although by way of example Figure 8 It is shown that the second thickness t2 is less than the first thickness t1, but the second thickness t2 can be greater than or equal to the first thickness t1.

[0051] In some embodiments, the first conductive layer 162 and the second conductive layer 164 may comprise Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polycrystalline silicon, or combinations thereof. In some embodiments, the first conductive layer 162 may comprise the same material as the second conductive layer 164. In some embodiments, the first conductive layer 162 may comprise a different material than the second conductive layer 164. Although by way of example Figure 8 The illustration shows that each of the first conductive layer 162 and the second conductive layer 164 is formed as a single layer, but in some embodiments, each of the first conductive layer 162 and the second conductive layer 164 may be formed as a multilayer structure having two or more material layers.

[0052] In some embodiments, the lower molding layer 142 may be disposed between the bottom surface of the first conductive layer 162 and the bit line BL, and between the bottom surface of the first conductive layer 162 and the first insulating layer 132. The opposite sidewalls of the lower molding layer 142 may be aligned with the opposite sidewalls of the first conductive layer 162, and the lower molding layer 142 may extend in the first horizontal direction X.

[0053] In some embodiments, the upper molding layer 144 may be disposed on the top surface of the first conductive layer 162. The opposite sidewalls of the upper molding layer 144 may be aligned with the opposite sidewalls of the first conductive layer 162, and the upper molding layer 144 may extend in a first horizontal direction X.

[0054] In some embodiments, the lower molding layer 142 and the upper molding layer 144 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0055] Insulating pad 172 and buried insulating layer 174 may be disposed on the sidewalls of the first conductive layer 162 and the second conductive layer 164. The insulating pad 172 may be conformally disposed on the sidewalls of the first conductive layer 162, the sidewalls and top surface of the second conductive layer 164, and the sidewalls of the gate insulating layer structure 150. The buried insulating layer 174 may be disposed on the insulating pad 172 to fill the space between two adjacent first conductive layers 162 and the space between two adjacent second conductive layers 164.

[0056] In some embodiments, in the cell array region MCA, the first word line WL1 and the second word line WL2 may be mirror-symmetrical to each other and may extend in a first horizontal direction X. In the interface region IA, the first word line WL1 and the second word line WL2 may extend in the first horizontal direction X, and the word line contact WLC may be disposed on at least one of the first word line WL1 and the second word line WL2.

[0057] Multiple landing pads 180 may be disposed on multiple unit transistors CTR. Each of the multiple landing pads 180 may be disposed in a landing pad opening 180H. The bottom surface of the landing pad 180 may contact the top surface of the vertical extension AP_V of each of the multiple active patterns AP, and a portion of the upper side of the landing pad 180 may be disposed on the top surface of the gate insulating layer structure 150 and the top surface of the upper molding layer 144. The multiple landing pads 180 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or combinations thereof.

[0058] The unit capacitor CAP can be disposed on each of the plurality of landing pads 180. The unit capacitor CAP can have a metal-insulator-metal type capacitor structure. For example, the unit capacitor CAP may include a first electrode, a second electrode, and a capacitor dielectric layer disposed between the first electrode and the second electrode.

[0059] In some embodiments, memory elements such as variable resistance memory elements, phase change memory elements, or magnetic memory elements may be arranged as an alternative to unit capacitors (CAP).

[0060] In some embodiments, the word line WL may include a first conductive layer 162 and a second conductive layer 164, and may be a GAA-type gate electrode arranged to surround all four sidewalls of each of the plurality of active patterns AP. Since the semiconductor device 100 includes a GAA-type unit transistor, the electrical performance of the unit transistor may be improved, for example, due to a reduction in the leakage current of the unit transistor and an increase in the unit operating current.

[0061] Figure 9 and Figure 10 This is a cross-sectional view showing a semiconductor device 100A according to some embodiments. Figure 11 yes Figure 9 A magnified view of part of EN1.

[0062] Reference Figures 9 to 11 The top surface of the first conductive layer 162 can be disposed at the second vertical horizontal LV2, and the top surface of the second conductive layer 164 can be disposed at the third vertical horizontal LV3, which is lower than the second vertical horizontal LV2. For example... Figure 10 As shown, since the top surface of the second conductive layer 164 is arranged lower than the top surface of the first conductive layer 162, a portion of the sidewall of the first conductive layer 162, which is arranged at a vertical level above the top surface of the second conductive layer 164, can be covered by the insulating pad 172. Additionally, the bottom surface of the landing pad 180 and the top surface of the second conductive layer 164 can be spaced apart from each other in the vertical direction Z.

[0063] In a manufacturing method according to some embodiments, an active pattern AP may be formed on the sidewall of the first conductive layer 162, and then a second conductive layer 164 may be formed on the sidewall of the active pattern AP. After the second conductive layer 164 is formed, a recessing process may be performed to reduce the height of the top surface of the second conductive layer 164, and in some embodiments, the height of the second conductive layer 164 may be reduced such that the top surface of the second conductive layer 164 is arranged at a vertical level below the top surface of the first conductive layer 162.

[0064] Figure 12 and Figure 13 This is a cross-sectional view showing a semiconductor device 100B according to some embodiments. Figure 14 yes Figure 12 A magnified view of part of EN1.

[0065] Reference Figures 12 to 14 The top surface of the first conductive layer 162 can be disposed at the second vertical horizontal LV2, and the top surface of the second conductive layer 164 can be disposed at the third vertical horizontal LV3, which is higher than the second vertical horizontal LV2. For example... Figure 13 As shown, since the top surface of the second conductive layer 164 is arranged higher than the top surface of the first conductive layer 162, the upper side of the sidewall of the second conductive layer 164, which is arranged at a vertical horizontal position higher than the top surface of the first conductive layer 162, can contact the sidewall of the upper molding layer 144.

[0066] In a manufacturing method according to some embodiments, an active pattern AP may be formed on the sidewall of the first conductive layer 162, and then a second conductive layer 164 may be formed on the sidewall of the active pattern AP. After the second conductive layer 164 is formed, a recessing process may be performed to reduce the height of the top surface of the second conductive layer 164, and in some embodiments, the second conductive layer 164 may be formed such that the top surface of the second conductive layer 164 is arranged at a vertical level higher than the top surface of the first conductive layer 162.

[0067] Figure 15 This is a cross-sectional view showing a semiconductor device 100C according to some embodiments.

[0068] Reference Figure 15 The character line WL may include a first conductive layer 162 and a second conductive layer 164, and the first conductive layer 162 and the second conductive layer 164 may include the same material. In some embodiments, the boundary between the first conductive layer 162 and the second conductive layer 164 may be visually indistinguishable.

[0069] Figure 16 This is a plan view showing a semiconductor device 100D according to some embodiments.

[0070] Reference Figure 16 A second gate insulating layer 154 may be disposed on the second sidewall SW2, third sidewall SW3, and fourth sidewall SW4 of the vertical extension portion AP_V of the active pattern AP, and a portion of the second gate insulating layer 154 may extend to the sidewall of the first conductive layer 162. The portion of the second gate insulating layer 154 extending to the sidewall of the first conductive layer 162 may be referred to as the tail 154_T. The tail 154_T may be disposed adjacent to at least one of the third sidewall SW3 and the fourth sidewall SW4 of the vertical extension portion AP_V.

[0071] In some embodiments, even if mask pattern misalignment or process tolerance exceedance occurs during the etching process of the second gate insulating layer 154, accidental electrical connection or bridging failure between the active pattern AP and the second conductive layer 164 can be prevented.

[0072] Figures 17 to 33 This is a schematic diagram illustrating a method of manufacturing a semiconductor device 100 according to some embodiments. Figure 18A , Figure 19A , Figure 20 , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 31 , Figure 32 and Figure 33 It is along Figure 3 The sectional view taken by line A1-A1'. Figure 26B and Figure 27B It is along Figure 3 The sectional view taken by line A2-A2'. Figure 17 , Figure 18B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 29B and Figure 30 It is along Figure 3 The sectional view taken by line A3-A3', and Figure 19B , Figure 21B , Figure 23C , Figure 24C , Figure 25C and Figure 28B Each is Figure 19A Plan view at the first vertical horizontal LV1.

[0073] Reference Figure 17 An active region AC can be formed on the substrate 110, and a peripheral circuit transistor PTR can be formed on the active region AC. For example, the peripheral circuit transistor PTR may include a gate electrode PTG and a gate insulating layer PTI.

[0074] Then, peripheral circuit wiring 122 and peripheral circuit contacts 124 electrically connected to the substrate 110 and the peripheral circuit transistor PTR can be formed, and a peripheral circuit insulating layer 126 covering the peripheral circuit wiring 122 and peripheral circuit contacts 124 can be formed on the substrate 110. The peripheral circuit insulating layer 126 can be formed using an oxide film, a nitride film, a low-dielectric film, or a combination thereof.

[0075] The peripheral circuit contact 124 located at the highest position can be referred to as the bit line contact BLC. The top surface of the bit line contact BLC may be coplanar with the uppermost surface of the peripheral circuit insulation layer 126.

[0076] Reference Figure 18A and Figure 18B Multiple bit lines BL and a first insulating layer 132 can be formed on the outer circuit insulating layer 126.

[0077] In some embodiments, a conductive layer may be formed on the peripheral circuit insulating layer 126, and multiple bit lines BL may be formed by patterning the conductive layer. Then, a first insulating layer 132 may be formed to fill the spaces between the multiple bit lines BL.

[0078] In some embodiments, multiple bit lines BL can be formed using Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polycrystalline silicon, or combinations thereof, using chemical vapor deposition or atomic layer deposition. In some embodiments, at least one of silicon oxide, silicon oxynitride, and silicon nitride can be used to form the first insulating layer 132.

[0079] Reference Figure 19A and Figure 19B A lower molding layer 142, a metal molding layer 162L, and an upper molding layer 144 can be sequentially formed on multiple bit lines BL and the first insulating layer 132.

[0080] In some embodiments, an insulating layer for lower molding, a conductive layer for metal molding, and an insulating layer for upper molding may be formed sequentially. Then, a mask pattern may be formed on the insulating layer for upper molding, and the insulating layer for lower molding, the conductive layer for metal molding, and the insulating layer for upper molding may be patterned using the mask pattern, thereby forming a lower molding layer 142, a metal molding layer 162L, and an upper molding layer 144.

[0081] In some embodiments, each of the lower molding layer 142, the metal molding layer 162L, and the upper molding layer 144 may have a line pattern shape extending in a first horizontal direction X. The lower molding layer 142, the metal molding layer 162L, and the upper molding layer 144 may have sidewalls aligned with each other. In this regard, the lower molding layer 142, the metal molding layer 162L, and the upper molding layer 144 may be collectively referred to as a molding pattern.

[0082] In some embodiments, the metal molding layer 162L may be formed using Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polycrystalline silicon, or combinations thereof. In some embodiments, the lower molding layer 142 and the upper molding layer 144 may be formed using at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0083] Reference Figure 20 A first gate insulating layer 152 may be formed on the top surface and sidewalls of a molded pattern including a lower molding layer 142, a metal molding layer 162L, and an upper molding layer 144. The first gate insulating layer 152 may also be conformally disposed on the top surface of the bit line BL and the top surface of the first insulating layer 132.

[0084] Reference Figure 21A and Figure 21B An anisotropic etching process can be performed on the first gate insulating layer 152 to remove the portion of the first gate insulating layer 152 disposed on the top surface of the molded pattern (e.g., the top surface of the upper molded layer 144), while leaving only the portion of the first gate insulating layer 152 disposed on the sidewalls of the molded pattern. In the anisotropic etching process, portions of the first gate insulating layer 152 disposed on the top surface of the bit line BL and the top surface of the first insulating layer 132 can also be removed.

[0085] Reference Figure 22A and Figure 22B An active material layer APL can be formed on the top surface and sidewalls of a molded pattern including a lower molding layer 142, a metal molding layer 162L, and an upper molding layer 144. In some embodiments, the active material layer APL may be conformally arranged on the sidewalls and top surface of the molded pattern, as well as on the top surface of the plurality of bit lines BL and the top surface of the first insulating layer 132.

[0086] In some embodiments, zinc tin oxide (Zn) can be used x Sn y O), indium zinc oxide (In x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxynitride (Zn)x ON z ), magnesium zinc oxide (Mg x Zn y O), zirconium indium zinc oxide (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc oxide (Al) x Sn y In z Zn a O), silicon indium zinc oxide (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of O and silicon forms an active material layer APL.

[0087] In some embodiments, an active material layer (APL) can be formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or plasma-enhanced ALD (PEALD).

[0088] Reference Figures 23A to 23C A mask pattern extending in the second horizontal direction Y can be formed on the active material layer APL. Then, a portion of the active material layer APL can be removed by using the mask pattern as an etching mask. Therefore, the active material layer APL can extend in the second horizontal direction Y along the top surface and sidewalls of the molded pattern. The portion of the active material layer APL remaining after the removal process can be referred to as the active pattern AP.

[0089] An active pattern AP may include a vertical extension AP_V disposed on the sidewall of the molded pattern and a horizontal extension AP_P disposed on the top surface of the bit line BL.

[0090] In some embodiments, the portion of the first gate insulating layer 152 disposed on the sidewall of the molded pattern may also be removed during the etching process for removing a portion of the active material layer APL. Therefore, the first gate insulating layer 152 may be disposed between the first sidewall SW1 of the vertical extension AP_V and the sidewall of the molded pattern (e.g., the sidewall of the lower molded layer 142, the sidewall of the metal molded layer 162L, and the sidewall of the upper molded layer 144).

[0091] Reference Figures 24A to 24C A second gate insulating layer 154 covering the active pattern AP can be formed on the top surface and sidewalls of the molded pattern. The second gate insulating layer 154 can cover the second sidewall SW2, the third sidewall SW3 and the fourth sidewall SW4 of the vertically extended portion AP_V, and can be disposed on the top surface of the horizontally extended portion AP_P.

[0092] Reference Figures 25A to 25C A mask pattern extending in the second horizontal direction Y can be formed on the top surface of the second gate insulating layer 154. The mask pattern can then be used as an etching mask to remove the portion of the second gate insulating layer 154 disposed on the sidewall of the molded pattern, while leaving only the portion of the second gate insulating layer 154 covering the active pattern AP.

[0093] In some embodiments, the second gate insulating layer 154 may extend along the top surface and sidewalls of the molded pattern in a second horizontal direction Y. The second gate insulating layer 154 may be arranged to cover the second sidewalls SW2, third sidewalls SW3, and fourth sidewalls SW4 of the vertical extension portion AP_V of the active pattern AP.

[0094] Reference Figure 26A and Figure 26B A second conductive layer 164 can be formed on the top and sidewalls of the molded pattern and on the sidewalls and top surface of the second gate insulating layer 154.

[0095] In some embodiments, the second conductive layer 164 may be formed using Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polycrystalline silicon, or combinations thereof.

[0096] Reference Figure 27A and Figure 27B An anisotropic etching process can be performed to leave a second conductive layer 164 on the sidewalls of the molded pattern and the sidewalls of the second gate insulating layer 154. As a result of this process, portions of the second conductive layer 164 disposed on the top surface of the molded pattern and the top surface of the second gate insulating layer 154 can be removed.

[0097] Additionally, an anisotropic etching process or recessed treatment can be performed to remove a portion of the upper side of the second conductive layer 164. In some embodiments, the top surface level of the second conductive layer 164 can be formed to be substantially the same as the top surface level of the metal molding layer 162L, and the sidewalls of the upper molding layer 144 can be exposed without being covered by the second conductive layer 164.

[0098] Reference Figure 28A and Figure 28B A mask pattern extending in a first horizontal direction X can be formed on the molded pattern, and the mask pattern can be used as an etching mask to remove a portion of the molded pattern (e.g., a portion of the upper molded layer 144, a portion of the metal molded layer 162L, and a portion of the lower molded layer 142), thereby forming a molding separation opening 140H. The molding separation opening 140H can extend from the cell array region MCA to the interface region IA.

[0099] In some embodiments, as the molding separation opening 140H is formed, a metal molding layer 162L can be divided into two first conductive layers 162 spaced apart from each other in a second horizontal direction Y. As the molding separation opening 140H is formed, the sidewalls of the upper molding layer 144, the sidewalls of the first conductive layers 162, and the sidewalls of the lower molding layer 142 exposed in the molding separation opening 140H can be arranged aligned with each other.

[0100] In some embodiments, the first thickness t1 of the first conductive layer 162 (or the width in the second horizontal direction Y) may be determined based on the width of the molding separation opening 140H. In some embodiments, the first thickness t1 of the first conductive layer 162 may be greater than the second thickness t2 of the second conductive layer 164, but the disclosed concept is not limited thereto.

[0101] Reference Figure 29A and Figure 29B An insulating pad 172 can be formed on the inner wall of the molded separation opening 140H, the sidewalls and top surface of the second conductive layer 164, and an embedded insulating layer 174 can be formed on the top surface of the insulating pad 172. For example... Figure 29B As shown, the insulating pad 172 and the embedded insulating layer 174 can even be arranged on the first conductive layer 162 and the second conductive layer 164 arranged in the interface area IA.

[0102] Reference Figure 30 The word line contact hole WLCH is formed by removing a portion of the embedded insulating layer 174 arranged in the interface region IA. The top surfaces of the first conductive layer 162 and the second conductive layer 164 can be exposed at the bottom of the word line contact hole WLCH. Then, the word line contact WLC can be formed within the word line contact hole WLCH using a conductive material.

[0103] Reference Figure 31The portion of the second gate insulating layer 154 disposed on the top surface of the upper molding layer 144 can be removed, and then the portion of the active pattern AP disposed on the top surface of the upper molding layer 144 can be removed, thereby forming the landing pad opening 180H.

[0104] Reference Figure 32 The landing pad 180 can be formed in the landing pad opening 180H using at least one of Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, and polysilicon. The landing pad 180 may have a bottom surface that contacts the top surface of the active pattern AP. In addition, a portion of the landing pad 180 may be disposed on the top surface of the upper molding layer 144 such that the width of the upper side of the landing pad 180 is greater than the width of its bottom.

[0105] Reference Figure 33 Unit capacitors (CAPs) can be formed on landing pad 180.

[0106] The semiconductor device 100 can be manufactured by performing the above process.

[0107] According to some embodiments, an active pattern AP can be formed on the sidewall of the metal molding layer 162L, and then a second conductive layer 164 can be formed on the sidewall of the active pattern AP. A unit transistor can be formed by dividing the metal molding layer 162L into two first conductive layers 162. According to this manufacturing method, GAA-type unit transistors can be formed by simplifying the process. The semiconductor device 100 can have superior electrical performance, such as reduced leakage current and increased unit operating current.

[0108] According to the present invention, a semiconductor device may include a GAA-type unit transistor, and the electrical performance of the unit transistor may be improved, for example, by reducing the leakage current of the unit transistor and increasing the unit operating current.

[0109] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Peripheral circuit area; as well as A unit array region disposed on the peripheral circuit region, wherein the unit array region includes: Multiple bit lines, which extend in the first horizontal direction; Multiple active patterns extend vertically along the multiple bit lines, and each includes a first sidewall and a second sidewall opposite to the first sidewall; A word line, which extends along the plurality of bit lines in a second horizontal direction intersecting the first horizontal direction, and includes: A first conductive layer, disposed on the first sidewall of each of the plurality of active patterns, and extending in the second horizontal direction, and A second conductive layer includes a first portion disposed on a second sidewall of each of the plurality of active patterns, and includes a second portion disposed on a sidewall of the first conductive layer; and Multiple unit capacitors are arranged on the multiple active patterns.

2. The semiconductor device according to claim 1, wherein, In the plan view, the letter lines surround the plurality of active patterns and extend in the second horizontal direction.

3. The semiconductor device according to claim 1, wherein: Each of the plurality of active patterns is arranged between the first portion of the second conductive layer and the first conductive layer, and The second portion of the second conductive layer is in contact with the sidewall of the first conductive layer.

4. The semiconductor device according to claim 1, further comprising: Multiple gate insulating layer structures are disposed between the word lines and each of the multiple active patterns, and include: A first gate insulating layer is disposed between the first sidewall and the first conductive layer in each of the plurality of active patterns; and A second gate insulating layer is disposed between the second sidewall of each of the plurality of active patterns and the first portion of the second conductive layer.

5. The semiconductor device according to claim 4, wherein: The plurality of active patterns extend in the vertical direction and each includes a vertically extending portion having a first sidewall and a second sidewall, and a horizontally extending portion connected to the bottom of the vertically extending portion and extending in the first horizontal direction. The first gate insulating layer is disposed between the first sidewall of the vertically extending portion and the first conductive layer, and The second gate insulating layer is disposed between the second sidewall of the vertical extension and the first portion of the second conductive layer, and extends to the top surface of the horizontal extension.

6. The semiconductor device according to claim 5, wherein, The vertical extension portion also includes: A third sidewall, which connects to the first sidewall and the second sidewall; and A fourth sidewall, which connects to the first and second sidewalls and is opposite to the third sidewall, and The second gate insulating layer extends to the third and fourth sidewalls and contacts the first gate insulating layer.

7. The semiconductor device according to claim 6, wherein, In the plan view, the first gate insulating layer and the second gate insulating layer together surround the vertical extension.

8. The semiconductor device according to claim 6, wherein: A portion of the second gate insulating layer is disposed between the first portion of the second conductive layer and the third sidewall of the vertically extending portion, and A portion of the second gate insulating layer is disposed between the first portion of the second conductive layer and the fourth sidewall of the vertically extending portion.

9. The semiconductor device according to claim 1, wherein, The multiple active patterns include zinc tin oxide (ZnO2). x Sn y O), indium zinc oxide (In x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxynitride (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), magnesium aluminum zinc oxide (Mg x Al y Zn z O), zirconium indium zinc oxide (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc oxide (Al) x Sn y In z Zn a O), silicon indium zinc oxide (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), zirconium zinc tin oxide (Zr) x Zn y Sn z At least one of O and silicon.

10. The semiconductor device according to claim 1, wherein: The first conductive layer has a first thickness in the first horizontal direction. The second conductive layer has a second thickness in the first horizontal direction, and The second thickness is less than the first thickness.

11. The semiconductor device according to claim 1, further comprising: A lower molding layer that extends along the plurality of bit lines in the second horizontal direction and whose top surface contacts the bottom surface of the first conductive layer; as well as An upper molding layer is disposed on the top surface of the first conductive layer and extends in the second horizontal direction.

12. The semiconductor device according to claim 11, wherein: The opposite sidewalls of the lower molded layer are aligned with the opposite sidewalls of the first conductive layer, and The opposite sidewalls of the upper molded layer are aligned with the opposite sidewalls of the first conductive layer.

13. The semiconductor device according to claim 1, wherein, The top surface of the second conductive layer is coplanar with the top surface of the first conductive layer.

14. The semiconductor device according to claim 1, wherein, The top surface of the second conductive layer is arranged at a vertical level that is higher than the top surface of the first conductive layer.

15. The semiconductor device according to claim 1, wherein, The top surface of the second conductive layer is arranged at a vertical level that is lower than the vertical level of the top surface of the first conductive layer.

16. A semiconductor device, comprising: Multiple bit lines are arranged on the substrate and extend in a first horizontal direction; Multiple active patterns extend vertically along the multiple bit lines, and each includes a first sidewall and a second sidewall opposite to each other, as well as a third sidewall and a fourth sidewall opposite to each other. A word line, which extends along the plurality of bit lines in a second horizontal direction intersecting the first horizontal direction, and includes: A first conductive layer, disposed on the first sidewall of each of the plurality of active patterns, and extending in the second horizontal direction, and The second conductive layer includes a first portion disposed on the second sidewall, the third sidewall, and the fourth sidewall of each of the plurality of active patterns, and extends in the second horizontal direction; as well as Unit capacitors are arranged on each of the plurality of active patterns.

17. The semiconductor device of claim 16, further comprising: Multiple gate insulating layer structures are disposed between the word lines and each of the multiple active patterns, and include: A first gate insulating layer, disposed between the first sidewall and the first conductive layer in each of the plurality of active patterns, and A second gate insulating layer is disposed between the second sidewall and the first portion of the second conductive layer of each of the plurality of active patterns, between the third sidewall and the first portion of the second conductive layer, and between the fourth sidewall and the first portion of the second conductive layer.

18. The semiconductor device according to claim 16, wherein, The second conductive layer further includes a second portion disposed on the sidewall of the first conductive layer.

19. The semiconductor device of claim 16, further comprising: The lower molding layer extends in the second horizontal direction along the plurality of bit lines and has a top surface that contacts the bottom surface of the first conductive layer; as well as An upper molding layer is disposed on the top surface of the first conductive layer and extends in the second horizontal direction. Wherein, the opposite sidewalls of the lower molding layer are aligned with the opposite sidewalls of the first conductive layer, and The opposite sidewalls of the upper molded layer are aligned with the opposite sidewalls of the first conductive layer.

20. A semiconductor device, comprising: Peripheral circuit area; as well as A unit array region disposed on the peripheral circuit region, wherein the unit array region includes: Multiple bit lines, which extend in the first horizontal direction; Multiple active patterns extend vertically along the multiple bit lines, and each includes a first sidewall and a second sidewall opposite to the first sidewall; A word line, which extends along the plurality of bit lines in a second horizontal direction intersecting the first horizontal direction, and includes: A first conductive layer, disposed on the first sidewall of each of the plurality of active patterns, and extending in the second horizontal direction, and The second conductive layer includes a first portion disposed on the second sidewall of each of the plurality of active patterns and a second portion disposed on the sidewall of the first conductive layer, the second conductive layer extending in the second horizontal direction. Multiple gate insulating layer structures are disposed between the word lines and each of the multiple active patterns, and include: A first gate insulating layer, disposed between the first sidewall and the first conductive layer in each of the plurality of active patterns, and A second gate insulating layer is disposed between the second sidewall of each of the plurality of active patterns and the first portion of the second conductive layer; and Multiple unit capacitors are respectively arranged on the multiple active patterns.

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