Semiconductor device

Abstract

The present disclosure relates to a semiconductor device, according to an embodiment, including: a substrate; a plurality of semiconductor patterns on the substrate, spaced apart in a direction substantially perpendicular to an upper surface of the substrate; a bit line connected to one side surface of the plurality of semiconductor patterns in a first direction and extending in a direction substantially perpendicular to the upper surface of the substrate; a plurality of capacitors respectively connected to another side surface of the plurality of semiconductor patterns in the first direction; a plurality of word lines respectively intersecting the plurality of semiconductor patterns and extending in a second direction intersecting the first direction; a plurality of word line pads overlapping the plurality of capacitors in the second direction; and a plurality of word line contacts connected to at least some of the plurality of word line pads, wherein the plurality of word line contacts are spaced apart in the first direction, and the plurality of word line contacts have different lengths in the direction substantially perpendicular to the upper surface of the substrate.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0043261, filed with the Korean Patent Office on April 3, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices. Background Technology

[0003] There is a need to develop technologies that can improve the integration density of semiconductor devices. In two-dimensional semiconductor devices, integration density mainly depends on the area occupied by a unit memory cell, and this integration density can be affected by the level of fine patterning technology.

[0004] However, due to the expensive equipment required for fine patterning techniques, the integration density of two-dimensional semiconductor devices remains limited despite continuous improvements. Accordingly, three-dimensional semiconductor memory devices comprising memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0005] This embodiment provides a semiconductor device that reduces the area occupied by multiple word line pads and minimizes the increase in area even as the number of stacked memory cell layers increases.

[0006] In an embodiment, a semiconductor device includes: a substrate; a plurality of semiconductor patterns on the substrate, spaced apart in a direction substantially perpendicular to an upper surface of the substrate; bit lines connected to a side surface of the plurality of semiconductor patterns along a first direction and extending in a direction substantially perpendicular to the upper surface of the substrate; a plurality of capacitors, each connected to another side surface of the plurality of semiconductor patterns along the first direction; a plurality of word lines intersecting the plurality of semiconductor patterns and extending in a second direction intersecting the first direction; a plurality of word line pads overlapping the plurality of capacitors in the second direction; and a plurality of word line contacts extending in a direction substantially perpendicular to the upper surface of the substrate; wherein at least some of the plurality of word line pads are respectively connected to the plurality of word line contacts, wherein the plurality of word line contacts are spaced apart in the first direction, and wherein the plurality of word line contacts have different lengths along a direction substantially perpendicular to the upper surface of the substrate.

[0007] In an embodiment, a semiconductor device includes: a substrate; a plurality of semiconductor patterns on the substrate, spaced apart in a direction substantially perpendicular to an upper surface of the substrate; bit lines connected to a side surface of the plurality of semiconductor patterns along a first direction and extending in a direction substantially perpendicular to the upper surface of the substrate; a plurality of capacitors, each connected to another side surface of the plurality of semiconductor patterns along the first direction; a plurality of word lines intersecting the plurality of semiconductor patterns and extending in a second direction intersecting the first direction; a plurality of word line pads overlapping the plurality of capacitors in the second direction; and a plurality of word line contacts extending in a direction substantially perpendicular to the upper surface of the substrate; wherein at least some of the plurality of word line pads are respectively connected to the plurality of word line contacts, wherein the plurality of word line contacts are spaced apart in the first direction, and wherein the plurality of word line contacts are connected to the upper surfaces of word line pads located on different layers.

[0008] In an embodiment, a semiconductor device includes: a substrate; a plurality of semiconductor patterns on the substrate, spaced apart in directions substantially parallel to an upper surface of the substrate and in directions substantially perpendicular to an upper surface of the substrate; a plurality of bit lines, spaced apart in a direction substantially parallel to an upper surface of the substrate, each of the plurality of bit lines being connected to a side surface of the plurality of semiconductor patterns spaced apart in a direction substantially perpendicular to an upper surface of the substrate along a first direction and extending in a direction substantially perpendicular to an upper surface of the substrate; a plurality of capacitors, respectively connected to another side surface of the plurality of semiconductor patterns along the first direction; and a plurality of word lines, spaced apart in a direction substantially perpendicular to an upper surface of the substrate. The plurality of word lines are spaced apart in a first direction and upward; each of the plurality of word lines intersects with a plurality of semiconductor patterns spaced apart in a second direction intersecting the first direction and extends in the second direction; a plurality of word line pads overlap with a plurality of capacitors in the second direction; each of the plurality of word line pads is connected between two adjacent word lines in the first direction; a capacitor is located between the two word lines; and a plurality of word line contacts extend in a direction substantially perpendicular to the upper surface of the substrate and are spaced apart in the first direction on each of the plurality of word line pads, wherein the plurality of word line contacts are connected to the upper surface of word line pads located on different layers.

[0009] According to an embodiment, a method of manufacturing a semiconductor device may include: forming a plurality of memory cells on a cell region of a substrate, the memory cells being spaced apart from each other in a first direction and a second direction substantially parallel to an upper surface of the substrate, and in a third direction substantially perpendicular to the upper surface of the substrate; each of the plurality of memory cells including: a semiconductor pattern; a bit line connected to a side surface of the semiconductor pattern along the first direction and extending upward in a third direction; a capacitor connected to another side surface of the semiconductor pattern along the first direction; and a word line intersecting the semiconductor pattern and extending in a second direction; forming a word line extension on a pad region of the substrate located on one side of the cell region along the second direction, the word line extension being connected to the word line and extending in the second direction; forming a word line pad on the pad region extending from the word line extension along the first direction and overlapping the capacitor in the second direction; and forming a plurality of word line contacts spaced apart from each other along the first direction and having different lengths along a third direction on the word line pad.

[0010] The step of forming word line extensions may include: etching portions of an interlayer insulating layer and a plurality of semiconductor layers alternately stacked on a pad region to form a plurality of first trenches spaced apart in a first direction, each of the plurality of first trenches being located on one side of a region in the pad region in the first direction, the region overlapping with a word line in a second direction; etching portions of the plurality of semiconductor layers through the plurality of first trenches to form a plurality of first grooves; forming a plurality of word line extensions in the plurality of first grooves respectively by depositing conductive material, the plurality of word line extensions being spaced apart in a third direction and the first direction; and forming a first insulating pattern in the plurality of first trenches by depositing insulating material.

[0011] The steps of forming word line pads may include: etching portions of an interlayer insulating layer and a plurality of semiconductor layers alternately stacked on a pad region to form a plurality of second trenches spaced apart in a second direction, the plurality of second trenches being located between two word line extensions spaced apart in a first direction, and the two word line extensions being respectively connected to two word lines located on both sides of two capacitors, the two capacitors being located between two adjacent semiconductor patterns in the first direction; etching portions of a plurality of semiconductor layers through the plurality of second trenches to form a plurality of holes, each of the plurality of holes being located between the plurality of second trenches spaced apart in the second direction; forming a plurality of word line pads in each of the plurality of holes by depositing a conductive material, the plurality of word line pads being spaced apart in a third direction and a second direction, and each of the plurality of word line pads being connected between two word line extensions spaced apart in the first direction; and forming a second insulating pattern in the plurality of second trenches by depositing an insulating material.

[0012] The steps of forming multiple word line contacts may include: forming multiple contact holes that penetrate portions of multiple word line pads and an interlayer insulating layer spaced apart from each other in a third direction, wherein the multiple contact holes have different lengths in the third direction; forming an insulating material layer by depositing an insulating material to cover the inner surfaces of the multiple contact holes and the upper surfaces of the multiple word line pads exposed by the multiple contact holes; etching portions of the insulating material layer covering the upper surfaces of the multiple word line pads by an anisotropic etching process; forming a material layer filling the remaining space of the multiple contact holes by depositing a conductive material; and etching portions of the insulating material layer and the conductive material layer by a planarization process to form multiple word line contacts in the multiple contact holes, each of the multiple word line contacts including an insulating layer and a conductive layer. The side surfaces of each of the multiple word line contacts may be formed by the insulating layer. The upper and lower surfaces of each of the multiple word line contacts may be formed by the insulating layer and the conductive layer. The lower surface of each of the multiple word line contacts may contact a word line pad.

[0013] The length of the multiple word line contacts spaced apart in the first direction on the multiple word line pads spaced apart in the third direction can be gradually increased or decreased in the third direction.

[0014] According to the embodiments, the area occupied by multiple word line pads in a semiconductor device can be reduced, and the increase in the area occupied by multiple word line pads can be minimized even if the number of layers stacked with multiple memory cells increases. Attached Figure Description

[0015] Figure 1 This is a plan view of a semiconductor device according to an embodiment.

[0016] Figure 2 It shows Figure 1 A perspective view of the enlarged view of region R1.

[0017] Figure 3 It is along Figure 1 A cross-sectional view taken along the midline A-A'.

[0018] Figure 4 It is along Figure 1 Cross-sectional views taken from the centerline B-B', line C-C', and line D-D'.

[0019] Figure 5 It shows Figure 1 A magnified plan view of region R2 in the middle.

[0020] Figure 6 It is along Figure 5 A cross-sectional view taken along the centerline E-E'.

[0021] Figure 7 It is along Figure 5 A cross-sectional view taken along the centerline F-F'.

[0022] Figure 8 It is along Figure 5 A cross-sectional view taken along the midline G-G'.

[0023] Figure 9 It is along Figure 1 Cross-sectional views taken from the centerline B-B', line C-C', and line D-D'.

[0024] Figure 10 It is along Figure 1 Cross-sectional views taken from the centerline B-B', line C-C', and line D-D'.

[0025] Figure 11 It is along Figure 1 Cross-sectional views taken from the centerline B-B', line C-C', and line D-D'.

[0026] Figure 12 This is a plan view of a semiconductor device according to an embodiment.

[0027] Figure 13 It is along Figure 12 A cross-sectional view taken along the midline H-H'.

[0028] Figure 14 It is along Figure 12 A cross-sectional view taken along the centerline I-I'.

[0029] Figure 15 It is along Figure 12 Cross-sectional views taken from the centerline J-J', line K-K', and line L-L'.

[0030] Figure 16 It is along Figure 12 Cross-sectional views taken from the centerline J-J', line K-K', and line L-L'.

[0031] Figure 17 It is along Figure 12 Cross-sectional views taken from the centerline J-J', line K-K', and line L-L'.

[0032] Figure 18 It is along Figure 12 Cross-sectional views taken from the centerline J-J', line K-K', and line L-L'.

[0033] Figure 19 It is along Figure 12 Cross-sectional views taken from the centerline J-J', line K-K', and line L-L'.

[0034] Figure 20 , Figure 23 , Figure 25 , Figure 28 , Figure 31 , Figure 33 and Figure 36 This is a plan view illustrating a portion of a method for manufacturing a semiconductor device according to an embodiment.

[0035] Figure 21 , Figure 22 , Figure 24 , Figure 26 , Figure 27 , Figure 29 , Figure 30 , Figure 32 , Figure 34 , Figure 35 , Figure 37 , Figure 38 and Figure 39 This is a cross-sectional view showing a portion of a method for manufacturing a semiconductor device according to an embodiment.

[0036] Figures 40 to 48 This is a cross-sectional view showing a portion of a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0037] In the following, various embodiments of the invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice the invention. The invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0038] For clarity of the invention, parts irrelevant to the description have been omitted, and throughout this specification, the same reference numerals are used for the same or similar components.

[0039] Furthermore, for ease of explanation, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated; therefore, the invention is not necessarily limited to what is shown. To clearly illustrate the various layers and regions in the drawings, their thicknesses are enlarged and shown. And in the drawings, for ease of explanation, the thicknesses of some layers and regions are exaggerated.

[0040] Furthermore, when we say that a component (such as a layer, membrane, region, or plate) is "above" or "on" another component, this includes not only the case where it is "directly" "on" the other component, but also the case where there are other components in between. Conversely, when we say that a component is "directly" "on" another component, it means that there are no other components in between. Also, "above" or "on" a reference component means being above or below the reference component, and does not necessarily mean being "above" or "on" in the opposite direction of gravity.

[0041] Additionally, throughout this specification, whenever a component is referred to as "including" an assembly, it does not mean that it excludes other components, but rather that it may include other components, unless otherwise expressly stated.

[0042] Additionally, throughout this specification, when we say "in a plan view," we mean when viewing the target portion from above; when we say "in a cross-sectional view," we mean when viewing the target portion from the side of a vertically cut cross-section.

[0043] As used herein, the term “substantially perpendicular” generally refers to the orientation of two elements that are at or near right angles (90°) to each other, and may include deviations from exact 90° within manufacturing tolerances, as will be understood by one of ordinary skill in the art.

[0044] As used herein, the term “substantially parallel” generally refers to the orientation of two elements extending in substantially the same direction or in substantially the same plane, and may include deviations from precise parallelism within manufacturing tolerances, as will be understood by one of ordinary skill in the art.

[0045] In the following text, reference will be made to Figures 1 to 8 A semiconductor device according to an embodiment is described.

[0046] Figure 1 This is a plan view of a semiconductor device according to an embodiment. Figure 1 The image shows a semiconductor device with a substrate 100, a semiconductor pattern 130, a bit line BL, a capacitor 170, a word line WL, a word line pad 510, and a word line contact 520; the remaining components are omitted. Figure 1 Only the first capacitor electrode 171 and plate electrode 174 of capacitor 170 are shown, and the rest of the components of capacitor 170 are omitted. Figure 2 It shows Figure 1 A perspective view of an enlarged view of region R1. For convenience, Figure 2 The substrate 100 and plate electrode 174 are further omitted. Figure 3 It is along Figure 1 A cross-sectional view taken along the midline A-A'. Figure 4 It is along Figure 1 Cross-sectional views taken from the centerline B-B', line C-C', and line D-D'. Figure 5 It shows Figure 1 A magnified plan view of region R2 in the middle. Figure 6 It is along Figure 5 A cross-sectional view taken along the centerline E-E'. Figure 7 It is along Figure 5 A cross-sectional view taken along the centerline F-F'. Figure 8 It is along Figure 5 A cross-sectional view taken along the midline G-G'.

[0047] like Figures 1 to 8As shown, the semiconductor device according to an embodiment includes: a substrate 100; a plurality of semiconductor patterns 130 disposed on the substrate 100 and spaced apart in a direction perpendicular to the upper surface of the substrate 100; a bit line BL connected to one side surface of the plurality of semiconductor patterns 130 along a first direction DR1 and extending in a direction perpendicular to the upper surface of the substrate 100; a plurality of capacitors 170 respectively connected to the other side surface of the plurality of semiconductor patterns 130 along the first direction DR1; a plurality of word lines WL respectively intersecting the plurality of semiconductor patterns 130 and extending in a second direction DR2 intersecting the first direction DR1; a plurality of word line pads 510 overlapping the plurality of capacitors 170 in the second direction DR2; and a plurality of word line contacts 520 extending in a direction perpendicular to the upper surface of the substrate 100. The first direction DR1 and the second direction DR2 may be directions parallel to the upper surface of the substrate 100.

[0048] Substrate 100 may include semiconductor materials. For example, substrate 100 may include group IV semiconductors, group III-V compound semiconductors, group II-VI compound semiconductors, etc. For example, substrate 100 may include semiconductors such as Si and Ge, or compound semiconductors such as SiGe, SiC, GaAs, InAs, or InP. For example, substrate 100 may be a single-crystal epitaxial layer grown on a single-crystal silicon substrate. However, the material of substrate 100 is not limited to these and can be changed in various ways.

[0049] Substrate 100 may include cell regions CR and pad regions PR. Cell regions CR and pad regions PR may be arranged along a second direction DR2 extending along word lines WL. Substrate 100 may include a plurality of cell regions CR spaced apart from each other along the second direction DR2. Pad regions PR may be located between adjacent cell regions CR along the second direction DR2. A plurality of memory cells may be located on the cell regions CR of substrate 100. Each of the plurality of memory cells may include a semiconductor pattern 130, a bit line BL, a capacitor 170, and a word line WL. Semiconductor pattern 130, bit line BL, capacitor 170, and word line WL may be located on the cell regions CR of substrate 100. Word line pads 510 and word line contacts 520 may be located on the pad regions PR of substrate 100. Word lines WL may be positioned to extend into the pad regions PR. Word lines WL may be positioned to extend along the second direction DR2, spanning the plurality of cell regions CR spaced apart from each other along the second direction DR2 and the pad regions PR between the plurality of cell regions CR.

[0050] Multiple semiconductor patterns 130 may be located on a cell region CR of substrate 100. The multiple semiconductor patterns 130 may be arranged and spaced apart along a third direction DR3 perpendicular to the upper surface of substrate 100. The multiple semiconductor patterns 130 may be arranged and spaced apart along a first direction DR1 parallel to the upper surface of substrate 100. Two capacitors 170 may be located between two adjacent semiconductor patterns 130 along the first direction DR1. Additionally, a bit line BL may be located between two adjacent semiconductor patterns 130 along the first direction DR1. The two capacitors 170 and the bit line BL may be arranged alternately along the first direction DR1. Two semiconductor patterns 130 adjacent to each other in the first direction DR1 may have a symmetrical structure based on two capacitors 170 respectively connected to the two semiconductor patterns 130. Another two adjacent semiconductor patterns 130 in the first direction DR1 may have a symmetrical structure based on a bit line BL connected thereto. The multiple semiconductor patterns 130 may be arranged and spaced apart along a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 may be a direction orthogonal to the first direction DR1.

[0051] Semiconductor pattern 130 may extend along a first direction DR1. Semiconductor pattern 130 may have a stripe extending along the first direction DR1. One side surface of semiconductor pattern 130 along the first direction DR1 may be connected to bit line BL. For example, semiconductor pattern 130 may contact bit line BL, but is not limited thereto. Another layer may be positioned between semiconductor pattern 130 and bit line BL. The other side surface of semiconductor pattern 130 along the first direction DR1 may be connected to capacitor 170.

[0052] Semiconductor pattern 130 may include a semiconductor material. For example, semiconductor pattern 130 may include silicon, germanium, or silicon-germanium. For example, semiconductor pattern 130 may include monocrystalline silicon or polycrystalline silicon. However, the examples are not limited to these.

[0053] Bit lines BL are connected to a side surface of a plurality of semiconductor patterns 130 spaced apart along a third direction DR3 and may extend along the third direction DR3. A semiconductor device according to an embodiment may include a plurality of bit lines BL spaced apart along a first direction DR1. Each bit line of the plurality of bit lines BL spaced apart along the first direction DR1 may connect between two adjacent semiconductor patterns 130 in the first direction DR1. That is, two semiconductor patterns 130 may be connected to one bit line BL. However, not all bit lines BL may be connected to two semiconductor patterns 130. For example, in the plurality of bit lines BL spaced apart along the first direction DR1, each bit line BL at both ends may be connected to one semiconductor pattern 130. The plurality of bit lines BL may be spaced apart along a second direction DR2. The plurality of bit lines BL spaced apart along the second direction DR2 may be respectively connected to the plurality of semiconductor patterns 130 spaced apart along the second direction DR2.

[0054] Bit lines BL may include conductive materials. For example, bit lines BL may include doped semiconductor materials (e.g., doped silicon or doped germanium), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), metals (e.g., tungsten, titanium, or tantalum), metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, or titanium silicide), or combinations thereof.

[0055] As described above, capacitor 170 can be connected to the other side surface of semiconductor pattern 130 along the first direction DR1. Capacitor 170 may include a first capacitor electrode 171, a second capacitor electrode 173, a dielectric layer 172 located between the first capacitor electrode 171 and the second capacitor electrode 173, and a plate electrode 174 located on the second capacitor electrode 173. First capacitor electrode 171 can be connected to the other side surface of semiconductor pattern 130 along the first direction DR1. First capacitor electrode 171 can extend along the first direction DR1. Dielectric layer 172 can cover the surface of first capacitor electrode 171. Dielectric layer 172 can cover the surface of first capacitor electrode 171 except for the surface in contact with semiconductor pattern 130.

[0056] The semiconductor device according to an embodiment may include a plurality of first capacitor electrodes 171, each first capacitor electrode 171 being connected to a plurality of semiconductor patterns 130. The plurality of first capacitor electrodes 171 may be spaced apart along a third direction DR3. The plurality of first capacitor electrodes 171 may be spaced apart along a second direction DR2. The plurality of first capacitor electrodes 171 may be spaced apart along a first direction DR1. A dielectric layer 172 may cover the plurality of first capacitor electrodes 171 spaced apart along the third direction DR3 and the second direction DR2. The dielectric layer 172 may cover two first capacitor electrodes 171 adjacent to each other along the first direction DR1. The dielectric layer 172 may cover two first capacitor electrodes 171 located between two adjacent bit lines BL along the first direction DR1 and facing each other on the first direction DR1.

[0057] The second capacitor electrode 173 may cover the surface of the dielectric layer 172. The second capacitor electrode 173 may be separated from the first capacitor electrode 171 through the dielectric layer 172. The plate electrode 174 may cover the surface of the second capacitor electrode 173. The plate electrode 174 may be connected to the second capacitor electrode 173. Between two adjacent bit lines BL on the first direction DR1, the dielectric layer 172, the second capacitor electrode 173, and the plate electrode 174 of a plurality of capacitors 170 arranged spaced apart along the third direction DR3 and the second direction DR2 and opposite to each other along the first direction DR1 may be integrally formed.

[0058] Each of the first capacitor electrode 171, the second capacitor electrode 173, and the plate electrode 174 may include a conductive material. Each of the first capacitor electrode 171, the second capacitor electrode 173, and the plate electrode 174 may include at least one of the following materials: a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a doped semiconductor material (e.g., doped silicon or doped germanium). The first capacitor electrode 171 and the second capacitor electrode 173 may include the same material. The plate electrode 174 may include a material different from that of the first capacitor electrode 171 and the second capacitor electrode 173. For example, the first capacitor electrode 171 and the second capacitor electrode 173 may include titanium nitride, while the plate electrode 174 may include doped silicon-germanium.

[0059] The dielectric layer 172 may include at least one of a dielectric, a ferromagnetic material, or an antiferromagnetic material. The dielectric may include a high-k material. For example, the dielectric may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

[0060] The word line WL may intersect the semiconductor pattern 130 and extend along the second direction DR2. The word line WL may overlap with the semiconductor pattern 130 on the third direction DR3. The word line WL may surround a portion of the surface of the semiconductor pattern 130. The word line WL may surround a portion of the outer surface of the semiconductor pattern 130 relative to a central axis on the first direction DR1. In this case, the word line WL may also overlap with the semiconductor pattern 130 on the second direction DR2. The word line WL may surround the portion of the semiconductor pattern 130 between its two ends along the first direction DR1. A channel may be formed along the surface of the semiconductor pattern 130 surrounded by the word line WL.

[0061] However, the embodiments described above are not limited to. For example, the word line WL may overlap with the semiconductor pattern 130 only in the third direction DR3, and not in the second direction DR2. For example, the word line WL may be located on one side surface of the semiconductor pattern 130 along the third direction DR3. As another example, two word lines WL may be located on each side surface of the semiconductor pattern 130 along the third direction DR3.

[0062] The word line WL may intersect with a plurality of semiconductor patterns 130 spaced apart along the second direction DR2. The word line WL may extend along the second direction DR2 to surround a portion of the surface of the plurality of semiconductor patterns 130 spaced apart along the second direction DR2. The word line WL may be electrically connected to the plurality of semiconductor patterns 130 spaced apart along the second direction DR2.

[0063] Multiple word lines WL can be arranged spaced apart along a third direction DR3. Each word line of the multiple word lines WL spaced apart along the third direction DR3 can surround each of the multiple semiconductor patterns 130 spaced apart along the third direction DR3. The multiple word lines WL spaced apart along the third direction DR3 can be electrically connected to the multiple semiconductor patterns 130 spaced apart along the third direction DR3, respectively.

[0064] Multiple word lines WL can be arranged spaced apart along the first direction DR1. Two capacitors 170 connected along the first direction DR1 can be located between two adjacent word lines WL along the first direction DR1. A bit line BL can be located between two adjacent word lines WL along the first direction DR1. The two capacitors 170 and the bit line BL connected along the first direction DR1 can be arranged alternately and repeatedly along the first direction DR1. Two adjacent word lines WL on the first direction DR1 can be spaced apart, and two capacitors 170 connected along the first direction DR1 are located between them. Two adjacent word lines WL on the first direction DR1 can be spaced apart, and a bit line BL is located between them. The distance between two word lines WL on both sides of the two capacitors 170 connected along the first direction DR1 can be greater than the distance between two word lines WL on both sides of the bit line BL along the first direction DR1.

[0065] The gate insulating layer Gox can be located between the word line WL and the semiconductor pattern 130. The word line WL can be separated from the surface of the semiconductor pattern 130 by the gate insulating layer Gox.

[0066] Word lines (WL) may include conductive materials. For example, word lines (WL) may include doped semiconductor materials (e.g., doped silicon or doped germanium), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), metals (e.g., tungsten, titanium, or tantalum), metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, or titanium silicide), or combinations thereof.

[0067] The gate insulating layer Gox may include at least one of a high-k material, silicon oxide, silicon nitride, or silicon oxynitride. The high-dielectric-constant material may include at least one of, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0068] Interlayer insulating layer 120 may be located between multiple word lines WL spaced apart along a third direction DR3. Interlayer insulating layer 120 may also be located between substrate 100 and the lowest word line WL. Interlayer insulating layer 120 may also be located between the highest word line WL and the upper insulating layer 180 described later.

[0069] Interlayer insulating layer 120 may be located between a plurality of semiconductor patterns 130 spaced apart along a third direction DR3. Interlayer insulating layer 120 may also be located on the lower surface of the lowermost semiconductor pattern 130 and the upper surface of the uppermost semiconductor pattern 130.

[0070] Interlayer insulating layer 120 may be located between substrate 100 and bit line BL. Interlayer insulating layer 120 may be located between the upper surface of substrate 100 and the lower surface of bit line BL. Bit line BL may be insulated from substrate 100 by interlayer insulating layer 120. Interlayer insulating layer 120 may be located between multiple bit lines BL spaced apart along the second direction DR2.

[0071] The upper insulating layer 180 and the upper wiring layer 182 may be located on multiple semiconductor patterns 130, multiple bit lines BL, multiple word lines WL, multiple capacitors 170, and an interlayer insulating layer 120. The upper wiring layer 182 may be composed of multiple layers. The multiple layers of the upper wiring layer 182 may be spaced apart on a third direction DR3 via the upper insulating layer 180. Although not shown, the multiple layers of the upper wiring layer 182 may be connected via vias penetrating the upper insulating layer 180. Each layer of the upper wiring layer 182 may include multiple wirings, and the multiple wirings may be spaced apart on a first direction DR1 or a second direction DR2 via the upper insulating layer 180. The upper insulating layer 180 may be located between the multiple wirings.

[0072] The upper wiring layer 182 can be electrically connected to each of a plurality of bit lines BL, a plurality of word lines WL, and a plurality of capacitors 170. The upper wiring layer 182 may include a bit line pad BLP connected to the upper surface of the bit line BL. The upper wiring layer 182 can be connected to the plate electrode 174 of the capacitor 170. The upper wiring layer 182 can be connected to the word line WL via word line pads 510 and word line contacts 520, described later.

[0073] The first connection pad 192 and the first pad insulating layer 190 may be located on the upper insulating layer 180. The first connection pad 192 may be arranged on the upper insulating layer 180 in a direction parallel to the upper surface of the substrate 100. The first pad insulating layer 190 may surround the side surface of the first connection pad 192.

[0074] Multiple semiconductor patterns 130, multiple bit lines BL, multiple word lines WL, multiple capacitors 170, interlayer insulating layer 120, upper insulating layer 180, upper wiring layer 182, first pad insulating layer 190 and first connection pad 192 located on substrate 100 can form a unit structure CS.

[0075] A peripheral circuit structure PS can be located on a cell structure CS. The peripheral circuit structure PS may include a peripheral circuit substrate 300 and a transistor TR located on a first surface 300a of the peripheral circuit substrate 300. The transistor TR can form various driving circuits that generate signals that can drive memory cells within the cell structure CS. The driving circuit composed of the transistor TR may include, for example, a sense amplifier, a sub-word line driver, a row decoder, and a column decoder. A first wiring layer 322, a first wiring via 324, and a first wiring insulating layer 320 can be located on the transistor TR. The first wiring layer 322 may include multiple layers, and the multiple layers of the first wiring layer 322 may be spaced apart on a third-direction DR3 by the first wiring insulating layer 320. The first wiring via 324 may penetrate the first wiring insulating layer 320 to connect the multiple layers of the first wiring layer 322 on the third-direction DR3. The first wiring layer 322 can be connected to the gate electrode and source / drain regions of the transistor TR through the first wiring via 324. An external connection pad 332 can be located on the upper surface of the first wiring insulating layer 320. External connection pads 332 may be spaced apart on the first wiring insulating layer 320 in a direction parallel to the first surface 300a of the peripheral circuit substrate 300. Semiconductor devices may be connected to other devices via the external connection pads 332.

[0076] The second wiring layer 382 and the second wiring insulating layer 380 may be located on the second surface 300b of the peripheral circuit substrate 300 opposite to the first surface 300a. The second wiring insulating layer 380 may be located between the second surface 300b of the peripheral circuit substrate 300 and the second wiring layer 382. The second wiring layer 382 is shown as a single layer, but is not limited thereto, and may include multiple layers. In this case, the multiple layers of the second wiring layer 382 may be spaced apart on the third-direction DR3 by the second wiring insulating layer 380. Additionally, second wiring vias may be provided to connect the multiple layers of the second wiring layer 382 on the third-direction DR3.

[0077] A via 328 can be provided to connect the first circuit wiring layer 322 and the second circuit wiring layer 382. The via 328 can penetrate the first wiring insulating layer 320, the peripheral circuit substrate 300 and the second wiring insulating layer 380 to connect the first circuit wiring layer 322 and the second circuit wiring layer 382.

[0078] A second connection pad 392 and a second pad insulating layer 390 can be disposed on a second wiring insulating layer 380. The second connection pad 392 and the second pad insulating layer 390 can be disposed on opposite sides of the surface of the second wiring insulating layer 380 that contacts the second surface 300b of the peripheral circuit substrate 300. The second connection pad 392 can be arranged above the second wiring insulating layer 380 in a direction parallel to the second surface 300b of the peripheral circuit substrate 300. The second pad insulating layer 390 can surround the side surface of the second connection pad 392.

[0079] The second connection pad 392 can be bonded to the first connection pad 192, and the second pad insulating layer 390 can be bonded to the first pad insulating layer 190. The first connection pad 192 and the second connection pad 392 may include metallic materials, and the first pad insulating layer 190 and the second pad insulating layer 390 may include insulating materials. For example, the first connection pad 192 and the second connection pad 392 may include, but are not limited to, copper (Cu). Because the bonding between metallic materials and the bonding between insulating materials occur simultaneously, the bonding between the unit structure CS and the peripheral circuit structure PS can be called a hybrid bonding. For example, when the metallic material is copper (Cu), the bonding between the unit structure CS and the peripheral circuit structure PS can be called a Cu-Cu hybrid bonding.

[0080] The semiconductor device according to an embodiment may include word line pads 510 and word line contacts 520. Referring below... Figure 1 , Figure 2 and Figure 4 The word line pads 510 and word line contacts 520 are described in detail.

[0081] like Figure 1 , Figure 2 and Figure 4 As shown, word line pads 510 and word line contacts 520 can be located on the pad region PR of the substrate 100. Word line pads 510 can extend from word lines WL along a first direction DR1. Word line pads 510 can overlap with capacitors 170 in a second direction DR2. Word line pads 510 can connect to two word lines WL spaced apart in the first direction DR1, and two capacitors 170 are located between these two word lines WL. Word line pads 510 can connect to two word lines WL located on either side of the two capacitors 170 connected in the first direction DR1 along the first direction DR1.

[0082] Multiple word line pads 510 may be located between two word lines WL. Multiple word line pads 510 may be arranged spaced apart between the two word lines WL along a second direction DR2. Each word line pad among the multiple word line pads 510 may be connected between the two word lines WL. The multiple word line pads 510 may have the same length along a first direction DR1.

[0083] Multiple word line pads 510 may include word line pads 510 spaced apart along a third direction DR3. The word line pads 510 spaced apart along the third direction DR3 can extend from each of the multiple word lines WL spaced apart along the third direction DR3 along a first direction DR1. An interlayer insulating layer 120 may be located between the word line pads 510 spaced apart along the third direction DR3. The interlayer insulating layer 120 may be located between the lowest word line pad 510 and the substrate 100, or it may be located on the upper surface of the highest word line pad 510.

[0084] Word line contacts 520 may be located on word line pads 510. Multiple word line contacts 520 may be spaced apart on word line pads 510 along a first direction DR1. For example, three word line contacts 520 are shown spaced apart along the first direction DR1, but this is not a limitation. The number of word line contacts 520 spaced apart along the first direction DR1 may vary.

[0085] A plurality of word line contacts 520 spaced apart along a first direction DR1 can be located on a plurality of word line pads 510 spaced apart along a third direction DR3. The plurality of word line contacts 520 spaced apart along the first direction DR1 can be respectively connected to at least some of the plurality of word line pads 510 spaced apart along the third direction DR3. Each word line contact 520 spaced apart along the first direction DR1 can be connected to one of the plurality of word line pads 510 spaced apart along the third direction DR3. The plurality of word line contacts 520 spaced apart along the first direction DR1 can be respectively connected to word line pads 510 located on different layers.

[0086] The plurality of word line contacts 520 may include word line contacts 520 spaced apart along the second direction DR2. The word line contacts 520 spaced apart along the second direction DR2 may be respectively connected to word line pads 510 located on different layers. The word line contacts 520 spaced apart along the second direction DR2 may be respectively connected to word line pads 510 spaced apart along the second direction DR2. The word line contacts 520 spaced apart along the second direction DR2 may be located on different layers and respectively connected to word line pads 510 at different positions along the second direction DR2.

[0087] Each of the plurality of word line contacts 520 can be electrically connected to one of the plurality of word line pads 510. Each of the plurality of word line contacts 520 may include a columnar conductive layer 521 extending in a third direction DR3 and an insulating layer 522 surrounding the side surface of the conductive layer 521. The outer surface of the word line contact 520 may be formed by the insulating layer 522, while the upper and lower surfaces of the word line contact 520 may be formed by the conductive layer 521 and the insulating layer 522. For example, when the lower surface of the word line contact 520 contacts the upper surface of the word line pad 510, the word line contact 520 may be electrically connected to the word line pad 510. For example, when the word line contact 520 penetrates the word line pad 510 such that the outer surface of the word line contact 520 contacts the inner surface of the word line pad 510, the word line contact 520 may not be electrically connected to the word line pad 510.

[0088] The lower surface of each of the plurality of word line contacts 520 may contact the upper surface of a word line pad 510. The plurality of word line contacts 520 may include a word line contact 520 that contacts the upper surface of the uppermost word line pad 510, and a word line contact 520 that penetrates at least one word line pad 510 and contacts the upper surface of a word line pad 510 located below the at least one word line pad 510. The word line contact 520 connected to the uppermost word line pad 510 penetrates the interlayer insulating layer 120, such that the lower surface of the word line contact 520 may contact the upper surface of the uppermost word line pad 510. Word line contacts 520 connected to word line pads 510 other than the uppermost word line pad 510 may penetrate the interlayer insulating layer 120 and at least one word line pad 510 located above the word line pad 510.

[0089] The number of word line pads 510 penetrated by each of the plurality of word line contacts 520 may be different. The lengths of the plurality of word line contacts 520 along the third direction DR3 may differ from one another. For example, a word line contact 520 connected to a word line pad 510 located on a relatively lower layer may penetrate more word line pads 510. For example, the length of a word line contact 520 connected to a word line pad 510 located on a relatively lower layer along the third direction DR3 may be longer. A word line pad 510 located on a relatively lower layer may mean that the word line pad is relatively close to the upper surface of the substrate 100.

[0090] according to Figure 4 In the illustrated embodiment, the length of the word line contacts 520 spaced apart along the first direction DR1 can gradually increase. The word line contacts 520 spaced apart along the first direction DR1 can be connected to word line pads 510 located in a continuous layer.

[0091] For example, multiple word line pads 510 may include a first layer word line pad 510a, a second layer word line pad 510b, a third layer word line pad 510c, a fourth layer word line pad 510d, a fifth layer word line pad 510e, a sixth layer word line pad 510f, a seventh layer word line pad 510g, an eighth layer word line pad 510h, and a ninth layer word line pad 510i, spaced apart from each other on a third-direction DR3. The first layer word line pad 510a, the second layer word line pad 510b, the third layer word line pad 510c, the fourth layer word line pad 510d, the fifth layer word line pad 510e, the sixth layer word line pad 510f, the seventh layer word line pad 510g, the eighth layer word line pad 510h, and the ninth layer word line pad 510i may be sequentially adjacent to the upper surface of the substrate 100.

[0092] For example, a plurality of character line contacts 520 may include a first character line contact 520a, a second character line contact 520b, a third character line contact 520c, a fourth character line contact 520d, a fifth character line contact 520e, a sixth character line contact 520f, a seventh character line contact 520g, an eighth character line contact 520h, and a ninth character line contact 520i spaced apart from each other in the first direction DR1. The first character line contact 520a, the second character line contact 520b, and the third character line contact 520c may be spaced apart from each other in the first direction DR1. The fourth character line contact 520d, the fifth character line contact 520e, and the sixth character line contact 520f may be spaced apart in the first direction DR1. The seventh character line contact 520g, the eighth character line contact 520h, and the ninth character line contact 520i may be spaced apart in the first direction DR1. The first syllable contact portion 520a, the fourth syllable contact portion 520d, and the seventh syllable contact portion 520g can be arranged spaced apart along the second direction DR2. The second syllable contact portion 520b, the fifth syllable contact portion 520e, and the eighth syllable contact portion 520h can be arranged spaced apart along the second direction DR2. The third syllable contact portion 520c, the sixth syllable contact portion 520f, and the ninth syllable contact portion 520i can be arranged spaced apart along the second direction DR2.

[0093] For example, the first word line contact 520a can be connected to the ninth layer word line pad 510i (which is the uppermost word line pad). The second word line contact 520b can penetrate the ninth layer word line pad 510i and connect to the eighth layer word line pad 510h. The third word line contact 520c can connect to the seventh layer word line pad 510g by penetrating the ninth layer word line pad 510i and the eighth layer word line pad 510h. The number of word line pads 510 penetrated by the first word line contact 520a, the second word line contact 520b, and the third word line contact 520c can gradually increase. The length of the first word line contact 520a, the second word line contact 520b, and the third word line contact 520c along the third direction DR3 can gradually increase. The ninth layer word line pad 510i, the eighth layer word line pad 510h, and the seventh layer word line pad 510g, which are respectively connected to the first word line contact portion 520a, the second word line contact portion 520b, and the third word line contact portion 520c, can be located in consecutive layers.

[0094] For example, the fourth word line contact 520d can be connected to the sixth word line pad 510f by penetrating the ninth-layer word line pad 510i, the eighth-layer word line pad 510h, and the seventh-layer word line pad 510g. The fifth word line contact 520e can be connected to the fifth-layer word line pad 510e by penetrating the ninth-layer word line pad 510i, the eighth-layer word line pad 510h, the seventh-layer word line pad 510g, and the sixth-layer word line pad 510f. The sixth word line contact 520f can be connected to the fourth-layer word line pad 510d by penetrating the ninth-layer word line pad 510i, the eighth-layer word line pad 510h, the seventh-layer word line pad 510g, the sixth-layer word line pad 510f, and the fifth-layer word line pad 510e. The number of word line pads 510 penetrated by the fourth word line contact 520d, the fifth word line contact 520e, and the sixth word line contact 520f can be gradually increased. The lengths of the fourth word line contact 520d, the fifth word line contact 520e, and the sixth word line contact 520f along the third direction DR3 can gradually increase. The sixth layer word line pad 510f, the fifth layer word line pad 510e, and the fourth layer word line pad 510d, which are respectively connected to the fourth word line contact 520d, the fifth word line contact 520e, and the sixth word line contact 520f, can be located in consecutive layers.

[0095] For example, the seventh word line contact 520g can be connected to the third word line pad 510c by penetrating the ninth, eighth, seventh, sixth, fifth, and fourth word line pads 510i, 510h, 510g, 510f, 510e, and 510d. The eighth word line contact 520h can be connected to the second word line pad 510b by penetrating the ninth, eighth, seventh, sixth, fifth, and fourth word line pads 510d. The ninth word line contact 520i can connect to the first layer word line pad 510a by penetrating the ninth layer word line pad 510i, the eighth layer word line pad 510h, the seventh layer word line pad 510g, the sixth layer word line pad 510f, the fifth layer word line pad 510e, the fourth layer word line pad 510d, the third layer word line pad 510c, and the second layer word line pad 510b. The number of word line pads 510 penetrated by the seventh, eighth, and ninth word line contacts 520g, 520h, and 520i can gradually increase. The length of the seventh, eighth, and ninth word line contacts 520g, 520h, and 520i along the third direction DR3 can gradually increase. The third-layer word line pad 510c, the second-layer word line pad 510b, and the first-layer word line pad 510a, which are respectively connected to the seventh word line contact 520g, the eighth word line contact 520h, and the ninth word line contact 520i, can be located in a continuous layer.

[0096] However, it is not limited to the above embodiments. For example, in the plurality of word line contacts 520, the length of the word line contacts 520 arranged at intervals along the first direction DR1 can be gradually reduced.

[0097] Below, for reference Figures 5 to 8 Describe in detail the connection relationship between bit line BL and global bit line GBL.

[0098] like Figures 5 to 8 As shown, the semiconductor device according to an embodiment may include multiple global bit lines (GBLs) connected to and extending along a first direction DR1, multiple bit lines (BLs) spaced apart along the first direction DR1. The global bit lines (GBLs) may connect the multiple bit lines (BLs) spaced apart along the first direction DR1 and a sense amplifier within a peripheral circuit structure PS.

[0099] Multiple global bit lines (GBLs) may include a first global bit line (GBL1) and a second global bit line (GBL2). Multiple first global bit lines (GBL1) may be spaced apart along a second direction DR2. Multiple second global bit lines (GBL2) may be spaced apart along a second direction DR2. Multiple first global bit lines (GBL1) may be connected to bit lines (BL) spaced apart along the second direction DR2. Multiple second global bit lines (GBL2) may be connected to bit lines (BL) spaced apart along the second direction DR2.

[0100] The second global bit line GBL2 can be different from the first global bit line GBL1. In a plan view, the first global bit line GBL1 and the second global bit line GBL2 can be arranged spaced apart from each other in the second direction DR2. Two adjacent bit lines BL in the first direction DR1 can be connected to different global bit lines GBL. Multiple bit lines BL arranged spaced apart in the first direction DR1 can be alternately connected to the first global bit line GBL1 and the second global bit line GBL2.

[0101] The semiconductor device according to an embodiment may include a plurality of bit line pads (BLPs), each BLP located on the upper surface of a plurality of bit lines (BLs). The plurality of bit line pads (BLPs) may be spaced apart in a first direction DR1. Each of the plurality of bit line pads (BLPs) overlaps with a bit line (BL) in a third direction DR3 and may extend in a second direction DR2. Two adjacent bit line pads (BLPs) in the first direction DR1 may extend in opposite directions in the second direction DR2. For example, refer to... Figure 5 On the first direction DR1, one of the two adjacent bit line pads BLP can extend upwards, while the other can extend downwards.

[0102] Two adjacent bit line pads BLP on the first direction DR1 may include a first sub-bit line pad BLP1 connected to a first global bit line GBL1 and a second sub-bit line pad BLP2 connected to a second global bit line GBL2. A semiconductor device according to an embodiment may include a first sub-bit line contact CT1 connected between the first sub-bit line pad BLP1 and the first global bit line GBL1, and a second sub-bit line contact CT2 connected between the second sub-bit line pad BLP2 and the second global bit line GBL2. The first sub-bit line contact CT1 and the second sub-bit line contact CT2 may be located on one side and the other side of a plurality of bit lines BL spaced apart along the second direction DR2 relative to the first direction DR1. The first sub-bit line contact CT1 and the second sub-bit line contact CT2 may not overlap in the first direction DR1.

[0103] The first sub-bit line pad BLP1 and the second sub-bit line pad BLP2 can be located on the same layer. The first global bit line GBL1 and the second global bit line GBL2 can be located on different layers. The lengths of the first sub-bit line contact CT1 and the second sub-bit line contact CT2 can be different. For example, Figure 7 and Figure 8 As shown, when the second global bit line GBL2 is located on a layer relatively higher than the first global bit line GBL1, the length of the second sub-bit line contact CT2 can be greater than the length of the first sub-bit line contact CT1. The lengths of the first sub-bit line contact CT1 and the second sub-bit line contact CT2 can represent the length along the third direction DR3. Since the first global bit line GBL1 and the second global bit line GBL2 are located on different layers, signal interference between them can be reduced.

[0104] According to the above embodiment, two word lines WL located on both sides of two capacitors 170 along the first direction DR1 can be connected via word line pads 510. These two capacitors 170 are connected to each of two adjacent semiconductor patterns 130 along the first direction DR1. The two word lines WL connected via word line pads 510 can be simultaneously turned on / off. For example, when two memory cells (each connected to the two word lines WL connected via word line pads 510) are connected to the same global bit line GBL, it may be impossible to know which of the two memory cells the readout amplifier senses via the global bit line GBL. In this embodiment, two adjacent bit lines BL on the first direction DR1 are connected to different global bit lines GBL, such that two memory cells each connected to the two word lines WL connected via word line pads 510 can be connected to different global bit lines GBL. Accordingly, the values ​​stored in the two memory cells each connected to the two word lines WL connected via word line pads 510 can be read separately via different global bit lines GBL.

[0105] Based on the above references Figures 1 to 8The semiconductor device described in the embodiment includes: a plurality of word line pads 510 extending from a plurality of word lines WL along a first direction DR1, the first direction DR1 intersecting with a second direction DR2 along which the word lines WL extend; and a plurality of word line contacts 520 extending in a direction perpendicular to the upper surface of the substrate 100 and spaced apart from each other along the first direction DR1. At least some of the word line pads 510 are respectively connected to the plurality of word line contacts 520, and the lengths of the plurality of word line contacts 520 along the third direction DR3 may be different. Each of the plurality of word line pads 510 may connect to two word lines WL located on both sides of two capacitors 170 along the first direction DR1, the two capacitors 170 being respectively connected to two semiconductor patterns 130 adjacent to each other along the first direction DR1. The lengths of the plurality of word line pads 510 along the first direction DR1 may be the same. The plurality of word line contacts 520 may include a word line contact 520 connected to the uppermost word line pad 510, and a word line contact 520 connected to a word line pad 510 located below the at least one word line pad 510 by penetrating at least one word line pad 510.

[0106] According to a comparative example, a semiconductor device may include: a plurality of word line pads extending from each word line WL along a second direction DR2 along which the word line WL extends, having a stepped shape and varying lengths; and a plurality of word line contacts respectively connected to the upper surfaces of the plurality of word line pads without penetrating other word line pads, and spaced apart from each other along the second direction DR2. In the comparative example, since the plurality of word line pads extend from the word line WL along the second direction DR2, and the capacitor is located on one side of the first direction DR1 intersecting the second direction DR2 relative to the word line WL, the plurality of word line pads and the capacitor may not overlap.

[0107] In the comparative example, capacitors can occupy a relatively large area. According to the embodiment, by utilizing the remaining space between the two word lines WL located on both sides of the two capacitors 170 connected along the first direction DR1, the area of ​​the pad region PR where the plurality of word line pads 510 are located can be reduced.

[0108] Furthermore, in the semiconductor device according to the comparative example, the area occupied by the plurality of word line pads in the plan view increases with the increase of the number of layers of the plurality of memory cells stacked, while in the semiconductor device according to the embodiment, even if the number of layers of the plurality of memory cells stacked increases, the area occupied by the plurality of word line pads 510 in the plan view can be the same.

[0109] In the following text, reference will be made to Figures 9 to 11 Description based on Figures 1 to 8 A modified version of the semiconductor device shown in the embodiment.

[0110] Figure 9 It is along Figure 1 Cross-sectional views taken from the centerline B-B', line C-C', and line D-D'. Figure 10 It is along Figure 1 Cross-sectional views taken from the centerline B-B', line C-C', and line D-D'. Figure 11 It is along Figure 1 Cross-sectional views taken along centerlines B-B', C-C', and D-D'. Figures 9 to 11 In the illustrated embodiment, with Figures 1 to 8 Components that are identical or corresponding to each other can be represented by the same symbol. Figures 9 to 11 The illustrated embodiments can be used with Figures 1 to 8 The illustrated embodiment differs in the connection relationship between the plurality of word line contacts 520 and the plurality of word line pads 510. The following mainly describes the differences from the previous example, and omits or simplifies any repetitive descriptions.

[0111] according to Figure 9 In the illustrated embodiment, the length of the word line contacts 520 spaced apart along the second direction DR2 can gradually increase. The word line contacts 520 spaced apart along the second direction DR2 can be connected to word line pads 510 located in a continuous layer.

[0112] For example, the first word line contact 520a can be connected to the ninth layer word line pad 510i (which is the uppermost word line pad). The fourth word line contact 520d can penetrate the ninth layer word line pad 510i and connect to the eighth layer word line pad 510h. The seventh word line contact 520g can be connected to the seventh layer word line pad 510g by penetrating the ninth layer word line pad 510i and the eighth layer word line pad 510h. The number of word line pads 510 penetrated by the first word line contact 520a, the fourth word line contact 520d, and the seventh word line contact 520g can be gradually increased. The lengths of the first word line contact 520a, the fourth word line contact 520d, and the seventh word line contact 520g along the third direction DR3 can be gradually increased. The ninth layer word line pad 510i, the eighth layer word line pad 510h, and the seventh layer word line pad 510g, which are respectively connected to the first word line contact portion 520a, the fourth word line contact portion 520d, and the seventh word line contact portion 520g, can be located in consecutive layers.

[0113] For example, the second word line contact 520b can be connected to the sixth layer word line pad 510f by penetrating the ninth layer word line pad 510i, the eighth layer word line pad 510h, and the seventh layer word line pad 510g. The fifth word line contact 520e can be connected to the fifth layer word line pad 510e by penetrating the ninth layer word line pad 510i, the eighth layer word line pad 510h, the seventh layer word line pad 510g, and the sixth layer word line pad 510f. The eighth word line contact 520h can be connected to the fourth layer word line pad 510d by penetrating the ninth layer word line pad 510i, the eighth layer word line pad 510h, the seventh layer word line pad 510g, the sixth layer word line pad 510f, and the fifth layer word line pad 510e. The number of word line pads 510 penetrated by the second word line contact 520b, the fifth word line contact 520e, and the eighth word line contact 520h can be gradually increased. The lengths of the second word line contact 520b, the fifth word line contact 520e, and the eighth word line contact 520h along the third direction DR3 can gradually increase. The sixth layer word line pad 510f, the fifth layer word line pad 510e, and the fourth layer word line pad 510d, which are respectively connected to the second word line contact 520b, the fifth word line contact 520e, and the eighth word line contact 520h, can be located in consecutive layers.

[0114] For example, the third word line contact 520c can be connected to the third layer word line pad 510c by penetrating the ninth layer word line pad 510i, the eighth layer word line pad 510h, the seventh layer word line pad 510g, the sixth layer word line pad 510f, the fifth layer word line pad 510e, and the fourth layer word line pad 510d. The sixth word line contact 520f can be connected to the second layer word line pad 510b by penetrating the ninth layer word line pad 510i, the eighth layer word line pad 510h, the seventh layer word line pad 510g, the sixth layer word line pad 510f, the fifth layer word line pad 510e, the fourth layer word line pad 510d, and the third layer word line pad 510c. The ninth word line contact 520i can connect to the first layer word line pad 510a by penetrating the ninth layer word line pad 510i, the eighth layer word line pad 510h, the seventh layer word line pad 510g, the sixth layer word line pad 510f, the fifth layer word line pad 510e, the fourth layer word line pad 510d, the third layer word line pad 510c, and the second layer word line pad 510b. The number of word line pads 510 penetrated by the third word line contact 520c, the sixth word line contact 520f, and the ninth word line contact 520i can gradually increase. The length of the third word line contact 520c, the sixth word line contact 520f, and the ninth word line contact 520i along the third direction DR3 can gradually increase. The third-layer word line pad 510c, the second-layer word line pad 510b, and the first-layer word line pad 510a, which are respectively connected to the third word line contact 520c, the sixth word line contact 520f, and the ninth word line contact 520i, can be located in consecutive layers.

[0115] However, it is not limited to the above embodiments. For example, in the plurality of word line contacts 520, the length of the word line contacts 520 arranged at intervals along the second direction DR2 can be gradually reduced.

[0116] according to Figure 10 In the embodiment shown, among the plurality of word line contacts 520, the shortest word line contact 520 and the longest word line contact 520 can be arranged along the first direction DR1.

[0117] For example, the diameter of the word line contact 520 can increase as its length extends along the third direction DR3. The longer the word line contact 520 extends along the third direction DR3, the more word line pads 510 it penetrates. As the length of the word line contact 520 increases along the third direction DR3, the word line pads 510 connected to the word line contact 520 can be located at lower layers. The diameter of the word line contact 520 connected to the relatively lower word line pad 510 can be larger than the diameter of the word line contact 520 connected to the relatively higher word line pad 510. Correspondingly, the diameter of the word line contact 520 connected to the uppermost word line pad 510 can be the smallest, while the diameter of the word line contact 520 connected to the lowermost word line pad 510 can be the largest. For example, the diameter of the word line contact 520 can gradually decrease as it approaches the upper surface of the substrate 100. In an embodiment, the diameter of the word line contact portion 520 may refer to the diameter of the top of the word line contact portion 520 or its maximum diameter.

[0118] For example, among a plurality of word line contacts 520, the word line contacts 520 arranged along the first direction DR1 may include a first word line contact 520a having the shortest length along the third direction DR3 and a third word line contact 520c having the longest length along the third direction DR3. The first word line contact 520a having the shortest length along the third direction DR3 and the third word line contact 520c having the longest length along the third direction DR3 may be arranged along the first direction DR1. The first word line contact 520a connected to the ninth layer word line pad 510i (which is the uppermost word line pad) and the third word line contact 520c connected to the first layer word line pad 510a (which is the lowermost word line pad) may be arranged along the first direction DR1. The first word line contact 520a having the smallest diameter and the third word line contact 520c having the largest diameter may be arranged along the first direction DR1.

[0119] For example, among the multiple word line contacts 520, the nth (n≥1) shortest word line contact 520 and the nth longest word line contact 520 can be arranged along the first direction DR1. The word line contact 520 connected to the nth (n≥1) uppermost word line pad 510 among the multiple word line pads 510 and the word line contact 520 connected to the nth (n≥1) lowermost word line pad 510 among the multiple word line pads 510 can be arranged along the first direction DR1.

[0120] For example, the second shortest fourth word line contact 520d and the second longest sixth word line contact 520f among the plurality of word line contacts 520 can be arranged along the first direction DR1. The fourth word line contact 520d connected to the eighth layer word line pad 510h located at the second highest layer among the plurality of word line pads 510 and the sixth word line contact 520f connected to the second layer word line pad 510b located at the second lowest layer among the plurality of word line pads 510 can be arranged along the first direction DR1.

[0121] For example, the third shortest seventh word line contact 520g and the third longest ninth word line contact 520i among the plurality of word line contacts 520 can be arranged along the first direction DR1. The seventh word line contact 520g, which is connected to the seventh layer word line pad 510g located in the third highest layer among the plurality of word line pads 510, and the ninth word line contact 520i, which is connected to the third layer word line pad 510c located in the third lowest layer among the plurality of word line pads 510, can be arranged along the first direction DR1.

[0122] Among the multiple word line contacts 520, the longest nth (n≥1) word line contact 520 and the shortest nth (n≥1) word line contact 520 are arranged along the first direction DR1. This means that among the multiple word line contacts 520, the word line contact 520 with the largest (n≥1) diameter and the word line contact 520 with the smallest (n≥1) diameter are arranged along the first direction DR1. By arranging the word line contact 520 with the largest (n≥1) diameter and the word line contact 520 with the smallest (n≥1) diameter along the first direction DR1, short circuits between the word line contacts 520 arranged along the first direction DR1 can be reduced or prevented.

[0123] according to Figure 11 The illustrated embodiment, and Figure 4 Similar to the illustrated embodiment, the length of the word line contacts 520 spaced apart from each other in the first direction DR1 can gradually increase. The word line contacts 520 spaced apart along the first direction DR1 can be connected to word line pads 510 located in a continuous layer.

[0124] according to Figure 11 The illustrated embodiment, and Figure 4 Unlike the illustrated embodiment, in the plurality of word line contacts 520, the word line contacts 520 spaced apart in the second direction DR2 have a longer length as they are farther from the cell region CR. In the plurality of word line contacts 520, the word line contacts 520 spaced apart in the second direction DR2 can connect to the word line pads 510 located on a lower layer as they are farther from the cell region CR. (See also...) Figure 1The cell region CR can be the area containing multiple semiconductor patterns 130, bit lines BL, multiple capacitors 170, and multiple word lines WL, while the pad region PR can be the area containing multiple word line pads 510. The pad region PR can be located on one side of the cell region CR along the second direction DR2. For example, multiple cell regions CR can be spaced apart along the second direction DR2, and the pad region PR can be located between the multiple cell regions CR spaced apart along the second direction DR2. Among the word line contacts 520 spaced apart along the second direction DR2, the word line contact 520 farthest from the cell region CR can have the longest length. Among the word line contacts 520 spaced apart along the second direction DR2, the word line pad 510 connected to the word line contact 520 farthest from the cell region CR can be located on the lowest layer.

[0125] For example, the first word line contact 520a can be connected to the ninth layer word line pad 510i, the fourth word line contact 520d can be connected to the third layer word line pad 510c, and the seventh word line contact 520g can be connected to the sixth layer word line pad 510f. Among the first word line contacts 520a, fourth word line contacts 520d, and seventh word line contacts 520g arranged at intervals along the second direction DR2, the fourth word line contact 520d, which is farthest from the cell region CR, can have the longest length along the third direction DR3. The third layer word line pad 510c, which is connected to the fourth word line contact 520d, which is farthest from the cell region CR among the first word line contacts 520a, fourth word line contacts 520d, and seventh word line contacts 520g, can be located on the lowest layer.

[0126] For example, the second word line contact 520b can be connected to the eighth layer word line pad 510h, the fifth word line contact 520e can be connected to the second layer word line pad 510b, and the eighth word line contact 520h can be connected to the fifth layer word line pad 510e. Among the second word line contacts 520b, fifth word line contacts 520e, and eighth word line contacts 520h spaced apart in the second direction DR2, the fifth word line contact 520e, which is farthest from the cell region CR, can have the longest length along the third direction DR3. The second layer word line pad 510b connected to the fifth word line contact 520e, which is farthest from the cell region CR among the second word line contacts 520b, fifth word line contacts 520e, and eighth word line contacts 520h, can be located on the lowest layer.

[0127] For example, the third word line contact 520c can be connected to the seventh layer word line pad 510g, the sixth word line contact 520f can be connected to the first layer word line pad 510a, and the ninth word line contact 520i can be connected to the fourth layer word line pad 510d. Among the third word line contact 520c, the sixth word line contact 520f, and the ninth word line contact 520i, which are spaced apart from the cell region CR and arranged along the second direction DR2, the sixth word line contact 520f can have the longest length along the third direction DR3.

[0128] The first layer word line pad 510a, which is connected to the sixth word line contact 520f, which is furthest from the cell region CR among the third word line contact 520c, the sixth word line contact 520f, and the ninth word line contact 520i, can be located on the lowest layer.

[0129] In the above embodiment, when the cell region CR is located on both sides of the pad region PR along the second direction DR2, among the word line contacts 520 spaced apart along the second direction DR2, the middle word line contact 520 can be the furthest from the cell region CR. However, the example is not limited to this. For example, when the cell region CR is only located on one side of the pad region PR along the second direction DR2, the length of the word line contacts 520 spaced apart along the second direction DR2 can increase as they are farther away from the cell region CR along the second direction DR2.

[0130] In the following text, reference will be made to Figures 12 to 15 Description based on Figures 1 to 8 A modified version of the semiconductor device shown in the embodiment.

[0131] Figure 12 This is a plan view of a semiconductor device according to an embodiment. Figure 13 It is along Figure 12 A cross-sectional view taken along the midline H-H'. Figure 14 It is along Figure 12 A cross-sectional view taken along the centerline I-I'. Figure 15 It is along Figure 12 Cross-sectional views taken from centerlines J-J', K-K', and L-L'. Figures 12 to 15 In the illustrated embodiment, with Figures 1 to 8 Components that are identical or corresponding to each other can be represented by the same symbol. Figures 12 to 15 The illustrated embodiments can be used with Figures 1 to 8 The embodiment shown differs in some respects: multiple unit structures CS1 and CS2 are stacked together. The following description mainly focuses on the differences from the previous examples, omitting or simplifying any repetitive descriptions.

[0132] like Figures 12 to 15As shown, multiple cell structures CS1 and CS2 can be located on the substrate 100. For example, the multiple cell structures CS1 and CS2 may include, but are not limited to, a first cell structure CS1 and a second cell structure CS2. For example, the multiple cell structures CS1 and CS2 may include three or more cell structures. The first cell structure CS1 and the second cell structure CS2 may be stacked sequentially on the substrate 100. Each cell structure in the multiple cell structures CS1 and CS2 may include multiple semiconductor patterns 130, bit lines BL, multiple capacitors 170, multiple word lines WL, and multiple word line pads 510.

[0133] The first cell structure CS1 may include multiple first semiconductor patterns 130_1, first bit lines BL_1, multiple first capacitors 170_1, multiple first word lines WL_1, and multiple first word line pads 510_1. The first cell structure CS1 may include multiple first bit lines BL_1. The first cell structure CS1 may include multiple first bit line pads BLP_1. The first cell structure CS1 may include multiple first gate insulating layers Gox_1. The first cell structure CS1 may include a first interlayer insulating layer 120_1.

[0134] The second cell structure CS2 may include multiple second semiconductor patterns 130_2, second bit lines BL_2, multiple second capacitors 170_2, multiple second word lines WL_2, and multiple second word line pads 510_2. The second cell structure CS2 may include multiple second bit lines BL_2. The second cell structure CS2 may include multiple second bit line pads BLP_2. The second cell structure CS2 may include multiple second gate insulating layers Gox_2. The second cell structure CS2 may include a second interlayer insulating layer 120_2.

[0135] The first semiconductor pattern 130_1 and the second semiconductor pattern 130_2 can be collectively referred to as semiconductor pattern 130. The first bit line BL_1 and the second bit line BL_2 can be collectively referred to as bit line BL. The first bit line pad BLP_1 and the second bit line pad BLP_2 can be collectively referred to as bit line pad BLP. The first capacitor 170_1 and the second capacitor 170_2 can be collectively referred to as capacitor 170. The first word line WL_1 and the second word line WL_2 can be collectively referred to as word line WL. The first gate insulating layer Gox_1 and the second gate insulating layer Gox_2 can be collectively referred to as gate insulating layer Gox. The first word line pad 510_1 and the second word line pad 510_2 can be collectively referred to as word line pad 510. Figures 12 to 15The first interlayer insulating layer 120_1 and the second interlayer insulating layer 120_2 shown can be collectively referred to as interlayer insulating layer 120. The semiconductor pattern 130, bit line BL, bit line pad BLP, capacitor 170, word line WL, gate insulating layer Gox, word line pad 510, and interlayer insulating layer 120 can be applied in the same or similar manner. Figures 1 to 8 The contents described in the illustrated embodiments are referenced to the same reference numerals.

[0136] The second unit structure CS2 may include an upper insulating layer 180 and an upper wiring layer 182. The second unit structure CS2 may include a first pad insulating layer 190 and a first connection pad 192. The upper insulating layer 180, upper wiring layer 182, first pad insulating layer 190, and first connection pad 192 can be applied to… Figures 1 to 8 The contents described in the illustrated embodiments are the same or similar to those described with reference to the same reference numerals.

[0137] The peripheral circuit structure PS can be located on top of multiple unit structures CS1 and CS2. The peripheral circuit structure PS can also be located on the second unit structure CS2. The peripheral circuit structure PS may include a peripheral circuit substrate 300 and a transistor TR located on a first surface 300a of the peripheral circuit substrate 300. A first wiring layer 322, a first wiring via 324, and a first wiring insulating layer 320 can be located on the transistor TR. An external connection pad 332 can be located on the upper surface of the first wiring insulating layer 320. A second wiring layer 382 and a second wiring insulating layer 380 can be located on a second surface 300b of the peripheral circuit substrate 300 opposite to the first surface 300a. A via 328 can be provided to connect the first wiring layer 322 and the second wiring layer 382. A second pad insulating layer 390 and a second connection pad 392 can be provided on the second wiring insulating layer 380. The same or similar principles can be applied to the peripheral circuit structure PS and its components. Figures 1 to 8 The contents described in the illustrated embodiments are referenced to the same reference numerals.

[0138] The peripheral circuit structure PS can be connected to the second unit structure CS2. The first connection pad 192 and the second connection pad 392 can be bonded, and the first pad insulating layer 190 and the second pad insulating layer 390 can be bonded. The first connection pad 192 and the second connection pad 392 may include metallic materials, and the first pad insulating layer 190 and the second pad insulating layer 390 may include insulating materials. Because the bonding between metallic materials and the bonding between insulating materials occur simultaneously, the bonding between the peripheral circuit structure PS and the second unit structure CS2 can be called a hybrid bonding. For example, when the metallic material is copper (Cu), the bonding between the peripheral circuit structure PS and the second unit structure CS2 can be called a Cu-Cu hybrid bonding.

[0139] Substrate 100 may include cell regions CR and pad regions PR. Substrate 100 may include a plurality of cell regions CR spaced apart along a second direction DR2, and the pad regions PR may be located between the plurality of cell regions CR spaced apart along the second direction DR2. A plurality of semiconductor patterns 130, a plurality of bit lines BL, a plurality of capacitors 170, and a plurality of word lines WL may be located on the cell regions CR of substrate 100. A plurality of word line pads 510 may be located on the pad regions PR of substrate 100. A plurality of word line contacts 520 may be located on the pad regions PR of substrate 100.

[0140] The following description of word line pad 510 also applies to each of the first word line pad 510_1 and the second word line pad 510_2.

[0141] Multiple word lines WL can extend further into pad region PR. Each word line pad 510 can extend from a portion of the multiple word lines WL located within pad region PR along a first direction DR1. Each word line pad 510 can overlap with capacitor 170 along a second direction DR2. Each word line pad 510 can connect two word lines WL located on either side of two capacitors 170, which are respectively connected to two semiconductor patterns 130 adjacent to each other along the first direction DR1. The multiple word line pads 510 can be spaced apart between two word lines WL along the second direction DR2.

[0142] Multiple word line contacts 520 can be arranged spaced apart along the first direction DR1 on the word line pads 510 connecting two word lines WL. For example, Figure 12 and Figure 15 As shown, the two word line contacts 520 can be arranged spaced apart along the first direction DR1 on the word line pad 510, but are not limited thereto. The number of word line contacts 520 spaced apart along the first direction DR1 and arranged on the word line pad 510 can vary.

[0143] Multiple word line contacts 520 spaced apart along the second direction DR2 can be located on multiple word line pads 510 spaced apart along the second direction DR2 between two word lines WL.

[0144] Each of the plurality of word line contacts 520 can be electrically connected to one of the plurality of first word line pads 510_1 and the plurality of second word line pads 510_2. The word line contact 520 can be connected to either the first word line pad 510_1 or the second word line pad 510_2.

[0145] Each of the plurality of word line contacts 520 may include a conductive layer 521 extending in a third direction DR3 and an insulating layer 522 surrounding the side surface of the conductive layer 521. The outer surface of the word line contact 520 may be formed of the insulating layer 522, while the upper and lower surfaces of the word line contact 520 may be formed of the conductive layer 521 and the insulating layer 522. For example, when the lower surface of the word line contact 520 contacts the upper surface of the first word line pad 510_1 or the second word line pad 510_2, the word line contact 520 may be electrically connected to the first word line pad 510_1 or the second word line pad 510_2. For example, when the word line contact portion 520 penetrates the first word line pad 510_1 or the second word line pad 510_2, and the outer surface of the word line contact portion 520 contacts the inner surface of the first word line pad 510_1 or the second word line pad 510_2, the word line contact portion 520 may not be electrically connected to the first word line pad 510_1 or the second word line pad 510_2.

[0146] The lower surface of each of the plurality of word line contacts 520 may contact the upper surface of the first word line pad 510_1 or the upper surface of the second word line pad 510_2. The plurality of word line contacts 520 may include: a word line contact 520 that contacts the upper surface of the uppermost second word line pad 510_2; a word line contact 520 that penetrates at least one second word line pad 510_2 and contacts the upper surface of the second word line pad 510_2 or the upper surface of the first word line pad 510_1 located below the at least one second word line pad 510_2; and a word line contact 520 that penetrates all second word line pads 510_2 and at least one first word line pad 510_1 and contacts the upper surface of the first word line pad 510_1 located below the at least one first word line pad 510_1. The word line contact 520 connected to the uppermost second word line pad 510_2 penetrates the second interlayer insulating layer 120_2, allowing the lower surface of the word line contact 520 to contact the upper surface of the uppermost second word line pad 510_2. The word line contact 520 connected to a second word line pad 510_2 other than the uppermost second word line pad 510_2 can penetrate the second interlayer insulating layer 120_2 and at least one second word line pad 510_2 located above that second word line pad 510_2. The word line contact 520 connected to the uppermost first word line pad 510_1 penetrates the second interlayer insulating layer 120_2, all second word line pads 510_2, and the first interlayer insulating layer 120_1, allowing the lower surface of the word line contact 520 to contact the upper surface of the uppermost first word line pad 510_1. The word line contact 520 connected to the first word line pad 510_1 other than the uppermost first word line pad 510_1 can penetrate the second interlayer insulation layer 120_2, the first interlayer insulation layer 120_1, all the second word line pads 510_2, and at least one first word line pad 510_1 located above the first word line pad 510_1.

[0147] The number of first word line pads 510_1 and second word line pads 510_2 penetrated by each of the plurality of word line contacts 520 can be different. The lengths of the plurality of word line contacts 520 along the third direction DR3 can be different. For example, a word line contact 520 connected to a first word line pad 510_1 or a second word line pad 510_2 located on a relatively lower layer can penetrate more of the first word line pad 510_1 and / or the second word line pad 510_2. For example, the length of a word line contact 520 connected to a first word line pad 510_1 or a second word line pad 510_2 located on a relatively lower layer along the third direction DR3 can be longer. A first word line pad 510_1 or a second word line pad 510_2 located on a relatively lower layer can mean a word line pad relatively close to the upper surface of the substrate 100.

[0148] according to Figure 15In the illustrated embodiment, the length of the word line contacts 520 spaced apart along the first direction DR1 can gradually increase. The word line contacts 520 spaced apart along the first direction DR1 can be connected to word line pads 510 located in a continuous layer.

[0149] For example, a plurality of word line pads 510 may include a first layer word line pad 510_1a, a second layer word line pad 510_1b, a third layer word line pad 510_1c, a fourth layer word line pad 510_2a, a fifth layer word line pad 510_2b, and a sixth layer word line pad 510_2c spaced apart from each other along a third direction DR3. The first layer word line pad 510_1a, the second layer word line pad 510_1b, the third layer word line pad 510_1c, the fourth layer word line pad 510_2a, the fifth layer word line pad 510_2b, and the sixth layer word line pad 510_2c may be adjacent to the upper surface of the substrate 100 in this order. The first layer word line pad 510_1a, the second layer word line pad 510_1b, and the third layer word line pad 510_1c can be included in the first unit structure CS1, and the fourth layer word line pad 510_2a, the fifth layer word line pad 510_2b, and the sixth layer word line pad 510_2c can be included in the second unit structure CS2.

[0150] For example, a plurality of character line contacts 520 may include a first character line contact 520a, a second character line contact 520b, a third character line contact 520c, a fourth character line contact 520d, a fifth character line contact 520e, and a sixth character line contact 520f spaced apart from each other in a first direction DR1 and a second direction DR2. The first character line contact 520a and the second character line contact 520b may be arranged spaced apart from each other in the first direction DR1. The third character line contact 520c and the fourth character line contact 520d may be arranged spaced apart from each other in the first direction DR1. The fifth character line contact 520e and the sixth character line contact 520f may be arranged spaced apart from each other in the first direction DR1. The first character line contact 520a, the third character line contact 520c, and the fifth character line contact 520e may be arranged spaced apart along the second direction DR2. The second syllable contact portion 520b, the fourth syllable contact portion 520d, and the sixth syllable contact portion 520f can be arranged at intervals along the second direction DR2.

[0151] For example, the first word line contact 520a can be connected to the sixth layer word line pad 510_2c (which is the topmost word line pad). The second word line contact 520b can be connected to the fifth layer word line pad 510_2b by penetrating the sixth layer word line pad 510_2c. The number of word line pads 510 penetrated by the first word line contact 520a and the second word line contact 520b can gradually increase. The lengths of the first word line contact 520a and the second word line contact 520b along the third direction DR3 can gradually increase. The sixth layer word line pad 510_2c and the fifth layer word line pad 510_2b, which are respectively connected to the first word line contact 520a and the second word line contact 520b, can be located in consecutive layers.

[0152] For example, the third word line contact 520c can be connected to the fourth word line pad 510_2a by penetrating the sixth layer word line pad 510_2c and the fifth layer word line pad 510_2b. The fourth word line contact 520d can be connected to the third layer word line pad 510_1c by penetrating the sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, and the fourth layer word line pad 510_2a. The number of word line pads 510 penetrated by the third word line contact 520c and the fourth word line contact 520d can gradually increase. The lengths of the third word line contact 520c and the fourth word line contact 520d along the third direction DR3 can gradually increase. The fourth layer word line pad 510_2a and the third layer word line pad 510_1c connected to the third word line contact 520c and the fourth word line contact 520d, respectively, can be located in consecutive layers.

[0153] For example, the fifth word line contact 520e can connect to the second layer word line pad 510_1b by penetrating the sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, the fourth layer word line pad 510_2a, and the third layer word line pad 510_1c. The sixth word line contact 520f can connect to the first layer word line pad 510_1a by penetrating the sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, the fourth layer word line pad 510_2a, the third layer word line pad 510_1c, and the second layer word line pad 510_1b. The number of word line pads 510 penetrated by the fifth and sixth word line contacts 520e and 520f can gradually increase. The lengths of the fifth and sixth word line contacts 520e and 520f along the third direction DR3 can gradually increase. The second layer word line pad 510_1b and the first layer word line pad 510_1a, which are respectively connected to the fifth word line contact 520e and the sixth word line contact 520f, can be located in a continuous layer.

[0154] However, it is not limited to the above embodiments. For example, in the plurality of word line contacts 520, the length of the word line contacts 520 arranged at intervals along the first direction DR1 can be gradually reduced.

[0155] In the following text, reference will be made to Figures 16 to 19 Description based on Figures 12 to 15 Example of modification of the semiconductor device in the illustrated embodiment.

[0156] Figure 16 It is along Figure 12 Cross-sectional views taken from the centerline J-J', line K-K', and line L-L'. Figure 17 It is along Figure 12 Cross-sectional views taken from the centerline J-J', line K-K', and line L-L'. Figure 18 It is along Figure 12 Cross-sectional views taken from the centerline J-J', line K-K', and line L-L'. Figure 19 It is along Figure 12 Cross-sectional views taken from centerlines J-J', K-K', and L-L'. Figures 16 to 19 In the illustrated embodiment, with Figures 12 to 15 Components that are identical or corresponding to each other can be represented by the same symbol. Figures 16 to 19 The illustrated embodiments can be used with Figures 12 to 15 The illustrated embodiment differs in the connection relationship between the plurality of word line contacts 520 and the plurality of word line pads 510. The following mainly describes the differences from the previous example, and omits or simplifies any repetitive descriptions.

[0157] according to Figure 16 In the embodiments shown, word line pads 510 connected to word line contacts 520 spaced apart along the first direction DR1 can be included in different unit structures.

[0158] The first word line contact portion 520a and the second word line contact portion 520b, which are arranged at intervals along the first direction DR1, can be connected to the second word line pad 510_2 included in the second unit structure CS2 and the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the first word line contact portion 520a can be connected to the sixth layer word line pad 510_2c included in the second unit structure CS2, and the second word line contact portion 520b can be connected to the third layer word line pad 510_1c included in the first unit structure CS1.

[0159] The third word line contact portion 520c and the fourth word line contact portion 520d, which are arranged at intervals along the first direction DR1, can be connected to the second word line pad 510_2 included in the second unit structure CS2 and the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the third word line contact portion 520c can be connected to the fifth layer word line pad 510_2b included in the second unit structure CS2, and the fourth word line contact portion 520d can be connected to the second layer word line pad 510_1b included in the first unit structure CS1.

[0160] The fifth word line contact portion 520e and the sixth word line contact portion 520f, which are spaced apart along the first direction DR1, can be connected to the second word line pad 510_2 included in the second unit structure CS2 and the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the fifth word line contact portion 520e can be connected to the fourth layer word line pad 510_2a included in the second unit structure CS2, and the sixth word line contact portion 520f can be connected to the first layer word line pad 510_1a included in the first unit structure CS1.

[0161] According to an embodiment, word line pads 510 that are respectively connected to word line contacts 520 arranged at intervals along the second direction DR2 may be included in the same unit structure.

[0162] The first word line contact portion 520a, the third word line contact portion 520c, and the fifth word line contact portion 520e, which are spaced apart along the second direction DR2, can be connected to the second word line pad 510_2 included in the second unit structure CS2, respectively. For example, the first word line contact portion 520a can be connected to the sixth layer word line pad 510_2c included in the second unit structure CS2, the third word line contact portion 520c can be connected to the fifth layer word line pad 510_2b included in the second unit structure CS2, and the fifth word line contact portion 520e can be connected to the fourth layer word line pad 510_2a included in the second unit structure CS2.

[0163] The second word line contact portion 520b, the fourth word line contact portion 520d, and the sixth word line contact portion 520f, which are spaced apart along the second direction DR2, can be connected to the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the second word line contact portion 520b can be connected to the third layer word line pad 510_1c included in the first unit structure CS1, the fourth word line contact portion 520d can be connected to the second layer word line pad 510_1b included in the first unit structure CS1, and the sixth word line contact portion 520f can be connected to the first layer word line pad 510_1a included in the first unit structure CS1.

[0164] According to an embodiment, the length of the plurality of word line contacts 520 spaced apart along the second direction DR2 can gradually increase along the second direction DR2. The word line contacts 520 spaced apart along the second direction DR2 can be connected to word line pads 510 located in a continuous layer.

[0165] For example, the first word line contact 520a can be connected to the sixth layer word line pad 510_2c (which is the topmost word line pad of the second unit structure CS2). The third word line contact 520c can be connected to the fifth layer word line pad 510_2b by penetrating the sixth layer word line pad 510_2c. The fifth word line contact 520e can be connected to the fourth layer word line pad 510_2a by penetrating both the sixth layer word line pad 510_2c and the fifth layer word line pad 510_2b. The number of word line pads 510 penetrated by the first, third, and fifth word line contacts 520a, 520c, and 520e can gradually increase. The lengths of the first, third, and fifth word line contacts 520a, 520c, and 520e along the third direction DR3 can gradually increase. The sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, and the fourth layer word line pad 510_2a, which are respectively connected to the first word line contact portion 520a, the third word line contact portion 520c, and the fifth word line contact portion 520e, can be located in consecutive layers.

[0166] For example, the second word line contact 520b can be connected to the third word line pad 510_1c (which is the topmost word line pad of the first unit structure CS1) by penetrating the sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, and the fourth layer word line pad 510_2a. The fourth word line contact 520d can be connected to the second layer word line pad 510_1b by penetrating the sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, the fourth layer word line pad 510_2a, and the third layer word line pad 510_1c. The sixth word line contact 520f can be connected to the first layer word line pad 510_1a by penetrating the sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, the fourth layer word line pad 510_2a, the third layer word line pad 510_1c, and the second layer word line pad 510_1b. The number of word line pads 510 penetrated by the second word line contact 520b, the fourth word line contact 520d, and the sixth word line contact 520f can be gradually increased. The lengths of the second word line contact 520b, the fourth word line contact 520d, and the sixth word line contact 520f along the third direction DR3 can be gradually increased. The third layer word line pad 510_1c, the second layer word line pad 510_1b, and the first layer word line pad 510_1a, which are respectively connected to the second word line contact 520b, the fourth word line contact 520d, and the sixth word line contact 520f, can be located in consecutive layers.

[0167] However, it is not limited to the above embodiments. For example, in the plurality of word line contacts 520, the length of the word line contacts 520 arranged at intervals along the second direction DR2 can be gradually reduced.

[0168] according to Figure 17 The illustrated embodiment, and Figure 16 Similar to the embodiments shown, word line pads 510 connected to word line contacts 520 spaced apart along the first direction DR1 can be included in different unit structures.

[0169] The first word line contact portion 520a and the second word line contact portion 520b, which are arranged at intervals along the first direction DR1, can be connected to the second word line pad 510_2 included in the second unit structure CS2 and the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the first word line contact portion 520a can be connected to the sixth layer word line pad 510_2c included in the second unit structure CS2, and the second word line contact portion 520b can be connected to the third layer word line pad 510_1c included in the first unit structure CS1.

[0170] The third word line contact portion 520c and the fourth word line contact portion 520d, which are arranged at intervals along the first direction DR1, can be connected to the second word line pad 510_2 included in the second unit structure CS2 and the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the third word line contact portion 520c can be connected to the fourth layer word line pad 510_2a included in the second unit structure CS2, and the fourth word line contact portion 520d can be connected to the first layer word line pad 510_1a included in the first unit structure CS1.

[0171] The fifth word line contact portion 520e and the sixth word line contact portion 520f, which are arranged at intervals along the first direction DR1, can be connected to the second word line pad 510_2 included in the second unit structure CS2 and the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the fifth word line contact portion 520e can be connected to the fifth layer word line pad 510_2b included in the second unit structure CS2, and the sixth word line contact portion 520f can be connected to the second layer word line pad 510_1b included in the first unit structure CS1.

[0172] According to the embodiments, with Figure 16 Similar to the embodiments shown, word line pads 510 connected to word line contacts 520 spaced apart along the second direction DR2 can be included in the same unit structure.

[0173] The first word line contact portion 520a, the third word line contact portion 520c, and the fifth word line contact portion 520e, which are spaced apart along the second direction DR2, can be connected to the second word line pad 510_2 included in the second unit structure CS2, respectively. For example, the first word line contact portion 520a can be connected to the sixth layer word line pad 510_2c included in the second unit structure CS2, the third word line contact portion 520c can be connected to the fourth layer word line pad 510_2a included in the second unit structure CS2, and the fifth word line contact portion 520e can be connected to the fifth layer word line pad 510_2b included in the second unit structure CS2.

[0174] The second word line contact portion 520b, the fourth word line contact portion 520d, and the sixth word line contact portion 520f, which are spaced apart along the second direction DR2, can be connected to the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the second word line contact portion 520b can be connected to the third layer word line pad 510_1c included in the first unit structure CS1, the fourth word line contact portion 520d can be connected to the first layer word line pad 510_1a included in the first unit structure CS1, and the sixth word line contact portion 520f can be connected to the second layer word line pad 510_1b included in the first unit structure CS1.

[0175] According to the embodiments, with Figure 16 Unlike the illustrated embodiment, in the plurality of word line contacts 520, the word line contacts 520 spaced apart along the second direction DR2 are longer the farther they are from the cell region CR. Among the plurality of word line contacts 520, the word line contacts 520 spaced apart along the second direction DR2 may have word line pads 510 connected to the word line contacts 520, wherein the farther the word line contacts 520 are from the cell region CR, the lower the layer in which the word line pads 510 connected to the word line contacts 520 are located. (See also...) Figure 12 The cell region CR can be the area containing multiple semiconductor patterns 130, bit lines BL, multiple capacitors 170, and multiple word lines WL, while the pad region PR can be the area containing multiple word line pads 510. The pad region PR can be located on one side of the cell region CR along the second direction DR2. For example, multiple cell regions CR can be spaced apart along the second direction DR2, and the pad region PR can be located between the multiple cell regions CR spaced apart along the second direction DR2. Among the word line contacts 520 spaced apart along the second direction DR2, the word line contact 520 farthest from the cell region CR can have the longest length. Among the word line contacts 520 spaced apart along the second direction DR2, the word line pad 510 connected to the word line contact 520 farthest from the cell region CR can be located on the lowest layer.

[0176] For example, the first word line contact 520a can be connected to the sixth layer word line pad 510_2c, the third word line contact 520c can be connected to the fourth layer word line pad 510_2a, and the fifth word line contact 520e can be connected to the fifth layer word line pad 510_2b. The fourth layer word line pad 510_2a can be the second word line pad 510_2 located at the lowest layer within the second unit structure CS2. Among the first word line contact 520a, the third word line contact 520c, and the fifth word line contact 520e arranged at intervals along the second direction DR2, the third word line contact 520c, which is farthest from the unit region CR, can have the longest length along the third direction DR3. The fourth layer word line pad 510_2a connected to the third word line contact 520c can be located at the lowest layer. The third word line contact 520c is the one furthest from the cell region CR among the first word line contact 520a, the third word line contact 520c and the fifth word line contact 520e.

[0177] For example, the second word line contact 520b can be connected to the third layer word line pad 510_1c, the fourth word line contact 520d can be connected to the first layer word line pad 510_1a, and the sixth word line contact 520f can be connected to the second layer word line pad 510_1b. The first layer word line pad 510_1a can be the first word line pad 510_1 located at the lowest layer within the first unit structure CS1. Among the second word line contacts 520b, the fourth word line contact 520d, and the sixth word line contact 520f arranged at intervals along the second direction DR2, the fourth word line contact 520d, which is farthest from the unit region CR, can have the longest length along the third direction DR3. The first layer word line pad 510_1a connected to the fourth word line contact 520d, which is farthest from the unit region CR among the second word line contacts 520b, the fourth word line contact 520d, and the sixth word line contact 520f, can be located at the lowest layer.

[0178] In the above embodiment, when the cell region CR is located on both sides of the pad region PR along the second direction DR2, among the word line contacts 520 spaced apart along the second direction DR2, the middle word line contact 520 can be the furthest from the cell region CR. However, the example is not limited to this. For example, when the cell region CR is only located on one side of the pad region PR along the second direction DR2, the length of the word line contacts 520 spaced apart along the second direction DR2 can increase as they are farther away from the cell region CR along the second direction DR2.

[0179] according to Figure 18 The illustrated embodiment, and Figure 16 Similar to the embodiments shown, word line pads 510 connected to word line contacts 520 spaced apart along the first direction DR1 can be included in different unit structures.

[0180] The first word line contact portion 520a and the second word line contact portion 520b, which are spaced apart along the first direction DR1, can be connected to the second word line pad 510_2 included in the second unit structure CS2 and the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the first word line contact portion 520a can be connected to the sixth layer word line pad 510_2c included in the second unit structure CS2, while the second word line contact portion 520b can be connected to the first layer word line pad 510_1a included in the first unit structure CS1.

[0181] The third word line contact portion 520c and the fourth word line contact portion 520d, which are arranged at intervals along the first direction DR1, can be connected to the second word line pad 510_2 included in the second unit structure CS2 and the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the third word line contact portion 520c can be connected to the fifth layer word line pad 510_2b included in the second unit structure CS2, and the fourth word line contact portion 520d can be connected to the second layer word line pad 510_1b included in the first unit structure CS1.

[0182] The fifth word line contact portion 520e and the sixth word line contact portion 520f, which are spaced apart along the first direction DR1, can be connected to the second word line pad 510_2 included in the second unit structure CS2 and the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the fifth word line contact portion 520e can be connected to the fourth layer word line pad 510_2a included in the second unit structure CS2, and the sixth word line contact portion 520f can be connected to the third layer word line pad 510_1c included in the first unit structure CS1.

[0183] According to the embodiments, with Figure 16 Similar to the embodiments shown, word line pads 510 connected to word line contacts 520 spaced apart along the second direction DR2 can be included in the same unit structure.

[0184] The first word line contact portion 520a, the third word line contact portion 520c, and the fifth word line contact portion 520e, which are spaced apart along the second direction DR2, can be connected to the second word line pad 510_2 included in the second unit structure CS2, respectively. For example, the first word line contact portion 520a can be connected to the sixth layer word line pad 510_2c included in the second unit structure CS2, the third word line contact portion 520c can be connected to the fifth layer word line pad 510_2b included in the second unit structure CS2, and the fifth word line contact portion 520e can be connected to the fourth layer word line pad 510_2a included in the second unit structure CS2.

[0185] The second word line contact portion 520b, the fourth word line contact portion 520d, and the sixth word line contact portion 520f, which are spaced apart along the second direction DR2, can be connected to the first word line pad 510_1 included in the first unit structure CS1, respectively. For example, the second word line contact portion 520b can be connected to the first layer word line pad 510_1a included in the first unit structure CS1, the fourth word line contact portion 520d can be connected to the second layer word line pad 510_1b included in the first unit structure CS1, and the sixth word line contact portion 520f can be connected to the third layer word line pad 510_1c included in the first unit structure CS1.

[0186] According to the embodiments, with Figure 16 In the embodiment shown, the shortest and longest word line contact portions 520 among the plurality of word line contact portions 520 can be arranged along the first direction DR1.

[0187] For example, the diameter of the word line contact 520 can increase as its length extends along the third direction DR3. The longer the word line contact 520 extends along the third direction DR3, the more word line pads 510 it penetrates. As the length of the word line contact 520 increases along the third direction DR3, the word line pads 510 connected to the word line contact 520 can be located at lower layers. The diameter of the word line contact 520 connected to the relatively lower word line pad 510 can be larger than the diameter of the word line contact 520 connected to the relatively higher word line pad 510. Correspondingly, the diameter of the word line contact 520 connected to the uppermost word line pad 510 can be the smallest, while the diameter of the word line contact 520 connected to the lowermost word line pad 510 can be the largest. For example, the diameter of the word line contact 520 can gradually decrease as it approaches the upper surface of the substrate 100. In an embodiment, the diameter of the word line contact portion 520 may refer to the diameter of the top of the word line contact portion 520 or its maximum diameter.

[0188] For example, among a plurality of word line contacts 520, the word line contacts 520 arranged along the first direction DR1 may include a first word line contact 520a having the shortest length along the third direction DR3 and a second word line contact 520b having the longest length along the third direction DR3. The first word line contact 520a having the shortest length along the third direction DR3 and the second word line contact 520b having the longest length along the third direction DR3 may be arranged along the first direction DR1. The first word line contact 520a connected to the sixth layer word line pad 510_2c (which is the uppermost word line pad) and the second word line contact 520b connected to the first layer word line pad 510_1a (which is the lowermost word line pad) may be arranged along the first direction DR1. The first word line contact 520a having the smallest diameter and the second word line contact 520b having the largest diameter may be arranged along the first direction DR1.

[0189] For example, among the plurality of word line contacts 520, the nth (n≥1) shortest word line contact 520 and the nth longest word line contact 520 can be arranged along the first direction DR1. The word line contact 520 connected to the nth (n≥1) highest layer word line pad 510 among the plurality of word line pads 510 and the word line contact 520 connected to the nth lowest layer word line pad 510 among the plurality of word line pads 510 can be arranged along the first direction DR1.

[0190] For example, among the plurality of word line contacts 520, the second short third word line contact 520c and the second long fourth word line contact 520d can be arranged along the first direction DR1. The third word line contact 520c connected to the fifth layer word line pad 510_2b located on the second higher layer among the plurality of word line pads 510, and the fourth word line contact 520d connected to the second layer word line pad 510_1b located on the second lower layer among the plurality of word line pads 510, can be arranged along the first direction DR1.

[0191] For example, the third shortest fifth word line contact 520e and the third longest sixth word line contact 520f among the plurality of word line contacts 520 can be arranged along the first direction DR1. The fifth word line contact 520e connected to the fourth layer word line pad 510_2a located in the third highest layer among the plurality of word line pads 510, and the sixth word line contact 520f connected to the third layer word line pad 510_1c located in the third lowest layer among the plurality of word line pads 510 can be arranged along the first direction DR1.

[0192] The fact that the longest (n≥1) and shortest (n≥1) word line contact 520 among the multiple word line contact portions 520 are arranged along the first direction DR1 means that the word line contact portion 520 with the largest (n≥1) diameter and the word line contact portion 520 with the smallest (n≥1) diameter are arranged along the first direction DR1. By arranging the word line contact portion 520 with the largest (n≥1) diameter and the word line contact portion 520 with the smallest diameter along the first direction DR1, short circuits between the word line contact portions 520 arranged along the first direction DR1 can be reduced or prevented.

[0193] according to Figure 19 In the embodiment shown, the plurality of word line contacts 520 are spaced apart from each other in the first direction DR1 and are... Figure 15The length of the word line contacts 520 arranged similarly in the illustrated embodiment can be gradually increased. The word line contacts 520 arranged at intervals along the first direction DR1 can be connected to the word line pads 510 located in a continuous layer.

[0194] For example, the first word line contact 520a can be connected to the sixth layer word line pad 510_2c (which is the topmost word line pad). The second word line contact 520b can be connected to the fifth layer word line pad 510_2b by penetrating the sixth layer word line pad 510_2c. The number of word line pads 510 penetrated by the first word line contact 520a and the second word line contact 520b can gradually increase. The lengths of the first word line contact 520a and the second word line contact 520b along the third direction DR3 can gradually increase. The sixth layer word line pad 510_2c and the fifth layer word line pad 510_2b, which are respectively connected to the first word line contact 520a and the second word line contact 520b, can be located in consecutive layers.

[0195] For example, the third word line contact 520c can connect to the second layer word line pad 510_1b by penetrating the sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, the fourth layer word line pad 510_2a, and the third layer word line pad 510_1c. The fourth word line contact 520d can connect to the first layer word line pad 510_1a by penetrating the sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, the fourth layer word line pad 510_2a, the third layer word line pad 510_1c, and the second layer word line pad 510_1b. The number of word line pads 510 penetrated by the third word line contact 520c and the fourth word line contact 520d can be gradually increased. The lengths of the third word line contact 520c and the fourth word line contact 520d along the third direction DR3 can be gradually increased. The second layer word line pad 510_1b and the first layer word line pad 510_1a, which are respectively connected to the third word line contact portion 520c and the fourth word line contact portion 520d, can be located in a continuous layer.

[0196] For example, the fifth word line contact 520e can be connected to the fourth layer word line pad 510_2a by penetrating the sixth layer word line pad 510_2c and the fifth layer word line pad 510_2b. The sixth word line contact 520f can be connected to the third layer word line pad 510_1c by penetrating the sixth layer word line pad 510_2c, the fifth layer word line pad 510_2b, and the fourth layer word line pad 510_2a. The number of word line pads 510 penetrated by the fifth and sixth word line contacts 520e and 520f can gradually increase. The lengths of the fifth and sixth word line contacts 520e and 520f along the third direction DR3 can gradually increase. The fourth layer word line pad 510_2a and the third layer word line pad 510_1c connected to the fifth and sixth word line contacts 520e and 520f, respectively, can be located in consecutive layers.

[0197] However, it is not limited to the above embodiments. For example, in the plurality of word line contacts 520, the length of the word line contacts 520 arranged at intervals along the first direction DR1 can be gradually reduced.

[0198] according to Figure 19 The illustrated embodiment, and Figure 15 Unlike the illustrated embodiment, in the plurality of word line contacts 520, the word line contacts 520 spaced apart in the second direction DR2 have a longer length as they are farther from the cell region CR. The word line contacts 520 spaced apart in the second direction DR2 may have word line pads 510 connected to the word line contacts 520, wherein the farther the word line contacts 520 are from the cell region CR, the lower the layer in which the word line pads 510 connected to the word line contacts 520 are located.

[0199] Let's refer to each other. Figure 12 The cell region CR can be the area containing multiple semiconductor patterns 130, bit lines BL, multiple capacitors 170, and multiple word lines WL, while the pad region PR can be the area containing multiple word line pads 510. The pad region PR can be located on one side of the cell region CR along the second direction DR2. For example, multiple cell regions CR can be spaced apart along the second direction DR2, and the pad region PR can be located between the multiple cell regions CR spaced apart along the second direction DR2. Among the word line contacts 520 spaced apart along the second direction DR2, the word line contact 520 farthest from the cell region CR can have the longest length. Among the word line contacts 520 spaced apart along the second direction DR2, the word line pad 510 connected to the word line contact 520 farthest from the cell region CR can be located on the lowest layer.

[0200] For example, the first word line contact 520a can be connected to the sixth layer word line pad 510_2c, the third word line contact 520c can be connected to the second layer word line pad 510_1b, and the fifth word line contact 520e can be connected to the fourth layer word line pad 510_2a. The second layer word line pad 510_1b can be located at the lowest layer among the sixth layer word line pad 510_2c, the second layer word line pad 510_1b, and the fourth layer word line pad 510_2a. Among the first word line contact 520a, the third word line contact 520c, and the fifth word line contact 520e arranged at intervals along the second direction DR2, the third word line contact 520c, which is farthest from the cell region CR, can have the longest length along the third direction DR3. The second layer word line pad 510_1b connected to the third word line contact 520c can be located at the lowest layer. The third word line contact 520c is the one furthest from the cell region CR among the first word line contact 520a, the third word line contact 520c and the fifth word line contact 520e.

[0201] For example, the second word line contact 520b can be connected to the fifth layer word line pad 510_2b, the fourth word line contact 520d can be connected to the first layer word line pad 510_1a, and the sixth word line contact 520f can be connected to the third layer word line pad 510_1c. The first layer word line pad 510_1a can be located at the lowest layer among the fifth layer word line pad 510_2b, the first layer word line pad 510_1a, and the third layer word line pad 510_1c. Among the second word line contacts 520b, the fourth word line contact 520d, and the sixth word line contact 520f arranged at intervals along the second direction DR2, the fourth word line contact 520d, which is farthest from the cell region CR, can have the longest length along the third direction DR3. The first layer word line pad 510_1a, which is connected to the fourth word line contact 520d, which is furthest from the cell region CR among the second word line contact 520b, the fourth word line contact 520d, and the sixth word line contact 520f, can be located on the lowest layer.

[0202] In the above embodiment, when the cell region CR is located on both sides of the pad region PR along the second direction DR2, among the word line contacts 520 spaced apart along the second direction DR2, the middle word line contact 520 can be the furthest from the cell region CR. However, the example is not limited to this. For example, when the cell region CR is only located on one side of the pad region PR along the second direction DR2, the length of the word line contacts 520 spaced apart along the second direction DR2 can increase as they are farther away from the cell region CR along the second direction DR2.

[0203] In the following text, reference will be made to Figures 20 to 39 Description based on Figures 1 to 8This is part of a method for manufacturing a semiconductor device according to the illustrated embodiment.

[0204] Figure 20 , Figure 23 , Figure 25 , Figure 28 , Figure 31 , Figure 33 and Figure 36 This is a plan view illustrating a portion of a method for manufacturing a semiconductor device according to an embodiment. Figure 21 , Figure 22 , Figure 24 , Figure 26 , Figure 27 , Figure 29 , Figure 30 , Figure 32 , Figure 34 , Figure 35 , Figure 37 , Figure 38 and Figure 39 This is a cross-sectional view showing a portion of a method for manufacturing a semiconductor device according to an embodiment. Figure 21 and Figure 22 It is along Figure 20 The cross-sectional view taken by line M-M'. Figure 24 It is along Figure 23 The cross-sectional view taken by line M-M'. Figure 26 and Figure 27 It is along Figure 25 A cross-sectional view taken from line M-M'. Figure 29 and Figure 30 It is along Figure 28 The cross-sectional view taken by line N-N'. Figure 32 It is along Figure 31 The cross-sectional view taken by line N-N'. Figure 34 and Figure 35 It is along Figure 33 The cross-sectional view taken from line N-N'. Figure 37 It is along Figure 36 A cross-sectional view taken from line O-O'. Figure 38 It is along Figure 36 A cross-sectional view taken from line P-P'. Figure 39 It is along Figure 36 The figure shows a cross-sectional view taken by line Q-Q'. The same reference numerals indicate the same cross-sectional line, which can represent the same location.

[0205] Multiple memory cells can be formed on the cell region CR of the substrate 100. Each memory cell may include: a semiconductor pattern 130 extending along a first direction DR1 parallel to the upper surface of the substrate 100; a bit line BL connected to one side surface of the semiconductor pattern 130 along the first direction DR1 and extending along a third direction DR3 perpendicular to the upper surface of the substrate 100; a capacitor 170 connected to the other side surface of the semiconductor pattern 130 along the first direction DR1; a word line WL intersecting the semiconductor pattern 130 and extending along a second direction DR2; and a gate insulating layer Gox located between the semiconductor pattern 130 and the word line WL. The second direction DR2 may be parallel to the upper surface of the substrate 100 and intersecting the first direction DR1. For example, the second direction DR2 may be orthogonal to the first direction DR1.

[0206] Multiple memory cells can be spaced apart along a first direction DR1 and a second direction DR2, and can also be spaced apart along a third direction DR3. That is, multiple semiconductor patterns 130 can be spaced apart along the first direction DR1 and the second direction DR2, and can also be spaced apart along the third direction DR3. Multiple word lines WL can be spaced apart along the first direction DR1 and the third direction DR3. Multiple bit lines BL can be spaced apart along the first direction DR1 and the second direction DR2. Multiple capacitors 170 can be spaced apart along the first direction DR1, the second direction DR2, and the third direction DR3. A word line WL can intersect with multiple semiconductor patterns 130 spaced apart along the second direction DR2. Between two semiconductor patterns 130 spaced apart along the first direction DR1, a bit line BL can be connected to the two semiconductor patterns 130. Between two semiconductor patterns 130 spaced apart along the first direction DR1, two capacitors 170 can be connected to each of the two semiconductor patterns 130. A bit line BL and two capacitors 170 can be arranged alternately along the first direction DR1. A plurality of semiconductor patterns 130 spaced apart along a third direction DR3 can be connected to a bit line BL. Capacitors 170 connected to the plurality of semiconductor patterns 130 spaced apart along the third direction DR3 can be connected to each other along the third direction DR3. Capacitors 170 connected to the plurality of semiconductor patterns 130 spaced apart along a second direction DR2 can be connected to each other along the second direction DR2. Two capacitors 170 located between two adjacent semiconductor patterns 130 along a first direction DR1 and each connected to these two semiconductor patterns 130 can be connected to each other along the first direction DR1.

[0207] like Figure 20 and Figure 21As shown, a plurality of first trenches T1 can be formed by etching a portion of alternately stacked interlayer insulating layers 120 and a plurality of semiconductor layers 122 on a pad region PR of a substrate 100 located on one side of the cell region CR along the second direction DR2. The plurality of first trenches T1 can be spaced apart along the first direction DR1. Each of the plurality of first trenches T1 is located on one side of the pad region PR along the first direction DR1 and can have a depth along the third direction DR3, the pad region PR overlapping with a word line WL along the second direction DR2. Some of the first trenches T1 can be located in the pad region PR, which overlaps with the region between two adjacent word lines WL along the first direction DR1, with a bit line BL located between the two word lines WL.

[0208] The substrate 100 may include a plurality of cell regions CR spaced apart along a second direction DR2, and the pad regions PR may be located between the plurality of cell regions CR spaced apart along the second direction DR2. A plurality of first trenches T1 may be located between the plurality of cell regions CR spaced apart along the second direction DR2.

[0209] When multiple first trenches T1 are formed, the upper surface of the substrate 100, the side surface of the interlayer insulating layer 120, and the side surface of multiple semiconductor layers 122 can be exposed.

[0210] The interlayer insulating layer 120 may include, for example, silicon oxide, but is not limited thereto. The semiconductor layer 122 may include the same semiconductor material as the semiconductor pattern 130. For example, the semiconductor layer 122 may include, but is not limited to, silicon.

[0211] like Figure 22 As shown, a plurality of first grooves R1 can be formed by etching portions of a plurality of semiconductor layers 122 via a plurality of first trenches T1. The depth of each of the plurality of first grooves R1 along the first direction DR1 can be substantially the same as the length of the word line WL along the first direction DR1.

[0212] like Figure 23 and Figure 24 As shown, multiple word line extensions WL_P can be formed within multiple first grooves R1 by depositing conductive material. The word line extensions WL_P can be, but are not limited to, the same material as the word lines WL.

[0213] Multiple word line extensions WL_P may be spaced apart on a third direction DR3. Multiple word line extensions WL_P may be spaced apart on a first direction DR1. Word line extensions WL_P may extend on a second direction DR2. Word line extensions WL_P may connect to the end of a word line WL located in a cell region CR along the second direction DR2. Word line extensions WL_P may connect to word lines WL in each of the multiple cell regions CR spaced apart along the second direction DR2. Word line extensions WL_P may be part of a word line WL.

[0214] Among the multiple word line extensions WL_P, the word line extensions WL_P located at the two edges along the first direction DR1 may not be connected to the word line WL located in the cell region CR.

[0215] Next, an insulating material may be deposited to form a first insulating pattern 140 within the plurality of first trenches T1. The first insulating pattern 140 may include, but is not limited to, the same material as the interlayer insulating layer 120. When the first insulating pattern 140 and the interlayer insulating layer 120 include the same material, the boundary between the first insulating pattern 140 and the interlayer insulating layer 120 may be invisible.

[0216] like Figure 25 and Figure 26 As shown, a portion of the interlayer insulating layer 120 overlapping the word line extensions WL_P at the two edges of the multiple word line extensions WL_P along the first direction DR1 can be etched to form two second trenches T2. The two second trenches T2 can be formed in the region where the word line extensions WL_P are located at the two edges along the first direction DR1. The second trenches T2 can have a depth along the third direction DR3.

[0217] With the formation of the two second grooves T2, word line extensions WL_P located at the two edges along the first direction DR1 and not connected to the word line WL located in the cell region CR can be removed.

[0218] Next, as Figure 27 As shown, insulating material can be deposited to form a second insulating pattern 142 within the two second trenches T2. The second insulating pattern 142 may include, but is not limited to, the same material as the first insulating pattern 140 and the interlayer insulating layer 120. When the second insulating pattern 142, the first insulating pattern 140, and the interlayer insulating layer 120 comprise the same material, the boundary between the second insulating pattern 142 and the first insulating pattern 140, and the boundary between the second insulating pattern 142 and the interlayer insulating layer 120, may be invisible.

[0219] like Figure 28 and Figure 29 As shown, a plurality of third trenches T3 can be formed by etching portions of interlayer insulating layers 120 and a plurality of semiconductor layers 122 alternately stacked on pad regions PR, with the pad regions PR and capacitors 170 of cell regions CR overlapping in the second direction DR2. The plurality of third trenches T3 can be located between two word line extensions WL_P spaced apart along the first direction DR1. Each word line extension WL_P can be connected to two word lines WL located on either side of two capacitors 170 located between two adjacent semiconductor patterns 130 along the first direction DR1. The plurality of third trenches T3 can be arranged spaced apart between the two word line extensions WL_P along the second direction DR2. The plurality of third trenches T3 can also be arranged spaced apart along the first direction DR1.

[0220] Each of the plurality of third trenches T3 may have a depth along a third direction DR3. When the plurality of third trenches T3 are formed, the upper surface of the substrate 100, the side surface of the interlayer insulating layer 120, and the side surface of the plurality of semiconductor layers 122 may be exposed.

[0221] The interlayer insulating layer 120 may include, for example, silicon oxide, but is not limited thereto. The semiconductor layer 122 may include the same semiconductor material as the semiconductor pattern 130. For example, the semiconductor layer 122 may include, but is not limited to, silicon.

[0222] like Figure 30 As shown, a plurality of second grooves R2 and a plurality of holes H can be formed by etching a portion of a plurality of semiconductor layers 122 via a plurality of third trenches T3.

[0223] Multiple holes H can be formed by etching portions of multiple semiconductor layers 122 located between multiple third trenches T3 spaced apart along the second direction DR2. Multiple second grooves R2 can be formed by etching portions of multiple semiconductor layers 122 on the side of the third trench T3 adjacent to the cell region CR located at two edges of the multiple third trenches T3 along the second direction DR2.

[0224] The depth of each of the plurality of holes H along the second direction DR2 can be substantially the same as the length of the plurality of third grooves T3 spaced apart along the second direction DR2. The depth of each of the plurality of second grooves R2 along the second direction DR2 can be substantially equal to half the depth of each of the plurality of holes H along the second direction DR2.

[0225] like Figure 31 and Figure 32 As shown, multiple word line pads 510 can be formed in multiple second grooves R2 and multiple holes H by depositing conductive material.

[0226] Each of the plurality of word line pads 510 can be connected between two word line extensions WL_P spaced apart in the first direction DR1. Each of the two word line extensions WL_P can be part of two word lines WL located on both sides of two capacitors 170 located between two adjacent semiconductor patterns 130 in the first direction DR1. The plurality of word line pads 510 can overlap with the capacitors 170 in the second direction DR2. The plurality of word line pads 510 can be spaced apart between two word lines WL along the second direction DR2. The plurality of word line pads 510 can be spaced apart along the third direction DR3. The plurality of word line pads 510 spaced apart in the third direction DR3 can have the same length along the first direction DR1. The plurality of word line pads 510 spaced apart in the third direction DR3 can have the same length along the second direction DR2. The plurality of word line pads 510 can also be spaced apart along the first direction DR1.

[0227] Next, an insulating material may be deposited to form a third insulating pattern 144 within the plurality of third trenches T3. The third insulating pattern 144 may include, but is not limited to, the same material as the interlayer insulating layer 120. When the third insulating pattern 144 and the interlayer insulating layer 120 include the same material, the boundary between the third insulating pattern 144 and the interlayer insulating layer 120 may be invisible.

[0228] like Figure 33 and Figure 34 As shown, word line pads 510 located at two edges along the second direction DR2 and the portion of interlayer insulating layer 120 overlapping with the word line pads on the third direction DR3 can be etched to form two fourth trenches T4. The two fourth trenches T4 can be formed in the region where the word line pads 510 are located at the two edges along the second direction DR2. The fourth trenches T4 can have a depth along the third direction DR3.

[0229] With the formation of the two fourth trenches T4, word line pads 510 located at the two edges along the second direction DR2 and whose length is half the length of the word line pad 510 along the second direction DR2 can be removed.

[0230] Next, as Figure 35As shown, insulating material can be deposited to form a fourth insulating pattern 146 within the two fourth trenches T4. The fourth insulating pattern 146 may include, but is not limited to, the same material as, the third insulating pattern 144 and the interlayer insulating layer 120. When the fourth insulating pattern 146, the third insulating pattern 144, and the interlayer insulating layer 120 comprise the same material, the boundaries between the fourth insulating pattern 146 and the third insulating pattern 144, and between the fourth insulating pattern 146 and the interlayer insulating layer 120, may be invisible.

[0231] like Figure 36 , Figure 37 , Figure 38 and Figure 39 As shown, a plurality of word line contacts 520 spaced apart along the first direction DR1 can be formed on a plurality of word line pads 510 spaced apart along the third direction DR3.

[0232] For example, multiple contact holes can be formed that penetrate multiple word line pads 510 and a portion of the interlayer insulating layer 120. The multiple contact holes may include: contact holes extending along the third direction DR3 through the interlayer insulating layer 120 located on the uppermost word line pad 510 to the upper surface of the uppermost word line pad 510; and contact holes extending along the third direction DR3 through the interlayer insulating layer 120 and at least one word line pad 510 to the upper surface of a word line pad 510 located below the at least one word line pad 510. The lengths of the multiple contact holes along the third direction DR3 may be different. The number of word line pads 510 penetrated by the multiple contact holes may vary. A portion of the upper surface of each of the multiple word line pads 510 spaced apart on the third direction DR3 can be exposed through each contact hole.

[0233] An insulating material layer can be formed by depositing an insulating material to cover the inner surfaces of the multiple contact holes and the upper surfaces of the multiple word line pads 510 exposed by the multiple contact holes. A portion of the insulating material layer covering the upper surfaces of the multiple word line pads 510 can be etched using an anisotropic etching process. Next, a conductive material layer can be formed by depositing a conductive material to fill the remaining space of each of the multiple contact holes. Next, a planarization process can be performed such that the upper surfaces of the insulating material layer and the conductive material layer are at the same height as the upper surface of the interlayer insulating layer 120. In the planarization process, a portion of the insulating material layer and the conductive material layer can be etched, and multiple word line contacts 520 can be formed within the multiple contact holes. Each of the multiple word line contacts 520 may include a columnar conductive layer 521 extending along a third direction DR3 and an insulating layer 522 surrounding the side surfaces of the conductive layer 521. The side surface of the word line contact 520 can be formed by an insulating layer 522, while the upper and lower surfaces of the word line contact 520 can be formed by a conductive layer 521 and an insulating layer 522. Since the lower surface of the word line contact 520 is in contact with the word line pad 510, the word line contact 520 and the word line pad 510 can be electrically connected.

[0234] Each of the plurality of word line pads 510 can connect two word lines WL spaced apart along a first direction DR1. The plurality of word line pads 510 can also be arranged between two word lines WL spaced apart along the first direction DR1 and spaced apart along a second direction DR2. For example, the plurality of word line contacts 520 located on the plurality of word line pads 510 may include a first word line contact 520a, a second word line contact 520b, a third word line contact 520c, a fourth word line contact 520d, a fifth word line contact 520e, a sixth word line contact 520f, a seventh word line contact 520g, an eighth word line contact 520h, and a ninth word line contact 520i.

[0235] For example, the first word line contact 520a, the second word line contact 520b, and the third word line contact 520c may be spaced apart from each other in the first direction DR1 and arranged on a plurality of word line pads 510 spaced apart from each other in the third direction DR3. The fourth word line contact 520d, the fifth word line contact 520e, and the sixth word line contact 520f may be spaced apart in the first direction DR1 and arranged on a plurality of word line pads 510 spaced apart in the third direction DR3. The seventh word line contact 520g, the eighth word line contact 520h, and the ninth word line contact 520i may be spaced apart in the first direction DR1 and arranged on a plurality of word line pads 510 spaced apart in the third direction DR3.

[0236] For example, the first word line contact 520a, the fourth word line contact 520d, and the seventh word line contact 520g can be arranged on a plurality of word line pads 510 spaced apart from each other along the second direction DR2. The second word line contact 520b, the fifth word line contact 520e, and the eighth word line contact 520h can be arranged on a plurality of word line pads 510 spaced apart from each other along the second direction DR2. The third word line contact 520c, the sixth word line contact 520f, and the ninth word line contact 520i can be arranged on a plurality of word line pads 510 spaced apart from each other along the second direction DR2. The third syllable contact portion 520c, the sixth syllable contact portion 520f, and the ninth syllable contact portion 520i can be arranged at intervals along the second direction DR2.

[0237] As shown in the figure, the number of word line contacts 520 spaced apart along the first direction DR1 and arranged on a plurality of word line pads 510 spaced apart along the third direction DR3 can be three, but is not limited thereto. For example, the number of word line contacts 520 spaced apart along the first direction DR1 and arranged on a plurality of word line pads 510 spaced apart along the third direction DR3 can be one or two, or four or more. As the number of word line contacts 520 spaced apart along the first direction DR1 and arranged on a plurality of word line pads 510 spaced apart along the third direction DR3 increases, the length of the pad region PR along the second direction DR2 can be reduced.

[0238] For example, a plurality of word line pads 510 spaced apart along the third direction DR3 may include a first layer word line pad 510a, a second layer word line pad 510b, a third layer word line pad 510c, a fourth layer word line pad 510d, a fifth layer word line pad 510e, a sixth layer word line pad 510f, a seventh layer word line pad 510g, an eighth layer word line pad 510h, and a ninth layer word line pad 510i. The first layer word line pad 510a, the second layer word line pad 510b, the third layer word line pad 510c, the fourth layer word line pad 510d, the fifth layer word line pad 510e, the sixth layer word line pad 510f, the seventh layer word line pad 510g, the eighth layer word line pad 510h, and the ninth layer word line pad 510i may be sequentially adjacent to the upper surface of the substrate 100.

[0239] According to an embodiment, word line pads 510, each connected to a plurality of word line contacts 520 spaced apart along a first direction DR1, can be located in consecutive layers. The number of word line pads 510 penetrated by word line contacts 520 connected to word line pads 510 located in a relatively lower layer can be greater than the number of word line pads 510 penetrated by word line contacts 520 connected to word line pads 510 located in a relatively higher layer. The length of word line contacts 520 connected to word line pads 510 located in a relatively lower layer along a third direction DR3 can be greater than the length of word line contacts 520 connected to word line pads 510 located in a relatively higher layer along a third direction DR3.

[0240] According to an embodiment, the layer containing the word line pads 510 that are respectively connected to a plurality of word line contacts 520 spaced apart along the first direction DR1 can be gradually lowered. The number of word line pads 510 penetrated by each of the plurality of word line contacts 520 spaced apart along the first direction DR1 can be gradually increased. The length of each of the plurality of word line contacts 520 spaced apart along the first direction DR1 on the third direction DR3 can be gradually increased.

[0241] For example, the first word line contact 520a can be connected to the ninth-layer word line pad 510i, which is the uppermost word line pad among multiple word line pads 510, by penetrating the interlayer insulating layer 120. The second word line contact 520b can be connected to the eighth-layer word line pad 510h, located below the ninth-layer word line pad 510i, by penetrating the interlayer insulating layer 120 and the ninth-layer word line pad 510i. The third word line contact 520c can be connected to the seventh-layer word line pad 510g by penetrating the interlayer insulating layer 120, the ninth-layer word line pad 510i, and the eighth-layer word line pad 510h. The first word line contact 520a can penetrate zero word line pads 510, the second word line contact 520b can penetrate one word line pad 510, and the third word line contact 520c can penetrate two word line pads 510. The number of word line pads 510 penetrated by the first word line contact portions 520a, 520b, and 520c, which are spaced apart along the first direction DR1, can gradually increase. The ninth layer word line pads 510i, eighth layer word line pads 510h, and seventh layer word line pads 510g, which are respectively connected to the first word line contact portions 520a, 520b, and 520c, which are spaced apart along the first direction DR1, can be located in consecutive layers. As the layers containing the ninth-layer word line pads 510i, the eighth-layer word line pads 510h, and the seventh-layer word line pads 510g, which are respectively connected to the first word line contact portions 520a, the second word line contact portions 520b, and the third word line contact portions 520c arranged at intervals along the first direction DR1, gradually decrease in height, the lengths of the first word line contact portions 520a, the second word line contact portions 520b, and the third word line contact portions 520c along the third direction DR3 can gradually increase.

[0242] For example, the fourth word line contact 520d can be connected to the sixth word line pad 510f by penetrating the interlayer insulating layer 120, the ninth word line pad 510i, the eighth word line pad 510h, and the seventh word line pad 510g. The fifth word line contact 520e can be connected to the fifth word line pad 510e by penetrating the interlayer insulating layer 120, the ninth word line pad 510i, the eighth word line pad 510h, the seventh word line pad 510g, and the sixth word line pad 510f. The sixth word line contact 520f can be connected to the fourth word line pad 510d by penetrating the interlayer insulating layer 120, the ninth word line pad 510i, the eighth word line pad 510h, the seventh word line pad 510g, the sixth word line pad 510f, and the fifth word line pad 510e. The fourth word line contact 520d can penetrate three word line pads 510, the fifth word line contact 520e can penetrate four word line pads 510, and the sixth word line contact 520f can penetrate five word line pads 510. The number of word line pads 510 penetrated by the fourth word line contact 520d, the fifth word line contact 520e, and the sixth word line contact 520f, which are spaced apart along the first direction DR1, can gradually increase. The sixth layer word line pads 510f, the fifth layer word line pads 510e, and the fourth layer word line pads 510d, which are connected to the fourth word line contact 520d, the fifth word line contact 520e, and the sixth word line contact 520f, which are spaced apart from each other along the first direction DR1, can be located in consecutive layers. As the layers containing the sixth-layer word line pads 510f, 510e, and 510d, which are respectively spaced apart from the fourth word line contact portion 520d, fifth word line contact portion 520e, and sixth word line contact portion 520f along the first direction DR1, gradually decrease in height, the lengths of the fourth word line contact portion 520d, fifth word line contact portion 520e, and sixth word line contact portion 520f on the third direction DR3 can gradually increase.

[0243] For example, the seventh word line contact 520g can be connected to the third word line pad 510c by penetrating the interlayer insulating layer 120, the ninth word line pad 510i, the eighth word line pad 510h, the seventh word line pad 510g, the sixth word line pad 510f, the fifth word line pad 510e, and the fourth word line pad 510d. The eighth word line contact 520h can be connected to the second word line pad 510b by penetrating the interlayer insulating layer 120, the ninth word line pad 510i, the eighth word line pad 510h, the seventh word line pad 510g, the sixth word line pad 510f, the fifth word line pad 510e, the fourth word line pad 510d, and the third word line pad 510c. The ninth word line contact 520i can connect to the first layer word line pad 510a by penetrating the interlayer insulating layer 120, the ninth layer word line pad 510i, the eighth layer word line pad 510h, the seventh layer word line pad 510g, the sixth layer word line pad 510f, the fifth layer word line pad 510e, the fourth layer word line pad 510d, the third layer word line pad 510c, and the second layer word line pad 510b. The seventh word line contact 520g can penetrate six word line pads 510, the eighth word line contact 520h can penetrate seven word line pads 510, and the ninth word line contact 520i can penetrate eight word line pads 510. The number of word line pads 510 penetrated by the seventh word line contact 520g, the eighth word line contact 520h, and the ninth word line contact 520i, which are spaced apart along the first direction DR1, can gradually increase. The third-layer word line pads 510c, second-layer word line pads 510b, and first-layer word line pads 510a, which are respectively connected to the seventh word line contact portion 520g, the eighth word line contact portion 520h, and the ninth word line contact portion 520i arranged at intervals along the first direction DR1, can be located in consecutive layers. As the layers containing the third-layer word line pads 510c, the second-layer word line pads 510b, and the first-layer word line pads 510a, which are respectively connected to the seventh word line contact portion 520g, the eighth word line contact portion 520h, and the ninth word line contact portion 520i arranged at intervals along the first direction DR1, gradually decrease in height, the lengths of the seventh word line contact portion 520g, the eighth word line contact portion 520h, and the ninth word line contact portion 520i on the third-layer DR3 can gradually increase.

[0244] However, the examples are not limited to this. For example, the length of a plurality of word line contacts 520 arranged at intervals in the first direction DR1 can gradually decrease along the third direction DR3. As another example, such as Figure 9 As shown, among the plurality of word line contacts 520, the length of the plurality of word line contacts 520 spaced apart along the second direction DR2 along the third direction DR3 can gradually increase or decrease. Additionally, as... Figure 10As shown, among the multiple word line contact portions 520, the shortest word line contact portion 520 and the longest word line contact portion 520 can be arranged along the first direction DR1. Furthermore, as... Figure 11 As shown, among the multiple word line contact portions 520, the word line contact portions 520 arranged at intervals along the second direction DR2 have a longer length as they are farther away from the cell region CR.

[0245] In the following text, reference will be made to Figures 40 to 48 Description based on Figures 12 to 15 This is part of a method for manufacturing a semiconductor device according to the illustrated embodiment.

[0246] Figures 40 to 48 This is a cross-sectional view showing a portion of a method for manufacturing a semiconductor device according to an embodiment.

[0247] like Figure 40 As shown, a first stacked structure ST1 can be formed. The first stacked structure ST1 may include a first cell substrate 100 and a plurality of memory cells located on the first cell substrate 100. The plurality of memory cells may be spaced apart along a first direction DR1 and a second direction DR2 parallel to the upper surface of the first cell substrate 100, and may also be spaced apart along a third direction DR3 perpendicular to the upper surface of the first cell substrate 100. The second direction DR2 may be a direction intersecting the first direction DR1. For example, the second direction DR2 may be a direction orthogonal to the first direction DR1. Each of the plurality of memory cells may include: a first semiconductor pattern; a first bit line connected to one side surface of the first semiconductor pattern along the first direction DR1; a first capacitor connected to the other side surface of the first semiconductor pattern along the first direction DR1; and a first word line WL_1 extending along the second direction DR2 and intersecting the first semiconductor pattern. The first stacked structure ST1 may include a first interlayer insulating layer 120_1 located between the plurality of first word lines WL_1, between the lowermost first word line WL_1 and the first cell substrate 100, and on the upper surface of the uppermost first word line WL_1. The first stacked structure ST1 may include a plurality of first word line pads extending from a plurality of first word lines WL_1 along a first direction DR1 and overlapping with a plurality of first capacitors in a second direction DR2. Each of the plurality of first word line pads may be connected between two first word lines WL_1 spaced apart along the first direction DR1. The two first word lines WL_1 connected by the first word line pads may be spaced apart in the first direction DR1, and two first capacitors are located between the two first word lines WL_1, situated between two adjacent first semiconductor patterns in the first direction DR1. Although Figure 40 Only the first word line WL_1 and the first interlayer insulating layer 120_1 are shown, but the first stacked structure ST1 may include the other components mentioned above.

[0248] like Figure 41 As shown, a second stacked structure ST2 can be formed. The second stacked structure ST2 may include a second cell substrate 200 and a plurality of memory cells located on the second cell substrate 200. The plurality of memory cells may be spaced apart along a first direction DR1 and a second direction DR2 parallel to the upper surface of the second cell substrate 200, and may also be spaced apart along a third direction DR3 perpendicular to the upper surface of the second cell substrate 200. The second direction DR2 may be a direction intersecting the first direction DR1. For example, the second direction DR2 may be a direction orthogonal to the first direction DR1. Each of the plurality of memory cells may include: a second semiconductor pattern; a second bit line connected to one side surface of the second semiconductor pattern along the first direction DR1; a second capacitor connected to the other side surface of the second semiconductor pattern along the first direction DR1; and a second word line WL_2 extending along the second direction DR2 and intersecting the second semiconductor pattern. The second stacked structure ST2 may include a second interlayer insulating layer 120_2 located between a plurality of second word lines WL_2, between the lowermost second word line WL_2 and the second unit substrate 200, and on the upper surface of the uppermost second word line WL_2. The second stacked structure ST2 may include a plurality of second word line pads extending from the plurality of second word lines WL_2 along a first direction DR1 and overlapping with a plurality of second capacitors in the second direction DR2. Each of the plurality of second word line pads may be connected between two second word lines WL_2 spaced apart in the first direction DR1. The two second word lines WL_2 connected by the second word line pads may be spaced apart in the first direction DR1, and two second capacitors are located between the two second word lines WL_2, situated between two adjacent second semiconductor patterns in the first direction DR1. Although Figure 40 Only the second word line WL_2 and the second interlayer insulating layer 120_2 are shown, but the second stacked structure ST2 may include the other components mentioned above.

[0249] like Figure 42 As shown, the second stacked structure ST2 can be flipped to bond it to the top of the first stacked structure ST1. The first interlayer insulating layer 120_1 and the second interlayer insulating layer 120_2 can be bonded by bringing the second interlayer insulating layer 120_2 of the second stacked structure ST2 into contact with the first interlayer insulating layer 120_1 of the first stacked structure ST1 and performing a heat treatment. Next, the second unit substrate 200 can be removed.

[0250] Although not shown, multiple first bit line contacts can be formed to connect multiple first bit lines and global bit lines of the first stack structure ST1. Multiple second bit line contacts can be formed to connect multiple second bit lines and global bit lines of the second stack structure ST2.

[0251] Although not shown, multiple word line contacts can be formed. In the following text, the first word line pad included in the first stack structure ST1 and the second word line pad included in the second stack structure ST2 can be collectively referred to as word line pads. Multiple word line contacts can be formed on multiple word line pads spaced apart along a third direction DR3. Multiple word line contacts can be spaced apart along a first direction DR1 on multiple word line pads spaced apart along a third direction DR3. Multiple word line contacts spaced apart along the first direction DR1 and arranged on multiple word line pads spaced apart along the third direction DR3 can be electrically connected to word line pads located on different layers. Word line contacts can extend along the third direction DR3, penetrating the interlayer insulating layer and some of the multiple word line pads. When the lower surface of a word line contact contacts the upper surface of a word line pad, the word line contact and the word line pad can be electrically connected. The lengths of the multiple word line contacts spaced apart along the first direction DR1 and arranged on multiple word line pads spaced apart along the third direction DR3 along the third direction DR3 can be different.

[0252] Multiple word line pads can be arranged between two word lines WL spaced apart along a first direction DR1 and spaced apart along a second direction DR2. Multiple word line contacts can be spaced apart along the second direction DR2 and respectively arranged on the multiple word line pads. The multiple word line contacts can be arranged spaced apart along the second direction DR2. The multiple word line contacts spaced apart along the second direction DR2 are respectively arranged on the multiple word line pads spaced apart along the second direction DR2, and the multiple word line contacts spaced apart along the second direction DR2 can be electrically connected to word line pads located on different layers. The multiple word line contacts spaced apart along the second direction DR2 are arranged on the multiple word line pads spaced apart along the second direction DR2, and the lengths of the multiple word line contacts spaced apart along the second direction DR2 along the third direction DR3 can be different.

[0253] The length relationship between multiple word line contacts spaced apart from each other on the first direction DR1 and the second direction DR2, and the relationship between multiple word line pads connected to the multiple word line contacts, can be determined according to... Figures 15 to 19 The various embodiments shown are implemented as described.

[0254] like Figure 43 As shown, an upper insulating layer 180 and an upper wiring layer 182 can be formed on the upper surface of the second interlayer insulating layer 120_2. Although not shown, global bit lines can be formed on the upper surface of the second interlayer insulating layer 120_2. For example, the global bit lines can be (but are not limited to) a portion of the upper wiring layer 182. As another example, the upper wiring layer 182 can be formed separately from the global bit lines. The upper wiring layer 182 can include a plurality of wiring layers spaced apart along the third direction DR3. Although not shown, additional wiring vias can be formed to connect the plurality of wiring layers spaced apart along the third direction DR3 by penetrating the upper insulating layer 180.

[0255] Next, a first pad insulating layer 190 and a first connection pad 192 can be formed on the upper wiring layer 182 and the upper insulating layer 180. The first pad insulating layer 190 may include an insulating material, and the first connection pad 192 may include a metallic material. For example, the first connection pad 192 may include copper (Cu). Although not shown, the first connection pad 192 may be electrically connected to the upper wiring layer 182. For example, the first connection pad 192 may be connected to the upper wiring layer 182 via a wiring via.

[0256] The order in which the first line contact, the second line contact, and the character line contact are formed can vary.

[0257] In the following text, the first unit substrate 100 may be referred to as substrate 100. The first unit structure CS1 and the second unit structure CS2 may be stacked on the substrate 100. The first unit structure CS1 may include components of the first stacked structure ST1 located on the substrate 100. The second unit structure CS2 may include an upper insulating layer 180, an upper wiring layer 182, a first pad insulating layer 190, and a first connection pad 192 additionally formed on the second stacked structure ST2.

[0258] like Figure 44 As shown, a third stacked structure ST3 can be formed, wherein a transistor TR is located on a first surface 300a of a peripheral circuit substrate 300, a first wiring insulating layer 320, a first wiring layer 322, and a first wiring via 324 are located on the transistor TR, and an external connection pad 332 is located on the upper surface of the first wiring insulating layer 320. The first wiring layer 322 may include a plurality of wiring layers spaced apart in a third direction DR3. The first wiring layer 322 may include a plurality of wiring layers spaced apart in a second direction DR2. The first wiring insulating layer 320 may be located between the plurality of wiring layers spaced apart along the third direction DR3 and between the plurality of wiring layers spaced apart along the second direction DR2. The first wiring via 324 may penetrate the first wiring insulating layer 320 to connect the first wiring layer 322 and the transistor TR. Although not shown, the first wiring via 324 may penetrate the first wiring insulating layer 320 to connect the plurality of wiring layers spaced apart in the third direction DR3. Although not shown, the first wiring via 324 can penetrate the first wiring insulation layer 320 to connect the first circuit wiring layer 322 and the external connection pad 332.

[0259] like Figure 45 As shown, the third stacked structure ST3 can be flipped so that its upper part faces the carrier substrate CW and is bonded to the carrier substrate CW. Although not shown, a bonding material or adhesive layer may be provided between the third stacked structure ST3 and the carrier substrate CW.

[0260] Next, a wafer thinning process can be performed on the second surface 300b (the opposite side of the first surface 300a) of the peripheral circuit substrate 300 to reduce the thickness of the peripheral circuit substrate 300 on the third-direction DR3.

[0261] like Figure 46 As shown, a second wiring insulating layer 380 can be formed on the second surface 300b of the peripheral circuit substrate 300, and a via 328 can be formed, which penetrates the second wiring insulating layer 380, the peripheral circuit substrate 300 and the first wiring insulating layer 320 along the third direction DR3 to connect to the first circuit wiring layer 322.

[0262] like Figure 47 As shown, a second circuit routing layer 382 can be formed on the via 328. The via 328 can connect the first circuit routing layer 322 and the second circuit routing layer 382 on the third-direction DR3. A second wiring insulation layer 380 can be additionally formed on the second circuit routing layer 382.

[0263] Although not shown, the second wiring layer 382 may include a plurality of wiring layers spaced apart on the third direction DR3. The second wiring layer 382 may also include a plurality of wirings spaced apart on the second direction DR2. A second wiring insulation layer 380 may be located between the plurality of wiring layers spaced apart along the third direction DR3 and between the plurality of wirings spaced apart along the second direction DR2. Although not shown, second wiring vias may be provided to connect the plurality of wiring layers spaced apart along the third direction DR3 by penetrating the second wiring insulation layer 380.

[0264] Next, a second pad insulating layer 390 and a second connection pad 392 can be formed on the second wiring insulating layer 380 and the second circuit wiring layer 382. The second pad insulating layer 390 may include an insulating material, and the second connection pad 392 may include a metallic material. For example, the second connection pad 392 may include copper (Cu). Although not shown, the second connection pad 392 may be electrically connected to the second circuit wiring layer 382. For example, the second connection pad 392 may be connected to the second circuit wiring layer 382 via a second wiring via.

[0265] Accordingly, a peripheral circuit structure PS can be formed. The peripheral circuit structure PS may include: a peripheral circuit substrate 300; a transistor TR, a first wiring insulating layer 320, a first wiring layer 322, and a first wiring via 324 on a first surface 300a of the peripheral circuit substrate 300; and a second wiring insulating layer 380, a second wiring layer 382, ​​a second pad insulating layer 390, and a second connection pad 392 on a second surface 300b of the peripheral circuit substrate 300, and may include a via 328 penetrating the first wiring insulating layer 320, the peripheral circuit substrate 300, and the second wiring insulating layer 380 to connect the first wiring layer 322 and the second wiring layer 382 on a third-direction DR3.

[0266] like Figure 48 As shown, the peripheral circuit structure PS can be flipped and bonded to the second unit structure CS2. The second connection pad 392 and the second pad insulating layer 390 of the peripheral circuit structure PS can be aligned and contacted with the first connection pad 192 and the first pad insulating layer 190 of the second unit structure CS2, respectively, and then subjected to heat treatment. Accordingly, the first connection pad 192 can be bonded to the second connection pad 392, and the first pad insulating layer 190 can be bonded to the second pad insulating layer 390. This bonding can be called a hybrid bonding. For example, when the first connection pad 192 and the second connection pad 392 comprise copper Cu, the bonding between the peripheral circuit structure PS and the second unit structure CS2 can be called a Cu-Cu hybrid bonding.

[0267] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concepts of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims

1. A semiconductor device, comprising: Substrate; Multiple semiconductor patterns on the substrate are spaced apart in a direction perpendicular to the upper surface of the substrate; Bit lines are connected to a side surface of the plurality of semiconductor patterns along a first direction and extend in a direction perpendicular to the upper surface of the substrate; Multiple capacitors are respectively connected to the other side surface of the multiple semiconductor patterns along the first direction; Multiple word lines intersect with the multiple semiconductor patterns respectively, and extend in a second direction that intersects with the first direction; Multiple word line pads overlap with the multiple capacitors in the second direction; as well as Multiple word line contacts extend in the direction perpendicular to the upper surface of the substrate; Wherein, at least some of the plurality of word line pads are respectively connected to the plurality of word line contacts. Wherein, the plurality of word line contacts are spaced apart in the first direction, and The plurality of word line contacts have different lengths along the direction perpendicular to the upper surface of the substrate.

2. The semiconductor device according to claim 1, in, The plurality of word line pads include word line pads spaced apart in the second direction. The plurality of word line contacts include word line contacts spaced apart in the second direction, and The word line contact portions spaced apart in the second direction are respectively connected to the word line pads spaced apart in the second direction.

3. The semiconductor device according to claim 2, in, Each of the plurality of word line contacts is electrically connected to one of the plurality of word line pads.

4. The semiconductor device according to claim 3, in, Each of the plurality of word line contacts includes: a conductive layer having a columnar shape extending in a direction perpendicular to the upper surface of the substrate; and an insulating layer surrounding the side surface of the conductive layer. In this configuration, the lower surface of each of the plurality of word line contacts contacts the upper surface of a word line pad, and... Among the plurality of word line contacts, except for the word line contact that contacts the upper surface of the uppermost word line pad, the word line contact penetrates the word line pad located above the one word line pad.

5. The semiconductor device according to claim 2, in, The lengths of the word line contacts spaced apart in the first direction gradually increase or decrease.

6. The semiconductor device according to claim 2, in, The lengths of the word line contacts spaced apart in the second direction among the plurality of word line contacts gradually increase or decrease.

7. The semiconductor device according to claim 2, in, The shortest and longest of the plurality of word line contacts are arranged along the first direction.

8. The semiconductor device according to claim 2, in, The plurality of semiconductor patterns, the bit lines, the plurality of capacitors, and the plurality of word lines are located on a cell region of the substrate, the plurality of word line pads are located on a pad region of the substrate, and the pad region is located on one side of the cell region along the second direction. Among the plurality of word line contact portions, the longer the word line contact portions that are spaced apart in the second direction are from the unit region, the longer their length.

9. The semiconductor device according to claim 2, in, Multiple unit structures are stacked on the substrate. Each of the plurality of unit structures includes the plurality of semiconductor patterns, the bit lines, the plurality of capacitors, the plurality of word lines, and the plurality of word line pads. The word line pads, which are respectively connected to the word line contacts spaced apart in the first direction, are included in different unit structures, and The word line pads, which are respectively connected to the word line contacts spaced apart in the second direction, are included in the same unit structure.

10. The semiconductor device according to claim 9, in, The word line contacts spaced apart in the first direction are respectively connected to word line pads with the same stacking order in the plurality of word line pads of each of the different unit structures.

11. The semiconductor device according to claim 10, in, The plurality of semiconductor patterns, bit lines, capacitors, and word lines of each of the plurality of unit structures are located on a unit region of the substrate. The plurality of word line pads of each of the plurality of unit structures are located on a pad region of the substrate, and the pad region is located on one side of the unit region along the second direction. Among them, the word line contacts that are spaced apart in the second direction are connected to the word line pads in the plurality of word line pads of the same unit structure. As the word line contacts are farther away from the unit area, the stacking order of the word line pads is lower.

12. The semiconductor device according to claim 1, in, The plurality of semiconductor patterns include semiconductor patterns spaced apart in the first direction. Specifically, between two adjacent semiconductor patterns along the first direction, two capacitors connected to the two semiconductor patterns or a bit line connected to the two semiconductor patterns are arranged respectively. The word line pads connect two word lines located on both sides of the two capacitors along the first direction.

13. The semiconductor device according to claim 12, Also includes: Multiple bit lines are respectively connected to the semiconductor pattern spaced apart in the first direction; And multiple global bit lines, connected to the multiple bit lines and extending in the first direction. The multiple bit lines are spaced apart in the first direction. In this configuration, two adjacent bit lines in the first direction are connected to different global bit lines.

14. The semiconductor device according to claim 13, Also includes: Multiple bit line pads located on the upper surface of the multiple bit lines respectively Wherein, the plurality of bit line pads are spaced apart in the first direction, and Wherein, two adjacent bit line pads in the first direction extend in opposite directions along the second direction.

15. The semiconductor device according to claim 14, in, The multiple global bit lines include a first global bit line and a second global bit line. In the planar diagram, the first global bit line and the second global bit line are spaced apart in the second direction. Wherein, two adjacent bit line pads in the first direction include a first sub-bit line pad connected to the first global bit line and a second sub-bit line pad connected to the second global bit line.

16. The semiconductor device according to claim 15, Also includes: The first sub-bit line contact portion is connected between the first sub-bit line pad and the first global bit line; And the second sub-bit line contact portion, connected between the second sub-bit line pad and the second global bit line. The first global bit line and the second global bit line are located in different layers, and The first sub-bit line contact portion and the second sub-bit line contact portion have different lengths along the direction perpendicular to the upper surface of the substrate.

17. A semiconductor device, comprising: Substrate; Multiple semiconductor patterns on the substrate are spaced apart in a direction perpendicular to the upper surface of the substrate; Bit lines are connected to a side surface of the plurality of semiconductor patterns in a first direction and extend in the direction perpendicular to the upper surface of the substrate; Multiple capacitors are respectively connected to the other side surface of the multiple semiconductor patterns along the first direction; Multiple word lines intersect with the multiple semiconductor patterns respectively, and extend in a second direction that intersects with the first direction; Multiple word line pads overlap with the multiple capacitors in the second direction; as well as Multiple word line contacts extend in the direction perpendicular to the upper surface of the substrate; Wherein, at least some of the plurality of word line pads are respectively connected to the plurality of word line contacts. Wherein, the plurality of word line contacts are spaced apart in the first direction, and The plurality of word line contacts are connected to the upper surface of word line pads located on different layers.

18. The semiconductor device according to claim 17, in, The plurality of semiconductor patterns are spaced apart in the first direction. Specifically, between two adjacent semiconductor patterns along the first direction, two capacitors connected to the two semiconductor patterns or a bit line connected to the two semiconductor patterns are arranged respectively. Each of the plurality of word line pads is connected between two word lines located on both sides of the two capacitors, and The plurality of word line pads have the same length in the first direction.

19. The semiconductor device according to claim 18, in, The plurality of word line pads include word line pads spaced apart in the second direction between the two word lines. The plurality of word line contacts include word line contacts spaced apart in the second direction, and The word line contact portions spaced apart in the second direction are respectively connected to the upper surface of the word line pads spaced apart in the second direction.

20. A semiconductor device, comprising: Substrate; The plurality of semiconductor patterns on the substrate are spaced apart in directions parallel to and perpendicular to the upper surface of the substrate. Multiple bit lines are spaced apart in a direction parallel to the upper surface of the substrate, each bit line being connected to a side surface of a plurality of semiconductor patterns spaced apart in a direction perpendicular to the upper surface of the substrate along a first direction, and extending in the direction perpendicular to the upper surface of the substrate. Multiple capacitors are respectively connected to the other side surface of the multiple semiconductor patterns along the first direction; Multiple word lines are spaced apart in a direction perpendicular to the upper surface of the substrate and in the first direction, each of the multiple word lines intersecting with the multiple semiconductor patterns spaced apart in a second direction intersecting the first direction, and extending in the second direction; Multiple word line pads overlap with the multiple capacitors in the second direction, each of the multiple word line pads connects two adjacent word lines in the first direction, and the capacitor is located between the two word lines; as well as Multiple word line contacts extend in a direction perpendicular to the upper surface of the substrate and are spaced apart in the first direction on each of the multiple word line pads. The plurality of word line contacts are connected to the upper surface of word line pads located on different layers.

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