Semiconductor device

Abstract

A semiconductor device includes a first bit line extending in a first direction; a first channel pattern located on the first bit line and connected to the first bit line; a first word line located on the first channel pattern and extending in a second direction; a lower gate insulating pattern located between the first channel pattern and the first word line; a second bit line extending in the second direction and spaced apart from the first word line in a third direction; a second channel pattern located on the second bit line and contacting the second bit line; an upper gate insulating pattern located between the first channel pattern and the second channel pattern and between the first channel pattern and the second bit line, contacting the first channel pattern, and including a ferroelectric material film; and a second word line located on the second channel pattern and extending in the first direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices, and more specifically, to semiconductor devices including vertical channel transistors (VCTs) and methods for manufacturing semiconductor devices including VCTs. Background Technology

[0002] To meet consumer demand for high performance and low cost, it is necessary to increase the integration level of semiconductor devices. In the case of semiconductor devices, integration level is a crucial factor determining product price, making increased integration particularly important.

[0003] In the case of two-dimensional or planar semiconductor devices, the integration density is primarily determined by the area occupied by a single memory cell, and is therefore greatly influenced by the level of fine patterning technology. However, because miniaturizing patterns requires extremely expensive equipment, the integration density of two-dimensional semiconductor devices remains limited despite improvements. Therefore, semiconductor devices incorporating vertical-channel transistors with channels extending vertically have been proposed. Summary of the Invention

[0004] One or more exemplary embodiments of this disclosure provide a semiconductor device that can have improved integration and improved electrical characteristics.

[0005] In addition, one or more example embodiments provide a method for manufacturing a semiconductor device that can have improved integration and improved electrical characteristics.

[0006] According to one aspect of this disclosure, a semiconductor device includes: a first bit line extending in a first direction and including a first side and a second side opposite to the first side; a first channel pattern located on the first side of the first bit line and connected to the first bit line; a first word line located on the first channel pattern and extending in a second direction; a lower gate insulating pattern located between the first channel pattern and the first word line; a second bit line extending in the second direction and spaced apart from the first word line in a third direction; a second channel pattern located on the second bit line and contacting the second bit line; an upper gate insulating pattern located between the first channel pattern and the second channel pattern and between the first channel pattern and the second bit line, and contacting the first channel pattern, the upper gate insulating pattern including a ferroelectric material film; and a second word line located on the second channel pattern and extending in the first direction.

[0007] According to one aspect of this disclosure, a semiconductor device includes: a first bit line extending in a first direction and including a first side and a second side opposite to the first side; a first channel pattern located on the first side of the first bit line and connected to the first bit line; a first word line located on the first channel pattern and extending in a second direction; a lower gate insulating pattern located between the first channel pattern and the first word line; an upper gate insulating pattern located on the first word line and the lower gate insulating pattern and including a ferroelectric material film; a second bit line located on the upper gate insulating pattern and extending in the second direction; a second channel pattern located on the second bit line and contacting the second bit line; and a second word line located on the second channel pattern and extending in the first direction, wherein the upper gate insulating pattern includes a horizontal portion extending in the first direction and a vertical portion extending in the third direction, and wherein the horizontal portion of the upper gate insulating pattern is located between the first word line and the second bit line.

[0008] According to one aspect of this disclosure, a semiconductor device includes: a first bit line extending in a first direction and including a first side and a second side opposite to the first side; a protruding insulating pattern located on the first side of the first bit line and including a channel trench extending in a second direction; a first channel pattern extending along the sidewalls and bottom side of the channel trench and connected to the first bit line; a first lower word line located on the first channel pattern and extending in the second direction; a second lower word line located on the first channel pattern, extending in the second direction, and spaced apart from the first lower word line in the first direction; and a lower gate insulating pattern located between the first channel pattern and the first lower word line and between the first channel pattern and the second lower word line. Between the lines; an upper gate insulating pattern, the upper gate insulating pattern being located on the first channel pattern, the first lower word line, and the second lower word line, and contacting the first channel pattern, the upper gate insulating pattern including a horizontal portion extending in the first direction and a vertical portion extending in the third direction; a first upper line, the first upper line being located on the upper gate insulating pattern and extending in the second direction; a second upper line, the second upper line extending in the second direction and spaced apart from the first upper line in the first direction; a second channel pattern, the second channel pattern being located on the first upper line and the second upper line, and contacting the first upper line and the second upper line; and a second word line, the second word line being located on the upper side of the protruding insulating pattern and extending in the first direction, wherein the upper gate insulating pattern includes a ferroelectric material film. Attached Figure Description

[0009] The above and other aspects and features will become clearer from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 It is a circuit diagram of a semiconductor device according to one or more example embodiments.

[0010] Figure 2 It is a perspective view of a semiconductor device according to one or more example embodiments.

[0011] Figure 3 It is a top view of a semiconductor device according to one or more example embodiments.

[0012] Figure 4 , Figure 5 and Figure 6 According to one or more example embodiments along Figure 3 The cross-sectional view taken from lines AA, BB and CC.

[0013] Figure 7 According to one or more example embodiments Figure 4 A magnified view of part P.

[0014] Figure 8 , Figure 9 and Figure 10 According to one or more example embodiments Figure 4 A magnified view of part of Q.

[0015] Figure 11 and Figure 12 A diagram illustrating a semiconductor device based on one or more example embodiments.

[0016] Figure 13 and Figure 14 A diagram illustrating a semiconductor device based on one or more example embodiments.

[0017] Figure 15 and Figure 16 A diagram illustrating a semiconductor device based on one or more example embodiments.

[0018] Figure 17 A diagram illustrating a semiconductor device based on one or more example embodiments.

[0019] Figure 18 These are diagrams illustrating semiconductor memory devices according to one or more example embodiments.

[0020] Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 , Figure 34 , Figure 35 , Figure 36 , Figure 37 , Figure 38 , Figure 39 , Figure 40 and Figure 41 This is an intermediate stage diagram illustrating a semiconductor device according to one or more example embodiments. Detailed Implementation

[0021] In the following description, exemplary embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and repeated descriptions will be omitted.

[0022] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of one or more exemplary embodiments, the first element, first component, first region, first layer, or first portion described below may be referred to as a second element, second component, second region, second layer, or second portion.

[0023] When expressions such as "at least one (or at least one of)" precede a list of elements, as used in this article, they modify the entire list of elements, not individual elements within the list. For example, the expression "at least one (or at least one of) a, b, or c" should be understood to include: only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0024] Figure 1 It is a circuit diagram of a semiconductor device according to one or more example embodiments.

[0025] refer to Figure 1 The memory cell MC may include a write transistor WTR and a read transistor RTR connected to the write transistor WTR. A semiconductor device according to one or more example embodiments may include a plurality of memory cells arranged in a two-dimensional or three-dimensional manner.

[0026] The write transistor WTR may include a write word line WWL connected to the gate terminal of the write transistor WTR and a write bit line WBL connected to the source terminal of the write transistor WTR. The read transistor RTR may include a read word line RWL and a read bit line RBL, each connected to the source / drain terminal of the read transistor RTR.

[0027] The drain terminal of the write transistor WTR can be connected to the gate terminal of the read transistor RTR. Furthermore, the ferroelectric film FE can be connected to the gate terminal of the read transistor RTR.

[0028] The drain terminal of the write transistor WTR can be called the storage node SN. The storage node SN can be used to store charge. The storage node SN can be connected to the ferroelectric film FE and can polarize the ferroelectric film FE. The charge stored in the storage node SN can induce polarization of the ferroelectric film FE. The charge stored in the storage node SN can switch the polarization direction of the ferroelectric film FE. Furthermore, the degree of polarization of the ferroelectric film FE can vary depending on the amount of charge stored in the storage node SN. The threshold voltage of the read transistor RTR can be changed according to the polarization direction and / or degree of polarization of the ferroelectric film FE. The ferroelectric film FE connected to the gate terminal of the read transistor RTR can serve as the gate insulating film of the read transistor RTR.

[0029] As an example, the programming operation of the memory cell MC can be as follows: a voltage is applied to the write word line WWL and the write bit line WBL, and the write transistor WTR can be turned on. With the write transistor WTR turned on, an electrical signal (charge) can be transferred (charged) to the memory node SN. Therefore, the electrical signal on the write bit line WBL can be stored in the memory node SN. The charge stored in the memory node SN can polarize the ferroelectric film FE. Therefore, the threshold voltage of the read transistor RTR can be changed.

[0030] During the programming operation of the memory cell MC, the amount of charge stored in the memory node SN can be changed according to the magnitude of the voltage applied to the write bit line WBL. In other words, the polarization of the ferroelectric material film FE can be changed according to the magnitude of the voltage applied to the write bit line WBL.

[0031] As an example, the read operation of the memory cell MC can be as follows: the write transistor WTR is turned off, the read bit line RBL is kept at 0V, and the read voltage V... read It can be applied to the read word line RWL. The polarization direction and / or polarization degree of the ferroelectric material film FE can be read by the current flowing through the read transistor RTR. In other words, the magnitude of the current flowing through the channel region of the read transistor RTR can be changed according to the polarization direction and / or polarization degree of the ferroelectric material film FE.

[0032] Because the magnitude of the voltage applied to the write bit line WBL is adjusted during the write operation, the polarization of the ferroelectric film FE can be varied in multiple levels. The threshold voltage of the read transistor RTR can also be varied in multiple levels depending on the polarization of the ferroelectric film FE. Therefore, multi-bit memory cells (MCs) can be implemented.

[0033] Semiconductor devices including storage cells (MC) can also be referred to as dual-transistor zero-capacitance (2T-OC) storage elements. Semiconductor devices according to one or more example embodiments may not include a separate capacitor for storing charge. Therefore, a high degree of integration of the semiconductor device can be achieved because the area required to form the capacitor can be reduced.

[0034] A semiconductor device including a 2T-0C memory element according to one or more example embodiments may include a vertical channel transistor (VCT). A vertical channel transistor refers to a transistor whose channel is perpendicular to the upper side of the substrate 100. Figure 4 The structure that extends from a third party to DR3).

[0035] When the memory node SN is used as the gate of the read transistor RTR, the threshold voltage of the read transistor RTR can vary depending on the amount of charge stored in the memory node SN. For example, the amount of charge stored in the memory node SN may decrease due to the leakage current of the write transistor WTR. As another example, during a write operation of the memory cell MC, the amount of charge stored in the memory node SN may decrease due to the capacitive coupling between the write word line WWL and the memory node SN. Similarly, during a read operation of the memory cell MC, the amount of charge stored in the memory node SN may decrease due to the capacitive coupling between the read word line RWL and the memory node SN.

[0036] When the amount of charge stored in the memory node SN decreases, the hold time and read current of the memory cell MC may decrease. Furthermore, the sensing margin may decrease during read operations of the memory cell MC. This can lead to a reduction in the performance and reliability of the semiconductor device.

[0037] The following describes the case where the ferroelectric film FE is used as the gate of the read transistor RTR. Even if leakage current occurs in the write transistor WTR, the polarization direction and / or polarization degree of the ferroelectric film FE will not change. Furthermore, even if capacitive coupling occurs between the write word line WWL and the memory node SN during the write operation of the memory cell MC, the polarization direction and / or polarization degree of the ferroelectric film FE will not change. Similarly, even if capacitive coupling occurs between the read word line RWL and the memory node SN during the read operation of the memory cell MC, the polarization direction and / or polarization degree of the ferroelectric film FE will not change. In other words, because the ferroelectric film FE is used as the gate of the read transistor RTR, the hold time of the memory cell MC can be improved. The read current of the memory cell MC will not decrease, and the sense margin will not decrease during the read operation of the memory cell MC. Therefore, the performance and reliability of semiconductor devices including 2T-0C memory elements can be improved.

[0038] Figure 2 It is a perspective view of a semiconductor device according to one or more example embodiments. Figure 3 It is a top view of a semiconductor device according to one or more example embodiments. Figure 4 , Figure 5 and Figure 6 It is along Figure 3 The cross-sectional view taken from lines AA, BB and CC. Figure 7 yes Figure 4 A magnified view of part P. Figure 8 , Figure 9 and Figure 10 yes Figure 4 A magnified view of part of Q.

[0039] For reference, Figure 3 The second channel pattern CH2 is not shown in the diagram.

[0040] refer to Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 A semiconductor device according to one or more example embodiments may include a first bit line BL1, first word lines WL11 and WL12, second bit lines BL21 and BL22, second word line WL2, a first channel pattern CH1, a second channel pattern CH2, a first lower gate insulating pattern GOX1, and a first upper gate insulating pattern GOX2.

[0041] As an example, substrate 100 may be a silicon substrate, or may include other materials, such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. As another example, substrate 100 may include a ceramic substrate, a quartz substrate, or a glass substrate. As yet another example, substrate 100 may include a flexible plastic substrate, such as polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), polycarbonate (PC), polyethersulfone (PES), or polyester.

[0042] A lower insulating film 105 can be disposed on the substrate 100. The lower insulating film 105 can be made of an insulating material. Figure 4 Unlike the example embodiment shown, the lower insulating film 105 may not be disposed on the substrate 100.

[0043] The first line BL1 can be disposed on the substrate 100. The first line BL1 can be disposed on the lower insulating film 105.

[0044] Each of the multiple first-position lines BL1 can extend in the first direction DR1. The multiple first-position lines BL1 can be adjacent to each other in the second direction DR2.

[0045] The first line BL1 may include a first side BL1_S1 and a second side BL1_S2 that are opposite to each other on the third-direction DR3. The second side BL1_S2 of the first line may face the substrate 100.

[0046] According to one or more example embodiments, the first direction DR1 and the second direction DR2 may be orthogonal to the third direction DR3. The first direction DR1 may intersect with the second direction DR2. For example, the third direction DR3 may be the thickness direction of the substrate 100. The first direction DR1 and the second direction DR2 may be parallel to the upper side of the substrate 100.

[0047] For example, the first line BL1 can correspond to Figure 1 The write bit line WBL of the write transistor WTR.

[0048] The first line BL1 may include a conductive material. The first line BL1 may include at least one of the following: a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a conductive metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, or a metal. According to one or more example embodiments, the first line BL1 is shown as a single film, but is not limited thereto.

[0049] In the semiconductor device according to one or more example embodiments, the two-dimensional material may be a metallic material and / or a semiconductor material. The two-dimensional material (2D material) may include 2D allotropes or 2D compounds, and may include, for example, at least one of the following: graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). That is, because the above-described 2D materials are listed only as examples, the 2D materials that may be included in the semiconductor device according to one or more example embodiments are not limited to the examples described above.

[0050] The first protruding insulating pattern 170 may be disposed on the first line BL1. The first protruding insulating pattern 170 may be disposed on the first side BL1_S1 of the first line BL1. The first protruding insulating pattern 170 may include insulating material.

[0051] The first protruding insulating pattern 170 may include a first side 170_S1 and a second side 170_S2 opposite to each other on a third-direction DR3. The second side 170_S2 of the first protruding insulating pattern 170 may face the first line BL1. For example, the first side 170_S1 of the first protruding insulating pattern 170 may be the upper side of the first protruding insulating pattern 170. The second side 170_S2 of the first protruding insulating pattern 170 may be the lower side of the first protruding insulating pattern 170.

[0052] and Figure 4 Unlike one or more example embodiments shown, an etch stop film extending along the second side 170_S2 of the first protruding insulating pattern 170 may be further disposed between the first protruding insulating pattern 170 and the substrate 100.

[0053] The first protruding insulating pattern 170 may include a plurality of first channel trenches CH_T. Each first channel trench CH_T may extend in a second direction DR2. Adjacent first channel trenches CH_T may be spaced apart in a first direction DR1.

[0054] Each first trench CH_T can intersect with a first first line BL1. One of the first trenches CH_T can expose multiple adjacent first first lines BL1 in the second direction DR2. One of the first trenches CH_T can expose the first side BL1_S1 of the first first line.

[0055] The bottom side of each first trench CH_T may be defined by the first line BL1 and the lower insulating film 105. The sidewall of each first trench CH_T may be defined by the first protruding insulating pattern 170.

[0056] The first channel pattern CH1 can be disposed on each first line BL1. For example, the first channel pattern CH1 can be disposed on the first side BL1_S1 of each first line BL1. Multiple first channel patterns CH1 can be connected to a first line BL1. Multiple first channel patterns CH1 disposed on a first line BL1 can be spaced apart in the first direction DR1.

[0057] A first channel pattern CH1 can be disposed within one of the first channel grooves CH_T extending along the second direction DR2. Multiple first channel patterns CH1 can be disposed within one of the first channel grooves CH_T. The multiple first channel patterns CH1 disposed within one of the first channel grooves CH_T can be spaced apart along the second direction DR2. For example, the first channel patterns CH1 can be disposed two-dimensionally along the intersecting first direction DR1 and second direction DR2.

[0058] The first channel pattern CH1 may extend along the sidewalls and bottom of the first channel trench CH_T. For example, the first channel pattern CH1 may contact the first protruding insulating pattern 170. In a semiconductor device according to one or more example embodiments, the first channel pattern CH1 may be U-shaped in a cross-section taken along the first direction DR1.

[0059] The first channel pattern CH1 may include a horizontal portion CH1_H and multiple vertical portions CH1_V1 and CH1_V2. The vertical portions CH1_V1 and CH1_V2 of the first channel pattern CH1 may include a first vertical portion CH1_V1 and a second vertical portion CH1_V2 spaced apart in the first direction DR1.

[0060] The horizontal portion CH1_H of the first channel pattern CH1 can extend along the bottom side of the first channel groove CH_T. From, for example... Figure 4 Viewed from the angle of the cross-sectional view, the horizontal portion CH1_H of the first channel pattern CH1 can extend in the first direction DR1. The horizontal portion CH1_H of the first channel pattern CH1 can be connected to the first side BL1_S1 of the first bit line BL1.

[0061] The first vertical portion CH1_V1 and the second vertical portion CH1_V2 of the first channel pattern CH1 can be disposed on the sidewall of the first channel groove CH_T. The first vertical portion CH1_V1 and the second vertical portion CH1_V2 of the first channel pattern CH1 can extend along the sidewall of the first channel groove CH_T. Both the first vertical portion CH1_V1 and the second vertical portion CH1_V2 of the first channel pattern CH1 can protrude from the horizontal portion CH1_H of the first channel pattern CH1 in the third direction DR3. Both the first vertical portion CH1_V1 and the second vertical portion CH1_V2 of the first channel pattern CH1 can extend in the third direction DR3. The first vertical portion CH1_V1 and the second vertical portion CH1_V2 of the first channel pattern CH1 can extend to the first side 170_S1 of the first protruding insulating pattern 170.

[0062] The vertical portions CH1_V1 and CH1_V2 of the first channel pattern CH1 may include a first sidewall CH1_VSW1 and a second sidewall CH1_VSW2 that are opposite to each other in the first direction DR1. The first sidewall CH1_VSW1 of the first vertical portion CH1_V1 of the first channel pattern CH1 and the first sidewall CH1_VSW1 of the second vertical portion CH1_V2 of the first channel pattern CH1 may face the first protruding insulating pattern 170. The second sidewall CH1_VSW2 of the first vertical portion CH1_V1 of the first channel pattern CH1 may face the second sidewall CH1_VSW2 of the second vertical portion CH1_V2 of the first channel pattern CH1.

[0063] The vertical portions CH1_V1 and CH1_V2 of the first channel pattern CH1 may include a first region CH1_VP1 and a second region CH1_VP2. The second region CH1_VP2 of the vertical portion of the first channel pattern CH1 may be disposed on the first region CH1_VP1 of the vertical portion of the first channel pattern CH1. The first region CH1_VP1 of the vertical portion of the first channel pattern CH1 may be disposed between the horizontal portion CH1_H of the first channel pattern CH1 and the second region CH1_VP2 of the vertical portion of the first channel pattern CH1. The first region CH1_VP1 of the vertical portion of the first channel pattern CH1 may be directly connected to the horizontal portion CH1_H of the first channel pattern CH1.

[0064] The first region CH1_VP1 of the vertical portion of the first channel pattern CH1 may overlap with the first word lines WL11 and WL12 in the first direction DR1, but may not overlap with the second bit lines BL21 and BL22 in the first direction DR1. The second region CH1_VP2 of the vertical portion of the first channel pattern CH1 may overlap with the second bit lines BL21 and BL22 in the first direction DR1, but may not overlap with the first word lines WL11 and WL12 in the first direction DR1. Although Figure 7 As shown, according to one or more example embodiments, a first region CH1_VP1 of the vertical portion of the first channel pattern CH1 and a second region CH1_VP2 of the vertical portion of the first channel pattern CH1 are divided in the lower part of the first upper gate insulating pattern GOX2, but this is only for ease of explanation and one or more example embodiments are not limited thereto.

[0065] For example, the first region CH1_VP1 of the vertical portion of the first channel pattern CH1 can be used as Figure 1 The channel region of the write transistor WTR shown in one or more example embodiments. The second region CH1_VP2 of the vertical portion of the first channel pattern CH1 can be the same as... Figure 1The portion corresponding to the storage node SN in one or more example embodiments shown.

[0066] As an example, the first channel pattern CH1 may include an oxide semiconductor material. The first channel pattern CH1 may include, for example, a metal oxide. As an example, the first channel pattern CH1 may be an amorphous metal oxide film. As another example, the first channel pattern CH1 may be a polycrystalline metal oxide film. As yet another example, the first channel pattern CH1 may be a combination of an amorphous metal oxide film and a polycrystalline metal oxide film. As yet another example, the first channel pattern CH1 may be a c-axis oriented crystalline (CAAC) metal oxide film.

[0067] The first channel pattern CH1 may include, for example, but not limited to, at least one of the following: indium oxide, tin oxide, zinc oxide, In-Zn-based oxide (IZO), Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide (IGO), In-Ga-Zn-based oxide (IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr -Zn-based oxides, In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides, In-Sn-Ga-Zn-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides.

[0068] According to one or more example embodiments, In-Ga-Zn based oxides refer to oxides whose main components are In, Ga, and Zn, but not necessarily the ratio of In, Ga, and Zn. That is, taking indium gallium zinc oxide (IGZO) as an example, the first channel pattern CH1 may include IGZO (In... x Ga y Zn zIGZO containing equal proportions of indium, gallium, and zinc (In:Ga:Zn=1:1:1) can be an In-Ga-Zn based oxide. Gallium-rich IGZO can have a higher gallium ratio and a lower indium ratio than IGZO (In:Ga:Zn=1:1:1). Gallium-rich IGZO can also be an In-Ga-Zn based oxide. Indium-rich IGZO can also have a higher indium ratio and a lower gallium ratio than IGZO (In:Ga:Zn=1:1:1). Indium-rich IGZO can also be an In-Ga-Zn based oxide.

[0069] While the above description uses IGZO, one or more example embodiments are not limited thereto. It goes without saying that the above description is equally applicable when the first channel pattern CH1 comprises ternary or more ternary metal oxides. Furthermore, when the first channel pattern CH1 comprises an In-Ga-Zn-based oxide, the first channel pattern CH1 may also include doped metal elements other than In, Ga, and Zn.

[0070] In a semiconductor device according to one or more example embodiments, the horizontal portion CH1_H of the first channel pattern CH1 and the first region CH1_VP1 of the vertical portion of the first channel pattern CH1 may be crystalline, and the second region CH1_VP2 of the vertical portion of the first channel pattern CH1 may be amorphous.

[0071] In a semiconductor device according to one or more example embodiments, the horizontal portion CH1_H of the first channel pattern CH1 and the first region CH1_VP1 of the vertical portion of the first channel pattern CH1 can have a relatively high oxygen concentration compared to the second region CH1_VP2 of the vertical portion of the first channel pattern CH1. Therefore, the second region CH1_VP2 of the vertical portion of the first channel pattern CH1 can have a relatively high metallicity compared to the first region CH1_VP1 of the vertical portion of the first channel pattern CH1.

[0072] As another example, the first channel pattern CH1 may include a two-dimensional semiconductor material.

[0073] The first letter lines WL11 and WL12 can be set on the first channel pattern CH1. The first letter lines WL11 and WL12 can be set inside the first channel groove CH_T.

[0074] The first letter lines WL11 and WL12 can be located on the horizontal portion CH1_H of the first channel pattern CH1. The first letter lines WL11 and WL12 can be located between the first vertical portion CH1_V1 and the second vertical portion CH1_V2 of the first channel pattern CH1.

[0075] The first character lines WL11 and WL12 may include a first lower character line WL11 and a second lower character line WL12. Each of the first lower character line WL11 and the second lower character line WL12 may extend in the second direction DR2. The first lower character line WL11 and the second lower character line WL12 may be arranged alternately in the first direction DR1. The first lower character line WL11 and the second lower character line WL12 may be spaced apart in the first direction DR1.

[0076] Compared to the second lower digit line WL12, the first vertical portion CH1_V1 of the first channel pattern CH1 can be closer to the first lower digit line WL11. The first lower digit line WL11 can be disposed on the second sidewall CH1_VSW2 of the first vertical portion CH1_V1 of the first channel pattern CH1. Compared to the first lower digit line WL11, the second vertical portion CH1_V2 of the first channel pattern CH1 can be closer to the second lower digit line WL12. The second lower digit line WL12 can be disposed on the second sidewall CH1_VSW2 of the second vertical portion CH1_V2 of the first channel pattern CH1.

[0077] The first lower letter line WL11 may not be set on the first sidewall CH1_VSW1 of the first vertical portion CH1_V1 of the first channel pattern CH1. The second lower letter line WL12 may not be set on the first sidewall CH1_VSW1 of the second vertical portion CH1_V2 of the first channel pattern CH1.

[0078] For example, each of the first lower digit line WL11 and the second lower digit line WL12 can correspond to Figure 1 The write word line WWL of the write transistor WTR in one or more example embodiments shown.

[0079] The first word lines WL11 and WL12 may comprise a conductive material. The first word lines WL11 and WL12 may comprise at least one of the following, for example: doped semiconductor material, conductive metal nitride, conductive metal silicon nitride, conductive metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, or metal. Although the first word lines WL11 and WL12 are shown as a single film, one or more example embodiments are not limited thereto.

[0080] The first lower gate insulating pattern GOX1 may extend along a portion of the outline of the first channel pattern CH1. For example, the first lower gate insulating pattern GOX1 may extend along the second sidewall CH1_VSW2 of the first vertical portion CH1_V1 of the first channel pattern CH1 and the second sidewall CH1_VSW2 of the second vertical portion CH1_V2 of the first channel pattern CH1.

[0081] The first lower gate insulating pattern GOX1 may not extend to the first side 170_S1 of the first protruding insulating pattern 170. Based on the first side BL1_S1 of the first bit line, the uppermost side GOX1_US of the first lower gate insulating pattern GOX1 may be lower than the first side 170_S1 of the first protruding insulating pattern 170.

[0082] A first lower gate insulating pattern GOX1 can be disposed between the first channel pattern CH1 and the first lower word line WL11, and between the first channel pattern CH1 and the second lower word line WL12. The first lower gate insulating pattern GOX1 between the first channel pattern CH1 and the first lower word line WL11 can be connected to the first lower gate insulating pattern GOX1 between the first channel pattern CH1 and the second lower word line WL12.

[0083] The first lower gate insulating pattern GOX1 may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film with a dielectric constant higher than that of the silicon oxide film, or a combination thereof. The high dielectric constant insulating film may include a metal oxide or a metal oxynitride. For example, the first lower gate insulating pattern GOX1 may include, but is not limited to, aluminum oxide.

[0084] The first isolation insulating pattern 151 can be disposed on the first lower gate insulating pattern GOX1. The first isolation insulating pattern 151 can be disposed inside the first channel trench CH_T.

[0085] The first insulating pattern 151 may be disposed between a first lower digit line WL11 and a second lower digit line WL12 that are adjacent to each other along the first direction DR1. The first insulating pattern 151 may cover the upper side of the first lower digit line WL11 and the upper side of the second lower digit line WL12. The first insulating pattern 151 may not contact the horizontal portion CH1_H of the first channel pattern CH1. The first insulating pattern 151 includes insulating material.

[0086] according to Figure 8 In one or more example embodiments shown, the upper side 151_US of the first isolation insulating pattern 151 may be located in the same plane as the uppermost side GOX1_US of the first lower gate insulating pattern GOX1. Figure 9In one or more example embodiments shown, the upper side 151_US of the first isolation insulating pattern 151 may be higher than the uppermost side GOX1_US of the first lower gate insulating pattern GOX1.

[0087] according to Figure 10 In one or more example embodiments shown, the upper side 151_US of the first isolation insulating pattern 151 may be lower than the uppermost side GOX1_US of the first lower gate insulating pattern GOX1. A portion of the first lower gate insulating pattern GOX1 may protrude beyond the upper side 151_US of the first isolation insulating pattern 151 on the third-direction DR3.

[0088] The first upper gate insulating pattern GOX2 can be disposed on the first lower word line WL11, the second lower word line WL12, and the first lower gate insulating pattern GOX1. The first upper gate insulating pattern GOX2 can be disposed on the first isolation insulating pattern 151.

[0089] The first upper gate insulating pattern GOX2 may extend along the second sidewall CH1_VSW2 of the first vertical portion CH1_V1 of the first channel pattern CH1 and the second sidewall CH1_VSW2 of the second vertical portion CH1_V2 of the first channel pattern CH1. The first upper gate insulating pattern GOX2 may extend along the upper side 151_US of the first isolation insulating pattern 151 and the first side 170_S1 of the first protruding insulating pattern 170.

[0090] The first upper gate insulating pattern GOX2 can be disposed between the first channel pattern CH1 and the second channel pattern CH2. The first upper gate insulating pattern GOX2 can be disposed between the first channel pattern CH1 and the second bit lines BL21 and BL22.

[0091] The first upper gate insulating pattern GOX2 may include a lower horizontal portion GOX2_H1, an upper horizontal portion GOX2_H2, and a vertical portion GOX2_V. The vertical portion GOX2_V of the first upper gate insulating pattern GOX2 can connect the lower horizontal portion GOX2_H1 of the first upper gate insulating pattern GOX2 to the upper horizontal portion GOX2_H2 of the first upper gate insulating pattern GOX2.

[0092] The lower horizontal portion GOX2_H1 of the first upper gate insulating pattern GOX2 can extend along the upper side 151_US of the first isolation insulating pattern 151. The upper horizontal portion GOX2_H2 of the first upper gate insulating pattern GOX2 can extend along the first side 170_S1 of the first protruding insulating pattern 170. The vertical portion GOX2_V of the first upper gate insulating pattern GOX2 can extend along the second sidewall CH1_VSW2 of the first vertical portion CH1_V1 of the first channel pattern CH1 and the second sidewall CH1_VSW2 of the second vertical portion CH1_V2 of the first channel pattern CH1. The vertical portion GOX2_V of the first upper gate insulating pattern GOX2 can be disposed between the first vertical portion CH1_V1 and the second vertical portion CH1_V2 of the first channel pattern CH1, which are adjacent to each other along the first direction DR1.

[0093] From such as Figure 4 and Figure 7 Viewed from the perspective of the cross-sectional view, both the lower horizontal portion GOX2_H1 and the upper horizontal portion GOX2_H2 of the first upper gate insulating pattern GOX2 can extend along the first direction DR1. The vertical portion GOX2_V of the first upper gate insulating pattern GOX2 can extend along the third direction DR3.

[0094] The vertical portion GOX2_V of the first upper gate insulating pattern GOX2 can be disposed between the first channel pattern CH1 and the second channel pattern CH2. The vertical portion GOX2_V of the first upper gate insulating pattern GOX2 can be disposed between the first channel pattern CH1 and the second bit lines BL21 and BL22. The lower horizontal portion GOX2_H1 of the first upper gate insulating pattern GOX2 can be disposed between the first word lines WL11 and WL12 and the second bit lines BL21 and BL22.

[0095] The first upper gate insulating pattern GOX2 can contact the first isolation insulating pattern 151. The lower horizontal portion GOX2_H1 of the first upper gate insulating pattern GOX2 can contact the upper side 151_US of the first isolation insulating pattern 151.

[0096] The first upper gate insulating pattern GOX2 can contact the first channel pattern CH1. The first upper gate insulating pattern GOX2 can contact the first channel pattern CH1 disposed on the sidewall of the first channel trench CH_T. The first upper gate insulating pattern GOX2 can contact the first vertical portion CH1_V1 and the second vertical portion CH1_V2 of the first channel pattern CH1. The vertical portion GOX2_V of the first upper gate insulating pattern GOX2 can contact the second sidewall CH1_VSW2 of the first vertical portion CH1_V1 of the first channel pattern CH1 and the second sidewall CH1_VSW2 of the second vertical portion CH1_V2 of the first channel pattern CH1.

[0097] according to Figure 8 and Figure 10 In one or more example embodiments shown, the first upper gate insulating pattern GOX2 may contact the first lower gate insulating pattern GOX1. The lower horizontal portion GOX2_H1 of the first upper gate insulating pattern GOX2 may contact the first lower gate insulating pattern GOX1. The first upper gate insulating pattern GOX2 may contact the uppermost side GOX1_US of the first lower gate insulating pattern GOX1.

[0098] according to Figure 9 In one or more example embodiments shown, the first upper gate insulating pattern GOX2 may not contact the first lower gate insulating pattern GOX1. Viewed from a cross-sectional perspective, a gate insulating pattern air gap GOX_AG may be disposed between the first upper gate insulating pattern GOX2 and the first lower gate insulating pattern GOX1.

[0099] and Figure 9 Unlike one or more example embodiments shown, the first upper gate insulating pattern GOX2 may fill the space between one of the plurality of first channel patterns CH1 and the first isolation insulating pattern 151. In this case, the first upper gate insulating pattern GOX2 may contact the uppermost side GOX1_US of the first lower gate insulating pattern GOX1.

[0100] The first upper gate insulating pattern GOX2 may include a ferroelectric material film. Figure 1 (FE in the text). The ferroelectric material film FE can include at least one of ferroelectric materials or antiferroelectric materials. In the following text, for ease of explanation, antiferroelectric materials will also be described as ferroelectric materials.

[0101] Ferroelectric material films (FE) may include at least one of, for example, hafnium oxide, zirconium hafnium oxide, barium strontium titanium oxide, barium titanium oxide, or zirconium lead titanium oxide. According to one or more example embodiments, zirconium hafnium oxide may be a hafnium oxide material doped with zirconium (Zr). As another example, zirconium hafnium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0102] Ferroelectric film FE may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). The type of dopants included in the ferroelectric film FE may vary depending on the type of ferroelectric material included in the ferroelectric film FE.

[0103] When the ferroelectric material film FE includes hafnium oxide, the dopants included in the ferroelectric material film FE may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) or yttrium (Y).

[0104] When the dopant is aluminum (Al), the ferroelectric film FE may comprise 3 at% to 8 at% (atomic percentage) aluminum. According to one or more example embodiments, the dopant ratio may be the ratio of aluminum to the sum of hafnium and aluminum.

[0105] When the dopant is silicon (Si), the ferroelectric film FE may include 2 at% to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric film FE may include 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric film FE may include 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric film FE may include 50 at% to 80 at% zirconium.

[0106] Ferroelectric material films (FE) can have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film can be, for example, but not limited to, 0.5 nm to 10 nm. Because the critical thickness for exhibiting ferroelectric properties can be different for each ferroelectric material, the thickness of the ferroelectric material film (FE) can vary depending on the ferroelectric material.

[0107] The first upper gate insulating pattern GOX2 can correspond to the ferroelectric material film FE connected to the gate terminal of the read transistor RTR. Furthermore, the first upper gate insulating pattern GOX2 can be used as the gate insulating film of the read transistor RTR. That is, the first upper gate insulating pattern GOX2 can be used as the gate of the read transistor RTR, and also as the gate insulating film of the read transistor RTR.

[0108] The second bit lines BL21 and BL22 can be located on the first word lines WL11 and WL12. The second bit lines BL21 and BL22 can be spaced apart from the first word lines WL11 and WL12 on the third-direction DR3. The second bit lines BL21 and BL22 can be located on the first upper gate insulating pattern GOX2.

[0109] The second bit lines BL21 and BL22 can be disposed inside the first channel trench CH_T. The second bit lines BL21 and BL22 can be disposed between the first vertical portion CH1_V1 of the first channel pattern CH1 and the second vertical portion CH1_V2 of the first channel pattern CH1. The second bit lines BL21 and BL22 can be disposed between the vertical portions GOX2_V of the first upper gate insulating pattern GOX2 that are adjacent to each other along the first direction DR1.

[0110] The second upper-level lines BL21 and BL22 may include a first upper-level line BL21 and a second upper-level line BL22. Each of the first upper-level line BL21 and the second upper-level line BL22 may extend in the second direction DR2. Multiple first upper-level lines BL21 and multiple second upper-level lines BL22 may be arranged alternately in the first direction DR1. The first upper-level lines BL21 and the second upper-level lines BL22 may be spaced apart from each other in the first direction DR1.

[0111] Compared to being closer to the second upper line BL22, the first vertical portion CH1_V1 of the first channel pattern CH1 can be positioned closer to the first upper line BL21. The first upper line BL21 can be positioned on the second sidewall CH1_VSW2 of the first vertical portion CH1_V1 of the first channel pattern CH1. Compared to being closer to the first upper line BL21, the second vertical portion CH1_V2 of the first channel pattern CH1 can be positioned closer to the second upper line BL22. The second upper line BL22 can be positioned on the second sidewall CH1_VSW2 of the second vertical portion CH1_V2 of the first channel pattern CH1.

[0112] The first upper line BL21 may not be set on the first sidewall CH1_VSW1 of the first vertical portion CH1_V1 of the first channel pattern CH1. The second upper line BL22 may not be set on the first sidewall CH1_VSW1 of the second vertical portion CH1_V2 of the first channel pattern CH1.

[0113] The first upper line BL21 and the first lower line WL11 can be spaced apart from each other on the third direction DR3. At least a portion of the first upper line BL21 can overlap with the first lower line WL11 on the third direction DR3.

[0114] The second upper-level line BL22 and the second lower-level word line WL12 may be spaced apart from each other on the third-direction DR3. At least a portion of the second upper-level line BL22 may overlap with the second lower-level word line WL12 on the third-direction DR3. The lower horizontal portion GOX2_H1 of the first upper-gate insulating pattern GOX2 may be located between the first upper-level line BL21 and the first lower-level word line WL11, and between the second upper-level line BL22 and the second lower-level word line WL12.

[0115] The second bit lines BL21 and BL22 may comprise conductive materials, and may include, for example, at least one of doped semiconductor materials, conductive metal nitrides, conductive metal silicon nitrides, metal carbonitrides, conductive metal silicides, conductive metal oxides, two-dimensional materials, and metals. Although the second bit lines BL21 and BL22 are shown as single films, one or more example embodiments are not limited thereto.

[0116] The second isolation insulating pattern 152 can be disposed on the first upper gate insulating pattern GOX2. The second isolation insulating pattern 152 can be disposed inside the first channel trench CH_T.

[0117] The second isolation insulation pattern 152 may be disposed between the first upper line BL21 and the second upper line BL22, which are adjacent to each other along the first direction DR1. The second isolation insulation pattern 152 may include an insulating film.

[0118] The second channel pattern CH2 can be disposed on the second bit lines BL21 and BL22. The second channel pattern CH2 can contact the second bit lines BL21 and BL22. The second channel pattern CH2 can be electrically connected to the second bit lines BL21 and BL22.

[0119] The second channel pattern CH2 may include an upper horizontal portion CH2_H1 and multiple vertical portions CH2_V1 and CH2_V2. The vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 may protrude from the upper horizontal portion CH2_H1 toward the first line BL1.

[0120] The upper horizontal portion CH2_H1 of the second channel pattern CH2 can extend along the first direction DR1. The upper horizontal portion CH2_H1 of the second channel pattern CH2 can be disposed on the first side 170_S1 of the first protruding insulating pattern 170. The upper horizontal portion CH2_H1 of the second channel pattern CH2 can be spaced apart from the first channel pattern CH1 along the third direction DR3.

[0121] The vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 can extend onto the third direction DR3. The vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 can be directly connected to the upper horizontal portion CH2_H1 of the second channel pattern CH2. The vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 can be located inside the first channel groove CH_T.

[0122] The vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 may include a first vertical portion CH2_V1 and a second vertical portion CH2_V2. The first vertical portion CH2_V1 and the second vertical portion CH2_V2 of the second channel pattern CH2 may be arranged alternately in the first direction DR1. The first vertical portion CH2_V1 and the second vertical portion CH2_V2 of the second channel pattern CH2 may be spaced apart from each other in the first direction DR1.

[0123] The first vertical portion CH2_V1 of the second channel pattern CH2 can contact the first upper line BL21. The second vertical portion CH2_V2 of the second channel pattern CH2 can contact the second upper line BL22.

[0124] Each of the first vertical portion CH2_V1 and the second vertical portion CH2_V2 of the second channel pattern CH2 can overlap with the first channel pattern CH1 in the first direction DR1. For example, the first vertical portion CH2_V1 and the second vertical portion CH2_V2 of the second channel pattern CH2 can overlap with the vertical portions CH1_V1 and CH1_V2 of the first channel pattern in the first direction DR1.

[0125] The first vertical portion CH2_V1 of the second channel pattern CH2 can be disposed on the second sidewall CH1_VSW2 of the first vertical portion CH1_V1 of the first channel pattern. The second vertical portion CH2_V2 of the second channel pattern CH2 can be disposed on the second sidewall CH1_VSW2 of the second vertical portion CH1_V2 of the first channel pattern CH1.

[0126] The upper horizontal portion CH2_H1 of the second channel pattern CH2 can be formed at different heights with the vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2.

[0127] According to one or more example embodiments, the second channel pattern CH2 may include an oxide semiconductor material or a two-dimensional semiconductor material similar to the first channel pattern CH1. For example, the upper horizontal portion CH2_H1 of the second channel pattern CH2 may include the same oxide semiconductor material as the vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2. For example, the upper horizontal portion CH2_H1 of the second channel pattern CH2 may include an oxide semiconductor material different from the vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2.

[0128] As another example, the second channel pattern CH2 may include a material different from the first channel pattern CH1. For example, the first channel pattern CH1 may include an oxide semiconductor material, while the second channel pattern CH2 may include polysilicon. Polysilicon may include, but is not limited to, doping with impurity elements.

[0129] As another example, the upper horizontal portion CH2_H1 of the second channel pattern CH2 may include an oxide semiconductor material or a two-dimensional semiconductor material. The vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 may include polysilicon.

[0130] As another example, the vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 may comprise an oxide semiconductor material or a two-dimensional semiconductor material. The upper horizontal portion CH2_H1 of the second channel pattern CH2 may comprise polysilicon.

[0131] The third insulating pattern 153 can be disposed on the second insulating pattern 152. The third insulating pattern 153 can be disposed inside one of the first channel grooves CH_T. The upper horizontal portion CH2_H1 of the second channel pattern CH2 can be disposed on the third insulating pattern 153.

[0132] The third insulating pattern 153 may be disposed between the first vertical portion CH2_V1 of the second channel pattern CH2 adjacent to each other along the first direction DR1 and the second vertical portion CH2_V2 of the second channel pattern CH2. The third insulating pattern 153 includes insulating material.

[0133] The second letter line WL2 can be set on the second channel pattern CH2. The second letter line WL2 can be set on the first side 170_S1 of the first protruding insulating pattern 170.

[0134] Multiple second letter lines WL2 can extend along the first direction DR1. The second letter lines WL2 can be adjacent to each other along the second direction DR2.

[0135] The second word line WL2 may include a first side WL2_S1 and a second side WL2_S2 that are opposite to each other on a third-direction DR3. The second side WL2_S2 of the second word line WL2 may face the second channel pattern CH2.

[0136] The second letter line WL2 can be connected to the second channel pattern CH2. For example, the second letter line WL2 can be connected to the upper horizontal portion CH2_H1 of the second channel pattern CH2. The second side WL2_S2 of the second letter line WL2 can be connected to the upper horizontal portion CH2_H of the second channel pattern CH2. The second letter line WL2 can contact the upper horizontal portion CH2_H of the second channel pattern CH2.

[0137] As an example, each of the first upper line BL21 and the second upper line BL22 can correspond to Figure 1 The read bit line RBL of the read transistor RTR. The second word line WL2 can correspond to Figure 1 The read word line RWL of the read transistor RTR.

[0138] As another example, each of the first upper line BL21 and the second upper line BL22 can correspond to Figure 1 The read word line RWL is the read word line of the read transistor RTR. The second word line WL2 can correspond to Figure 1 The read bit line RBL of the read transistor RTR.

[0139] The second word line WL2 may include a conductive material, and may include at least one of, for example, a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a conductive metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, or a metal. The second word line WL2 is shown as a single film, but one or more example embodiments are not limited thereto.

[0140] Figure 11 and Figure 12 A diagram illustrating a semiconductor device based on one or more example embodiments. Figure 13 and Figure 14 These are diagrams illustrating a semiconductor device based on one or more example embodiments. For ease of explanation, the description and use will be primarily as described. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 The differences described in one or more example embodiments.

[0141] refer to Figure 11 and Figure 12 In a semiconductor device according to one or more example embodiments, the second channel pattern CH2 may further include a lower horizontal portion CH2_H2.

[0142] The lower horizontal portion CH2_H2 of the second channel pattern CH2 can be disposed inside the first channel groove CH_T. The lower horizontal portion CH2_H2 of the second channel pattern CH2 can be disposed between the second isolation insulation pattern 152 and the third isolation insulation pattern 153. The third isolation insulation pattern 153 can be disposed on the lower horizontal portion CH2_H2 of the second channel pattern CH2.

[0143] The lower horizontal portion CH2_H2 of the second channel pattern CH2 can be directly connected to the first vertical portion CH2_V1 and the second vertical portion CH2_V2 of the second channel pattern CH2. The lower horizontal portion CH2_H2 of the second channel pattern CH2 can comprise the same material as the first vertical portion CH2_V1 and the second vertical portion CH2_V2 of the second channel pattern CH2. The lower horizontal portion CH2_H2 of the second channel pattern CH2 can be formed at the same height as the vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2. According to one or more example embodiments, "same height" means that they are formed by the same manufacturing process.

[0144] exist Figure 11 In the first vertical portion CH2_V1 of the second channel pattern CH2 and the second vertical portion CH2_V2 of the second channel pattern CH2 can be connected by the upper horizontal portion CH2_H1 of the second channel pattern CH2 located on the first side 170_S1 of the first protruding insulating pattern 170. Viewed from a cross-sectional perspective, the third insulating isolation pattern 153 can be disposed between the upper horizontal portion CH2_H1 and the lower horizontal portion CH2_H2 of the second channel pattern CH2.

[0145] according to Figure 12 In one or more example embodiments shown, the first vertical portion CH2_V1 of the second channel pattern CH2 and the second vertical portion CH2_V2 of the second channel pattern CH2 may not be connected by the upper horizontal portion CH2_H1 of the second channel pattern CH2 located on the first side 170_S1 of the first protruding insulating pattern 170. Viewed from a cross-sectional perspective, the third insulating pattern 153 may extend to the second side WL2_S2 of the second letter line WL2. For example, the upper horizontal portion CH2_H1, the lower horizontal portion CH2_H2, and the vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 may be formed at the same height.

[0146] refer to Figure 13 The semiconductor device according to one or more example embodiments shown may further include an inserted gate insulating pattern GOX2_IF.

[0147] The inserted gate insulating pattern GOX2_IF can be located between the first upper gate insulating pattern GOX2 and the first vertical portion CH2_V1 of the second channel pattern CH2, and between the first upper gate insulating pattern GOX2 and the second vertical portion CH2_V2 of the second channel pattern CH2.

[0148] The inserted gate insulating pattern GOX2_IF may include, for example, silicon oxide. The vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 may include polysilicon.

[0149] refer to Figure 14 In one or more example embodiments shown, in a semiconductor device according to one or more example embodiments, a first lower gate insulating pattern GOX1 located between a first channel pattern CH1 and a first lower word line WL11 may be separated from a first lower gate insulating pattern GOX1 located between a first channel pattern CH1 and a second lower word line WL12.

[0150] The first insulating pattern 151 may contact the first channel pattern CH1. The first insulating pattern 151 may contact the horizontal portion CH1_H of the first channel pattern.

[0151] Figure 15 and Figure 16 These are diagrams illustrating a semiconductor device based on one or more example embodiments. For ease of explanation, the primary focus will be on description and use. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 The differences described in one or more example embodiments.

[0152] refer to Figure 15 and Figure 16 The semiconductor device according to one or more example embodiments may include a first memory structure ST1 and a second memory structure ST2 stacked on a third-party DR3.

[0153] The second storage structure ST2 can be set on the first storage structure ST1.

[0154] For example, the above reference Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10The semiconductor device described in one or more example embodiments shown may constitute a first memory structure ST1. In other words, the first memory structure ST1 may include a first bit line BL1, first word lines WL11 and WL12, second bit lines BL21 and BL22, a second word line WL2, a first channel pattern CH1, a second channel pattern CH2, a first lower gate insulating pattern GOX1, and a first upper gate insulating pattern GOX2.

[0155] The following description will focus on the second storage structure ST2.

[0156] The second memory structure ST2 may include a third bit line BL3, third word lines WL31 and WL32, fourth bit lines BL41 and BL42, fourth word line WL4, a third channel pattern CH3, a fourth channel pattern CH4, a second lower gate insulating pattern GOX3, and a second upper gate insulating pattern GOX4.

[0157] The descriptions of the third bit line BL3, third word lines WL31 and WL32, fourth bit lines BL41 and BL42, fourth word line WL4, third channel pattern CH3, and fourth channel pattern CH4 included in the second memory structure ST2 are substantially the same as the descriptions of the first bit line BL1, first word lines WL11 and WL12, second bit lines BL21 and BL22, second word line WL2, first channel pattern CH1, and second channel pattern CH2 included in the first memory structure ST1. The description of the second lower gate insulating pattern GOX3 is substantially the same as the description of the first lower gate insulating pattern GOX1. The description of the second upper gate insulating pattern GOX4 is substantially the same as the description of the first upper gate insulating pattern GOX2.

[0158] The third channel pattern CH3 may include a horizontal portion CH3_H, a first vertical portion CH3_V1, and a second vertical portion CH3_V2. The fourth channel pattern CH4 may include an upper horizontal portion CH4_H1, a first vertical portion CH4_V1, and a second vertical portion CH4_V2.

[0159] The second lower gate insulating pattern GOX3 can be disposed between the third channel pattern CH3 and the third word lines WL31 and WL32. The second lower gate insulating pattern GOX3 can extend along a portion of the outline of the third channel pattern CH3.

[0160] The second upper gate insulating pattern GOX4 can be disposed between the third channel pattern CH3 and the fourth channel pattern CH4. The second upper gate insulating pattern GOX4 can be disposed between the third channel pattern CH3 and the fourth bit lines BL41 and BL42. The second upper gate insulating pattern GOX4 can be disposed between the third word lines WL31 and WL32 and the fourth bit lines BL41 and BL42.

[0161] The second protruding insulating pattern 175 may include a second channel groove CH_T1 extending in the second direction DR2. The third word lines WL31 and WL32, the fourth bit lines BL41 and BL42, the third channel pattern CH3, and the vertical portions CH4_V1 and CH4_V2 of the fourth channel pattern CH4 may be disposed inside the second channel groove CH_T1.

[0162] Each of the fourth isolation insulation pattern 156, the fifth isolation insulation pattern 157 and the sixth isolation insulation pattern 158 may be provided in the second channel trench CH_T1.

[0163] according to Figure 15 In one or more example embodiments shown, a second memory structure ST2, including a third bit line BL3, third word lines WL31 and WL32, fourth bit lines BL41 and BL42, and a fourth word line WL4, can be sequentially formed on a support substrate. The support substrate including the second memory structure ST2 can be bonded to the substrate 100. The support substrate can then be removed. An interlayer insulating film 140 can be disposed between the support substrate and the substrate 100 to bond the support substrate and the substrate 100. Therefore, the second word line WL2 and the fourth word line WL4 can be disposed between the second channel pattern CH2 and the fourth channel pattern CH4. The interlayer insulating film 140 comprises an insulating material.

[0164] and Figure 15 Unlike one or more example embodiments shown, the interlayer insulating film 140 may not be disposed between the second word line WL2 and the fourth word line WL4. The second word line WL2 and the fourth word line WL4 may be in contact with each other. The support substrate and the substrate 100 may be bonded through the second word line WL2 and the fourth word line WL4.

[0165] according to Figure 16 In one or more example embodiments shown, the second memory structure ST2 may be formed on a substrate 100 on which the first memory structure ST1 is formed. A third bit line BL3 may be disposed between the second word line WL2 and the third channel pattern CH3.

[0166] Figure 17 These are diagrams illustrating a semiconductor device based on one or more example embodiments. For ease of explanation, the primary focus will be on description and use. Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 The differences described in one or more example embodiments.

[0167] refer to Figure 17 The semiconductor device according to one or more example embodiments may further include a peripheral gate structure PG. That is, Figure 17 The semiconductor device may include a cell array region and a peripheral circuit region. The cell array region may include a first bit line BL1, first word lines WL11 and WL12, second bit lines BL21 and BL22, second word line WL2, a first channel pattern CH1, a second channel pattern CH2, a first lower gate insulating pattern GOX1, and a first upper gate insulating pattern GOX2. The peripheral circuit region may include a peripheral gate structure PG, a first upper peripheral insulating film 261, a second upper peripheral insulating film 262, a third upper peripheral insulating film 263, a first lower peripheral insulating film 227, a second lower peripheral insulating film 228, a first peripheral wiring line 241a, a peripheral contact plug 241b, a second peripheral wiring line 243, a peripheral path plug 242, and a cell connection plug 244.

[0168] A peripheral gate structure PG can be disposed on the substrate 100. The peripheral gate structure PG can be included in a sensing transistor, a transmission transistor, a driving transistor, etc. According to one or more example embodiments, the types of transistors disposed in the cell array region and the peripheral circuit region can vary depending on the design layout of the semiconductor memory device.

[0169] The peripheral gate structure PG may include a peripheral gate insulating film 215, a peripheral lower conductive pattern 223, and a peripheral upper conductive pattern 225. The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film with a dielectric constant higher than that of the silicon oxide film, or a combination thereof. The high dielectric constant insulating film may include, for example, but not limited to, at least one of metal oxide, metal oxynitride, metal silicon oxide, and metal silicon oxynitride.

[0170] Each of the lower peripheral conductive pattern 223 and the upper peripheral conductive pattern 225 may include a conductive material. For example, each of the lower peripheral conductive pattern 223 and the upper peripheral conductive pattern 225 may include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a conductive metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, or a metal. The peripheral gate structure PG is shown as including, but not limited to, a plurality of conductive patterns.

[0171] A first lower outer insulating film 227 and a second lower outer outer insulating film 228 are disposed on the substrate 100. Each of the first lower outer outer insulating film 227 and the second lower outer outer insulating film 228 may include an insulating material.

[0172] The first peripheral wiring line 241a and the peripheral contact plug 241b may be disposed inside the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228. The first peripheral wiring line 241a and the peripheral contact plug 241b are shown as different films from each other, but are not limited thereto. The boundary between the first peripheral wiring line 241a and the peripheral contact plug 241b may not be defined. Each of the first peripheral wiring line 241a and the peripheral contact plug 241b may include a conductive material.

[0173] The first peripheral insulating film 261 and the second peripheral insulating film 262 may be disposed on the first peripheral wiring line 241a and the peripheral contact plug 241b. Each of the first peripheral insulating film 261 and the second peripheral insulating film 262 may include insulating material.

[0174] The second peripheral wiring line 243 and the peripheral access plug 242 can be disposed on the first peripheral wiring line 241a. The peripheral access plug 242 can be disposed inside the insulating film 261 on the first periphery. The second peripheral wiring line 243 can be disposed inside the insulating film 262 on the second periphery.

[0175] The second peripheral wiring line 243 and the peripheral access plug 242 can be connected to the first peripheral wiring line 241a. The peripheral access plug 242 can connect the first peripheral wiring line 241a and the second peripheral wiring line 243. Both the second peripheral wiring line 243 and the peripheral access plug 242 can include conductive material. The second peripheral wiring line 243 and the peripheral access plug 242 are shown as different films from each other, but one or more example embodiments are not limited thereto. The boundary between the second peripheral wiring line 243 and the peripheral access plug 242 may not be defined.

[0176] The first bit line BL1, the first word lines WL11 and WL12, the second bit lines BL21 and BL22, the second word line WL2, the first channel pattern CH1, the second channel pattern CH2, the first lower gate insulating pattern GOX1, and the first upper gate insulating pattern GOX2 can be disposed on the peripheral gate structure PG.

[0177] The unit connection plug 244 can be disposed inside the insulating film 263 on the third periphery. The unit connection plug 244 can be connected to the second periphery wiring line 243. The unit connection plug 244 may include a conductive material. The insulating film 263 on the third periphery may all include an insulating material.

[0178] The first line BL1 can be set on the unit connection plug 244. The first line BL1 can be connected to the unit connection plug 244. The first word lines WL11 and WL12, the second bit lines BL21 and BL22, and the second word line WL2 can be connected to the second peripheral wiring line 243.

[0179] Figure 18 These are diagrams illustrating semiconductor memory devices according to one or more example embodiments. For ease of explanation, the description and use will be primarily focused on... Figure 17 The differences described in one or more example embodiments.

[0180] refer to Figure 18 The semiconductor memory device according to one or more example embodiments may further include a first bonding pad BP1 and a second bonding pad BP2.

[0181] The first bonding pad BP1 and the first pad plug 281 can be disposed on the second peripheral wiring line 243. The first bonding pad BP1 and the first pad plug 281 can be disposed inside the insulating film 263 on the third peripheral.

[0182] The first pad plug 281 can be disposed between the first bonding pad BP1 and the second peripheral wiring line 243. The first pad plug 281 can connect the first bonding pad BP1 and the second peripheral wiring line 243.

[0183] The second bonding pad BP2 and the second pad plug 282 can be disposed on the first bonding pad BP1. The second bonding pad BP2 and the second pad plug 282 can be disposed inside the fourth peripheral insulating film 264.

[0184] The second bonding pad BP2 can be connected to the first bonding pad BP1. For example, the second bonding pad BP2 can contact the first bonding pad BP1. Because the second bonding pad BP2 is electrically connected to the first bonding pad BP1, the second bonding pad BP2 can be connected to peripheral wiring lines 241a and 243.

[0185] The first line BL1 can be located on the second bonding pad BP2. The second pad plug 282 can be located between the first line BL1 and the second bonding pad BP2. The second pad plug 282 can connect the first line BL1 and the second bonding pad BP2.

[0186] Because the second bonding pad BP2 is connected to the first bonding pad BP1, peripheral wiring lines 241a and 243 can be connected to the first bit line BL1. The first word lines WL11 and WL12, the second bit lines BL21 and BL22, and the second word line WL2 can be connected to the second bonding pad BP2.

[0187] The first pad plug 281 and the second pad plug 282 may include a conductive material comprising metal. Both the first bonding pad BP1 and the second bonding pad BP2 may include a conductive material comprising metal. Although both the first bonding pad BP1 and the second bonding pad BP2 are shown as single films, this is for illustrative purposes only, and one or more example embodiments are not limited thereto.

[0188] The fourth peripheral insulating film 264 may include an insulating material. Although the boundary between the third peripheral insulating film 263 and the fourth peripheral insulating film 264 is defined, this is only for illustrative purposes, and one or more example embodiments are not limited thereto. If the third peripheral insulating film 263 and the fourth peripheral insulating film 264 comprise the same material, the boundary between them may not be defined. According to one or more example embodiments, the boundary between the third peripheral insulating film 263 and the fourth peripheral insulating film 264 may be defined using the boundary between the first bonding pad BP1 and the second bonding pad BP2.

[0189] The bonding insulating film may be further disposed between the third peripheral insulating film 263 and the fourth peripheral insulating film 264. For example, the bonding insulating film may include, but is not limited to, SiCN.

[0190] and Figure 18 Unlike one or more example embodiments shown, the second word line WL2 may be disposed on the second bonding pad BP2. A second pad plug 282 may be disposed between the second word line WL2 and the second bonding pad BP2. The second pad plug 282 may connect the second word line WL2 and the second bonding pad BP2. In other words, having Figure 15 The storage cells in the shape of the second storage structure ST2 can be set on the second bonding pad BP2.

[0191] Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 , Figure 34 , Figure 35 , Figure 36 , Figure 37 , Figure 38 , Figure 39 , Figure 40 and Figure 41 This is an intermediate stage diagram illustrating a semiconductor device according to one or more example embodiments. For the sake of simplicity, repeated descriptions will be simplified or omitted.

[0192] refer to Figure 19 and Figure 20 In one or more example embodiments shown, the first line BL1 may be formed on the substrate 100.

[0193] As an example, a first portion of the lower insulating film 105 can be formed on the substrate 100. A lower conductive line film can be formed on the first portion of the lower insulating film 105. The lower conductive line film can be patterned to form a first line BL1. Next, a second portion of the lower insulating film 105 can be formed between the first lines BL1 that are adjacent to each other along the second direction DR2. Thus, the lower insulating film 105 can be formed.

[0194] As another example, a lower insulating film 105 can be formed on the substrate 100. A lower conductive trench can be formed inside the lower insulating film 105. Next, a first line BL1 filling the lower conductive trench can be formed.

[0195] refer to Figure 21 and Figure 22 In one or more example embodiments shown, a first protruding insulating pattern 170 may be formed on the first line BL1.

[0196] The first prominent insulating pattern 170 may include a plurality of first channel trenches CH_T that expose the first line BL1.

[0197] More specifically, a raised insulating film can be formed on the first line BL1. A first channel trench CH_T can be formed inside the raised insulating film. This forms a first raised insulating pattern 170.

[0198] refer to Figure 23 and Figure 24 In one or more example embodiments shown, multiple pre-channel patterns CH1_P can be formed along the sidewalls and bottom of the first channel groove CH_T.

[0199] Multiple pre-channel patterns CH1_P can be formed along the upper side of the first protruding insulating pattern 170. The pre-channel patterns CH1_P can be spaced apart in the second direction DR2.

[0200] More specifically, a pre-channel film can be formed on the first protruding insulating pattern 170. The pre-channel film can be completely formed on the sidewalls and bottom of the first channel trench CH_T. The pre-channel film can completely cover the upper side of the first protruding insulating pattern 170. Then, the pre-channel film can be patterned using a photolithography process. This forms a pre-channel pattern CH1_P extending in the first direction DR1.

[0201] refer to Figure 25 and Figure 26 In one or more example embodiments shown, the sacrificial pattern 176 can be formed on the pre-channel pattern CH1_P.

[0202] Sacrifice pattern 176 can fill a portion of the first channel groove CH_T.

[0203] exist Figure 25 In the process of forming the sacrificial pattern 176, an implantation process 50 can be performed. The implantation process 50 can implant materials such as boron (B), argon (Ar), and / or fluorine (F) into the pre-channel pattern CH1_P. The implantation process 50 can be performed in an inclined state. Because the sacrificial pattern 176 acts as a mask, a portion of the pre-channel pattern CH1_P that is shielded by the sacrificial pattern 176 is unaffected by the implantation process 50. That is, a portion of the pre-channel pattern CH1_P is physically damaged by the implantation process 50. While the implantation process 50 is being performed, the pre-channel pattern CH1_P that is shielded by the sacrificial pattern 176 is unaffected by the physical damage caused by the implantation process 50. Oxygen can escape from the pre-channel pattern CH1_P that has been physically damaged by the implantation process 50. As a result, a portion with a relatively low oxygen concentration can be formed inside the pre-channel pattern CH1_P.

[0204] Therefore, the portion of the pre-channel pattern CH1_P with a relatively low oxygen concentration can have metallic properties compared to other portions.

[0205] according to Figure 26 In one or more example embodiments shown, an impurity film 177 can be formed on the pre-channel pattern CH1_P and the sacrificial pattern 176. The impurity film 177 can be in direct contact with the pre-channel pattern CH1_P that is not covered by the sacrificial pattern 176. The impurity film 177 can include, for example, boron (B). After the impurity film 177 is formed, the boron (B) contained in the impurity film 177 can be diffused into the pre-channel pattern CH1_P that is not covered by the sacrificial pattern 176 by heat treatment. Therefore, the portion of the pre-channel pattern CH1_P with diffused boron (B) can have stronger metallic properties compared to the portion without diffused boron.

[0206] Then, the sacrificial pattern 176 located on the pre-channel pattern CH1_P can be removed.

[0207] It can be selectively applied and used. Figure 25 and Figure 26 The manufacturing process is described. Therefore, based on one or more example embodiments, the process can be performed using... Figure 27 and Figure 28 The manufacturing process is described, but not used. Figure 25 and Figure 26 The manufacturing process described.

[0208] refer to Figure 27 and Figure 28 In one or more example embodiments shown, the pre-channel pattern CH1_P formed on the upper side of the first protruding insulating pattern 170 may be removed to form the first channel pattern CH1.

[0209] A first channel pattern CH1 can be formed along the sidewalls and bottom of the first channel groove CH_T. The first channel pattern CH1 can contact the first line BL1 exposed by the first channel groove CH_T.

[0210] refer to Figure 29 and Figure 30 In one or more example embodiments shown, a pre-gate insulating pattern GOX1_P may be formed on the first channel pattern CH1.

[0211] A pre-gate insulating pattern GOX1_P can be formed along the outline of the first channel pattern CH1. The pre-gate insulating pattern GOX1_P can be formed on the upper side of the first protruding insulating pattern 170.

[0212] refer to Figure 31 and Figure 32 In one or more example embodiments shown, the first word lines WL11 and WL12 may be formed on the pre-gate insulating pattern GOX1_P.

[0213] More specifically, the first word line film can be formed on the pre-gate insulating pattern GOX1_P. The first word line film can be anisotropically etched to remove a portion of it. As a result, the first word lines WL11 and WL12 can be formed along the sidewalls of the first channel trench CH_T.

[0214] refer to Figure 33 and Figure 34 In one or more example embodiments shown, a first isolation insulation pattern 151 may be formed on the first word lines WL11 and WL12.

[0215] The first insulating pattern 151 may cover the first letter lines WL11 and WL12. The first insulating pattern 151 may fill a portion of the first channel groove CH_T.

[0216] Because the first isolation insulation pattern 151 fills a portion of the first channel trench CH_T, a portion of the pre-gate insulation pattern GOX1_P can be exposed.

[0217] refer to Figure 33 , Figure 34 , Figure 35 and Figure 36 In one or more example embodiments shown, the pre-gate insulation pattern GOX1_P exposed by the first isolation insulation pattern 151 can be removed.

[0218] Therefore, a first lower gate insulating pattern GOX1 can be formed. The pre-gate insulating pattern GOX1_P formed on the upper side of the first protruding insulating pattern 170 and the pre-gate insulating pattern GOX1_P formed on a portion of the sidewall of the first channel trench CH_T can be removed, and the first lower gate insulating pattern GOX1 can be formed.

[0219] refer to Figure 37 and Figure 38 In one or more example embodiments shown, a first upper gate insulating pattern GOX2 may be formed on the first channel pattern CH1 and the first isolation insulating pattern 151.

[0220] The first upper gate insulating pattern GOX2 can be formed along the sidewall of the first channel trench CH_T and the upper side of the first isolation insulating pattern 151. The first upper gate insulating pattern GOX2 can be formed along the upper side of the first protruding insulating pattern 170. The first upper gate insulating pattern GOX2 can be formed along the outline of the first channel pattern CH1 that extends beyond the upper side of the first isolation insulating pattern 151.

[0221] Next, second bit lines BL21 and BL22 can be formed on the first upper gate insulating pattern GOX2. More specifically, a bit line film can be formed on the first upper gate insulating pattern GOX2. The bit line film can be anisotropically etched to remove a portion of the bit line film. Therefore, the second bit lines BL21 and BL22 can be formed along the sidewalls of the first channel trench CH_T.

[0222] refer to Figure 39 and Figure 40 In one or more example embodiments shown, a second isolation insulation pattern 152 may be formed on the first upper gate insulation pattern GOX2.

[0223] A second isolation insulation pattern 152 may be formed inside the first channel trench CH_T. The second isolation insulation pattern 152 may be formed between adjacent second bit lines BL21 and BL22 along the first direction DR1. The second isolation insulation pattern 152 may not cover the upper side of the second bit lines BL21 and BL22.

[0224] Next, the vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2 can be formed on the second bit lines BL21 and BL22.

[0225] More specifically, a first pre-channel film can be formed on the second bit lines BL21 and BL22 and the second insulating pattern 152. The first pre-channel film can be formed along a portion of the sidewall of the first channel trench CH_T and the upper side of the first protruding insulating pattern 170. Next, the first pre-channel film can be patterned to form a first pre-channel pattern, such as a pre-channel pattern CH1_P. Viewed from a top view, the first pre-channel pattern can have a linear pattern shape extending in the first direction DR1. The first pre-channel pattern can be anisotropically etched to remove the first pre-channel pattern located on the upper side of the second insulating pattern 152 and the upper side of the first protruding insulating pattern 170. As a result, vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2, spaced apart in the first direction DR1, can be formed inside the first channel trench CH_T.

[0226] refer to Figure 41 In one or more example embodiments shown, a third isolation insulation pattern 153 may be formed on the second isolation insulation pattern 152.

[0227] A third insulating pattern 153 may be formed between the vertical portions CH2_V1 and CH2_V2 that are adjacent to each other along the first direction DR1 of the second channel pattern CH2. The third insulating pattern 153 may not cover the upper side of the vertical portions CH2_V1 and CH2_V2 of the second channel pattern CH2.

[0228] Subsequently, the horizontal portion CH2_H of the second channel pattern CH2 can be formed on the vertical portions CH2_V1 and CH2_V2 of the third insulating pattern 153 and the second channel pattern CH2. The second word line WL2 can be formed on the horizontal portion CH2_H of the second channel pattern CH2.

[0229] With use Figure 39 , Figure 40 and Figure 41 The descriptions of one or more example embodiments differ, and as an example, the shape is similar to a pre-channel pattern ( Figure 23 and Figure 24 The first pre-channel pattern of CH1_P can be a part of the second channel pattern CH2. In this case, the shape of the second channel pattern CH2 can be similar to... Figure 11 The shape is the same as described in the text.

[0230] With use Figure 39 , Figure 40 and Figure 41 The descriptions of one or more example embodiments differ, and as an example, the shape is similar to a pre-channel pattern ( Figure 23 and Figure 24 The first pre-channel pattern of CH1_P can be the second channel pattern CH2. In this case, the shape of the second channel pattern CH2 can be the same as... Figure 12 The shape is the same as described in the text.

[0231] In some embodiments, a method for manufacturing a semiconductor device includes: forming a first line extending in a first direction; forming a protruding insulating pattern on the first line, the protruding insulating pattern including a channel trench extending in a second direction; forming a first channel pattern extending along the sidewalls and bottom of the channel trench; forming a pre-gate insulating pattern along the outline of the first channel pattern and the upper side of the protruding insulating pattern; forming a first word line extending in the second direction on the pre-gate insulating pattern; forming an isolation insulating pattern covering the first word line and exposing a portion of the pre-gate insulating pattern disposed on the sidewalls of the channel trench; removing the pre-gate insulating pattern exposed by the isolation insulating pattern to form a lower gate insulating pattern; after forming the lower gate insulating pattern, forming an upper gate insulating pattern extending along the upper side of the protruding insulating pattern, the sidewalls of the channel trench, and the upper side of the isolation insulating pattern, the upper gate insulating pattern including a ferroelectric material film; forming a second bit line extending in the second direction on the upper gate insulating pattern inside the channel trench; forming a second channel pattern on the second bit line; and forming a second word line on the second channel pattern.

[0232] While one or more exemplary embodiments have been specifically shown and described above, these embodiments are not limited to the examples described above, but can be implemented in various different forms. It will be apparent to those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: The first line extends in a first direction and includes a first side and a second side opposite to the first side; A first channel pattern, the first channel pattern being located on the first side of the first bit line and connected to the first bit line; The first character line is located on the first channel pattern and extends in the second direction; A lower gate insulating pattern, wherein the lower gate insulating pattern is located between the first channel pattern and the first word line; The second bit line extends in the second direction and is spaced apart from the first bit line in the third direction; The second channel pattern is located on the second bit line and is in contact with the second bit line; An upper gate insulating pattern is located between the first channel pattern and the second channel pattern and between the first channel pattern and the second bit line, and is in contact with the first channel pattern. The upper gate insulating pattern includes a ferroelectric material film. as well as The second letter line is located on the second channel pattern and extends in the first direction.

2. The semiconductor device according to claim 1, wherein, The upper gate insulating pattern is in contact with the lower gate insulating pattern.

3. The semiconductor device according to claim 1, wherein, The first channel pattern includes a horizontal portion extending in the first direction and a vertical portion extending upward in the third direction, and Wherein, the first side of the first bit line is connected to the horizontal portion of the first channel pattern.

4. The semiconductor device according to claim 3, wherein, The vertical portion of the first channel pattern includes a first sidewall and a second sidewall opposite to the first sidewall. Wherein, the first sidewall and the second sidewall are spaced apart in the first direction, and The first character line and the second position line are disposed on the first sidewall of the vertical portion of the first channel pattern.

5. The semiconductor device according to claim 3, wherein, The upper gate insulating pattern contacts the vertical portion of the first channel pattern.

6. The semiconductor device according to claim 1, wherein, The second channel pattern includes a horizontal portion extending in the first direction and a vertical portion extending upward in the third direction, and The vertical portion of the second channel pattern overlaps with the first channel pattern in the first direction.

7. The semiconductor device according to claim 6, wherein, The horizontal portion of the second channel pattern is spaced apart from the first channel pattern in the third direction and contacts the second letter line.

8. The semiconductor device according to claim 1, wherein, Each of the first channel pattern and the second channel pattern comprises a metal-oxide-semiconductor.

9. The semiconductor device according to claim 1, wherein, The first channel pattern comprises a metal-oxide-semiconductor, and The second channel pattern comprises polycrystalline silicon.

10. A semiconductor device, the semiconductor device comprising: The first line extends in a first direction and includes a first side and a second side opposite to the first side; A first channel pattern is located on the first side of the first bit line and is connected to the first bit line; The first character line is located on the first channel pattern and extends in the second direction; A lower gate insulating pattern, wherein the lower gate insulating pattern is located between the first channel pattern and the first word line; An upper gate insulating pattern is located on the first word line and the lower gate insulating pattern, and includes a ferroelectric material film; The second bit line is located on the upper gate insulating pattern and extends in the second direction; The second channel pattern is located on the second bit line and is in contact with the second bit line; as well as The second letter line is located on the second channel pattern and extends in the first direction. The upper gate insulating pattern includes a horizontal portion extending in the first direction and a vertical portion extending upward in the third direction. The horizontal portion of the upper gate insulating pattern is located between the first word line and the second bit line.

11. The semiconductor device according to claim 10, wherein, The upper gate insulating pattern is in contact with the first channel pattern.

12. The semiconductor device according to claim 11, wherein, The horizontal portion of the upper gate insulating pattern is in contact with the lower gate insulating pattern.

13. The semiconductor device according to claim 10, wherein, The second bit line is located between the vertical portions of the upper gate insulating pattern, and The vertical portions of the upper gate insulating pattern are adjacent to each other in the first direction.

14. The semiconductor device according to claim 10, wherein, The first channel pattern includes a horizontal portion extending in the first direction and a vertical portion extending upward in the third direction, and Wherein, the first side of the first bit line is connected to the horizontal portion of the first channel pattern.

15. The semiconductor device according to claim 14, wherein, The vertical portion of the upper gate insulating pattern is located between the vertical portions of the first channel pattern, and The vertical portions of the upper gate insulating pattern are adjacent to each other in the first direction.

16. The semiconductor device of claim 14, wherein, The upper gate insulating pattern contacts the vertical portion of the first channel pattern.

17. The semiconductor device according to claim 10, wherein, The second channel pattern includes a horizontal portion extending in the first direction and a plurality of vertical portions extending upward in the third direction, and Each of the vertical portions of the second channel pattern protrudes from the horizontal portion of the second channel pattern toward the first bit line.

18. A semiconductor device, the semiconductor device comprising: The first line extends in a first direction and includes a first side and a second side opposite to the first side; A prominent insulating pattern is located on the first side of the first bit line and includes a channel or groove extending in a second direction; The first channel pattern extends along the sidewalls and bottom of the channel groove and connects to the first bit line; The first lower character line is located on the first channel pattern and extends in the second direction; The second lower character line is located on the first channel pattern, extends in the second direction, and is spaced apart from the first lower character line in the first direction; A lower gate insulating pattern, wherein the lower gate insulating pattern is located between the first channel pattern and the first lower word line and between the first channel pattern and the second lower word line; An upper gate insulating pattern is located on the first channel pattern, the first lower word line, and the second lower word line, and is in contact with the first channel pattern. The upper gate insulating pattern includes a horizontal portion extending in the first direction and a vertical portion extending upward in the third direction. The first upper-level line is located on the upper gate insulating pattern and extends in the second direction; The second upper line extends in the second direction and is spaced apart from the first upper line in the first direction; The second channel pattern is located on the first upper line and the second upper line, and is in contact with the first upper line and the second upper line. as well as The second letter line is located on the upper side of the protruding insulating pattern and extends in the first direction. The upper gate insulating pattern includes a ferroelectric material film.

19. The semiconductor device according to claim 18, wherein, The horizontal portion of the upper gate insulating pattern is in contact with the lower gate insulating pattern.

20. The semiconductor device according to claim 18, wherein, The upper gate insulating pattern extends along the upper side of the protruding insulating pattern.

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