Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate including a stack region and a pad region arranged in a first horizontal direction, a first word line and a second word line arranged at a same vertical level, extending in the first horizontal direction in the stack region and the pad region, and spaced apart in a second horizontal direction intersecting the first horizontal direction, a plurality of bit lines extending in a vertical direction in the stack region and spaced apart in the first horizontal direction, a plurality of memory cells located in the stack region, a word line pad between the first word line and the second word line in the pad region, and a word line contact extending in the vertical direction on the word line pad.

Description

Cross-reference to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0043051, filed on April 2, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to semiconductor memory devices, and more specifically, to three-dimensional (3D) semiconductor memory devices comprising a plurality of memory cells arranged in three dimensions. Background Technology

[0003] To meet the demand for miniaturized, multifunctional, and high-performance electronic products, high-capacity semiconductor memory devices are required. To provide high-capacity semiconductor memory devices, increased integration density is necessary. Since the integration density of existing two-dimensional (2D) semiconductor memory devices is determined based on the area occupied by a single memory cell, the integration density of 2D semiconductor memory devices is increasing, but remains limited. Therefore, 3D semiconductor memory devices have been proposed to increase memory capacity by vertically stacking multiple memory cells on a substrate. Summary of the Invention

[0004] This disclosure provides a three-dimensional (3D) semiconductor memory device with increased integration density.

[0005] The purpose of this disclosure is not limited to the foregoing, but those skilled in the art will clearly understand from the following description other purposes not described herein.

[0006] A semiconductor memory device according to an embodiment includes: a substrate including a stacked region and a pad region disposed in a first horizontal direction; a first word line and a second word line disposed at the same vertical horizontal direction, extending in the first horizontal direction in the stacked region and the pad region, and spaced apart in a second horizontal direction intersecting the first horizontal direction; a plurality of bit lines extending in the stacked region in a vertical direction and spaced apart in the first horizontal direction; a plurality of memory cells located in the stacked region; word line pads located in the pad region between the first word line and the second word line; and word line contacts extending in a vertical direction on the word line pads.

[0007] A semiconductor memory device according to an embodiment includes: a substrate including a stacked region and a pad region disposed in a first horizontal direction; a first word line stack including a plurality of first word lines, each of the plurality of first word lines extending in the stacked region and the pad region in the first horizontal direction and stacked in a vertical direction; a second word line stack spaced apart from the first word line stack in a second horizontal direction intersecting the first horizontal direction and including a plurality of second word lines, each of the plurality of second word lines extending in the stacked region and the pad region in the first horizontal direction and stacked in a vertical direction; a plurality of bit lines extending in the stacked region in a vertical direction and spaced apart in the first horizontal direction; and a plurality of word line pads located in the pad region between the first word line stack and the second word line stack and spaced apart in the vertical direction and the first horizontal direction.

[0008] A semiconductor memory device according to an embodiment includes: a substrate including a stacked region and a pad region disposed in a first horizontal direction; a first word line stack including a plurality of first word lines, each of the plurality of first word lines extending in the stacked region and the pad region in the first horizontal direction and stacked in a vertical direction; a second word line stack spaced apart from the first word line stack in a second horizontal direction intersecting the first horizontal direction and including a plurality of second word lines, each of the plurality of second word lines extending in the stacked region and the pad region in the first horizontal direction and stacked in a vertical direction; and a plurality of bit lines, each of which extends in the stacked region in a vertical direction. Extending upward and spaced apart from each other in a first horizontal direction; a plurality of memory cells located in a stacked region and including cell transistors and information storage elements; a plurality of word line pads arranged in the pad region between a first word line stack and a second word line stack in a first horizontal direction to have different vertical levels; and a plurality of word line contacts extending vertically on the plurality of word line pads, each word line contact including a plurality of contact portions spaced apart in a second horizontal direction, wherein the width of each of the plurality of word line pads in the first horizontal direction is smaller than the width of each word line pad in the second horizontal direction.

[0009] A method for manufacturing a semiconductor memory device according to an embodiment includes: forming a substrate including a stacked region and a pad region arranged in a first horizontal direction; forming a first word line stack, a second word line stack, a plurality of bit lines and a plurality of memory cells on the substrate, wherein the plurality of bit lines extend in a vertical direction in the stacked region and are spaced apart from each other in the first horizontal direction, and the plurality of memory cells are located in the stacked region; and forming a plurality of word line contacts and a plurality of word line pads, wherein the plurality of word line contacts extend in a vertical direction between the first word line stack and the second word line stack in the pad region, and the plurality of word line pads have different vertical levels and are spaced apart from each other in the first horizontal direction between the first word line stack and the second word line stack, wherein the first word line stack includes a plurality of first word lines extending in the first horizontal direction and stacked in the vertical direction, and the second word line stack is adjacent to the first word line stack in a second horizontal direction intersecting the first horizontal direction and includes a plurality of word lines extending in the first horizontal direction and stacked in the vertical direction.

[0010] The process of forming multiple word line contacts can create multiple through-holes to pass through the insulation structure between the first word line stack and the second word line stack.

[0011] Multiple through holes of different depths can be arranged in a first horizontal direction between the first word line stack and the second word line stack.

[0012] Multiple through holes of the same depth can be arranged in a second horizontal direction between the first letter stack and the second letter stack.

[0013] The process of forming multiple word line pads can be achieved by injecting material into through-holes to form the multiple word line pads.

[0014] The width of each of the multiple word line pads in the first horizontal direction may be smaller than the width of each word line pad in the second horizontal direction.

[0015] The width of each of the multiple word line pads in the second horizontal direction can be equal to the distance between the first word line stack and the second word line stack in the second horizontal direction. Attached Figure Description

[0016] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is an equivalent circuit diagram showing a stacked cell array of a semiconductor memory device according to an embodiment; Figure 2 This is a block diagram illustrating a semiconductor memory device according to an embodiment; Figure 3This is a perspective view showing a semiconductor memory device according to an embodiment; Figure 4 This is a perspective view schematically showing the pad area of ​​a semiconductor memory device according to an embodiment; Figure 5 This is a schematic plan view of the pad area of ​​a semiconductor memory device according to an embodiment; Figure 6 This is a perspective view showing a semiconductor memory device according to an embodiment; Figure 7A , Figure 7B and Figure 7C This is a plan view showing the arrangement of a semiconductor memory device according to an embodiment; Figure 8A This is a perspective view showing a portion of a semiconductor memory device according to an embodiment; Figure 8B This is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment; Figure 9 This is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment; Figure 10 This is an equivalent circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment; Figure 11A This is a perspective view showing a portion of a semiconductor memory device according to an embodiment; Figure 11B This is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment; Figure 12 This is a plan view showing the arrangement of a semiconductor memory device according to an embodiment; Figure 13 This is a plan view illustrating the arrangement of a semiconductor memory device according to an embodiment; and Figure 14A , Figure 14B , Figure 14C and Figure 14D This is a cross-sectional view used to describe a method of manufacturing a semiconductor memory device according to an embodiment. Detailed Implementation

[0017] In the following description, embodiments will be illustrated in detail with reference to the accompanying drawings. The same reference numerals refer to the same elements in the drawings, and redundant descriptions are omitted.

[0018] In embodiments, the terms "first" and "second" may be used to distinguish one element from another, rather than to limit the meaning. In embodiments, unless another case is clearly specified in the context, the singular form of an element may include the plural form.

[0019] Figure 1 This is an equivalent circuit diagram showing a stacked cell array of a semiconductor memory device according to an embodiment.

[0020] Reference Figure 1 According to an embodiment, the memory cell array 1 of the semiconductor memory device may include a plurality of sub-cell arrays SCA. Each of the plurality of sub-cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC. Each of the plurality of memory cells MC may include a cell transistor CT and an information storage element SP. The cell transistor (e.g., a single cell transistor) CT may be disposed between a word line (e.g., a single word line) WL and a bit line (e.g., a single bit line) BL. The information storage element SP may be a memory element that stores data. The information storage element SP may be a memory element that uses a capacitor, a memory element that uses a magnetic tunnel junction pattern, or a memory element that uses a variable resistor including a phase change material. In some embodiments, the memory cell MC may be dynamic random access memory (DRAM), the information storage element SP may be a capacitor, and reference will be made below. Figure 4 Describe its detailed examples.

[0021] Word lines (WL) can be conductive patterns (e.g., word lines) spaced apart from and disposed on / above the substrate. Multiple word lines (WL) can extend in a first horizontal direction (e.g., the X-axis direction). The word lines (WL) of a subcell array (e.g., a single subcell array) SCA can be spaced apart from each other in a vertical direction (e.g., the Z-axis direction). Bit lines (BL) can extend from the substrate in a vertical direction (e.g., the Z-axis direction). The bit lines (BL) of a subcell array SCA can be spaced apart from each other in a first horizontal direction (e.g., the X-axis direction).

[0022] In memory cell array 1, multiple word lines WL can extend in a first horizontal direction (e.g., the X-axis direction) and can be spaced apart from each other in each of a second horizontal direction (e.g., the Y-axis direction) and a vertical direction (e.g., the Z-axis direction). In memory cell array 1, multiple bit lines BL can extend in a vertical direction (e.g., the Z-axis direction) and can be spaced apart from each other in each of the first horizontal direction (e.g., the X-axis direction) and the second horizontal direction (e.g., the Y-axis direction). Multiple sub-cell arrays SCA can be arranged in the second horizontal direction (e.g., the Y-axis direction). The second horizontal direction (e.g., the Y-axis direction) can be perpendicular to the first horizontal direction (e.g., the X-axis direction).

[0023] The gate of the unit transistor CT can be connected to the word line WL, and the source region of the unit transistor CT can be connected to the bit line BL. The information storage element SP can be connected to the drain region of the unit transistor CT. In some embodiments, the information storage element SP can be a capacitor including a first electrode, a second electrode, and a capacitor dielectric layer disposed between the first electrode and the second electrode. The first electrode of the capacitor can be connected to the drain region of the unit transistor CT, and the second electrode of the capacitor can be connected to the ground line PP.

[0024] The memory cell array 1 of a semiconductor memory device may include a plurality of sub-cell arrays SCA, each of the plurality of sub-cell arrays SCA comprising: a plurality of memory cells MC, which are spaced apart from each other in a first horizontal direction (e.g., the X-axis direction) and a vertical direction (e.g., the Z-axis direction) to form rows and columns; a plurality of bit lines BL, which are connected to the cell transistors CT of the memory cells MC arranged in the vertical direction (e.g., the Z-axis direction) and are spaced apart from each other in the first horizontal direction (e.g., the X-axis direction) to extend in the vertical direction (e.g., the Z-axis direction); and a plurality of word lines WL, which are spaced apart from each other in the vertical direction (e.g., the Z-axis direction) to extend in the first horizontal direction (e.g., the X-axis direction), and the plurality of sub-cell arrays SCA may be arranged in a second horizontal direction (e.g., the Y-axis direction). The semiconductor memory device may include a plurality of memory cell arrays 1.

[0025] A first horizontal direction (e.g., the X-axis direction), a second horizontal direction (e.g., the Y-axis direction), and a vertical direction (e.g., the Z-axis direction) may be referred to as the first direction, the second direction, and the third direction, respectively. In another example, the first horizontal direction (e.g., the X-axis direction), the vertical direction (e.g., the Z-axis direction), and the second horizontal direction (e.g., the Y-axis direction) may be referred to as the first direction, the second direction, and the third direction, respectively. The first direction, the second direction, and the third direction may be perpendicular to each other.

[0026] Two adjacent subcell arrays (SCAs) in a second horizontal direction (e.g., the Y-axis direction) may share a bit line BL. The source regions of the cell transistors CT included in each of the two subcell arrays (SCAs) may be connected to the bit line BL shared by the two subcell arrays (SCAs). From each of the bit lines BL shared by the two subcell arrays (SCAs), the source and drain regions of the information storage elements SP and the cell transistors CT of each of the two subcell arrays (SCAs) may be arranged in opposite directions. For example, the information storage elements SP and the source and drain regions of the cell transistors CT of one subcell array (SCA) connected to the bit line BL shared by the two subcell arrays (SCAs) may be arranged sequentially in the second horizontal direction (e.g., the Y-axis direction), and the information storage elements SP and the source and drain regions of the cell transistors CT of the other subcell array (SCA) may be arranged in a direction opposite to the second horizontal direction (e.g., the Y-axis direction). For example, two memory cells MC can be arranged sequentially adjacent to each other in a second horizontal direction (e.g., the Y-axis direction) among multiple bit lines BL, and positioned in the same vertical direction in the second horizontal direction (e.g., the Y-axis direction).

[0027] Figure 2 This is a block diagram illustrating a semiconductor memory device 700 according to an embodiment.

[0028] Reference Figure 2 The semiconductor memory device 700 may include a memory cell array 701, which includes DRAM cells as memory cells and various circuit blocks for driving the DRAM cells. For example, a timing register 702 may be activated when the chip select signal CS transitions from an inactive level (e.g., logic high) to an active level (e.g., logic low). The timing register 702 may receive external command signals, such as a clock signal CLK, a clock enable signal CKE, a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and a data input / output (I / O) mask signal DQM. The timing register 702 may process the received external command signals to generate various internal command signals LCKE, LRAS, LCBR, LWE, LCAS, LWCBR, and LDQM for controlling the circuit blocks.

[0029] Some internal command signals generated by timing register 702 can be stored in programming register 704. For example, delay information or burst length information associated with data output can be stored in programming register 704. The internal command signals stored in programming register 704 can be provided to delay and burst length controller 706. Delay and burst length controller 706 can provide control signals for controlling the delay and / or burst length of data output to column decoder 710 or output buffer 712 through column address buffer 708.

[0030] Address register 720 can receive clock signal CLK and address signal ADD from an external source. Row address signals can be provided to row decoder 724 via row address buffer 722. Similarly, column address signals can be provided to column decoder 710 via column address buffer 708. Row address buffer 722 can also receive refresh address signals generated by the refresh counter in response to refresh commands LRAS and LCBR, and can provide either row address signals or refresh address signals to row decoder 724. For example, address register 720 can provide a memory bank signal to memory bank selector 726 for selecting a memory bank.

[0031] The row decoder 724 can decode the row address signal or refresh address signal input to the row address buffer 722. The row decoder 724 may include a plurality of sub-word line drivers (SWDs) 725. The plurality of sub-word line drivers 725 can activate word lines WL of the memory cell array 701. The plurality of sub-word line drivers 725 may be arranged adjacent to the memory cell array 701 and arranged at specific intervals along one side of the row decoder 724. For example, the plurality of sub-word line drivers 725 may be arranged adjacent to a first side (e.g., the left side) of the memory cell array 701, and the sense amplifier 730 may be arranged adjacent to a second side (e.g., the bottom side) of the memory cell array 701.

[0032] The column decoder 710 can decode the column address signal and perform selection operations on the bit lines BL of the memory cell array 701. For example, column select lines can be applied to the semiconductor memory device 700, and therefore selection operations can be performed via the column select lines.

[0033] The sense amplifier 730 amplifies the data in the memory cells MC of the memory cell array 701 selected by the row decoder 724 and the column decoder 710, and provides the amplified data to the output buffer 712. The data DQi to be written to the memory cells can be provided to the memory cell array 701 through the data input register 732, and the I / O controller 734 can control the data transfer operation through the data input register 732.

[0034] Figure 3 This is a perspective view showing a semiconductor memory device according to an embodiment. Figure 4 This is a perspective view schematically showing the pad area of ​​a semiconductor memory device according to an embodiment. Figure 5 This is a schematic plan view of the pad area of ​​a semiconductor memory device according to an embodiment.

[0035] Reference Figure 3 According to an embodiment, the semiconductor memory device 100 may include a stacked region STR and a pad region WPR. A stacked cell array structure CAR may be disposed in the stacked region STR. The stacked region STR and the pad region WPR may be arranged in a first horizontal direction (e.g., the X-axis direction). For ease of illustration, Figure 3 A single stacked region STR and a single pad region WPR are shown, but in some embodiments, the semiconductor memory device 100 may include a plurality of stacked regions STR and a plurality of pad regions WPR arranged alternately in a first horizontal direction (e.g., the X-axis direction).

[0036] The stacked cell array structure CAR can include multiple sub-cell arrays SCA (see Figure 1 A single stacked cell array (CAR) structure may include multiple sub-cell arrays (SCAs) arranged in a second horizontal direction (e.g., the Y-axis direction). Each of the multiple sub-cell arrays (SCAs) may include multiple bit lines (BLs), multiple word lines (WLs), and multiple memory cells (MCs). Each of the multiple memory cells (MCs) may include a cell transistor (CT) and an information storage element (SP). The cell transistor (CT) may include a semiconductor pattern 110. In some embodiments, the semiconductor pattern 110 may extend in the second horizontal direction (e.g., the Y-axis direction). The semiconductor pattern 110 may include a source region and a drain region. The source region and drain region may be located at the ends (e.g., opposite ends) of the semiconductor pattern 110 in the second horizontal direction (e.g., the Y-axis direction).

[0037] Multiple word lines (WLs) can extend in a first horizontal direction (e.g., the X-axis direction). In a stacked cell array (CAR) structure, multiple word lines (WLs) can extend in a first horizontal direction (e.g., the X-axis direction) and can be spaced apart from each other in each of a second horizontal direction (e.g., the Y-axis direction) and a vertical direction (e.g., the Z-axis direction). The word lines (WLs) of a single subcell array (SCA) can be spaced apart from each other in the vertical direction (e.g., the Z-axis direction). Multiple word lines (WLs) can extend in a first horizontal direction (e.g., the X-axis direction) within a stacked region (STR) and a pad region (WPR).

[0038] Two word lines WL positioned at the same vertical level and adjacent to each other in a second horizontal direction (e.g., the Y-axis direction) can be referred to as a first word line WL(A) and a second word line WL(B), respectively. Multiple first word lines WL(A) that overlap in the vertical direction (e.g., the Z-axis direction) among multiple word lines WL can be defined as a first word line stack WLS(A), and multiple second word lines WL(B) that overlap in the vertical direction (e.g., the Z-axis direction) among multiple word lines WL can be defined as a second word line stack WLS(B).

[0039] Bit lines BL can extend from the substrate in a vertical direction (e.g., the Z-axis direction). In a stacked cell array structure CAR, multiple bit lines BL can extend in a vertical direction (e.g., the Z-axis direction) and can be spaced apart from each other in each of a first horizontal direction (e.g., the X-axis direction) and a second horizontal direction (e.g., the Y-axis direction). A single subcell array SCA (see...) Figure 1 The bit lines BL can be spaced apart from each other in a first horizontal direction (e.g., the X-axis direction). For example, multiple bit lines BL can include a bit line column arranged with the bit lines BL spaced apart from each other to form a column in the first horizontal direction (e.g., the X-axis direction), and the bit line columns can be arranged with the bit lines spaced apart from each other in a second horizontal direction (e.g., the Y-axis direction). In some embodiments, a bit line column and a pair of word lines WL can be arranged one-dimensionally in the second horizontal direction (e.g., the Y-axis direction).

[0040] A cell transistor (e.g., a single cell transistor) CT can be disposed between a word line (e.g., a single word line) WL and a bit line (e.g., a single bit line) BL. An information storage element SP can be connected to the cell transistor CT. The information storage element SP can be a memory element for storing data. The gate of the cell transistor CT can be connected to the word line WL, and the source region of the cell transistor CT can be connected to the bit line BL. The information storage element SP can be connected to the drain region of the cell transistor CT.

[0041] In some embodiments, the source and drain regions of the unit transistor CT and the information storage element SP can be arranged in a second horizontal direction (e.g., the Y-axis direction) from the bit line BL connected to the source region of the unit transistor CT. The source and drain regions of the unit transistor CT and the information storage element SP connected to each of two adjacent bit lines BL in the second horizontal direction (e.g., the Y-axis direction) can be arranged in opposite directions. For example, the source and drain regions of the unit transistor CT and the information storage element SP connected to one of the two adjacent bit lines BL in the second horizontal direction (e.g., the Y-axis direction) (e.g., a selected bit line) BL can be arranged sequentially in the second horizontal direction (e.g., the Y-axis direction), and the source and drain regions of the unit transistor CT and the information storage element SP connected to the other bit line BL can be arranged in a direction opposite to the second horizontal direction (e.g., the Y-axis direction).

[0042] According to various embodiments, word line pads WLP can be disposed between a first word line WL(A) and a second word line WL(B), each disposed in a pad region WPR. One side of the word line pad WLP in a second horizontal direction (e.g., the Y-axis direction) can be connected to the first word line WL(A), and the other side of the word line pad WLP in the second horizontal direction (e.g., the Y-axis direction) can be connected to the second word line WL(B). One side of the word line pad WLP in the second horizontal direction (e.g., the Y-axis direction) can contact the first word line WL(A), and the other side of the word line pad WLP in the second horizontal direction (e.g., the Y-axis direction) can contact the second word line WL(B). The word line pad WLP can contact the side surface of the first word line WL(A) and can also contact the side surface of the second word line WL(B). The word line pad WLP can be connected (e.g., electrically connected) to the first word line WL(A) and the second word line WL(B).

[0043] like Figure 3 As shown, the word line pad WLP, the first word line WL(A), and the second word line WL(B) can be positioned at the same vertical level, but the embodiment is not limited to this. For example, the word line pad WLP can have a lower surface that contacts the lower surface of the first word line WL(A) and the lower surface of the second word line WL(B), and the word line pad WLP can have an upper surface that contacts the upper surface of the first word line WL(A) and the upper surface of the second word line WL(B).

[0044] Reference Figures 3 to 5The word line contact WLC can be disposed on the word line pad WLP. The word line contact WLC can extend vertically (e.g., in the Z-axis direction) on the word line pad WLP. The word line contact WLC can connect (e.g., electrically connect) the word line pad WLP to the sub-word line driver SWD.

[0045] The word line contact WLC may include a plurality of contact portions spaced apart from each other. For example, the plurality of contact portions of the word line contact WLC may include a first contact portion WLCa and a second contact portion WLCb extending in a vertical direction (e.g., the Z-axis direction) on the word line pad WLP. The lengths of the first contact portion WLCa and the second contact portion WLCb in the vertical direction (e.g., the Z-axis direction) may be equal to each other. The first contact portion WLCa and the second contact portion WLCb may be arranged spaced apart from each other in a direction that separates the first word line WL(A) and the second word line WL(B). For example, the first contact portion WLCa and the second contact portion WLCb may be arranged spaced apart from each other in a second horizontal direction (e.g., the Y-axis direction). The arrangement of the plurality of contact portions of the word line contact WLC according to the embodiment is not limited thereto. For example, the plurality of contact portions of the word line contact WLC may include a third contact portion and a fourth contact portion extending in a vertical direction (e.g., the Z-axis direction) and arranged in a first horizontal direction (e.g., the X-axis direction) on the word line pad WLP. In another example, the word line contact WLC may include only one contact portion.

[0046] According to an embodiment, because the word line contact WLC includes multiple contact portions having a first contact portion WLCa and a second contact portion WLCb, the shape and width of the word line pad WLP can be adjusted. According to an embodiment, during the operation of forming the word line contact WLC, it can be adjusted via through-holes (e.g., corresponding to the multiple contact portions). Figure 14A The TH) is injected with material to form the word line pads (WLP), and the vias (corresponding to multiple contact portions) can be adjusted (e.g., Figure 14A The number and position of the TH) are adjusted to modify the shape of the word line pad WLP.

[0047] In an embodiment, contact connection wiring CCL, which connects multiple contact portions of the word line contact WLC to each other, can be disposed on the word line contact WLC. For example, the contact connection wiring CCL can be connected to the first contact portion WLCa and the second contact portion WLCb, and can extend in a second horizontal direction (e.g., the Y-axis direction).

[0048] The word line pad (WLP) can be connected to the sub-word line driver (SWD) via word line contacts (WLC) and / or contact connections (CCL). See reference. Figure 5The diagram illustrates the contact connection wiring CCL for the sub-word line driver SWD, but the embodiments are not limited thereto. For example, wiring and / or contacts instead of the contact connection wiring CCL can be provided between the word line contact WLC and the sub-word line driver SWD, and the word line contact WLC can be connected (e.g., electrically connected) to the sub-word line driver SWD.

[0049] The sub-word line driver SWD can activate a word line WL connected to a memory cell MC to select the memory cell MC and a bit line BL. For example, the sub-word line driver SWD can activate a first word line WL(A) via a word line pad WLP to select a memory cell MC from the memory cells MC connected to the first word line WL(A) and the corresponding bit line BL among multiple bit lines BL, and can activate a second word line WL(B) via a word line pad WLP to select a memory cell MC from the memory cells MC connected to the second word line WL(B) and the corresponding bit line BL among multiple bit lines BL. Therefore, the first word line WL(A) and the second word line WL(B), each connected to a word line pad (e.g., a single word line pad) WLP, can share the word line pad (e.g., a single word line pad) WLP and the word line contact WLC and the sub-word line driver SWD, respectively connected to the word line pad WLP. The first word line WL(A) and the second word line WL(B), each connected to a word line pad (e.g., a single word line pad) WLP, can be driven by a sub-word line driver (e.g., a single sub-word line driver) SWD.

[0050] Reference Figure 5 Multiple sub-word line drivers (SWDs) can be configured. These multiple SWDs are alternately positioned on the side of the first word line WL(A) and the side of the second word line WL(B) in a first horizontal direction (e.g., the X-axis direction). The first word line WL(A) side can represent a position closer to the first word line WL(A) than the second word line WL(B), and the second word line WL(B) side can represent a position closer to the second word line WL(B) than the first word line WL(A). For example... Figure 5 As shown, because multiple sub-word line drivers SWD are alternately arranged on the side of the first word line WL(A) and the side of the second word line WL(B), wiring design can be facilitated, but the embodiment is not limited to this, and the multiple sub-word line drivers SWD can be arranged at selected locations based on the design.

[0051] Reference Figures 3 to 5Multiple word line pads (WLPs) can be configured. These multiple WLPs can be positioned between a first word line stack (WLS(A)) and a second word line stack (WLS(B)). Each of the multiple WLPs can be connected between a selected first word line (WL(A)) from among the multiple first word lines (WL(A)) included in the first word line stack (WLS(A)) and a selected second word line (WL(B)) from among the multiple second word lines (WL(B)) included in the second word line stack (WLS(B)). The selected first word line (WL(A)) and the selected second word line (WL(B)) can be positioned at the same vertical level.

[0052] To provide different descriptions, each of the multiple word line pads (WLPs) can be positioned at different vertical levels between word line pairs (e.g., first word line WL(A) and second word line WL(B)). The multiple word line pads (WLPs) can be spaced apart from each other in the vertical direction (e.g., the Z-axis direction).

[0053] The number of word line pads (WLP) can be the same as the number of first word lines (WL(A)) included in the first word line stack (WLS(A)). The number of word line pads (WLP) can be the same as the number of second word lines (WL(B)) included in the second word line stack (WLS(B)).

[0054] Multiple word line pads (WLPs) can be arranged in a row (e.g., a single row) in a first horizontal direction (e.g., the X-axis direction). The multiple word line pads (WLPs) can be spaced apart from each other in the first horizontal direction (e.g., the X-axis direction). Multiple word line pads (WLPs) with different vertical levels may not overlap each other in the vertical direction (e.g., the Z-axis direction). However, the embodiments are not limited to this. For example, the area of ​​a selected word line pad (WLP) among the multiple word line pads (WLPs) may overlap in the vertical direction (e.g., the Z-axis direction) with another word line pad (WLP) adjacent to the selected word line pad (WLP) in the first horizontal direction (e.g., the X-axis direction).

[0055] Reference Figures 3 to 5 The width W1 of each of the plurality of word line pads WLP in a first horizontal direction (e.g., the X-axis direction) can be smaller than the width W2 of each of the plurality of word line pads WLP in a second horizontal direction (e.g., the Y-axis direction). In an embodiment, the width W1 of the word line pad WLP in the first horizontal direction (e.g., the X-axis direction) can be smaller than the width of the pad region WPR in the first horizontal direction (e.g., the X-axis direction). Figure 6 The value obtained by dividing WPR_W by the number of word lines WL that overlap each other in the vertical direction (e.g., the Z-axis direction) (e.g., the number of first word lines WL(A) included in the first word line stack WLS(A)).

[0056] The width W2 of each of the multiple word line pads WLP in the second horizontal direction (e.g., the Y-axis direction) can be equal to the distance between the first word line WL(A) and the second word line WL(B) in the second horizontal direction (e.g., the Y-axis direction). The distance between the first word line WL(A) and the second word line WL(B) in the second horizontal direction (e.g., the Y-axis direction) can be defined as the distance between the inner surface IS1 of the first word line WL(A) facing the second word line WL(B) and the inner surface IS2 of the second word line WL(B) facing the first word line WL(A).

[0057] Reference Figures 3 to 5 The word line pads WLP in the pad region WPR may overlap with the information storage element SP in the stack region STR in a first horizontal direction (e.g., the X-axis direction). The word line pads WLP may be positioned between two adjacent word lines in a second horizontal direction (e.g., the Y-axis direction), with the information storage element SP located between these two word lines. For example, the first word line WL(A) and the second word line WL(B) may be spaced apart from each other in the second horizontal direction (e.g., the Y-axis direction), with the information storage element SP located between them.

[0058] A third word line stack WLS(C), comprising multiple third word lines WL(C) extending in a first horizontal direction (e.g., the X-axis direction) and stacked in a vertical direction (e.g., the Z-axis direction), can be disposed in the pad area WPR. The third word line stack WLS(C) can be adjacent to a first word line stack WLS(A) in a second horizontal direction (e.g., the Y-axis direction), with a bit line BL located between them. The bit line BL can be disposed one-dimensionally (or horizontally) between the first word line stack WLS(A) and the third word line stack WLS(C).

[0059] Multiple memory cells MC can be arranged with a cell pitch CPT in a second horizontal direction (e.g., the Y-axis direction). For example, when two sub-cell arrays SCA are adjacent to each other in the second horizontal direction (e.g., the Y-axis direction) (see...) Figure 1 When sharing a bit line BL, the cell pitch CPT can be the length from the portion between two adjacent information storage elements SP in a second horizontal direction (e.g., the Y-axis direction) to the center of the bit line BL in the second horizontal direction (e.g., the Y-axis direction). In some embodiments, such as in Figure 1 In the semiconductor memory device shown, when two sub-cell arrays SCA that are adjacent to each other in the second horizontal direction (e.g., the Y-axis direction) do not share bit lines BL, the cell pitch CPT can be the length of the portion from two information storage elements SP that are adjacent to each other in the second horizontal direction (e.g., the Y-axis direction) to the portion between two bit lines BL that are adjacent to each other in the second horizontal direction (e.g., the Y-axis direction).

[0060] Typically, when word line contacts are positioned on word lines extending from the stack area to the pad area, the word line thickness (e.g., thickness in the Y-axis direction) may need to be formed relatively large to accommodate the word line contacts, and thus the cell pitch may increase. Furthermore, due to the large thickness of the word lines overlapping each other in the vertical direction (e.g., the Z-axis direction), the parasitic capacitance between the word lines may increase.

[0061] A semiconductor memory device according to various embodiments may include a word line contact WLC disposed in a pad region WPR on a word line pad WLP disposed between a first word line WL(A) and a second word line WL(B). As described above, when the word line contact WLC is disposed on the word line pad WLP, the thickness of the first word line WL(A) and the second word line WL(B) in a second horizontal direction (e.g., the Y-axis direction) can be small, and therefore, the cell pitch CPT can be reduced, and the integration density of the semiconductor memory device 100 can be increased. When the thickness of the first word line WL(A) and the second word line WL(B) in the second horizontal direction (e.g., the Y-axis direction) is small, the word line contact WLC can be formed between the first word line WL(A) and the second word line WL(B), and therefore, the word line contact WLC can be formed more easily.

[0062] Furthermore, the thickness of multiple word lines WL that overlap each other in the vertical direction (e.g., the Z-axis direction) can be small, and multiple word line pads WLP can be spaced apart from each other in the first horizontal direction (e.g., the X-axis direction). Therefore, the area (or size) of the metal that overlaps each other in the vertical direction (e.g., the Z-axis direction) can be reduced, thereby reducing the size of parasitic capacitance occurring in the pad area WPR.

[0063] For example, a single sub-word line driver SWD can connect two word lines WL together via word line pads WLP and word line contacts WLC. Therefore, the available area (or size) for setting up the sub-word line driver SWD can be increased.

[0064] Refer again Figures 3 to 5 Word line contacts (WLCs) can be configured in multiple ways to be disposed on each of multiple word line pads (WLPs). The multiple word line contacts (WLCs) can be arranged in the same direction as the arrangement direction of the multiple word line pads (WLPs). For example, the word line contacts (WLCs) can be arranged in a first horizontal direction (e.g., the X-axis direction) between a first word line (WL) (A) and a second word line (WL) (B). The length of each of the multiple word line contacts (WLCs) disposed on different word line pads (WLPs) can be different in the vertical direction (e.g., the Z-axis direction).

[0065] Figure 6This is a perspective view showing a semiconductor memory device 100a according to an embodiment. Figure 6 In, with Figure 3 The same reference numerals in the accompanying drawings can refer to the above references. Figure 3 The components described are essentially the same, and therefore redundant descriptions can be omitted; the differences between them will be described below.

[0066] Reference Figure 6 The semiconductor memory device 100a according to an embodiment may include a plurality of stacked regions STR. The plurality of stacked regions STR may include a first stacked region STR1 and a second stacked region STR2. A pad region WPR may be disposed between the first stacked region STR1 and the second stacked region STR2. For example, the first stacked region STR1, the pad region WPR, and the second stacked region STR2 may be arranged in a first horizontal direction (e.g., the X-axis direction). For example, the first stacked region STR1 may be adjacent to one side of the pad region WPR in the first horizontal direction (e.g., the X-axis direction), and the second stacked region STR2 may be adjacent to the other side (e.g., the opposite side) of the pad region WPR in the first horizontal direction (e.g., the X-axis direction). Components in the first stacked region STR1 may be the same as components in the second stacked region STR2.

[0067] Each of the first word line WL(A) and the second word line WL(B) may extend in a first horizontal direction (e.g., the X-axis direction) to be disposed in the first stacked region STR1, the pad region WPR, and the second stacked region STR2. According to various embodiments, the word line pad WLP may be connected to the first word line WL(A) and the second word line WL(B), and therefore, the sub-word line driver SWD (see...) Figure 5 The memory cell MC located in each of the first stack region STR1 and the second stack region STR2 can be selected by using the word line contact WLC and the word line pad WLP.

[0068] Figure 7A , Figure 7B and Figure 7C This is a plan view showing the arrangement of a semiconductor memory device according to an embodiment.

[0069] Combination Figure 3 Reference Figure 7A The information storage element SP can be disposed between a first word line WL(A) and a second word line WL(B) respectively connected to a word line pad WLP. The first word line WL(A) and the second word line WL(B) respectively connected to the word line pad WLP can be connected to different bit lines BL. According to the embodiment, the semiconductor memory device can connect the first word line WL(A) and the second word line WL(B) that do not share a bit line BL.

[0070] When the first word line WL(A) and the second word line WL(B) are driven together, it may be difficult to compare the signal of the bit line BL connected to the first word line WL(A) with the signal of the bit line BL connected to the second word line WL(B) to perform a sense amplifier operation. Therefore, in one embodiment, a sense amplifier operation comparing bit line signals with complementary bit line signals can be performed by comparing the signal of the bit line BL connected to the first word line WL(A) with the signal of another line BL other than the bit line BL connected to the second word line WL(B). In another example, a sense amplifier operation can be performed by comparing the signal of the bit line BL connected to the second word line WL(B) with the signal of another line BL other than the bit line BL connected to the first word line WL(A).

[0071] Reference Figure 7B The semiconductor memory device 100 according to an embodiment may include striplines connecting bit lines BL spaced apart from each other in a second direction (e.g., the Y-axis direction). The striplines may include a first stripline SL1, which connects bit lines BL connected to a first word line WL(A) and another bit line BL, excluding the bit line BL connected to a second word line WL(B). The striplines may include a second stripline SL2, which connects bit lines BL connected to a second word line WL(B) and another bit line BL, excluding the bit line BL connected to the first word line WL(A). The striplines may also include a third stripline SL1' and a fourth stripline SL2', where complementary signals with respect to the first stripline SL1 are transmitted to the third stripline SL1', and complementary signals with respect to the second stripline SL2 are transmitted to the fourth stripline SL2'. The semiconductor memory device according to the embodiment may include a stripline wiring that connects bit lines BL spaced apart from each other in a second direction (e.g., the Y-axis direction) to each other, thereby reducing the number of sense amplifiers required to operate the semiconductor memory device.

[0072] Combination Figure 7A Reference Figure 7C In an embodiment, a single word line contact (WLC) disposed on a single word line pad (WLP) may include a single contact portion. As described above, the number, arrangement, and shape of the contact portions of the word line contact (WLC) can be varied depending on the design.

[0073] Figure 8A This is a perspective view showing a portion of a semiconductor memory device according to an embodiment. Figure 8B This is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment, and Figure 9 This is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment. In detail, Figure 8A It is shown Figure 3 A three-dimensional view of part I. Figure 8B It is along Figure 8A The cross-sectional view taken from line Ⅲ-Ⅲ', and Figure 9 It is along Figure 3 The cross-sectional view taken from line Ⅱ-Ⅱ'.

[0074] Reference Figure 8A , Figure 8B and Figure 9 According to an embodiment, the semiconductor memory device 100b may include a substrate 102 and a plurality of subcell arrays SCA. The plurality of subcell arrays SCA may be arranged in a second horizontal direction (e.g., the Y-axis direction). Each subcell array SCA may include a substrate 102, a plurality of word lines WL spaced apart from the substrate 102 and disposed on a main surface 102M of the substrate 102, a plurality of bit lines BL extending from the main surface 102M of the substrate 102 in a vertical direction (e.g., the Z-axis direction), a plurality of cell transistors CT disposed between the plurality of word lines WL and the plurality of bit lines BL, and a plurality of information storage elements SP respectively connected to the plurality of cell transistors CT. The cell transistors CT and the information storage elements SP may construct (or form) a memory cell MC.

[0075] Substrate 102 may include, for example, silicon (Si), such as polycrystalline Si, monocrystalline Si, or amorphous Si. In another example, substrate 102 may include at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and semiconductor elements such as germanium (Ge). In another example, substrate 102 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. For example, substrate 102 may include a buried oxide (BOX) layer. Substrate 102 may include conductive regions and, for example, may include impurity-doped wells or impurity-doped structures.

[0076] Multiple word lines WL may extend on substrate 102 in a first horizontal direction (e.g., the X-axis direction) and may be spaced apart from each other in a vertical direction (e.g., the Z-axis direction). Multiple bit lines BL may extend from substrate 102 in a vertical direction (e.g., the Z-axis direction) and may be spaced apart from each other in a first horizontal direction (e.g., the X-axis direction). Figure 8A The diagram shows multiple bit lines BL extending vertically (e.g., the Z-axis direction) and spaced apart from each other in a first horizontal direction (e.g., the X-axis direction), but as... Figure 1 and Figure 3As shown, multiple bit lines BL can extend in a vertical direction (e.g., the Z-axis direction) and can be spaced apart from each other in a first horizontal direction (e.g., the X-axis direction) and a second horizontal direction (e.g., the Y-axis direction).

[0077] A cell transistor (e.g., a single cell transistor) CT can be disposed between a word line (e.g., a single word line) WL and a bit line (e.g., a single bit line) BL. An information storage element SP can be connected to the cell transistor CT. The cell transistor CT and the information storage element SP can be arranged sequentially from the bit line BL connected to the cell transistor CT in a second horizontal direction (e.g., the Y-axis direction).

[0078] A word line WL may be adjacent to a semiconductor pattern 110. In some embodiments, the word line WL may surround the semiconductor pattern 110. A gate dielectric layer 132 may be disposed between the word line WL and the semiconductor pattern 110. The word line WL and the gate dielectric layer 132 may form a word line structure WLS. The semiconductor pattern 110 and the word line structure WLS may form a cell transistor CT.

[0079] Semiconductor pattern 110 may include a source region SD1, a drain region SD2, and a channel region CH disposed between the source region SD1 and the drain region SD2. The source region SD1 may be connected to a bit line BL, and the drain region SD2 may be connected to an information storage element SP. The source region SD1 may be referred to as a direct contact, and the drain region SD2 may be referred to as a buried contact.

[0080] The source region SD1, channel region CH, and drain region SD2 can be arranged sequentially from the bit line BL in either the second horizontal direction (e.g., the Y-axis direction) or the opposite direction of the second horizontal direction (e.g., the Y-axis direction). For example, two sub-cell arrays SCA that are adjacent to each other in the second horizontal direction (e.g., the Y-axis direction) can share the bit line BL between the two sub-cell arrays SCA. The source region SD1 of the cell transistor CT included in each of the two sub-cell arrays SCA can be connected to the bit line BL shared by the two sub-cell arrays SCA. The source region SD1, channel region CH, and drain region SD2 of the cell transistor CT of each of the two sub-cell arrays SCA, as well as the information storage element SP, can be arranged from the shared bit line BL in opposite directions (e.g., the positive Y-axis direction or the negative Y-axis direction). For example, the source region SD1, channel region CH, and drain region SD2 of the cell transistor CT of one sub-cell array SCA connected to a bit line BL shared by two sub-cell arrays SCA, as well as the information storage element SP, can be arranged sequentially in a second horizontal direction (e.g., the Y-axis direction). The source region SD1, channel region CH, and drain region SD2 of the cell transistor CT of the other sub-cell array SCA connected to the bit line BL, as well as the information storage element SP, can be arranged sequentially in the opposite direction of the second horizontal direction (e.g., the Y-axis direction). For example, two memory cells MC can be arranged sequentially adjacent to each other in the second horizontal direction (e.g., the Y-axis direction) between a pair of bit lines BL arranged at the same vertical level in the second horizontal direction (e.g., the Y-axis direction).

[0081] In some embodiments, the semiconductor pattern 110 may include a material having the same or similar etching properties as the substrate 102. In some embodiments, the semiconductor pattern 110 may include the same material as the substrate 102. In some embodiments, the semiconductor pattern 110 may include Si. In some embodiments, the semiconductor pattern 110 may include a single-crystal semiconductor material. For example, the semiconductor pattern 110 may include single-crystal Si. In other embodiments, the semiconductor pattern 110 may include a two-dimensional (2D) semiconductor material or an oxide semiconductor material.

[0082] Corresponding portions of the semiconductor pattern 110 and the word line WL may overlap each other in a vertical direction (e.g., the Z-axis direction). In some embodiments, the semiconductor pattern 110 may extend through the word line WL and may extend in a second horizontal direction (e.g., the Y-axis direction). At least a portion of the channel region CH may overlap with the word line WL in a vertical direction (e.g., the Z-axis direction). In some embodiments, the channel region CH may include a portion extending through the word line WL. For example, the channel region CH may be a portion of the semiconductor pattern 110 that overlaps with the word line WL in a vertical direction (e.g., the Z-axis direction). In some embodiments, the channel region CH may be a portion of the semiconductor pattern 110 that extends through the word line WL. The length of the channel region CH in the second horizontal direction (e.g., the Y-axis direction) may be equal to the length of the word line WL in the second horizontal direction (e.g., the Y-axis direction). The length of the source region SD1 in the second horizontal direction (e.g., the Y-axis direction) may be equal to the interval between the word line WL and the bit line BL in the second horizontal direction (e.g., the Y-axis direction).

[0083] The source region SD1 and drain region SD2 of semiconductor pattern 110 may be doped with a first impurity. In some embodiments, the channel region CH may be doped with a second impurity different from the first impurity. For example, the first impurity may allow each of the source region SD1 and drain region SD2 to have a first conductivity type, and the second impurity may allow the channel region CH to have a second conductivity type different from the first conductivity type. In some embodiments, the first conductivity type may be n-type, and the second conductivity type may be p-type, but this disclosure is not limited thereto. For example, the first conductivity type may be p-type, and the second conductivity type may be n-type, but this disclosure is not limited thereto. When the first conductivity type is n-type, the first impurity may be phosphorus (P), arsenic (As), or antimony (Sb), and when the second conductivity type is p-type, the second impurity may be boron (B), aluminum (Al), gallium (Ga), or indium (In). For example, the source region SD1 and drain region SD2 of semiconductor pattern 110 may be doped with phosphorus (P).

[0084] The word line WL may surround a portion of the semiconductor pattern 110 and the gate dielectric layer 132 may be located therebetween. For example, the gate dielectric layer 132 may cover the upper and lower surfaces of a portion of the semiconductor pattern 110 and may cover two side surfaces of the semiconductor pattern 110 in a first horizontal direction (e.g., the X-axis direction), and the word line WL may cover the gate dielectric layer 132, which covers the upper and lower surfaces of a portion of the semiconductor pattern 110 and covers two side surfaces of the semiconductor pattern 110 in the first horizontal direction (e.g., the X-axis direction).

[0085] In some embodiments, the word line WL may include a conductive barrier layer covering the gate dielectric layer 132 and a conductive fill layer covering the conductive barrier layer. The conductive barrier layer may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof.

[0086] The gate dielectric layer 132 may include at least one material selected from silicon oxide, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, and a ferroelectric material. In some embodiments, the gate dielectric layer 132 may have a stacked structure comprising a first dielectric layer comprising silicon oxide and a second dielectric layer comprising at least one material selected from high-k dielectric materials and ferroelectric materials.

[0087] Bit line BL can include metals. For example, bit line BL can include metals (such as titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), or nickel (Ni)), conductive metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium ruthenium nitride (RuTiN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or tantalum silicon nitride (TaSiN)), metal silicides (such as titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide (TaSi), cobalt silicide (CoSi), or nickel silicide (NiSi)), or combinations thereof.

[0088] An isolation insulating layer 105 may be disposed between the substrate 102 and the bit line BL. The bit line BL may be disposed on the isolation insulating layer 105. The semiconductor memory device 100b may include a plurality of isolation insulating layers 105 corresponding to a plurality of bit lines BL. The isolation insulating layer 105 may electrically insulate the substrate 102 from the bit line BL. At least a portion of the isolation insulating layer 105 may be embedded in the substrate 102. The isolation insulating layer 105 may be spaced apart from the semiconductor pattern 110. In some embodiments, the isolation insulating layer 105 may include an insulating material containing impurities. The impurities included in the isolation insulating layer 105 may be the same as the impurities included in the source region SD1. For example, the isolation insulating layer 105 may include a first impurity. In some embodiments, the isolation insulating layer 105 may include phosphosilicate glass (PSG) or borosilicate glass (BSG). For example, when the source region SD1 has an n-type as a first conductivity type, the isolation insulating layer 105 may include PSG. For example, when the source region SD1 has a p-type as a first conductivity type, the isolation insulating layer 105 may include BSG.

[0089] In some embodiments, the information storage element SP can be a capacitor structure 150, which includes a first electrode 152, a second electrode 156, and a capacitor dielectric layer 154 disposed between the first electrode 152 and the second electrode 156. The capacitor structure 150 may include: a first electrode 152 connected to the drain region SD2 of the semiconductor pattern 110 and extending in a second horizontal direction (e.g., the Y-axis direction); a capacitor dielectric layer 154 covering the first electrode 152; and a second electrode 156 covering the capacitor dielectric layer 154. The second electrode 156 may be connected to... Figure 1 The ground wiring PP shown may be a portion thereof. The first electrode 152 and the second electrode 156 may be referred to as the lower electrode and the upper electrode, respectively. The capacitor dielectric layer 154 may be disposed between the first electrode 152 and the second electrode 156.

[0090] The first electrode 152 may include a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. The capacitor dielectric layer 154 may include at least one material selected from ferroelectric materials and high-k dielectric materials having a dielectric constant higher than that of silicon oxide. For example, the capacitor dielectric layer 154 may include at least one of metal oxides and perovskite-structured dielectric materials. The second electrode 156 may include, for example, doped silicon, ruthenium (Ru), ruthenium oxide (RuO), platinum (Pt), platinum oxide (PtO), iridium (Ir), iridium oxide (IrO), strontium ruthenium oxide (SRO: SrRuO), barium strontium ruthenium oxide (BSRO: (Ba,Sr)RuO), calcium ruthenium oxide (CRO: CaRuO), barium ruthenium oxide (BaRuO), lanthanum strontium cobalt oxide (La(Sr,Co)O), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN), tantalum aluminum nitride (TaAlN), tantalum silicon nitride (TaSiN), or combinations thereof. Figure 3 The diagram illustrates multiple information storage elements SP spaced apart from each other, but this disclosure is not limited thereto. In some embodiments, when the multiple information storage elements SP are multiple capacitor structures 150, the multiple second electrodes 156 of the multiple capacitor structures 150 included in the sub-cell array SCA can be connected to each other to construct (or form) a single body. In some embodiments, when the multiple information storage elements SP are multiple capacitor structures 150, when the multiple capacitor structures 150 included in each of a pair of sub-cell array SCAs adjacent to each other in a second horizontal direction (e.g., the Y-axis direction) are adjacent to each other and face each other, the multiple second electrodes 156 of the multiple capacitor structures 150 included in each of the pair of sub-cell array SCAs can be connected to each other to construct (or form) a single body.

[0091] Multiple word line pads (WLPs) spaced apart from each other in a vertical direction (e.g., the Z-axis direction) can be positioned within a pad area (WPR). Word line contacts (WLCs) can be connected to the word line pads (WLPs). The word line contacts (WLCs) can include metal, conductive metal nitride, conductive metal silicide, or combinations thereof.

[0092] The insulating structure 190 may cover the subcell array SCA, word line pads WLP, and word line contacts WLC on the substrate 102. The insulating structure 190 may surround multiple word lines WL and multiple word line contacts WLC. In some embodiments, the insulating structure 190 may be formed of a single layer or multiple layers.

[0093] In some embodiments, the insulating structure 190 may include silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof. The low-k dielectric material may be a material having a dielectric constant lower than that of silicon oxide, and may include, for example, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), organosilicon glass (OSG), spin-on glass (SOG), spin-on polymer, or a combination thereof. In some embodiments, the insulating structure 190 may include an ultra-low k (ULK) layer having an ultra-low dielectric constant K of approximately 2.2 to approximately 2.4. The ULK layer may include SiOC or SiCOH.

[0094] Reference Figure 9 The width W1 of the word line pad WLP in the first horizontal direction (e.g., the X-axis direction) can be smaller than the width W2 of the word line pad WLP in the second horizontal direction (e.g., the Y-axis direction). Each of the plurality of word line pads WLP can be positioned at the same vertical level as its corresponding pair among the plurality of word lines WL. For example, the word line pad WLP can contact the lower or upper surface of the corresponding pair among the plurality of word lines WL.

[0095] An insulating structure 190 may surround multiple word lines WL. The insulating structure 190 may include a first insulating structure 190(A) and a second insulating structure 190(B) stacked in a vertical direction (e.g., the Z-axis direction). In an embodiment, the first insulating structure 190(A) may be disposed between word lines WL spaced apart in a horizontal direction. The second insulating structure 190(B) may be disposed between word lines WL spaced apart in a horizontal direction. In an embodiment, word line pads WLP may be disposed between adjacent second insulating structures 190(B) in a vertical direction (e.g., the Z-axis direction) and... Figure 9 Unlike the arrangement shown, in another embodiment, at least a portion of the first insulating structure 190(A) may be disposed on the lower and / or upper surface of the word line pad WLP.

[0096] Figure 10 This is an equivalent circuit diagram showing the memory cell array 1a of a semiconductor memory device according to an embodiment.

[0097] Reference Figure 10 The memory cell array 1a of the semiconductor memory device according to an embodiment may include a plurality of sub-cell arrays SCA. Each of the plurality of sub-cell arrays SCA may include a plurality of bit lines BLa, a plurality of word lines WL, and a plurality of memory cells MC. Each of the plurality of memory cells MC may include a cell transistor CT and an information storage element SP. The cell transistor (e.g., a single cell transistor) CT may be disposed between a word line (e.g., a single word line) WL and a bit line (e.g., a single bit line) BLa. The plurality of sub-cell arrays SCA may be arranged in a second horizontal direction (e.g., the Y-axis direction).

[0098] Multiple word lines WL can extend in a first horizontal direction (e.g., the X-axis direction). The word lines WL of a subcell array (e.g., a single subcell array) SCA can be spaced apart from each other in a vertical direction (e.g., the Z-axis direction). Bit lines BLa can extend in a vertical direction (e.g., the Z-axis direction). The bit lines BLa of a subcell array (e.g., a single subcell array) SCA can be spaced apart from each other in a first horizontal direction (e.g., the X-axis direction).

[0099] The gate of the unit transistor CT can be connected to the word line WL, and the source region of the unit transistor CT can be connected to the bit line BLa. The information storage element SP can be connected to the drain region of the unit transistor CT.

[0100] In some embodiments, the source and drain regions of the unit transistor CT and the information storage element SP can be arranged from the bit line BLa connected to the source region of the unit transistor CT in a second horizontal direction (e.g., the Y-axis direction) or in the opposite direction of the second horizontal direction (e.g., the Y-axis direction). The source and drain regions of the unit transistor CT connected to each of two adjacent bit lines BLa in the second horizontal direction (e.g., the Y-axis direction) and the information storage element SP can be arranged in opposite directions. For example, the source and drain regions of the unit transistor CT connected to one of the two adjacent bit lines BLa in the second horizontal direction (e.g., the Y-axis direction) and the information storage element SP can be arranged sequentially in the second horizontal direction (e.g., the Y-axis direction), and the source and drain regions of the unit transistor CT connected to the other bit line BLa and the information storage element SP can be arranged in the opposite direction to the second horizontal direction (e.g., the Y-axis direction).

[0101] Figure 11AThis is a perspective view showing a portion of a semiconductor memory device 101 according to an embodiment, and Figure 11B This is a cross-sectional view showing a portion of a semiconductor memory device 101 according to an embodiment. In detail, Figure 11B It is along Figure 11A The cross-sectional view taken from line V-V'.

[0102] Reference Figure 11A and Figure 11B The semiconductor memory device 101 may include a substrate 102 and a plurality of subcell arrays SCAa. The plurality of subcell arrays SCAa may be arranged in a second horizontal direction (e.g., the Y-axis direction). The subcell arrays SCAa may include: a substrate 102; a plurality of word lines WL spaced apart from and disposed on a main surface 102M of the substrate 102; a plurality of bit lines BLa extending from the main surface 102M of the substrate 102 in a vertical direction (e.g., the Z-axis direction); a plurality of cell transistors CT disposed between the plurality of word lines WL and the plurality of bit lines BLa; and a plurality of information storage elements SP respectively connected to the plurality of cell transistors CT. The plurality of cell transistors CT and the plurality of information storage elements SP may construct (or form) a plurality of memory cells MC.

[0103] Multiple word lines WL may extend on the substrate 102 in a first horizontal direction (e.g., the X-axis direction) and may be spaced apart from each other in each of a second horizontal direction (e.g., the Y-axis direction) and a vertical direction (e.g., the Z-axis direction). Multiple bit lines BLa may extend from the substrate 102 in a vertical direction (e.g., the Z-axis direction) and may be spaced apart from each other in each of the first horizontal direction (e.g., the X-axis direction) and the second horizontal direction (e.g., the Y-axis direction).

[0104] A cell transistor (e.g., a single cell transistor) CT can be disposed between a word line (e.g., a single word line) WL and a bit line (e.g., a single bit line) BLa. An information storage element SP can be connected to the cell transistor CT. The cell transistor CT and the information storage element SP can be arranged sequentially from the bit line BLa connected to the cell transistor CT in a second horizontal direction (e.g., the Y-axis direction) or in the opposite direction of the second horizontal direction (e.g., the Y-axis direction).

[0105] The source region SD1, channel region CH, and drain region SD2 can be arranged sequentially from bit line BLa in the second horizontal direction (e.g., the Y-axis direction) or in the opposite direction of the second horizontal direction (e.g., the Y-axis direction). Two sub-cell arrays SCAa that are adjacent to each other in the second horizontal direction (e.g., the Y-axis direction) may not share bit line BLa. The source region SD1, channel region CH, and drain region SD2 of the cell transistor CT connected to each of the two adjacent bit lines BLa in the second horizontal direction (e.g., the Y-axis direction), as well as the information storage element SP, can be arranged in opposite directions.

[0106] For example, the source region SD1, channel region CH, and drain region SD2 of the unit transistor CT connected to one of two adjacent bit lines BLa in the second horizontal direction (e.g., the Y-axis direction), as well as the information storage element SP, can be arranged sequentially in the second horizontal direction (e.g., the Y-axis direction), and the source region SD1, channel region CH, and drain region SD2 of the unit transistor CT connected to the other bit line BLa, as well as the information storage element SP, can be arranged in the opposite direction to the second horizontal direction (e.g., the Y-axis direction).

[0107] An insulating layer 105 may be disposed between the substrate 102 and the bit line BLa. The bit line BLa may be spaced apart from the substrate 102, and the insulating layer 105 is located between the bit line BLa and the substrate 102. The insulating layer 105 may electrically insulate the substrate 102 from the bit line BLa. At least a portion of the insulating layer 105 may be embedded in the substrate 102. The insulating layer 105 may be spaced apart from the semiconductor pattern 110. For example, the upper surface of the insulating layer 105 may be disposed at a vertical level lower than the lower surface of the lowest semiconductor pattern 110. The upper surface of the insulating layer 105 may be disposed at a vertical level equal to or higher than the upper surface of the substrate 102.

[0108] A pair of adjacent bit lines BLa in the second horizontal direction (e.g., the Y-axis direction) can be disposed on the insulating layer 105. The pair of bit lines BLa disposed on the insulating layer 105 can be spaced apart from each other, and an insulating structure 148 is located between these bit lines BLa. The pair of adjacent bit lines BLa in the second horizontal direction (e.g., the Y-axis direction) and the insulating structure 148 filling the area between these bit lines BLa can be disposed on the insulating layer 105. The sum of the width of the pair of adjacent bit lines BLa in the second horizontal direction (e.g., the Y-axis direction) and the width of the insulating structure 148 filling the area between these bit lines BLa in the second horizontal direction (e.g., the Y-axis direction) can be substantially equal to the width of the insulating layer 105 in the second horizontal direction (e.g., the Y-axis direction).

[0109] In some embodiments, the information storage element SP can be a capacitor structure 150, which includes a first electrode 152, a second electrode 156, and a capacitor dielectric layer 154 disposed between the first electrode 152 and the second electrode 156. The capacitor structure 150 may include: a first electrode 152 connected to the drain region SD2 of the semiconductor pattern 110 and extending in a second horizontal direction (e.g., the Y-axis direction); a capacitor dielectric layer 154 covering the first electrode 152; and a second electrode 156 covering the capacitor dielectric layer 154. The second electrode 156 may be connected to... Figure 10 The ground wiring PP shown in the figure may be a part of the ground wiring PP.

[0110] Figure 12 This is a plan view showing the arrangement of a semiconductor memory device according to an embodiment, and Figure 13 This is a plan view illustrating the arrangement of a semiconductor memory device according to an embodiment. Figure 12 and Figure 13 In, with Figure 7A The same reference numerals may denote substantially the same elements, and therefore redundant descriptions may be omitted, and the differences between them will be described below.

[0111] Reference Figure 12 Multiple bit lines BLa can include bit line columns, which are bit lines BLa arranged spaced apart from each other to form (or construct) columns in a first horizontal direction (e.g., the X-axis direction), and the bit line columns can be arranged spaced apart from each other in a second horizontal direction (e.g., the Y-axis direction). In a plan view, each of the bit line columns may not overlap with the word line pad WLP disposed between the first word line WL(A) and the second word line WL(B) in the first horizontal direction (e.g., the X-axis direction).

[0112] Reference Figure 13 Multiple bit lines BLa can include bit line columns, which are bit lines BLa arranged spaced apart from each other to form (or construct) columns in a first horizontal direction (e.g., the X-axis direction), and the bit line columns can be arranged spaced apart from each other in a second horizontal direction (e.g., the Y-axis direction). In a planar view, each of the bit line columns can overlap with a word line pad WLP disposed between a first word line WL(A) and a second word line WL(B) in the first horizontal direction (e.g., the X-axis direction). In a planar view, each of the bit line columns can be disposed between the first word line WL(A) and the second word line WL(B).

[0113] Figures 14A to 14D This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and shows... Figure 4 The cross-sectional surface of part IV. Figures 14A to 14D In, with Figure 3 The same reference numerals may denote substantially the same elements, and therefore redundant descriptions may be omitted, and the method of manufacturing the semiconductor memory device 100 will be described briefly.

[0114] A method for manufacturing a semiconductor memory device 100 according to an embodiment may include: forming a substrate (e.g., Figure 8A The operation of 102) includes a substrate comprising a first horizontal direction (e.g., Figure 3 Stacked areas arranged along the X-axis direction (e.g., Figure 3 STR) and pad areas (e.g., Figure 3 WPR); on a substrate (e.g., Figure 8A The first letter line stack is formed on 102) (e.g., Figure 3 WLS(A)), second word line stack (e.g., Figure 3 WLS(B)), set in the stacking area (e.g., Figure 3 Multiple bit lines in the STR (e.g., Figure 3 (BL) and multiple memory units (e.g., Figure 3 The operation of the MC; and the formation of multiple word line contacts (e.g., Figure 3 WLC) and multiple word line pads (e.g., Figure 3 The operation of WLP, multiple word line contacts (e.g., Figure 3 WLC) in the pad area (e.g., Figure 3 In the WPR) in the first word line stack (e.g., Figure 3 WLS(A)) and second word line stack (e.g., Figure 3 The WLS(B) extends vertically (e.g., along the Z-axis) between multiple word line pads (e.g., Figure 3The WLP) has different vertical and horizontal dimensions and is stacked in the first letter line (e.g., Figure 3 WLS(A)) and second word line stack (e.g., Figure 3 The WLS(B) are spaced apart from each other in the first horizontal direction (e.g., the X-axis direction).

[0115] Reference Figure 14A A first word line stack WLS(A) and a second word line stack WLS(B) can be formed on substrate 102, and then vias TH can be formed in an insulating structure 190 surrounding the first word line stack WLS(A) and the second word line stack WLS(B). The insulating structure 190 may include the first insulating structure 190(A) and the second insulating structure 190(B) stacked in a vertical direction (e.g., the Z-axis direction). Multiple vias TH can be provided. Multiple vias TH can be formed between the first word line stack WLS(A) and the second word line stack WLS(B). Figures 14A to 14D The process for forming word line pads (WLPs) is shown, and as follows: Figure 14A As shown, the lower surfaces of multiple vias TH can be of equal verticality. The lower surfaces of vias TH formed at the location where a word line pad WLP is formed and the lower surfaces of vias TH formed at the location where another word line pad WLP is formed can have different vertical levels.

[0116] Reference Figures 14A to 14D An empty space can be formed by removing at least a portion of the first insulating structure 190(A) below the through-hole TH via the through-hole TH. The word line pad WLP can be formed by injecting material for forming the word line pad WLP into the empty space via the through-hole TH. Subsequently, the word line contact WLC can be formed by injecting material for forming the word line contact WLC into the through-hole TH, and subsequently, contact connection wiring CCL can be formed on the word line contact WLC.

[0117] In the foregoing, embodiments have been described in the accompanying drawings and specification. Embodiments have been described using the terminology described herein, but this is merely for descriptive purposes and not for limiting the meaning or scope of the disclosure as defined in the appended claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be implemented from this disclosure. Accordingly, the spirit and scope of this disclosure may be defined based on the spirit and scope of the appended claims.

[0118] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, comprising: The substrate includes a stacked region and a pad region arranged in a first horizontal direction; First letter line and second letter line, the first letter line and the second letter line are located at the same vertical level and extend in the first horizontal direction in the stack area and the pad area, the first letter line and the second letter line are spaced apart in a second horizontal direction that intersects the first horizontal direction; Multiple bit lines that extend vertically in the stacked region and are spaced apart in the first horizontal direction; Multiple memory cells are located in the stacked area; Word line pads, which are located in the pad region between the first word line and the second word line; as well as A letter line contact that extends in the vertical direction on the letter line pad.

2. The semiconductor memory device according to claim 1, wherein, The word line pads are configured to be electrically connected to the first word line and the second word line.

3. The semiconductor memory device according to claim 1, wherein, The word line contact includes a first contact portion and a second contact portion arranged on the word line pad in the second horizontal direction.

4. The semiconductor memory device according to claim 3, further comprising: The contact connection wiring connects the first contact portion to the second contact portion and extends in the second horizontal direction.

5. The semiconductor memory device according to claim 1, wherein, The width of the word line pad in the second horizontal direction is equal to the distance between the first word line and the second word line in the second horizontal direction.

6. The semiconductor memory device according to claim 1, wherein, The width of the word line pad in the first horizontal direction is smaller than the width of the word line pad in the second horizontal direction.

7. The semiconductor memory device according to claim 1, wherein, The stacked region includes a first stacked region adjacent to a first side of the pad region in the first horizontal direction and a second stacked region adjacent to a second side of the pad region in the first horizontal direction. Each of the first word line and the second word line extends to the first stack area, the pad area, and the second stack area.

8. The semiconductor memory device according to claim 1, wherein, Each of the plurality of memory cells includes a unit transistor and an information storage element, and The unit transistor includes a semiconductor pattern extending in the second horizontal direction from each of the plurality of bit lines and at least one of the first word line and the second word line.

9. The semiconductor memory device according to claim 8, wherein, The word line pads in the pad region overlap with the information storage elements in the stack region in the first horizontal direction.

10. The semiconductor memory device according to claim 8, wherein, The word line pads in the pad region overlap with the plurality of bit lines in the stack region in the first horizontal direction.

11. The semiconductor memory device according to claim 1, wherein, The word line pad contacts the first word line on a first side in the second horizontal direction, and the word line pad contacts the second word line on a second side in the second horizontal direction.

12. A semiconductor memory device, comprising: The substrate includes a stacked region and a pad region arranged in a first horizontal direction; The first word line stack includes a plurality of first word lines, each of which extends in the first horizontal direction and is stacked in the vertical direction in the stacking area and the pad area. The second word line stack is spaced apart from the first word line stack in a second horizontal direction intersecting the first horizontal direction, and includes a plurality of second word lines, each of which extends in the first horizontal direction and stacks in the vertical direction in the stacking area and the pad area. Multiple bit lines that extend in the stacked region in the vertical direction and are spaced apart in the first horizontal direction; as well as Multiple word line pads are located in the pad region between the first word line stack and the second word line stack and are spaced apart in the vertical direction and the first horizontal direction.

13. The semiconductor memory device according to claim 12, wherein, The plurality of word line pads are arranged in a row in the first horizontal direction.

14. The semiconductor memory device according to claim 12, wherein, Each of the plurality of word line pads is configured to be electrically connected to a selected first word line among the plurality of first word lines and a selected second word line among the plurality of second word lines, the selected first word line and the selected second word line being located at the same vertical level.

15. The semiconductor memory device of claim 12, further comprising: Multiple word line contacts are located on the multiple word line pads in the pad area; as well as Multiple sub-word line drivers are configured to be electrically connected to the multiple word line contacts.

16. The semiconductor memory device according to claim 15, wherein, Each of the plurality of word line contacts includes a plurality of contact portions spaced apart in the second horizontal direction on a selected word line pad among the plurality of word line pads.

17. The semiconductor memory device of claim 12, further comprising: A third letter stack, adjacent to the second letter stack in the second horizontal direction, includes a plurality of third letter lines, each of which extends in the first horizontal direction and stacks in the vertical direction within the stacking region and the pad region. The multiple bit lines are horizontally located between the second word line stack and the third word line stack.

18. The semiconductor memory device according to claim 12, wherein, The multiple bit lines are horizontally located between the first word line stack and the second word line stack.

19. The semiconductor memory device according to claim 12, wherein, The number of the plurality of word line pads is equal to the number of the plurality of first word lines included in the first word line stack.

20. A semiconductor memory device, comprising: The substrate includes a stacked region and a pad region arranged in a first horizontal direction; The first word line stack includes a plurality of first word lines, each of which extends in the first horizontal direction and is stacked in the vertical direction in the stacking area and the pad area. The second word line stack is spaced apart from the first word line stack in a second horizontal direction intersecting the first horizontal direction and includes a plurality of second word lines, each of the plurality of second word lines extending in the first horizontal direction and stacked in the vertical direction in the stacking area and the pad area. Multiple bit lines that extend in the stacked region in the vertical direction and are spaced apart in the first horizontal direction; Multiple memory cells are located in the stacked region and include unit transistors and information storage elements; Multiple word line pads are arranged at different vertical levels in the first horizontal direction within the pad region between the first word line stack and the second word line stack. as well as A plurality of word line contacts extending in the vertical direction on the plurality of word line pads, each word line contact including a plurality of contact portions spaced apart from each other in the second horizontal direction. Wherein, the width of each of the plurality of word line pads in the first horizontal direction is smaller than the width of each word line pad in the second horizontal direction.

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