A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a shallow trench isolation structure in a substrate and a word line structure in the shallow trench isolation structure. The shallow trench isolation structure comprises a first shallow trench isolation structure, a second shallow trench isolation structure and a third shallow trench isolation structure with different widths, and the word line structure in the different shallow trench isolation structures comprises different film layer materials. Thus, the parasitic capacitance between adjacent word line structures is avoided, the stability of the word line structure is improved, and the performance and reliability of the semiconductor device are finally improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] As semiconductor devices become miniaturized and integrated circuits become more complex, the size of components continues to shrink, and their structures are constantly changing. Therefore, maintaining the performance of small-sized semiconductor components is currently the industry's main goal. In semiconductor manufacturing processes, multiple shallow trench isolation structures and active regions are often defined on a substrate as a basis, and then the required components, such as word line structures, are formed on the active regions or within the shallow trench isolation structures.

[0003] Generally, word line structures contain conductive materials. However, with the requirements of miniaturization and increased integration, the parasitic capacitance between adjacent word line structures increases, which also poses many limitations and challenges to the manufacturing process, leading to performance degradation and reduced reliability of semiconductor devices. Summary of the Invention

[0004] One objective of this application is to provide a semiconductor device and a method for manufacturing the same, which avoids parasitic capacitance between adjacent word line structures by changing the film material contained in word line structures disposed in different shallow trench isolation structures, thereby improving the structural stability of the word line structures and ultimately improving the performance and reliability of the semiconductor device.

[0005] To achieve the above objectives, one embodiment of this application provides a semiconductor device, comprising:

[0006] The substrate includes a shallow trench isolation structure and a plurality of active regions defined by the shallow trench isolation structure, the shallow trench isolation structure including a first shallow trench isolation structure, a second shallow trench isolation structure and a third shallow trench isolation structure with different widths;

[0007] The word line structure is located in the shallow trench isolation structure and extends along the first direction to above the adjacent active area, and the word line structure located in the first shallow trench isolation structure includes a conductive layer and an insulating cap layer arranged sequentially from bottom to top.

[0008] In a second direction perpendicular to the first direction, the top surface of the first shallow trench isolation structure has a first width, the top surface of the second shallow trench isolation structure has a second width, and the top surface of the third shallow trench isolation structure has a third width, wherein the first width is smaller than the second width, and the second width is smaller than the third width;

[0009] The first shallow trench isolation structure and the second shallow trench isolation structure each include a first insulating layer, and the third shallow trench isolation structure includes the first insulating layer, the second insulating layer and the third insulating layer stacked from bottom to top.

[0010] Optionally, the semiconductor device may further include:

[0011] A dummy word line structure is located in the second shallow trench isolation structure and extends along the first direction above the adjacent active area. The dummy word line structure located in the second shallow trench isolation structure includes the insulating cap layer, which is made of the same material as the second insulating layer.

[0012] Optionally, the lowest point of the bottom surface of the dummy word line structure is higher than the top surface of the conductive layer in the word line structure.

[0013] Optionally, the insulating cap layer is made of the same material as the second insulating layer.

[0014] Optionally, the insulating capping layer comprises silicon nitride.

[0015] Optionally, both the word line structure and the dummy word line structure further include a gate dielectric layer; the gate dielectric layer is located above the first insulating layer, and the lowest point of the bottom surface of the gate dielectric layer in the first shallow trench isolation structure is lower than the lowest point of the bottom surface of the gate dielectric layer in the second shallow trench isolation structure.

[0016] Optionally, in the second direction, the first insulating layer located in the third shallow trench isolation structure has a fourth width, which is greater than half of the second width.

[0017] Optionally, the second shallow trench isolation structure further includes a second insulating layer, wherein the lowest point of the bottom surface of the second insulating layer is higher than the lowest point of the bottom surface of the word line structure.

[0018] To achieve the above objectives, another embodiment of this application provides a semiconductor device, comprising:

[0019] The substrate includes a shallow trench isolation structure and a plurality of active regions defined by the shallow trench isolation structure, the shallow trench isolation structure including a first shallow trench isolation structure, a second shallow trench isolation structure and a third shallow trench isolation structure;

[0020] The first silicon oxide layer is located in the first shallow trench isolation structure, the second shallow trench isolation structure and the third shallow trench isolation structure, respectively;

[0021] A silicon nitride layer is located on the first silicon oxide layer in the third shallow trench isolation structure;

[0022] A second silicon oxide layer is located on the silicon nitride layer in the third shallow trench isolation structure; wherein, in the second direction, the width of the first silicon oxide layer in the third shallow trench isolation structure is greater than half the width of the second shallow trench isolation structure.

[0023] The word line structure is located in the first shallow trench isolation structure and includes a conductive layer and an insulating cover layer arranged sequentially from bottom to top;

[0024] A dummy word line structure is located in the second shallow trench isolation structure. The dummy word line structure includes the insulating capping layer, and the lowest point of the bottom surface of the dummy word line structure is higher than the top surface of the conductive layer in the word line structure.

[0025] Optionally, the insulating capping layer comprises silicon nitride.

[0026] Optionally, both the word line structure and the dummy word line structure further include a gate dielectric layer; the gate dielectric layer is located above the first silicon oxide layer, and the lowest point of the bottom surface of the gate dielectric layer in the first shallow trench isolation structure is lower than the lowest point of the bottom surface of the gate dielectric layer in the second shallow trench isolation structure.

[0027] Optionally, the second shallow trench isolation structure further includes the silicon nitride layer, wherein the lowest point of the bottom surface of the silicon nitride layer is higher than the lowest point of the bottom surface of the word line structure.

[0028] Optionally, in the second direction, the top surface of the first shallow trench isolation structure has a first width, the top surface of the second shallow trench isolation structure has a second width, and the top surface of the third shallow trench isolation structure has a third width, wherein the first width is smaller than the second width, and the second width is smaller than the third width.

[0029] As described above, the semiconductor device and its fabrication method of this application include: a shallow trench isolation structure located in a substrate, and word line structures located within the shallow trench isolation structure. The shallow trench isolation structure includes a first shallow trench isolation structure, a second shallow trench isolation structure, and a third shallow trench isolation structure with different widths. The word line structures located within different shallow trench isolation structures contain different film layer materials. For example, the word line structure in the first shallow trench isolation structure includes a conductive layer and an insulating capping layer, while the word line structures in at least one other shallow trench isolation structure only contain an insulating capping layer. This avoids parasitic capacitance between adjacent word line structures, improves the stability of the word line structure, eliminates the need for additional process steps, and ultimately improves the performance and reliability of the semiconductor device. Attached Figure Description

[0030] The accompanying drawings provide a more in-depth understanding of embodiments of this application and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams and are for illustrative and drawing convenience, and relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0031] Figure 1 This is a top view of a partial structure of the semiconductor device in an embodiment of this application;

[0032] Figure 2 for Figure 1 A cross-sectional view of an example of a partial structure of the semiconductor device shown along the AA' tangent direction;

[0033] Figure 3 for Figure 1 A cross-sectional view of another example of the local structure of the semiconductor device shown along the AA' tangent direction;

[0034] Figure 4 for Figure 1 A cross-sectional view of another example of the local structure of the semiconductor device shown along the AA' tangent direction;

[0035] Figures 5-11 For this Figure 3 The example shown is a partial structural cross-sectional view of the semiconductor device fabrication method at each step;

[0036] Figures 12-17 For this Figure 2 and Figure 4 The example shown is a partial structural cross-sectional view of the semiconductor device fabrication method at each step;

[0037] The attached figures are labeled as follows:

[0038] 100 - Substrate, 100A - First Region, 100B - Second Region, ACT - Active Region, 110 - Shallow Trench Isolation Structure, 111 - First Shallow Trench Isolation Structure, 112 - Second Shallow Trench Isolation Structure, 113 - Third Shallow Trench Isolation Structure, 114 - Fourth Shallow Trench Isolation Structure, 1101 - First Insulating Layer (First Silicon Oxide Layer), 1102 - Second Insulating Layer (Silicon Nitride Layer), 1103 - Third Insulating Layer (Second Silicon Oxide Layer), 101 - First Isolation Trench, 102 - Second Isolation Trench, 103 - Third Isolation Trench 104-First word line groove, 105-Second word line groove, 106-Dummy word line groove, 121-Gate dielectric layer, 122-Work function layer, 123-Conductive layer, 124-Insulating capping layer, 120-Word line structure, 120a-First word line structure, 120b-Dummy word line structure, 120c-Second word line structure, W1-First width, W2-Second width, W3-Third width, H1-Height difference between the top surface of the first insulating layer (first silicon oxide layer) in the first shallow trench isolation structure and the second shallow trench isolation structure.

[0039] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0040] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0041] To make the technical solutions and advantages of the embodiments of this application clearer, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the implementation methods described herein. Rather, these implementation methods are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0042] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the present application. It is understood that the meanings of "on," "above," and "over" in the present application should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the present application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.

[0043] To facilitate explanation and understanding of the semiconductor device of this application, spatial reference directions such as a first direction D1, a second direction D2, and a third direction D3 are shown in the figure. The first direction D1 and the second direction D2 are substantially parallel to the surface of the substrate 100, and the third direction D3 is substantially perpendicular to the surface of the substrate 100. Furthermore, the first direction D1, the second direction D2, and the third direction D3 are all mutually perpendicular. In this document, the first direction D1 and the second direction D2 may also be referred to as horizontal directions, and the third direction D3 may also be referred to as vertical directions.

[0044] Please see Figure 1 , Figure 1 This is a partial top view of the semiconductor device in an embodiment of this application.

[0045] The semiconductor device is, for example, a dynamic random access memory device, which includes at least one transistor element and at least one capacitor to serve as the smallest unit of a DRAM array (memory cell) and to receive voltage signals from a bit line structure (not shown) and a word line structure.

[0046] like Figure 1As shown, the semiconductor device in this embodiment may specifically include: a substrate 100, multiple active regions ACT, multiple shallow trench isolation structures 110, multiple word line structures 120, and at least one dummy word line structure 120b. The substrate 100 may be divided into a first region 100A and a second region 100B. The first region 100A is, for example, a cell region of the semiconductor device, and the second region 100B is, for example, an isolation region, the intermediate region between the first region 100A and other regions, such as a peripheral region, in the semiconductor device. The first region 100A and the second region 100B are arranged adjacently, but this is not a limitation. Multiple shallow trench isolation structures 110 are disposed within the substrate 100, defining multiple active regions ACT on the substrate 100. Furthermore, the shallow trench isolation structures 110 may be specifically divided into a first shallow trench isolation structure 111, a second shallow trench isolation structure 112, a third shallow trench isolation structure 113, and a fourth shallow trench isolation structure 114 with different widths. The top surface of the first shallow trench isolation structure 111 has a first width in the second direction D2, the top surface of the second shallow trench isolation structure 112 has a second width in the second direction D2, and the top surface of the third shallow trench isolation structure 113 has a third width in the second direction D2; for example, the first width is smaller than the second width, and the second width is smaller than the third width. Multiple word line structures 120 and at least one dummy word line structure 120b can all span along the first direction D1 across multiple active regions ACT and shallow trench isolation structures 110 in the first region 100A.

[0047] To clearly illustrate the positional relationship between the word line structure 120, the dummy word line structure 120b, and the shallow trench isolation structure 110 in the various embodiments of this application, the following content will be related to... Figure 1 The local structure shown is explained in conjunction with the sectional view along the AA' tangent direction.

[0048] Please see Figure 2 and combined Figure 1 ,in Figure 2 for Figure 1 An example of a partial cross-sectional view of a semiconductor device shown along the AA' line. Figure 2As shown, the semiconductor device in the first embodiment of the present application may specifically include: a substrate 100, a plurality of shallow trench isolation structures 111, a plurality of active regions ACT, and a plurality of word line structures 120. The substrate 100 includes a first region 100A and a second region 100B, and the first region 100A and the second region 100B are exemplarily arranged in an adjacent manner, but are not limited thereto. In one embodiment, the substrate 100 is any suitable substrate material known in the art, for example, may be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto.

[0049] The plurality of first shallow trench isolation structures 111 and the plurality of second shallow trench isolation structures 112 are disposed in the first region 100A of the substrate 100 and define a plurality of active regions ACT. The third shallow trench isolation structure 113 is disposed in the second region 100B of the substrate 100, and the fourth shallow trench isolation structure 114 is disposed between the first region 100A and the second region 100B along the first direction D1. Each of the first shallow trench isolation structure 111, the second shallow trench isolation structure 112 and the fourth shallow trench isolation structure 114 may specifically include a first insulating layer 1101, and the third shallow trench isolation structure 113 may specifically include a first insulating layer 1101, a second insulating layer 1102 and a third insulating layer 1103 stacked sequentially from bottom to top. In addition, the top surface widths of the first shallow trench isolation structure 111, the second shallow trench isolation structure 112, the third shallow trench isolation structure 113, and the fourth shallow trench isolation structure 114 in the second direction D2 may be different. For example, the width of the top surface of the first shallow trench isolation structure 111 in the second direction D2 is a first width W1, the width of the top surfaces of the second shallow trench isolation structure 112 and the fourth shallow trench isolation structure 114 in the second direction D2 is a second width W2, and the width of the top surface of the third shallow trench isolation structure 113 in the second direction D2 is a third width W3; from the first shallow trench isolation structure 111 and the second shallow trench isolation structure 112 to the third shallow trench isolation structure 113, the top surface width thereof shows a gradually increasing trend, that is, W1<W2<W3. Furthermore, the first insulating layer 1101 in the third shallow trench isolation structure 113 has a fourth width W4 in the second direction D2, and the fourth width W4 is greater than half of the second width W2 (W4>1 / 2W2). It can be seen that in the process of forming the shallow trench isolation structure 110 in this embodiment, since the width of the first insulating layer 1101 in the third shallow trench isolation structure 113 is relatively large, the corresponding isolation trenches of the first shallow trench isolation structure 111 and the second shallow trench isolation structure 112 are filled when the first insulating layer 1101 is formed, so that both of them only include the first insulating layer 1101.

[0050] In an embodiment, each of the first insulating layer 1101, the second insulating layer 1102 and the third insulating layer 1103 may be a dielectric material, which may include, for example, silicon oxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silicaglass (FSG), silicon oxycarbide (SiCOH), spin-on glass, porous low-k dielectric materials, organic polymer dielectric materials, or a combination of the foregoing materials, but is not limited thereto. Preferably, the material of the second insulating layer 1102 may be different from the materials of the first insulating layer 1101 and the third insulating layer 1103, and the materials of the first insulating layer 1101 and the third insulating layer 1103 may be the same, but the present disclosure is not limited thereto.

[0051] A plurality of word line structures 120 are disposed in the plurality of shallow trench isolation structures 110, and may be in a long strip shape extending along the first direction D1. The word line structures 120 may include a plurality of first word line structures 120a disposed in the first shallow trench isolation structure 111 (which may also be referred to as the word line structures located in the first shallow trench isolation structure 111), and a plurality of second word line structures 120c disposed in the active region ACT. In this embodiment, the first word line structures 120a and the second word line structures 120c have the same width in the second direction D2, for example, both have a fifth width W5, and the fifth width W5 is smaller than the first width W1 of the first shallow trench isolation structure 111, that is, W5<W1. This ensures that the first word line structures 120a and the second word line structures 120c are effectively isolated by the first shallow trench isolation structure 111. In addition, the film layer materials included in the first word line structures 120a and the second word line structures 120c are also the same, for example, both may include a gate dielectric layer 121 (the material may be, for example, an oxide or a nitride), a work function layer 122 (the material may be, for example, titanium nitride or metal tungsten), a conductive layer 123 (the material may be, for example, metal tungsten or polysilicon), and an insulating cap layer 124 (the material may be, for example, an oxide or a nitride), which are sequentially stacked from bottom to top along the third direction D3, but are not limited thereto. Preferably, the material of the insulating cap layer 124 in this embodiment is the same as the material of the second insulating layer 1102 in the third shallow trench isolation structure 113, for example, both are silicon oxide.

[0052] Furthermore, the semiconductor device in this embodiment may also include a dummy word line structure 120b. Specifically, the dummy word line structure 120b is disposed in the second shallow trench isolation structure 112 and extends along the first direction D1 above the adjacent active region ACT, that is, the dummy word line structure 120b and the word line structure 120 have the same shape and extension direction. However, the difference between the two is that the dummy word line structure 120b is specifically disposed in the second shallow trench isolation structure 112, and the details of the dummy word line structure 120b only include the gate dielectric layer 121 and the insulating cap layer 124 sequentially stacked from bottom to top along the third direction D3, that is, the dummy word line structure 120b only includes insulating material and does not include the conductive material in the word line structure 120. This avoids the generation of parasitic capacitance between the dummy word line structure 120b and its adjacent word line structure (such as the second word line structure 120c), improves the stability of the word line structure 120, and improves the performance and reliability of the semiconductor device. In this embodiment, the lowest point of the bottom surface of the dummy word line structure 120b is higher than the top surface of the conductive layer 123 in the word line structure 120 (the first word line structure 120a or the dummy word line structure 120b). For example, on the third direction D3, the distance between the lowest point of the top surface of the first insulating layer 1101 in the second shallow trench isolation structure 112 where the dummy word line structure 120b is located and the lowest point of the top surface of the first insulating layer 1101 in the first shallow trench isolation structure 111 where the first word line structure 120a is located can be H1, where H1 > 0.

[0053] Furthermore, the gate dielectric layer 121 in the dummy word line structure 120b is specifically located above the first insulating layer 1101. That is, the bottom of the gate dielectric layer 121 in the dummy word line structure 120b is in direct contact with the first insulating layer 1101 inside, while its top is in direct contact with the insulating cap layer 124. This ensures that the second shallow trench isolation structure 112 contains only insulating material. Secondly, the lowest point of the bottom surface of the gate dielectric layer 121 in the first shallow trench isolation structure 111 is lower than the lowest point of the bottom surface of the gate dielectric layer 121 in the second shallow trench isolation structure 112. That is, the lowest point of the bottom surface of the gate dielectric layer 121 in the first word line structure 120a is lower than the lowest point of the bottom surface of the gate dielectric layer 121 in the dummy word line structure 120b.

[0054] Those skilled in the art to which this application pertains will readily understand that, to meet actual product requirements, the semiconductor device of this application may have other forms and is not limited to those described above. Further embodiments or variations of the semiconductor device of this application will be described below. For the sake of simplicity, identical components in the various embodiments of this application are designated with the same reference numerals to facilitate comparison between embodiments.

[0055] Continue reading Figure 2 and combined Figure 1 , the structure of the semiconductor device in the second embodiment of the present application is substantially the same as the structure of the semiconductor device in the aforementioned first embodiment. For example, the semiconductor device also includes a substrate 100, a plurality of shallow trench isolation structures 110, a plurality of active regions ACT, and a plurality of word line structures 120 (including a plurality of first word line structures 120a, a plurality of second word line structures 120b and one dummy word line structure 120b). The substrate 100 may also be divided into a first region 100A and a second region 100B. The plurality of shallow trench isolation structures 110 are also disposed in the substrate 100, and a plurality of active regions ACT are also defined on the substrate 100. Moreover, the shallow trench isolation structures 110 may also be specifically divided into a first shallow trench isolation structure 111, a second shallow trench isolation structure 112, a third shallow trench isolation structure 113 and a fourth shallow trench isolation structure 114 with different widths. The width of the top surface of the first shallow trench isolation structure 111 in the second direction D2 is a first width W1, the width of the top surface of the second shallow trench isolation structure 112 in the second direction D2 is a second width W2, and the width of the top surface of the third shallow trench isolation structure 113 in the second direction D2 is a third width W3. The first width W1 is smaller than the second width W2, and the second width W2 is smaller than the third width W3, that is, W1<W2<W3. The plurality of word line structures 120 may all span across the plurality of active regions ACT and the shallow trench isolation structures 110 in the first region 100A along the first direction D1. The word line structures 120 may also include a plurality of first word line structures 120a disposed in the first shallow trench isolation structure 111, a plurality of second word line structures 120c disposed in the active regions ACT, a dummy word line structure 120b disposed in the second shallow trench isolation structure 112, and the like. The same points will not be repeated here. The main difference between the semiconductor device of this embodiment and the aforementioned first embodiment lies in that the semiconductor device in the second embodiment of the present application further includes: a first silicon oxide layer 1101, a silicon nitride layer 1102, and a second silicon oxide layer 1103.

[0056] The first silicon oxide layer 1101 is located in the first shallow trench isolation structure 111, the second shallow trench isolation structure 112, the third shallow trench isolation structure 113, and the fourth shallow trench isolation structure 114; the silicon nitride layer 1102 is located on the first silicon oxide layer 1101 in the third shallow trench isolation structure 113; the second silicon oxide layer 1103 is located on the silicon nitride layer 1102 in the third shallow trench isolation structure 113; and the width of the first silicon oxide layer 1101 in the third shallow trench isolation structure 113 in the second direction D2 is greater than half the width of the second shallow trench isolation structure 112. Obviously, in the second embodiment of this application, the first silicon oxide layer 1101 corresponds to the first insulating layer 1101 in the first embodiment, the silicon nitride layer 1102 corresponds to the second insulating layer 1102 in the first embodiment, and the second silicon oxide layer 1103 corresponds to the third insulating layer 1103 in the first embodiment. Therefore, the width of the first silicon oxide layer 1101 in the third shallow trench isolation structure 113 in the second direction D2 is the fourth width W4, and the width of the second shallow trench isolation structure 112 in the second direction D2 is the second width W2. That is, the fourth width W4 is greater than half of the second width W2 (W4>1 / 2W2).

[0057] Please see Figure 3 , Figure 3 for Figure 1 Another example of a partial structural view of a semiconductor device shown along the AA' cut line. Figure 3As shown, the structure of the semiconductor device in the third embodiment of the present application is substantially the same as the structure of the semiconductor device in the aforementioned first or second embodiment. For example, the semiconductor device also includes a substrate 100, a plurality of shallow trench isolation structures 110, a plurality of active regions ACT, and a plurality of word line structures 120 (including a plurality of first word line structures 120a, a plurality of second word line structures 120b, and one dummy word line structure 120b). The substrate 100 may also be divided into a first region 100A and a second region 100B. The plurality of shallow trench isolation structures 110 are also disposed in the substrate 100, and the shallow trench isolation structures 110 may also be specifically divided into a first shallow trench isolation structure 111, a second shallow trench isolation structure 112, a third shallow trench isolation structure 113, and a fourth shallow trench isolation structure 114 with different widths. The width of the top surface of the first shallow trench isolation structure 111 in the second direction D2 is a first width W1, the width of the top surfaces of the second shallow trench isolation structure 112 and the fourth shallow trench isolation structure 114 in the second direction D2 is a second width W2, and the width of the top surface of the third shallow trench isolation structure 113 in the second direction D2 is a third width W3. Moreover, the first width W1 is smaller than the second width W2, and the second width W2 is smaller than the third width W3, that is, W1<W2<W3. All of the plurality of word line structures 120 may span across the plurality of active regions ACT and the shallow trench isolation structures 110 in the first region 100A along the first direction D1. The word line structures 120 may also include a plurality of first word line structures 120a disposed in the first shallow trench isolation structure 111, a plurality of second word line structures 120c disposed in the active regions ACT, and a dummy word line structure 120b disposed in the second shallow trench isolation structure 112. The same parts will not be repeated here. The main difference between the semiconductor device of this embodiment and the aforementioned first or second embodiment is that the second shallow trench isolation structure 112 not only includes a first insulating layer 1101 (first silicon oxide layer), but also includes a second insulating layer 1102 (silicon nitride layer). That is, the second shallow trench isolation structure 112 in the third embodiment of the present application contains a double-layer insulating material. Since the second shallow trench isolation structure 112 in the third embodiment of the present application only adds one more layer of insulating material, it can also achieve the purposes of avoiding parasitic capacitance between the dummy word line structure 120b and the word line structure adjacent thereto (for example, the second word line structure 120c), improving the stability of the word line structures 120, and enhancing the performance and reliability of the semiconductor device.

[0058] Please refer to Figure 4 , Figure 4 is Figure 1 another example of a cross-sectional view of a partial structure of the illustrated semiconductor device taken along the AA' section. As shown in Figure 4As shown, the structure of the semiconductor device in the fourth embodiment of the present application is substantially the same as the structure of the semiconductor device in the aforementioned first or second embodiment. For example, the semiconductor device also includes a substrate 100, a plurality of shallow trench isolation structures 110, a plurality of active regions ACT, and a plurality of word line structures 120. The substrate 100 may also be divided into a first region 100A and a second region 100B. The plurality of shallow trench isolation structures 110 are also disposed in the substrate 100, and the shallow trench isolation structures 110 may also be specifically divided into a first shallow trench isolation structure 111, a second shallow trench isolation structure 112, a third shallow trench isolation structure 113 and a fourth shallow trench isolation structure 114 with different widths. The width of the top surface of the first shallow trench isolation structure 111 in the second direction D2 is a first width W1, the width of the top surfaces of the second shallow trench isolation structure 112 and the fourth shallow trench isolation structure 114 in the second direction D2 is a second width W2, and the width of the top surface of the third shallow trench isolation structure 113 in the second direction D2 is a third width W3; and the first width W1 is smaller than the second width W2, and the second width W2 is smaller than the third width W3, that is, W1<W2<W3. The plurality of word line structures 120 may also include a plurality of first word line structures 120a disposed in the first shallow trench isolation structure 111, a plurality of second word line structures 120c disposed in the active region ACT, and the like. The identical parts will not be repeated here. The main difference between the semiconductor device of this embodiment and the aforementioned first or second embodiment is that no dummy word line structure 120b is disposed in the second shallow trench isolation structure 112. In this way, by removing the dummy word line structure 120b, the additional parasitic capacitance caused by the dummy word line structure 120b is avoided, that is, the purpose of improving the performance and reliability of the semiconductor device is achieved. It should be particularly noted that the second shallow trench isolation structure 112 in the fourth embodiment of the present application may also include the two layers of insulating material shown in the aforementioned third embodiment, that is, the first insulating layer 1101 and the second insulating layer 1102.

[0059] In order to enable those of ordinary skill in the art to which the present application pertains to easily understand the manufacturing methods of the semiconductor devices in the first to fourth embodiments of the present application, the following description will further explain the manufacturing method of the semiconductor device proposed in the present application with reference to each structural schematic diagram in the preparation process of the manufacturing method described above.

[0060] wherein, Figures 5-11 is a partial structural cross-sectional view of Figure 3 the manufacturing method of the semiconductor device in the third embodiment shown in each step.

[0061] As shown in Figure 5As shown, a substrate 100 (material such as a silicon substrate) is first provided; then, the substrate 100 is divided into two adjacent regions, a first region 100A and a second region 100B; then, using at least one of photolithography and etching processes, such as dry etching or wet etching, a plurality of first isolation trenches 101 and a plurality of second isolation trenches 102 are formed in the first region 100A of the substrate 100, a third isolation trench 103 is formed in the second region 100B, and a plurality of fourth isolation trenches (not shown) are formed at the boundary between the first region 100A and the second region 100B. The width of the first isolation trench 101 in the second direction D2 (first width W1) is smaller than the width of the second isolation trench 102 in the second direction D2 (second width W2), and the width of the second isolation trench 102 in the second direction D2 (second width W2) is smaller than the width of the third isolation trench 103 in the second direction D2 (third width W3).

[0062] like Figure 6 and Figure 7 As shown, a first insulating layer 1101 (material such as silicon dioxide) is then deposited on the inner surfaces of the first isolation trench 101 to the fourth isolation trench. Since the first isolation trench 101 has the smallest width in the second direction D2, while the third isolation trench 103 has the largest width in the second direction D2, the insulating material of the first insulating layer 1101 deposited in this step will fill the first isolation trench 101, but will not fill the second isolation trench 102, the third isolation trench 103 and the fourth isolation trench (not shown). That is, the first insulating layer 1101 is only formed on the inner surfaces of the second isolation trench 102, the third isolation trench 103 and the fourth isolation trench (not shown). Subsequently, a second insulating layer 1102 (material, for example, silicon nitride) is formed on the first insulating layer 1101 in the second isolation trench 102, the third isolation trench 103, and the fourth isolation trench using a deposition process. A third insulating layer 1103 (material, for example, silicon oxide) is further formed on the second insulating layer 1102 in the third isolation trench 103. This forms a first shallow trench isolation structure 111 in the first isolation trench 101, a second shallow trench isolation structure 112 in the second isolation trench 102, a third shallow trench isolation structure 113 in the third isolation trench 103, and a fourth shallow trench isolation structure 114 in the fourth isolation trench. Figure 7 (not shown), such as Figure 7 As shown. Furthermore, combined with... Figure 3The top surface of the first shallow trench isolation structure 111 has a width of W1 in the second direction D2, the top surface of the second shallow trench isolation structure 112 has a width of W2 in the second direction D2, and the top surface of the third shallow trench isolation structure 113 has a width of W3 in the second direction D2; the first width W1 is less than the second width W2, and the second width W2 is less than the third width W3, that is, W1 <W2<W3。

[0063] like Figure 8 As shown, an etching process is used to remove a portion of the insulating material at the top depth of the first shallow trench isolation structure 111 to the fourth shallow trench isolation structure 114, thereby forming a first word line groove 104 in the first shallow trench isolation structure 111, a second word line groove 105 in the active region ACT, and a dummy word line groove 106 in the second shallow trench isolation structure 112. Because the widths of the first shallow trench isolation structure 111 and the second shallow trench isolation structure 112 are different in the second direction D2, the depth of the dummy word line groove 106 along the third direction D3 is less than the depth of the first word line groove 104, while the depths of the first word line groove 104 and the second word line groove 105 along the third direction D3 are the same.

[0064] like Figures 9-11 As shown, a gate dielectric layer 121 (material such as oxide or nitride) is then formed on the inner surfaces of the first word line groove 104, the second word line groove 105, and the dummy word line groove 106 using a deposition process. Figure 9 As shown; next, using a deposition process again, a work function layer 122 (material such as titanium nitride or tungsten metal) is uniformly formed on the gate dielectric layer 121 within the first word line recess 104, the second word line recess 105, and the dummy word line recess 106. At this point, the work function layer 122 fills the first word line recess 104, the second word line recess 105, and the dummy word line recess 106, and extends onto the exposed surface of the substrate 100, as shown. Figure 10 As shown; then, using a reverse etching process, a portion of the work function layer 122 extending on the exposed surface of the substrate 100 and within the first word line groove 104, the second word line groove 105, and the dummy word line groove 106 is removed, such that the remaining work function layer 122 only fills the lower part of the first word line groove 104, the second word line groove 105, and the dummy word line groove 106, as shown. Figure 11 As shown. Finally, a conductive layer 123 (material such as tungsten metal or polysilicon) and an insulating capping layer 124 (material such as oxide or nitride) are sequentially formed in the remaining space of the first character line groove 104, the second character line groove 105, and the dummy character line groove 106. The insulating capping layer 124 is located on the conductive layer 123.

[0065] Figure 5 and 12~ Figure 17 For this Figure 2 and Figure 4 Partial structural cross-sectional views of the semiconductor device fabrication methods in each step of the first, second, and fourth embodiments shown.

[0066] like Figure 5 and 12~ Figure 17 As can be seen from the description, the embodiments of this application are formed in... Figure 2 or Figure 4 The process of the semiconductor device shown is the same as described above. Figures 5-11 The semiconductor device fabrication method shown in the third embodiment is largely the same. For example, multiple first isolation trenches 101, multiple second isolation trenches 102, a third isolation trench 103, and multiple fourth isolation trenches (not shown) are first formed in a substrate 100 (material such as a silicon substrate). Then, a first shallow trench isolation structure 111, a second shallow trench isolation structure 112, a third shallow trench isolation structure 113, and a fourth shallow trench isolation structure 114 are formed in the first isolation trenches 101, second isolation trenches 102, third isolation trenches 103, and fourth isolation trenches, respectively. Afterwards, a first word line structure 120a is formed in the first shallow trench isolation structure 111, a second word line structure 120c is formed in the active region ACT, and a dummy word line structure 120b is formed in the second shallow trench isolation structure 112, etc. The similarities are not repeated here. The main difference between the fabrication method of this embodiment and the fabrication method in the previous embodiments is that: Figure 12 As shown, when forming the first insulating layer 1101 in the first isolation trench 101 to the third isolation trench 103, in this embodiment, the first insulating layer 1101 at least fills the first isolation trench 101 and the second isolation trench 102; however, since the third isolation trench 103 is wider, this step still only forms the wider first insulating layer 1101 on the inner surface of the third isolation trench 103; then, when forming the second insulating layer 1102 and the third insulating layer 1103 using a deposition process, they will only be stacked sequentially on the first insulating layer 1101 in the third isolation trench 103, and will not be stacked on the first insulating layer 1101 in the first isolation trench 101 and the second isolation trench 102, as shown. Figure 13 As shown.

[0067] In summary, the semiconductor device and its fabrication method of this application include a shallow trench isolation structure located within a substrate and word line structures located within the shallow trench isolation structure. The shallow trench isolation structure includes a first shallow trench isolation structure, a second shallow trench isolation structure, and a third shallow trench isolation structure with different widths. The word line structures located within different shallow trench isolation structures contain different film layer materials. For example, the word line structure in the first shallow trench isolation structure includes a conductive layer and an insulating capping layer, while the word line structures in at least one other shallow trench isolation structure only contain an insulating capping layer. This avoids parasitic capacitance between adjacent word line structures, improves the stability of the word line structure, eliminates the need for additional process steps, and ultimately improves the performance and reliability of the semiconductor device.

[0068] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a shallow trench isolation structure and a plurality of active regions defined by the shallow trench isolation structure, the shallow trench isolation structure including a first shallow trench isolation structure, a second shallow trench isolation structure and a third shallow trench isolation structure with different widths; The word line structure is located in the shallow trench isolation structure and extends along the first direction to above the adjacent active area, and the word line structure located in the first shallow trench isolation structure includes a conductive layer and an insulating cap layer arranged sequentially from bottom to top. In a second direction perpendicular to the first direction, the top surface of the first shallow trench isolation structure has a first width, the top surface of the second shallow trench isolation structure has a second width, and the top surface of the third shallow trench isolation structure has a third width, wherein the first width is smaller than the second width, and the second width is smaller than the third width; The first shallow trench isolation structure and the second shallow trench isolation structure each include a first insulating layer, and the third shallow trench isolation structure includes the first insulating layer, the second insulating layer and the third insulating layer stacked from bottom to top.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A dummy word line structure is located in the second shallow trench isolation structure and extends along the first direction above the adjacent active area. The dummy word line structure located in the second shallow trench isolation structure includes the insulating cap layer, which is made of the same material as the second insulating layer.

3. The semiconductor device as described in claim 1, characterized in that, The lowest point of the bottom surface of the dummy word line structure is higher than the top surface of the conductive layer in the word line structure.

4. The semiconductor device as described in claim 3, characterized in that, The insulating cap layer is made of the same material as the second insulating layer.

5. The semiconductor device as described in claim 4, characterized in that, The insulating capping layer comprises silicon nitride.

6. The semiconductor device as claimed in claim 2, characterized in that, Both the word line structure and the dummy word line structure further include a gate dielectric layer; the gate dielectric layer is located above the first insulating layer, and the lowest point of the bottom surface of the gate dielectric layer in the first shallow trench isolation structure is lower than the lowest point of the bottom surface of the gate dielectric layer in the second shallow trench isolation structure.

7. The semiconductor device as claimed in claim 1, characterized in that, In the second direction, the first insulating layer located in the third shallow trench isolation structure has a fourth width, which is greater than half of the second width.

8. The semiconductor device as claimed in claim 1, characterized in that, The second shallow trench isolation structure also includes a second insulating layer, wherein the lowest point of the bottom surface of the second insulating layer is higher than the lowest point of the bottom surface of the word line structure.

9. A semiconductor device, characterized in that, include: The substrate includes a shallow trench isolation structure and a plurality of active regions defined by the shallow trench isolation structure, the shallow trench isolation structure including a first shallow trench isolation structure, a second shallow trench isolation structure and a third shallow trench isolation structure; The first silicon oxide layer is located in the first shallow trench isolation structure, the second shallow trench isolation structure and the third shallow trench isolation structure, respectively; A silicon nitride layer is located on the first silicon oxide layer in the third shallow trench isolation structure; A second silicon oxide layer is located on the silicon nitride layer in the third shallow trench isolation structure; wherein, in the second direction, the width of the first silicon oxide layer in the third shallow trench isolation structure is greater than half the width of the second shallow trench isolation structure. The word line structure is located in the first shallow trench isolation structure and includes a conductive layer and an insulating cover layer arranged sequentially from bottom to top; A dummy word line structure is located in the second shallow trench isolation structure. The dummy word line structure includes the insulating capping layer, and the lowest point of the bottom surface of the dummy word line structure is higher than the top surface of the conductive layer in the word line structure.

10. The semiconductor device as claimed in claim 9, characterized in that, The insulating capping layer comprises silicon nitride.

11. The semiconductor device as claimed in claim 9, characterized in that, Both the word line structure and the dummy word line structure further include a gate dielectric layer; the gate dielectric layer is located above the first silicon oxide layer, and the lowest point of the bottom surface of the gate dielectric layer in the first shallow trench isolation structure is lower than the lowest point of the bottom surface of the gate dielectric layer in the second shallow trench isolation structure.

12. The semiconductor device as claimed in claim 9, characterized in that, The second shallow trench isolation structure also includes the silicon nitride layer, wherein the lowest point of the bottom surface of the silicon nitride layer is higher than the lowest point of the bottom surface of the word line structure.

13. The semiconductor device as claimed in claim 9, characterized in that, In the second direction, the top surface of the first shallow trench isolation structure has a first width, the top surface of the second shallow trench isolation structure has a second width, and the top surface of the third shallow trench isolation structure has a third width, wherein the first width is smaller than the second width, and the second width is smaller than the third width.

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