Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a unit region and a peripheral region arranged outside the unit region; a plurality of unit structures arranged above the unit region, the unit structure comprising alternately arranged active structures and first isolation structures; a plurality of second isolation structures arranged above the peripheral region and arranged along the outside of the unit structure; and a plurality of word lines comprising a first part arranged above the unit region and a second part extending to the upper side of the peripheral region, the first part covering the sidewall of the unit structure, and the second part covering the sidewall of the second isolation structure; wherein the first part has a first height in the direction away from the substrate, and the second part has a second height in the direction away from the substrate, and the second height is higher than the first height. The application can avoid short circuit between adjacent word lines.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] In an exemplary memory, a word line (WL) is typically used to select a row of memory cells in a memory array.

[0003] As memory manufacturing processes advance, critical dimensions (CDs) continue to shrink. Conductive structures located on and electrically connected to word lines are prone to short-circuiting adjacent word lines if misaligned due to misalignment or other reasons. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method that can solve the aforementioned short-circuit problem.

[0005] A semiconductor structure includes: a substrate including a cell region and a peripheral region disposed outside the cell region; a plurality of cell structures located above the cell region, the cell structures including alternating active structures and first isolation structures and a plurality of second isolation structures located above the peripheral region and arranged along the outer side of the cell structures; a plurality of word lines including a first portion located above the cell region and a second portion extending above the peripheral region, the first portion covering the sidewalls of the cell structures and the second portion covering the sidewalls of the second isolation structures; wherein the first portion has a first height in a direction away from the substrate, and the second portion has a second height in a direction away from the substrate, the second height being higher than the first height.

[0006] In the aforementioned semiconductor structure, the word line includes a first portion located above the cell region and a second portion extending above the peripheral region. In the case where a conductive structure electrically connected to the word line is provided on the word line, when the conductive structure is not aligned (due to process errors, etc.) with the second portion and is offset to the word line of the adjacent cell structure, since there is a height difference between the first portion and the second portion, the bottom of the conductive structure will not contact the first portion of the word line of the adjacent cell structure, thus avoiding short circuit between the two adjacent word lines.

[0007] In one embodiment, the semiconductor structure further includes a plurality of contact plugs disposed above the second portion and in direct contact with the top surface of the second portion.

[0008] In one embodiment, the top surface of the second portion is higher than the top surface of the first portion.

[0009] In one embodiment, the top surface of the first portion is lower than the top surface of the active structure.

[0010] In one embodiment, the top surface of the second portion is flush with the top surface of the active structure.

[0011] In one embodiment, the semiconductor structure further includes an isolation layer that completely covers the top surface of the first portion.

[0012] In one embodiment, the bottom surface of the contact plug is higher than the bottom surface of the insulating layer.

[0013] In one embodiment, the orthographic projection of at least one of the contact plugs along a direction perpendicular to the substrate overlaps with the orthographic projection of the first portion along a direction perpendicular to the substrate.

[0014] In one embodiment, at least three sides of the second isolation structure are surrounded by the corresponding second portion.

[0015] A semiconductor structure includes: a substrate including a cell region and a peripheral region disposed outside the cell region; a plurality of cell structures located above the cell region, including alternating active structures and first isolation structures; a plurality of second isolation structures located above the peripheral region and arranged along the outer side of the cell structures; a plurality of first word lines located above the cell region and extending above the peripheral region, covering the sidewalls of each active structure, wherein the top surface of the first word lines is lower than the top surface of the active structure; a plurality of second word lines located above the peripheral region and covering the sidewalls of the second isolation structures; the second word lines directly contacting the corresponding first word lines; a plurality of contact plugs disposed above the second word lines and directly contacting the top surface of the second word lines; wherein the top surface of the second word lines is higher than the top surface of the first word lines, and the second word lines are disposed between adjacent first word lines.

[0016] In the aforementioned semiconductor structure, the top surface of the second word line is higher than the top surface of the first word line. Even if the contact plug on the second word line overlaps above the first word line corresponding to the adjacent cell structure due to alignment deviation, it will not be connected (short-circuited) with the adjacent word line. Therefore, the contact hole corresponding to the contact plug has a large process window.

[0017] In one embodiment, the semiconductor structure further includes an isolation layer that completely covers the top surface of the first word line.

[0018] In one embodiment, the bottom surface of the contact plug is higher than the bottom surface of the insulating layer.

[0019] In one embodiment, the orthographic projection of at least one of the contact plugs along a direction perpendicular to the substrate partially overlaps with the orthographic projection of the first letter line along a direction perpendicular to the substrate.

[0020] In one embodiment, the top surface of the first character line is lower than the top surface of the active structure, and the top surface of the second character line is flush with the top surface of the active structure.

[0021] In one embodiment, at least three sides of the second isolation structure are surrounded by corresponding second letter lines.

[0022] A method for fabricating a semiconductor structure includes: obtaining a substrate; the substrate including a cell region and a peripheral region disposed outside the cell region; forming a plurality of cell structures above the cell region and a plurality of second isolation structures above the peripheral region; the cell structure including alternating active structures and first isolation structures, the second isolation structures being arranged along the outer side of the cell structure; forming a plurality of word lines; the word lines including a first portion above the cell region and a second portion extending above the peripheral region, the first portion covering the sidewall of the cell structure, the second portion covering the sidewall of the second isolation structure; forming a word line etching barrier structure on the second portion; etching the word lines such that the first portion decreases from a second height to a first height, the second portion remains at the second height, the first height and the second height being heights in a direction away from the substrate.

[0023] In the above-described semiconductor structure fabrication method, when a conductive structure electrically connected to the word line is provided on the word line, if the conductive structure is not aligned with the second part and is offset to the word line of the adjacent unit structure, since the second part is etched to a position lower than the first part, the bottom of the conductive structure will not contact the first part of the word line of the adjacent unit structure, thus avoiding short circuit between the two adjacent word lines. Attached Figure Description

[0024] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0025] Figure 1 (a) is a top view of a semiconductor structure in one embodiment, (b) is a cross-sectional view along line B-B1 in (a), and (c) is a cross-sectional view along line B-B2 in (a).

[0026] Figure 2(a) is a schematic diagram of the rectangular second isolation structure 114a surrounded by the second part 124, and (b) is a schematic diagram of the semi-circular second isolation structure 114a surrounded by the second part 124.

[0027] Figure 3 This is a flowchart of a method for preparing a semiconductor structure according to an embodiment of this application.

[0028] Figure 4 (a) is a top view of the semiconductor structure after step S122 in one embodiment of this application, (b) is a cross-sectional view along line B-B1 in (a), and (c) is a cross-sectional view along line A-A1 in (a).

[0029] Figure 5 (a) is a top view of the semiconductor structure after step S124 in one embodiment of this application, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a).

[0030] Figure 6 (a) is a top view of the semiconductor structure after step S126 in one embodiment of this application, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a).

[0031] Figure 7 (a) is a top view of the semiconductor structure after the second insulating layer 133 is formed in one embodiment of this application, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a).

[0032] Figure 8 (a) is a top view of the semiconductor structure after step S130 in one embodiment of this application, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a).

[0033] Figure 9 (a) is a top view of the semiconductor structure after step S140 in one embodiment of this application, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a).

[0034] Figure 10(a) is a top view of the semiconductor structure after step S150 in one embodiment of this application, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a).

[0035] Figure 11 This is a top view of a semiconductor structure in another embodiment of this application.

[0036] Figure 12 This is a top view of the semiconductor structure after step S123 is completed in another embodiment of this application.

[0037] Figure 13 This is a top view of the semiconductor structure after step S125 is completed in another embodiment of this application.

[0038] Figure 14 This is a top view of the semiconductor structure after step S130 is completed in another embodiment of this application.

[0039] Figure 15 This is a top view of the semiconductor structure after step S140 is completed in another embodiment of this application.

[0040] Explanation of reference numerals in the attached figures:

[0041] Substrate 10; First insulating layer 12; Bit line 20; First wall structure 102; Second wall structure 104; Insulating layer 105; Unit structure 110; Active structure 112; Source line 113; First isolation structure 114; Second isolation structure 114a; Dielectric layer 121; Word line 120; First part 122; First word line 122a; Second part 124; Second word line 124a; Third word line 126; Fourth word line 128; Isolation layer 131; Contact plug 132; Second insulating layer 133; Word line etching barrier structure 134; First mask layer 135; Second mask layer 136; Isolation trench 141; Isolation trench structure 142; Peripheral trench 143; Peripheral trench structure 144; Square trench 145; Insulating pillar 150. Detailed Implementation

[0042] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0045] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0048] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0049] This application provides a semiconductor structure. Figure 1 (a) is a top view of a semiconductor structure in one embodiment, (b) is a cross-sectional view along line B-B1 in (a), and (c) is a cross-sectional view along line B-B2 in (a). The semiconductor structure includes:

[0050] The substrate 10 includes a cell region and a peripheral region disposed outside the cell region;

[0051] Multiple unit structures 110 are located above the unit area. Each unit structure 110 includes an alternating active structure 112 and a first isolation structure 114.

[0052] Multiple second isolation structures 114a are located above the peripheral area and are arranged along the outer side of the unit structure 110;

[0053] Multiple word lines, including a first portion 122 located above the unit area, and a second portion 124 extending above the peripheral area, the first portion 122 covering the sidewall of the unit structure 110, and the second portion 124 covering the sidewall of the second isolation structure;

[0054] The first part 122 has a first height H1 in the direction away from the substrate 10, and the second part 124 has a second height H2 in the direction away from the substrate 10, wherein the second height H1 is higher than the first height H1.

[0055] In the aforementioned semiconductor structure, the word line includes a first portion 122 located above the cell region and a second portion 124 extending above the peripheral region. In the case where a conductive structure electrically connected to the word line is provided on the word line, when the conductive structure is not aligned (due to process errors, etc.) with the second portion 124 and is offset to the word line of the adjacent cell structure 110, since there is a height difference between the first portion 122 and the second portion 124, the bottom of the conductive structure will not contact the first portion 122 of the word line of the adjacent cell structure 110 and short-circuit the two adjacent word lines.

[0056] In one embodiment of this application, each unit structure 110 is parallel to each other and along a first direction (i.e. Figure 1 Extending along the Y-axis, multiple (multi-column) unit structures 110 are parallel to each other. Each unit structure 110 includes alternating active structures 112 and first isolation structures 114. The active structures 112 in each unit structure 110 are arranged in an array, and the first isolation structures 114 in each unit structure 110 are also arranged in an array. The column direction of the array is the first direction (i.e., Figure 1 The Y-axis direction in the middle), the row direction is the second direction (i.e. Figure 1 The plane containing the first and second directions is parallel to the top surface of the substrate 10. The aforementioned second isolation structure 114a is arranged along the outer side of the unit structure 110, which means it is arranged along the outer side of the first direction.

[0057] The active structure 112 is part of a three-dimensional or non-planar transistor. In one embodiment of this application, each active structure 112 may include a source region, a drain region, and a channel region of a three-dimensional or non-planar transistor. In one embodiment of this application, in a third direction (i.e. Figure 1Along the Z-axis direction, the active structure 112 may include a bottom, a middle, and a top from bottom to top. A source region of a three-dimensional or non-planar transistor is formed in the bottom, a channel region of a three-dimensional or non-planar transistor is formed in the middle, and a drain region of a three-dimensional or non-planar transistor is formed in the top. The third direction is perpendicular to the top surface of the substrate 10. In one embodiment of this application, the bottom of each row of active structures 112 is connected as one unit by source lines 113, thus the source regions of each row of active structures 112 are electrically connected by source lines 113. It should be noted that in other embodiments, a drain region of a three-dimensional or non-planar transistor may also be formed in the bottom of the active structure 112, a channel region of a three-dimensional or non-planar transistor may be formed in the middle, and a source region of a three-dimensional or non-planar transistor may be formed in the top.

[0058] The active structure 112 is made of a semiconductor material. In some embodiments, the active structure 112 is made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC), or may include other materials, such as group III-V compounds like gallium arsenide, or may be a metal oxide semiconductor, such as indium gallium zinc oxide (In). x Ga y Zn z O, commonly known as "IGZO"), zinc tin oxide (Zn) x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn) x O), Indium gallium silicon oxide (In x Ga y Si z O, commonly known as "IGSO"), indium tungsten oxide (In) x W y O (commonly known as "IWO"). The active structure 112 can be doped with certain impurity ions as needed. For example, for N-type stereo or non-planar transistors, N-type impurity ions can be doped in the source and drain regions, and P-type impurity ions can be doped in the channel region; for P-type stereo or non-planar transistors, P-type impurity ions can be doped in the source and drain regions, and N-type impurity ions can be doped in the channel region. In one example, the P-type impurity ions include one or more of boron ions, gallium ions, or indium ions, and the N-type impurity ions include one or more of phosphorus ions, arsenic ions, or antimony ions.

[0059] The first isolation structure 114 is used for electrical isolation between adjacent active structures 112. In some embodiments, the material of the first isolation structure 114 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

[0060] The substrate 10 is made of a semiconductor material. In one embodiment of this application, the substrate 10 may be made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may include other materials, such as gallium arsenide or other group III-V compounds.

[0061] In one embodiment of this application, the semiconductor structure further includes a plurality of contact plugs 132. Each contact plug 132 is disposed above the second portion 124, and the bottom of the contact plug 132 is in direct contact with the top surface of the corresponding second portion 124, thereby forming an electrical connection between the contact plug 132 and the second portion 124. In one embodiment of this application, the contact plug 132 is a metal plug in a contact hole (CT), and its material includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN, such as a tungsten plug.

[0062] In one embodiment of this application, the second portion 124 is disposed in the second direction (i.e. Figure 1 The first portions 122 adjacent to each other in the X-axis direction (i.e., between the first portions 122 of adjacent unit structures 110 (corresponding) are connected. Therefore, even if the contact plug 132 overlaps above the first portion 122 corresponding to the adjacent unit structure 110 due to alignment deviation, it will not be connected (short-circuited) with the adjacent word line. Thus, the contact hole corresponding to the contact plug 132 has a large process window. In one embodiment of this application, for every two adjacent unit structures 110, one unit structure 110 has a second portion 124 at the first end, and the other unit structure 110 has a second portion 124 at the second end, with the first end and the second end being opposite ends.

[0063] In one embodiment of this application, the top surface of the second portion 124 is higher than the top surface of the first portion 122.

[0064] In one embodiment of this application, the bottom surface of the contact plug 132 is higher than the top surface of the first portion 122.

[0065] In one embodiment of this application, the bottom surface of the contact plug 132 is higher than the bottom surface of the isolation layer 131.

[0066] In one embodiment of this application, each plug 132 is connected to each second part 124 in a one-to-one correspondence.

[0067] In one embodiment of this application, the top surface of the first portion 122 is lower than the top surface of the active structure 112.

[0068] In one embodiment of this application, the top surface of the second portion 124 is flush with the top surface of the active structure 112.

[0069] In one embodiment of this application, the bottom surface of the first portion 122 and the bottom surface of the second portion 124 are higher than the bottom surface of the active structure 112.

[0070] In one embodiment of this application, the semiconductor structure further includes an isolation layer 131 that completely covers the top surface of the first portion 122. In one embodiment of this application, the material of the isolation layer 131 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

[0071] In one embodiment of this application, at least one contact plug 132 is along a third direction (i.e. Figure 1 The orthographic projection of the first part 122 (in the Z-axis direction) overlaps with the orthographic projection of the third part 122 along the third direction. The overlapping contact plug 132 may be a contact plug 132 that has a large alignment deviation.

[0072] In one embodiment of this application, the semiconductor structure further includes a first insulating layer 12 located on the substrate 10 and a bit line 20 located on the first insulating layer 12. The unit structure 110 is located on the first insulating layer 12 and the bit line 20. The bit line 20 is electrically connected to the source line 113, and a voltage signal can be applied to the source region through the bit line 20. In one embodiment of this application, both the bit line 20 and the source line 113 are along a second direction (i.e., Figure 1The first insulating layer 12 extends along the X-axis direction. A semiconductor device (such as a transistor) can be formed in the substrate 10, and the first insulating layer 12 covers the semiconductor device. The bit line 20 can be electrically connected to the semiconductor device. In one embodiment of this application, the first insulating layer 12 can be a single-layer or multi-layer structure. The material of the first insulating layer 12 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), and low dielectric constant materials (K less than 2.5). In one embodiment of this application, the bit line 20 can be a single-layer or multi-layer structure. In a specific example, bit line 20 may include a first barrier layer, a conductive layer and a second barrier layer stacked sequentially. The first barrier layer and the second barrier layer are used to prevent metal elements in the conductive layer from diffusing outward. The materials of the first barrier layer and the second barrier layer include one or more of Ti, Ta, TiN, TaN, TaC and WN. The materials of the conductive layer include one or more of Cu, W, Al, Ti, Ag, Au, Pt and Ni.

[0073] In one embodiment of this application, the orthographic projection of the second portion 124 on the sidewall of the corresponding unit structure 110 (i.e., the orthographic projection along the second direction) does not overlap with the active structure 112.

[0074] In one embodiment of this application, at least three sides of a second isolation structure 114a are surrounded by corresponding second portions 124. See also Figure 2 In (a), the second isolation structure 114a has a rectangular cross-section, and three sides of the second isolation structure 114a are surrounded by the corresponding second portion 124 (the remaining side is the side that contacts the active structure 112). The second isolation structure 114a can also have other shapes, such as a triangular or semi-circular cross-section. See also Figure 2 In (b), the second isolation structure 114a, except for the side that contacts the active structure 112, is surrounded by the corresponding second part 124 on the other sides.

[0075] This application provides a method for preparing a semiconductor structure, which can be used to manufacture the semiconductor structure described in any of the above embodiments. Figure 3 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application, including the following steps:

[0076] S110, Obtain the substrate.

[0077] The substrate 10 includes a cell region and a peripheral region disposed outside the cell region. The substrate 10 is made of a semiconductor material. In one embodiment of this application, the substrate 10 may be made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may include other materials, such as gallium arsenide or other group III-V compounds.

[0078] In one embodiment of this application, after obtaining the substrate 10, a first insulating layer 12 is formed on the substrate 10, and then a bit line 20 is formed on the first insulating layer 12. In one embodiment of this application, both the bit line 20 and the source line 113 are along a second direction (i.e., Figure 4 The first insulating layer 12 extends along the X-axis direction. A semiconductor device (such as a transistor) can be formed in the substrate 10, and the first insulating layer 12 covers the semiconductor device. The bit line 20 can also be electrically connected to the semiconductor device. In one embodiment of this application, the first insulating layer 12 can be a single-layer or multi-layer structure. The material of the first insulating layer 12 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), and low dielectric constant materials (K less than 2.5). In one embodiment of this application, the bit line 20 can be a single-layer or multi-layer structure. In a specific example, bit line 20 may include a first barrier layer, a conductive layer and a second barrier layer stacked sequentially. The first barrier layer and the second barrier layer are used to prevent metal elements in the conductive layer from diffusing outward. The materials of the first barrier layer and the second barrier layer include one or more of Ti, Ta, TiN, TaN, TaC and WN. The materials of the conductive layer include one or more of Cu, W, Al, Ti, Ag, Au, Pt and Ni.

[0079] S120, forming multiple unit structures 110 located above the unit area and multiple second isolation structures located above the peripheral area.

[0080] In one embodiment of this application, step S120 specifically includes:

[0081] S122, an active region layer and an insulating layer are formed on the substrate.

[0082] See Figure 4 , Figure 4 (a) is a top view of the semiconductor structure after step S122, (b) is a cross-sectional view along line B-B1 in (a), and (c) is a cross-sectional view along line A-A1 in (a). In one embodiment of this application, an active region layer is formed on bit line 20, and the active region layer includes a plurality of discrete regions along a second direction (i.e., Figure 4An active structure 112 extends along the X-axis direction, and an insulating layer 105 is formed between adjacent active structures 112 and on the outside of the active structure 112.

[0083] In one embodiment of this application, the formation process of the active region layer and the insulating layer 105 includes: forming an active region layer on the bit line 20 using a deposition process; forming a patterned mask layer (e.g., a photoresist layer) on the active region layer; etching the active region layer using the patterned mask layer as a mask to form a plurality of discrete active structures 112; forming an insulating layer 105 covering the active structures 112, and planarizing the insulating layer 105 to expose the top surface of the active structures 112.

[0084] S124 forms an isolation trench.

[0085] See Figure 5 , Figure 5 (a) is a top view of the semiconductor structure after step S124, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a).

[0086] right Figure 4 The structure shown is etched (i.e., the active region layer and the insulating layer 105 are etched) to form several discrete structures along the first direction (i.e. Figure 5 An isolation trench 141 extends along the Y-axis direction. The structure between adjacent isolation trenches 141 forms a unit structure 110, and the insulating layer 105 between adjacent isolation trenches 141 forms a first isolation structure 114. Each unit structure 110 includes active structures 112 and the first isolation structure 114 alternately arranged in a first direction. In each unit structure 110, adjacent active structures 112 are isolated from each other by the first isolation structure 114. Figure 5 In the illustrated embodiment, the etching in step S124 does not etch through the bottom of the active region layer. The remaining active region layer at the bottom of the isolation trench 141 serves as the source line 113, so that in the second direction (i.e. Figure 5 The bottoms of multiple active structures 112 connected in a straight line along the X-axis direction are connected by source lines 113.

[0087] In one embodiment of this application, prior to step S124, a patterned mask layer may be formed on the active region layer and the insulating layer 105, the mask layer including a first mask layer 135 and a second mask layer 136 on the first mask layer 135.

[0088] S126 forms the outer trench.

[0089] See Figure 6 , Figure 6(a) is a top view of the semiconductor structure after step S126, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a).

[0090] right Figure 5 The structure shown is etched (i.e., the insulating layer 105 above the peripheral region is etched), and a peripheral trench 143 is formed above the peripheral region, cutting off the second isolation structure 114a on both sides of the unit structure 110 from the outer insulating layer 105. Figure 6 In the embodiment shown, the peripheral trench 143 is along the second direction (i.e. Figure 6 Extending in the X-axis direction, each unit structure 110 and the second isolation structure 114a on both sides of the unit structure 110 in the second direction are located between two peripheral trenches 143, and the second isolation structure 114a is part of the insulating layer 105 above the peripheral area.

[0091] In one embodiment of this application, the isolation trench 141 and the peripheral trench 143 may also be formed simultaneously by etching in the same etching step.

[0092] In one embodiment of this application, after step S126, a step of forming a second insulating layer 133 at the bottom of the isolation trench 141 and the bottom of the peripheral trench 143 is further included. See also Figure 7 , Figure 7 (a) is a top view of the semiconductor structure after the formation of the second insulating layer 133, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a). The second insulating layer 133 can be formed by deposition. In one embodiment of this application, the material of the second insulating layer 133 includes silicon oxide.

[0093] After the second insulating layer 133 is formed, step S130 is performed.

[0094] S130 forms multiple character lines.

[0095] See Figure 8 , Figure 8(a) is a top view of the semiconductor structure after step S130, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a). In one embodiment of this application, before forming the word line 120, a dielectric layer 121 is further formed on the sidewalls of the isolation trench 141 and the sidewalls of the peripheral trench 143. In one embodiment of this application, the dielectric layer 121 serves as a gate oxide layer, and its material can be silicon oxide or a high-k dielectric material, such as one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO. In one embodiment of this application, the dielectric layer 121 is formed by thermal oxidation.

[0096] After the dielectric layer 121 is formed, a plurality of word lines 120 are formed. The word lines 120 cover the sidewalls of the unit structure 110 and the sidewalls of the second isolation structure 114a.

[0097] In one embodiment of this application, the word line 120 is formed by depositing a word line material. The word line material may be titanium nitride (TiN), or other metals and / or alloys, such as one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0098] In one embodiment of this application, step S130, while forming the word line 120, also forms a third word line 126 surrounding the isolation trench 141 and the peripheral trench 143. Specifically, word line material is deposited on the sidewalls of the isolation trench 141 and the peripheral trench 143 to form the word line 120 and the third word line 126.

[0099] In one embodiment of this application, after step S130, the method further includes filling the isolation trench 141 and the peripheral trench 143 with an isolation material. In one embodiment of this application, the isolation material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. By filling with the isolation material, an isolation trench structure 142 is formed in the isolation trench 141, and a peripheral trench structure 144 is formed in the peripheral trench 143.

[0100] S140, forming a character line etching barrier structure on the second part of the character line.

[0101] See Figure 9 , Figure 9In diagram (a), a top view of the semiconductor structure after step S140 is completed; (b), a cross-sectional view along line B-B1 in (a); (c), a cross-sectional view along line A-A1 in (a); and (d), a cross-sectional view along line A-A2 in (a). In one embodiment of this application, patterned photoresist is formed on the second portion of the word line (i.e., the portion covering the sidewall of the second isolation structure 114a) by photolithography, serving as a word line etch barrier structure 134. The portion of the word line not covered by the word line etch barrier structure 134 serves as the first portion 122.

[0102] S150, etched lettering.

[0103] See Figure 10 , Figure 10 (a) is a top view of the semiconductor structure after step S150, (b) is a cross-sectional view along line B-B1 in (a), (c) is a cross-sectional view along line A-A1 in (a), and (d) is a cross-sectional view along line A-A2 in (a). Using the word line etching barrier structure 134 as the barrier layer for etching in step S150, word lines are etched. The first portion 122, due to etching, descends from the second height H2 to the first height H1, while the second portion 124 remains at the second height H2. The first height H1 and the second height H2 are heights in the direction away from the substrate 10.

[0104] In one embodiment of this application, the third word line 126 is etched together to a first height H1 in step S150.

[0105] In the above-described semiconductor structure fabrication method, when a conductive structure electrically connected to the word line is provided on the word line, if the conductive structure is not aligned with the second part 124 and is offset to the word line of the adjacent unit structure 110, since the second part 124 is etched to a position lower than the first part 122, the bottom of the conductive structure will not contact the first part 122 of the word line of the adjacent unit structure 110 and short-circuit the two adjacent word lines.

[0106] In one embodiment of this application, after step S150, a step of forming an isolation layer 131 that completely covers the top surface of the first portion 122 is further included. In one embodiment of this application, the isolation layer 131 can be formed by a deposition process, and the material of the isolation layer 131 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

[0107] In one embodiment of this application, after forming the isolation layer 131, the step of forming a contact plug 132 over the second portion 124 is further included. In one embodiment of this application, in Figure 10A dielectric layer is deposited on the front side of the formed structure, and then the dielectric layer is patterned. A contact hole is formed above the second portion 124, and then a conductive material is filled into the contact hole as a contact plug 132. The contact plug 132 is in direct contact with the top surface of the second portion 124. In one embodiment of this application, the material of the contact plug 132 includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN, such as a tungsten plug.

[0108] Figure 11 This is a top view of a semiconductor structure according to another embodiment of this application. In this embodiment, the semiconductor structure includes:

[0109] Substrate 10 ( Figure 11 (Not shown in the text) includes the unit area and the peripheral area located outside the unit area;

[0110] Multiple unit structures 110 are located above the unit region, including alternating active structures 112 and a first isolation structure 114;

[0111] Multiple second isolation structures 114a are located above the peripheral area and are arranged along the outer side of the unit structure 110;

[0112] Multiple first word lines 122a are located above the unit area and extend above the surrounding area, covering the sidewalls of each active structure 112, and the top surface of the first word line 122a is lower than the top surface of the active structure 112.

[0113] Multiple second character lines 124a are located above the peripheral area and cover the sidewall of the second isolation structure 114a; the second character lines 124a are in direct contact with the corresponding first character lines 122a (corresponding to the first character lines 122a and the second character lines 124a located around the same unit structure 110);

[0114] Multiple contact plugs 132 ( Figure 11 (Not shown in the image), is positioned above the second character line 124a and is in direct contact with the top surface of the second character line 124a;

[0115] The top surface of the second character line 124a is higher than the top surface of the first character line 122a, and the second character line 124a is positioned between adjacent first character lines 122a.

[0116] In the above semiconductor structure, the top surface of the second word line 124a is higher than the top surface of the first word line 122a. Even if the contact plug 132 on the second word line 124a overlaps above the first word line 122a corresponding to the adjacent cell structure 110 due to alignment deviation, it will not be connected (short-circuited) with the adjacent word line. Therefore, the contact hole corresponding to the contact plug 132 has a large process window.

[0117] In one embodiment of this application, the semiconductor structure further includes an isolation layer 131 that completely covers the top surface of the first word line 122a. Figure 11 (Not shown in the text).

[0118] In one embodiment of this application, the bottom surface of the contact plug 132 is higher than the bottom surface of the isolation layer 131.

[0119] In one embodiment of this application, the orthographic projection of at least one contact plug 132 along the direction perpendicular to the substrate 10 partially overlaps with the orthographic projection of the first word line 122a along the direction perpendicular to the substrate 10.

[0120] In one embodiment of this application, the top surface of the first word line 122a is lower than the top surface of the active structure 112, and the top surface of the second word line 124a is flush with the top surface of the active structure 112.

[0121] In one embodiment of this application, at least three sides of a second isolation structure 114a are surrounded by corresponding second letter lines 124a.

[0122] Figure 11 The semiconductor structure shown can also be used. Figure 3 The method shown is used for fabrication, and the following focuses on the differences between it and the semiconductor structure fabrication method of the aforementioned embodiments. In one embodiment of this application, the trench formation step S120 includes:

[0123] S123 forms multiple rectangular grooves.

[0124] Reference Figure 12 The long side of each frame groove 145 along the second direction (i.e. Figure 12 Extending along the Y-axis direction, adjacent rectangular grooves 145 are separated by a first wall structure 102 extending along the second direction, and each rectangular groove 145 is divided into a second wall structure 104 extending along the second direction. Both the first wall structure 102 and the second wall structure 104 include an active structure 112 and a first isolation structure 114 alternately arranged along the second direction. In one embodiment of this application, the rectangular grooves 145 can be formed by photolithography and etching.

[0125] S125 forms the outer trench.

[0126] Reference Figure 13This forms a peripheral groove 143 that cuts the second wall structure 104 at both ends and the middle portion, and severs the first wall structure 102 at both ends. The remaining middle portion of the second wall structure 104 and the remaining middle portion of the first wall structure 102 after severance serve as unit structure 110 and second isolation structure 114a, with the second isolation structure 114a arranged along the outer side of unit structure 110. The two ends of the second wall structure 104 that are separated serve as insulating pillars 150. In one embodiment of this application, the peripheral groove 143 can be formed by photolithography and etching.

[0127] In one embodiment of this application, step S130, while forming the word line 120, also forms a third word line 126 surrounding the square groove 145 and the outer groove 143, and a fourth word line 128 surrounding the insulating post 150, as shown below. Figure 14 Specifically, letter line material is deposited on the sidewalls of the isolation trench 141 and the outer trench 143 to form letter line 120, third letter line 126 and fourth letter line 128.

[0128] Following step S130, the word lines 120 are also photolithographically and etched, referring to... Figure 15 This forms the first character line 122a and the second character line 124a, which will not be elaborated here.

[0129] The method for preparing the semiconductor structure in this application is based on the same inventive concept as the semiconductor structure itself. For details not specifically described in the method for preparing the semiconductor structure, please refer to the preceding introduction to the semiconductor structure.

[0130] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0131] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0132] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a cell region and a peripheral region disposed outside the cell region; Multiple unit structures are located above the unit region, and the unit structures include alternating active structures and a first isolation structure; Multiple second isolation structures are located above the peripheral area and arranged along the outer side of the unit structure; Multiple character lines, including a first portion located above the unit area and a second portion extending above the peripheral area, the first portion covering the sidewall of the unit structure and the second portion covering the sidewall of the second isolation structure; The first portion has a first height in a direction away from the substrate, and the second portion has a second height in a direction away from the substrate, wherein the second height is higher than the first height.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: Multiple contact plugs are disposed above the second part and are in direct contact with the top surface of the second part.

3. The semiconductor structure according to claim 1, characterized in that, The top surface of the second part is higher than the top surface of the first part.

4. The semiconductor structure according to claim 1, characterized in that, The top surface of the first part is lower than the top surface of the active structure.

5. The semiconductor structure according to claim 4, characterized in that, The top surface of the second part is flush with the top surface of the active structure.

6. The semiconductor structure according to claim 2, characterized in that, It also includes an isolation layer that completely covers the top surface of the first part.

7. The semiconductor structure according to claim 6, characterized in that, The bottom surface of the contact plug is higher than the bottom surface of the isolation layer.

8. The semiconductor structure according to claim 1, characterized in that, At least three sides of the second isolation structure are surrounded by the corresponding second portion.

9. The semiconductor structure according to claim 2, characterized in that, The orthographic projection of at least one of the contact plugs along a direction perpendicular to the substrate overlaps with the orthographic projection of the first portion along a direction perpendicular to the substrate.

10. A semiconductor structure, characterized in that, include: The substrate includes a cell region and a peripheral region disposed outside the cell region; Multiple unit structures are located above the unit region, including alternating active structures and a first isolation structure; Multiple second isolation structures are located above the peripheral area and arranged along the outer side of the unit structure; Multiple first character lines are located above the unit area and extend above the peripheral area, covering the sidewalls of each active structure, and the top surface of the first character lines is lower than the top surface of the active structure; Multiple second letter lines are located above the peripheral area and cover the sidewall of the second isolation structure; the second letter lines are in direct contact with the corresponding first letter lines; Multiple contact plugs are positioned above the second letter line and in direct contact with the top surface of the second letter line; The top surface of the second character line is higher than the top surface of the first character line, and the second character line is positioned between adjacent first character lines.

11. The semiconductor structure according to claim 10, characterized in that, It also includes an isolation layer that completely covers the top surface of the first character line.

12. The semiconductor structure according to claim 11, characterized in that, The bottom surface of the contact plug is higher than the bottom surface of the isolation layer.

13. The semiconductor structure according to claim 10, characterized in that, The orthographic projection of at least one of the contact plugs along a direction perpendicular to the substrate partially overlaps with the orthographic projection of the first letter line along a direction perpendicular to the substrate.

14. The semiconductor structure according to claim 10, characterized in that, The top surface of the first character line is lower than the top surface of the active structure, and the top surface of the second character line is flush with the top surface of the active structure.

15. The semiconductor structure according to claim 10, characterized in that, At least three sides of the second isolation structure are surrounded by the corresponding second letter lines.

16. A method for fabricating a semiconductor structure, characterized in that, include: Obtain a substrate; the substrate includes a cell region and a peripheral region disposed outside the cell region; Multiple unit structures are formed above the unit area, and multiple second isolation structures are formed above the peripheral area; the unit structure includes alternating active structures and first isolation structures, and the second isolation structures are arranged along the outer side of the unit structure; Forming multiple character lines; The word line includes a first portion located above the unit area and a second portion extending above the peripheral area, the first portion covering the sidewall of the unit structure and the second portion covering the sidewall of the second isolation structure; A word line etching barrier structure is formed on the second part; The word lines are etched such that the first portion descends from a second height to a first height, while the second portion remains at the second height. The first and second heights are heights in a direction away from the substrate.

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