Semiconductor device

Abstract

The application provides a semiconductor device, a composite insulating layer is located on a substrate, the composite insulating layer comprises a first insulating layer, a second insulating layer and a third insulating layer which are stacked from bottom to top; a first bit line structure is located on the composite insulating layer, a side wall structure is located on the side wall of the first bit line structure, the part of the side wall structure corresponding to the second insulating layer comprises a first recess, the part of the side wall structure corresponding to the third insulating layer comprises a second recess, and the depth of the first recess is less than the depth of the second recess. In the application, the first recess and the second recess can expand the spacing of the bottom of adjacent structures, improve the process window of the storage node contact structure, and thus improve the reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Technology

[0002] As semiconductor manufacturing process nodes continue to shrink, the size and spacing of device structures are constantly decreasing, placing unprecedented demands on the precision of photolithography and etching processes. In current semiconductor manufacturing processes, various micro and nanostructures (such as fins, trenches, and isolation structures) are typically formed on the substrate through etching processes.

[0003] However, in conventional etching processes, due to the anisotropic differences in plasma etching, lateral ion reflection, or the influence of physicochemical mechanisms such as polymer deposition, the bottom edge of the structure is prone to developing a footing effect (commonly referred to in the industry) when etching to form the aforementioned structure. Specifically, the footing effect manifests as a morphological defect in which the bottom of the structure extends laterally to one or both sides.

[0004] This foot-based phenomenon can have a serious negative impact on subsequent manufacturing processes. In subsequent processes, other structures, such as memory node contact plugs between bit lines, typically need to be formed next to the aforementioned structure. Because the foot-based structure in the initial formation occupies the bottom space between adjacent structures, the effective spacing between the bottoms of adjacent structures is significantly reduced. When the plug is subsequently formed, due to the limited bottom space, the lateral dimension of the plug's bottom is forced to decrease, resulting in an excessively small cross-sectional area at the plug's bottom.

[0005] Reducing the bottom area of ​​the plug significantly increases contact resistance and may even lead to electrical disconnection or poor contact between the plug and the underlying substrate. This not only limits device performance improvement but also causes a significant decrease in device reliability and product yield. Existing conventional etching processes are insufficient to effectively eliminate the bottom feet while preserving the overall structure morphology; therefore, a new process method is urgently needed to address these issues. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor device that, by performing additional etching on the bottom region of the bit line structure after conventional etching, expands the spacing between the bottoms of adjacent structures, increases the process window of the memory node contact structure, and improves the reliability of the semiconductor device.

[0007] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0008] Substrate;

[0009] A composite insulating layer is located on the substrate, and the composite insulating layer includes a first insulating layer, a second insulating layer and a third insulating layer stacked from bottom to top;

[0010] The first line structure is located on the composite insulating layer;

[0011] A sidewall structure is located on the sidewall of the first bit line structure. The portion of the sidewall structure corresponding to the second insulating layer includes a first recess, and the portion of the sidewall structure corresponding to the third insulating layer includes a second recess. The depth of the first recess is less than the depth of the second recess.

[0012] Optionally, it also includes a memory node contact structure located on one side of the first bit line structure and extending into the substrate, the memory node contact structure at least partially filling the first recess and the second recess.

[0013] Optionally, the second thickness of the sidewall structure at the second recess is greater than the first thickness of the sidewall structure at the first recess.

[0014] Optionally, the sidewall structure includes a first sidewall layer, a second sidewall layer, and a third sidewall layer, wherein the first sidewall layer, the second sidewall layer, and the third sidewall layer are stacked outward from the sidewall of the first bit line structure.

[0015] Optionally, the bottom surface of the second sidewall layer is higher than the bottom surface of the first sidewall layer.

[0016] Optionally, the third sidewall layer covers the sidewall of the composite insulation layer and defines the first recess and the second recess.

[0017] Optionally, the bottom surface of the first sidewall layer and the bottom surface of the second sidewall layer include a stepped structure, and the third sidewall layer further covers the stepped structure and defines a third recess.

[0018] Optionally, the depth of the third recess is less than the depth of the first recess.

[0019] Optionally, it also includes a second bit line structure located on the substrate and in direct contact with the substrate, wherein the first sidewall layer, the second sidewall layer and the third sidewall layer are also located on the sidewall of the second bit line structure, and the first sidewall layer further includes a groove portion that contacts the substrate.

[0020] Optionally, a fourth sidewall layer is also included, which fills the groove portion of the first sidewall layer of the second bit line structure sidewall.

[0021] Optionally, a portion of the third sidewall layer is sandwiched between the second sidewall layer and the fourth sidewall layer in a direction perpendicular to the substrate.

[0022] Optionally, the bottom surface of the clamped portion of the third sidewall layer is higher than the bottom surface of the composite insulation layer and lower than the top surface of the composite insulation layer.

[0023] Optionally, it also includes a memory node contact structure located on one side of the second bit line structure and extending into the substrate, with a portion of the third sidewall layer sandwiched between the fourth sidewall layer and the memory node contact structure.

[0024] Optionally, the third sidewall layer comprises two discontinuous sections.

[0025] Optionally, the width of the second insulating layer is greater than the width of the first insulating layer, and the width of the first insulating layer is greater than the width of the third insulating layer.

[0026] Optionally, the first insulating layer and the third insulating layer are made of silicon oxide, and the second insulating layer is made of silicon nitride.

[0027] Optionally, a gap may be included between the storage node contact structure and the third sidewall layer at the second recess.

[0028] The present invention also provides a semiconductor device, comprising:

[0029] Substrate;

[0030] A composite insulating layer is located on the substrate. The composite insulating layer includes a first insulating layer, a second insulating layer and a third insulating layer stacked from bottom to top. The width of the second insulating layer is greater than the width of the first insulating layer, and the width of the first insulating layer is greater than the width of the third insulating layer.

[0031] The first line structure is located on the composite insulating layer;

[0032] A sidewall structure is located on the sidewall of the first bit line structure. The portion of the sidewall structure corresponding to the second insulating layer includes a first recess, and the portion of the sidewall structure corresponding to the third insulating layer includes a second recess.

[0033] Optionally, it also includes a memory node contact structure located on one side of the first bit line structure and extending into the substrate, the memory node contact structure at least partially filling the first recess and the second recess.

[0034] Optionally, the sidewall structure includes a first sidewall layer, a second sidewall layer, and a third sidewall layer, wherein the first sidewall layer, the second sidewall layer, and the third sidewall layer are stacked outward from the sidewall of the first bit line structure.

[0035] Optionally, the third sidewall layer covers the sidewall of the composite insulation layer and defines the first recess and the second recess.

[0036] Optionally, the bottom surface of the first sidewall layer and the bottom surface of the second sidewall layer include a stepped structure, and the third sidewall layer further covers the stepped structure and defines a third recess.

[0037] Optionally, the depth of the third recess is less than the depth of the first recess.

[0038] Optionally, it also includes a second bit line structure located on the substrate and in direct contact with the substrate, wherein the first sidewall layer, the second sidewall layer and the third sidewall layer are also located on the sidewall of the second bit line structure, and the first sidewall layer further includes a groove portion that contacts the substrate.

[0039] Optionally, a fourth sidewall layer is also included, which fills the groove portion of the first sidewall layer of the second bit line structure sidewall.

[0040] Optionally, a portion of the third sidewall layer is sandwiched between the second sidewall layer and the fourth sidewall layer in a direction perpendicular to the substrate.

[0041] Optionally, it also includes a memory node contact structure located on one side of the second bit line structure and extending into the substrate, with a portion of the third sidewall layer sandwiched between the fourth sidewall layer and the memory node contact structure.

[0042] Optionally, a gap may be included between the storage node contact structure and the third sidewall layer at the second recess.

[0043] In the semiconductor device provided by this invention, a composite insulating layer is located on a substrate. The composite insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer stacked sequentially from bottom to top. A first bit line structure is located on the composite insulating layer, and a sidewall structure is located on the sidewall of the first bit line structure. The portion of the sidewall structure corresponding to the second insulating layer includes a first recess, and the portion of the sidewall structure corresponding to the third insulating layer includes a second recess. The depth of the first recess is less than the depth of the second recess. In this invention, the first bit line structure is located on the composite insulating layer. After conventional etching, an additional etching process is performed on the bottom region of the bit line structure, i.e., the composite insulating layer is etched. After the sidewall structure is formed, the portion of the sidewall structure corresponding to the second insulating layer includes a first recess, and the portion of the sidewall structure corresponding to the third insulating layer includes a second recess. The first and second recesses can increase the spacing between the bottoms of adjacent structures, improve the process window of the memory node contact structure, and thus improve the reliability of the semiconductor device. Attached Figure Description

[0044] Figure 1This is a cross-sectional schematic diagram of a semiconductor device provided in Embodiment 1 of the present invention.

[0045] Figure 2 and Figure 3 for Figure 1 A cross-sectional view of the area within the dashed frame T1.

[0046] Figure 4 for Figure 1 A cross-sectional view of the area within the dashed frame at T2.

[0047] Figure 5 This is a cross-sectional schematic diagram of the semiconductor device provided in Embodiment 2 of the present invention.

[0048] Figure 6 for Figure 5 A cross-sectional view of the area within the dashed box.

[0049] Figures 7-16 This is a cross-sectional schematic diagram of a corresponding step in the method for fabricating a semiconductor device provided in Embodiment 3 of the present invention.

[0050] The attached figures are labeled as follows:

[0051] 100 - Substrate; 120 - Trench isolation structure; 200a - First bit line structure; 200b - Second bit line structure; 210 - First bit line conductive layer; 220 - Second bit line conductive layer; 230 - Bit line capping layer; 300 - Composite insulating layer; 310 - First insulating layer; 320 - Second insulating layer; 330 - Third insulating layer; 410 - First sidewall layer; 420 - Second sidewall layer; 430 - Third sidewall layer; 440 - Fourth sidewall layer; 430a - First recess; 430b - Second recess; 430c - Third recess; 500 - Storage node contact structure; 610 - First barrier layer; 620 - First metal layer; 630 - Second metal layer; 700 - Insulating structure; 800 - Second barrier layer. Detailed Implementation

[0052] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0053] Example 1

[0054] Please refer to Figure 1 , Figure 2 and Figure 4This embodiment provides a semiconductor device, including a substrate 100, a composite insulating layer 300, a first line structure, and a sidewall structure. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. A plurality of trench isolation structures 120 are provided in the substrate 100, and adjacent trench isolation structures 120 are active regions. The material of the trench isolation structures 120 includes one or more of silicon oxide, silicon nitride, and silicon carbonitride, and is not limited thereto.

[0055] The composite insulating layer 300 is located on the substrate 100 and on a portion of the trench isolation structure 120. The composite insulating layer 300 includes a first insulating layer 310, a second insulating layer 320, and a third insulating layer 330 stacked sequentially from bottom to top. The first insulating layer 310 and the third insulating layer 330 are preferably made of the same material. The second insulating layer 320 is preferably made of a different material than the first insulating layer 310 and the third insulating layer 330. The first insulating layer 310 and the third insulating layer 330 are made of silicon oxide, and the second insulating layer 320 is made of silicon nitride. The first insulating layer 310, the second insulating layer 320, and the third insulating layer 330 can form a stacked structure of silicon oxide layer, silicon nitride layer, and silicon oxide layer. The width of the second insulating layer 320 is greater than the width of the first insulating layer 310, and the width of the first insulating layer 310 is greater than the width of the third insulating layer 330.

[0056] The first wire structure 200a is located on the composite insulation layer 300 and is in direct contact with the composite insulation layer 300. The first wire structure 200a is Figure 1 The bit line structure is shown in the dashed box T1. The device also includes a second bit line structure 200b, which is located on and in direct contact with the substrate 100. The second bit line structure 200b is... Figure 1 The bitline structure is shown in the dashed box T2, with the bottom surface of the second bitline structure 200b lower than the bottom surface of the first bitline structure 200a. Both the first bitline structure 200a and the second bitline structure 200b include a first bitline conductive layer 210, a second bitline conductive layer 220, and a bitline capping layer 230 stacked sequentially from bottom to top. The bottom surface of the first bitline conductive layer 210 in the first bitline structure 200a is higher than the bottom surface of the first bitline conductive layer 210 in the second bitline structure 200b. The material of the first bitline conductive layer 210 can be a semiconductor material, such as doped polysilicon; the material of the second bitline conductive layer 220 can be a metal material; and the material of the bitline capping layer 230 can be an insulating material, such as silicon nitride.

[0057] Please continue to refer to this. Figure 2The sidewall structure is located on the sidewall of the first wire structure 200a and also on the sidewall of the composite insulation layer 300. The sidewall structure includes a first sidewall layer 410, a second sidewall layer 420, and a third sidewall layer 430. The first sidewall layer 410, the second sidewall layer 420, and the third sidewall layer 430 are stacked outward from the sidewall of the first wire structure 200a. That is, the first sidewall layer 410 first covers the sidewall of the first wire structure 200a and is in direct contact with the sidewall of the first wire structure 200a, then the second sidewall layer 420 covers the first sidewall layer 410, and the third sidewall layer 430 covers the second sidewall layer 420.

[0058] The portion of the sidewall structure corresponding to the second insulating layer 320 includes a first recess 430a, and the portion corresponding to the third insulating layer 330 includes a second recess 430b. The depth of the first recess 430a is less than the depth of the second recess 430b, meaning the end of the second recess 430b is closer to the composite insulating layer 300 than the end of the first recess 430a. Specifically, the bottom surface of the second sidewall layer 420 is higher than the bottom surface of the first sidewall layer 410, and the third sidewall layer 430 extends to cover the sidewall of the composite insulating layer 300 and defines the first recess 430a and the second recess 430b. The second thickness W2 of the sidewall structure at the second recess 430b is greater than the first thickness W1 of the sidewall structure at the first recess 430a, meaning the second thickness W2 of the third sidewall layer 430 at the second recess 430b is greater than the first thickness W1 of the third sidewall layer 430 at the first recess 430a.

[0059] Please continue to refer to this. Figure 4 The sidewall structure is also located on the sidewall of the second bit line structure 200b. Specifically, the first sidewall layer 410, the second sidewall layer 420, and the third sidewall layer 430 are also located on the sidewall of the second bit line structure 200b. The first sidewall layer 410, the second sidewall layer 420, and the third sidewall layer 430 are stacked outward from the sidewall of the second bit line structure 200b. The first sidewall layer 410 on the sidewall of the second bit line structure 200b also includes a groove portion that contacts the substrate 100. Figure 4(As shown by the dashed rectangular frame). The sidewall structure also includes a fourth sidewall layer 440, which fills the groove portion of the first sidewall layer 410 of the second bit line structure 200b, and the bottom surface of the fourth sidewall layer 440 is higher than the bottom surface of the composite insulating layer 300. In a direction perpendicular to the substrate 100, a portion of a third sidewall layer 430 is sandwiched between the second sidewall layer 420 and the fourth sidewall layer 440, and the sandwiched portion of the third sidewall layer 430 is in direct contact with the first sidewall layer 410. The bottom surface of the sandwiched portion of the third sidewall layer 430 is higher than the bottom surface of the composite insulating layer 300 and lower than the top surface of the composite insulating layer 300. In this embodiment, the first sidewall layer 410 and the second sidewall layer 420 are made of silicon oxide, and the third sidewall layer 430 and the fourth sidewall layer 440 are made of silicon nitride.

[0060] Please continue to refer to this. Figure 2 and reference Figure 3 It also includes a memory node contact structure 500, which is located on one side of the first line structure 200a and extends into the substrate 100. The top surface of the memory node contact structure 500 is lower than the top surface of the first line structure 200a. The memory node contact structure 500 at least partially fills the first recess 200a and the second recess 200b, such as... Figure 2 The storage node contact structure 500 shown completely fills the first recess 200a and the second recess 200b. For example... Figure 3 The storage node contact structure 500 shown partially fills the first recess 200a and the second recess 200b, and a gap is included between the third sidewall layer 430 at the storage node contact structure 500 and the second recess 200b. Figure 3 (As shown in the dashed circular frame).

[0061] Please continue to refer to this. Figure 4 It also includes a memory node contact structure 500, which is located on one side of the second bit line structure 200b and extends into the substrate 100. The top surface of the memory node contact structure 500 is lower than the top surface of the second bit line structure 200b. A portion of a third sidewall layer 430 (not shown in the figure) is sandwiched between the fourth sidewall layer 440 and the memory node contact structure 500, or a portion of the third sidewall layer 430 is sandwiched between the groove portion of the first sidewall layer 410 and the memory node contact structure 500 (e.g., Figure 4 (As shown in the circular dashed frame). The third sidewall layer 430 of the second sidewall structure 200b includes two discontinuous parts, one part of which covers the second sidewall layer 420, and the other part is the sandwiched part (as shown in the circular dashed frame). Figure 4 (As shown in the dashed circular frame).

[0062] For further information, please continue to refer to [link / reference]. Figure 1It also includes a first barrier layer 610, a first metal layer 620, a second metal layer 630, and an insulating structure 700, wherein the first barrier layer 610 covers the top surface of the storage node contact structure 500, the first metal layer 620 conformally covers the first barrier layer 610, the sidewall structure, and the bit line structure (the first bit line structure and the second bit line structure), the second metal layer 630 covers the first metal layer 620, and the insulating structure 700 penetrates the second metal layer 630 and the first metal layer 620 and extends into the sidewall structure.

[0063] In this embodiment, the first bit line structure 200a is disposed on the composite insulating layer 300. After conventional etching, additional etching is performed on the bottom region of the bit line structure (first bit line structure 200a), that is, the composite insulating layer 300 is etched. After the sidewall structure is formed, the part of the sidewall structure corresponding to the second insulating layer 320 includes a first recess 430a, and the part of the sidewall structure corresponding to the third insulating layer 330 includes a second recess 430b. The first recess 430a and the second recess 430b can expand the spacing between the bottoms of adjacent structures, improve the process window of the memory node contact structure 500, and thus improve the reliability of the semiconductor device.

[0064] Example 2

[0065] Please refer to Figure 5 and Figure 6 The difference between this embodiment and embodiment one is that the bottom surface of the first sidewall layer 410 and the bottom surface of the second sidewall layer 420 include a stepped structure, and the third sidewall layer 430 also covers the stepped structure and defines a third recess 430c. The depth of the third recess 430c is less than the depth of the first recess 430a. By providing the third recess 430c in the sidewall structure, the process window of the memory node contact structure 500 can be further improved, thereby improving the reliability of the semiconductor device.

[0066] Example 3

[0067] Figures 7-16 This is a cross-sectional schematic diagram of a corresponding step in the fabrication method of the semiconductor device provided in this embodiment. This embodiment provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device in Embodiment 1, and the specific steps are as follows:

[0068] Please refer to Figure 7 A substrate 100 is provided, which can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. A plurality of trench isolation structures 120 are provided in the substrate 100, and adjacent trench isolation structures 120 are active regions. The material of the trench isolation structures 120 includes one or more of silicon oxide, silicon nitride, and silicon carbonitride, and is not limited thereto.

[0069] Please refer to Figure 8 A first insulating layer 310, a second insulating layer 320, and a third insulating layer 330 are formed on a substrate 100 and stacked sequentially from bottom to top. The first insulating layer 310 and the third insulating layer 330 are made of silicon oxide, and the second insulating layer 320 is made of silicon nitride. The first insulating layer 310, the second insulating layer 320, and the third insulating layer 330 can form a stacked structure of silicon oxide layer, silicon nitride layer, and silicon oxide layer.

[0070] Please refer to Figure 9 The substrate 100 between adjacent trench isolation structures 120 and a portion of the trench isolation structures 120 are etched to form a groove. Then, a first bit line structure 200a is formed on the third insulating layer 330, and a second bit line structure 200b is formed on the substrate 100 within the groove. Both the first bit line structure 200a and the second bit line structure 200b include a first bit line conductive layer 210, a second bit line conductive layer 220, and a bit line capping layer 230 stacked sequentially from bottom to top. The bottom surface of the first bit line conductive layer 210 in the first bit line structure 200a is higher than the bottom surface of the first bit line conductive layer 210 in the second bit line structure 200b. The first bit line conductive layer 210 can be made of a semiconductor material, such as doped polysilicon; the second bit line conductive layer 220 can be made of a metal material; and the bit line capping layer 230 can be made of an insulating material, such as silicon nitride. Furthermore, the second insulating layer 320 and the third insulating layer 330 are etched so that the width of the second insulating layer 320 and the third insulating layer 330 is the same as the bottom width of the first line structure 200a.

[0071] Please refer to Figure 10 A first sidewall layer 410 is formed to conformally cover the surfaces of the first bit line structure 200a and the second bit line structure 200b, the surface of the first insulating layer 310, and the sides of the second insulating layer 320 and the third insulating layer 330. The first sidewall layer 410 on the sidewall of the second bit line structure 200b also includes a groove portion that contacts the substrate 100. Furthermore, a fourth sidewall layer 440 is formed to fill the groove portion of the first sidewall layer 410 on the sidewall of the second bit line structure 200b, and the bottom surface of the fourth sidewall layer 440 is higher than the bottom surface of the first insulating layer 310. The first sidewall layer 410 is made of silicon oxide, and the fourth sidewall layer 440 is made of silicon nitride.

[0072] Please refer to Figure 11 A second sidewall layer 420 is formed to conformally cover the surface of the first sidewall layer 410 and the top surface of the fourth sidewall layer 440. The material of the second sidewall layer 420 includes silicon oxide.

[0073] Please refer to Figure 12 A second barrier layer 800 is formed to conformally cover the surface of the second sidewall layer 420, and the material of the second barrier layer 800 includes titanium nitride.

[0074] Please refer to Figure 13 The second barrier layer 800 on the top of the first bit line structure 200a and the second bit line structure 200b and the second barrier layer 800 above the substrate 100 are removed by etching, while the second barrier layer 800 on the sidewalls of the first bit line structure 200a and the second bit line structure 200b is retained.

[0075] Please refer to Figure 14 Using the second barrier layer 800 on the sidewalls of the first bit line structure 200a and the second bit line structure 200b as a mask, wet etching is performed on a portion of the second sidewall layer 420, a portion of the first sidewall layer 410, a portion of the first insulating layer 310, and a portion of the third insulating layer 330. Simultaneously, a portion of the trench isolation structure 120 is etched to form recesses on both sides of the second bit line structure 200b. In another embodiment, a larger portion of the second sidewall layer 420 is etched, see reference [reference needed]. Figure 5 By performing additional etching on the bottom region of the bit line structure (first bit line structure 200a) after conventional etching, primarily etching the composite insulating layer, the spacing between the bottoms of adjacent structures is increased, the process window of the memory node contact structure is improved, and the reliability of the semiconductor device is enhanced. Please refer to [reference needed]. Figure 15 Remove the second blocking layer 800.

[0076] Please refer to Figure 16 The third sidewall layer 430 is formed to conformally cover the top surface of the first bit line structure 200a and the second bit line structure 200b, the side surface of the composite insulating layer, and the surface of the second sidewall layer 420, the fourth sidewall layer 440 and the substrate 100, and fills the recesses on both sides of the second bit line structure 200b. The material of the third sidewall layer 430 includes silicon nitride.

[0077] Please continue to refer to this. Figure 1 A memory node contact structure 500 is formed between the first bit line structure and the second bit line structure, extending into the substrate 100. Specifically, a memory node contact hole is formed by etching the third sidewall layer 430, the fourth sidewall layer 440, and the substrate 100, and then filling the memory node contact hole with conductive material to form the memory node contact structure 500. Furthermore, a first barrier layer 610 is formed to cover the top surface of the memory node contact structure 500, a first metal layer 620 is formed to conformally cover the first barrier layer 610, the sidewall structure, and the bit line structure (the first bit line structure and the second bit line structure), a second metal layer 630 is formed to cover the first metal layer 620, and an insulating structure 700 is formed to penetrate the second metal layer 630 and the first metal layer 620 and extend into the sidewall structure. For the specific structure of the above film layers, please refer to the description of Embodiment 1.

[0078] In summary, in the semiconductor device provided by this invention, a composite insulating layer is located on a substrate, comprising a first insulating layer, a second insulating layer, and a third insulating layer stacked sequentially from bottom to top. A first bit line structure is located on the composite insulating layer, and a sidewall structure is located on the sidewall of the first bit line structure. The portion of the sidewall structure corresponding to the second insulating layer includes a first recess, and the portion corresponding to the third insulating layer includes a second recess. The depth of the first recess is less than the depth of the second recess. In this invention, the first bit line structure is located on the composite insulating layer. After conventional etching, an additional etching process is performed on the bottom region of the bit line structure, i.e., etching is performed on the composite insulating layer. After forming the sidewall structure, the portion of the sidewall structure corresponding to the second insulating layer includes a first recess, and the portion corresponding to the third insulating layer includes a second recess. The first and second recesses can increase the spacing between the bottoms of adjacent structures, improve the process window of the memory node contact structure, and thus improve the reliability of the semiconductor device.

[0079] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A composite insulating layer is located on the substrate, and the composite insulating layer includes a first insulating layer, a second insulating layer and a third insulating layer stacked from bottom to top; The first line structure is located on the composite insulating layer; A sidewall structure is located on the sidewall of the first bit line structure. The portion of the sidewall structure corresponding to the second insulating layer includes a first recess, and the portion of the sidewall structure corresponding to the third insulating layer includes a second recess. The depth of the first recess is less than the depth of the second recess.

2. The semiconductor device as claimed in claim 1, characterized in that, It also includes a memory node contact structure located on one side of the first bit line structure and extending into the substrate, the memory node contact structure at least partially filling the first recess and the second recess.

3. The semiconductor device as described in claim 1, characterized in that, The second thickness of the sidewall structure at the second recess is greater than the first thickness of the sidewall structure at the first recess.

4. The semiconductor device as claimed in claim 1, characterized in that, The sidewall structure includes a first sidewall layer, a second sidewall layer, and a third sidewall layer, which are stacked sequentially outward from the sidewall of the first bit line structure onto the sidewall of the first bit line structure.

5. The semiconductor device as claimed in claim 4, characterized in that, The bottom surface of the second sidewall layer is higher than the bottom surface of the first sidewall layer.

6. The semiconductor device as claimed in claim 4, characterized in that, The third sidewall layer covers the sidewall of the composite insulation layer and defines the first recess and the second recess.

7. The semiconductor device as claimed in claim 4, characterized in that, The bottom surfaces of the first sidewall layer and the second sidewall layer include a stepped structure, and the third sidewall layer also covers the stepped structure and defines a third recess.

8. The semiconductor device as claimed in claim 7, characterized in that, The depth of the third depression is less than the depth of the first depression.

9. The semiconductor device as claimed in claim 4, characterized in that, It also includes a second bit line structure located on the substrate and in direct contact with the substrate. The first sidewall layer, the second sidewall layer and the third sidewall layer are also located on the sidewall of the second bit line structure. The first sidewall layer also includes a groove portion that contacts the substrate.

10. The semiconductor device as claimed in claim 9, characterized in that, It also includes a fourth sidewall layer that fills the groove portion of the first sidewall layer of the second bit line structure sidewall.

11. The semiconductor device as claimed in claim 9, characterized in that, A portion of the third sidewall layer is sandwiched between the second sidewall layer and the fourth sidewall layer in a direction perpendicular to the substrate.

12. The semiconductor device as claimed in claim 11, characterized in that, The bottom surface of the clamped portion of the third sidewall layer is higher than the bottom surface of the composite insulation layer and lower than the top surface of the composite insulation layer.

13. The semiconductor device as claimed in claim 11, characterized in that, It also includes a memory node contact structure located on one side of the second bit line structure and extending into the substrate, with a portion of the third sidewall layer sandwiched between the fourth sidewall layer and the memory node contact structure.

14. The semiconductor device as claimed in claim 13, characterized in that, The third sidewall layer comprises two discontinuous sections.

15. The semiconductor device as claimed in claim 1, characterized in that, The width of the second insulating layer is greater than the width of the first insulating layer, and the width of the first insulating layer is greater than the width of the third insulating layer.

16. The semiconductor device as claimed in claim 1, characterized in that, The first insulating layer and the third insulating layer are made of silicon oxide, and the second insulating layer is made of silicon nitride.

17. The semiconductor device as claimed in claim 2, characterized in that, A gap is included between the storage node contact structure and the third sidewall layer at the second recess.

18. A semiconductor device, characterized in that, include: Substrate; A composite insulating layer is located on the substrate. The composite insulating layer includes a first insulating layer, a second insulating layer and a third insulating layer stacked from bottom to top. The width of the second insulating layer is greater than the width of the first insulating layer, and the width of the first insulating layer is greater than the width of the third insulating layer. The first line structure is located on the composite insulating layer; A sidewall structure is located on the sidewall of the first bit line structure. The portion of the sidewall structure corresponding to the second insulating layer includes a first recess, and the portion of the sidewall structure corresponding to the third insulating layer includes a second recess.

19. The semiconductor device as claimed in claim 18, characterized in that, It also includes a memory node contact structure located on one side of the first bit line structure and extending into the substrate, the memory node contact structure at least partially filling the first recess and the second recess.

20. The semiconductor device as claimed in claim 18, characterized in that, The sidewall structure includes a first sidewall layer, a second sidewall layer, and a third sidewall layer, which are stacked sequentially outward from the sidewall of the first bit line structure onto the sidewall of the first bit line structure.

21. The semiconductor device as claimed in claim 20, characterized in that, The third sidewall layer covers the sidewall of the composite insulation layer and defines the first recess and the second recess.

22. The semiconductor device as claimed in claim 20, characterized in that, The bottom surfaces of the first sidewall layer and the second sidewall layer include a stepped structure, and the third sidewall layer also covers the stepped structure and defines a third recess.

23. The semiconductor device as claimed in claim 22, characterized in that, The depth of the third depression is less than the depth of the first depression.

24. The semiconductor device as claimed in claim 20, characterized in that, It also includes a second bit line structure located on the substrate and in direct contact with the substrate. The first sidewall layer, the second sidewall layer and the third sidewall layer are also located on the sidewall of the second bit line structure. The first sidewall layer also includes a groove portion that contacts the substrate.

25. The semiconductor device as claimed in claim 24, characterized in that, It also includes a fourth sidewall layer that fills the groove portion of the first sidewall layer of the second bit line structure sidewall.

26. The semiconductor device as claimed in claim 25, characterized in that, A portion of the third sidewall layer is sandwiched between the second sidewall layer and the fourth sidewall layer in a direction perpendicular to the substrate.

27. The semiconductor device as claimed in claim 26, characterized in that, It also includes a memory node contact structure located on one side of the second bit line structure and extending into the substrate, with a portion of the third sidewall layer sandwiched between the fourth sidewall layer and the memory node contact structure.

28. The semiconductor device as claimed in claim 19, characterized in that, A gap is included between the storage node contact structure and the third sidewall layer at the second recess.

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