Semiconductor structure and method of forming the same

Abstract

The present disclosure provides a semiconductor structure including a bit line on a substrate. The bit line includes a polysilicon contact, a conductive layer on the polysilicon contact, and a hard mask layer on the conductive layer. The polysilicon contact includes a seed layer and a doped polysilicon layer. The seed layer directly contacts an active region of the substrate. The doped polysilicon layer directly contacts the seed layer on the seed layer. The doped polysilicon layer includes a first portion and a second portion on the first portion. A first ratio of a total number of N-type dopants to a total number of silicon in the first portion is greater than a second ratio of a total number of N-type dopants to a total number of silicon in the second portion, and a first thickness of the first portion is less than a second thickness of the second portion. The first portion having a higher dopant concentration and a smaller thickness and the second portion having a lower dopant concentration and a larger thickness on the first portion can reduce the resistance of the polysilicon contact and reduce voids and seams therein, and the sidewalls of the polysilicon contact are straight.

Description

Technical Field

[0001] This disclosure pertains to semiconductor structures and their formation methods. Background Technology

[0002] As the semiconductor industry develops, there is a growing need to integrate more components into a given area of ​​a wafer. To increase component integration density, individual components must be shrunk accordingly. However, as components shrink, various challenges arise. For example, in manufacturing bit line structures for dynamic random-access memory (DRAM), smaller bit line structures can lead to a smaller contact area between the bit line contacts and the active area of ​​the semiconductor substrate, resulting in increased resistance of the bit line structure and consequently reduced electrical performance of the DRAM. Increasing the dopant in the bit line contacts may reduce resistance, but voids and seams may appear in the material during bit line structure fabrication, also reducing the electrical performance of the DRAM. Therefore, novel semiconductor structures including bit lines and their fabrication methods are needed. Summary of the Invention

[0003] This disclosure provides a semiconductor structure including bit lines on a substrate. The bit lines include a polysilicon contact, a conductive layer on the polysilicon contact, and a hard masking layer on the conductive layer. The polysilicon contact includes a seed layer and a doped polysilicon layer. The seed layer directly contacts an active region of the substrate. The doped polysilicon layer directly contacts the seed layer. The doped polysilicon layer includes a first portion and a second portion on the first portion. A first ratio of the total number of N-type dopants to the total number of silicon atoms in the first portion is greater than a second ratio of the total number of N-type dopants to the total number of silicon atoms in the second portion, and a first thickness of the first portion is less than a second thickness of the second portion.

[0004] In some implementations, the first quantity ratio is 1 to 2, and the second quantity ratio is 0.04 to 0.09.

[0005] In some implementations, the first thickness is 2 nm to 6 nm, and the second thickness is 35 nm to 45 nm.

[0006] In some implementations, the thickness of the seed layer is 0.5 nm to 1 nm.

[0007] In some embodiments, the first width of the first portion is 6 nm to 12 nm, and the second width of the second portion is 6 nm to 12 nm.

[0008] In some implementations, the difference between the bottom width and the top width of the polysilicon contact is less than 1.2 nm.

[0009] This disclosure also provides a semiconductor structure formed by thermal annealing of the polysilicon contacts in the above semiconductor structure, wherein the concentration of the N-type dopant in the second part has a gradient increasing toward the interface between the first part and the second part.

[0010] In some embodiments, the average concentration of the N-type dopant in the first and second portions is 2.5 × 10⁻⁶. 20 atoms / cm 3 Up to 5.0×10 20 atoms / cm 3 .

[0011] This disclosure also provides a method for forming a semiconductor structure, comprising the following operations: forming a first doped polysilicon layer on a seed layer on a substrate by using an N-type dopant precursor and a silicon precursor in a carrier gas, wherein the volume of the N-type dopant precursor is in a first volume ratio relative to the volume of the carrier gas, the seed layer contacts an active region of the substrate, and the first doped polysilicon layer contacts the seed layer. forming a second doped polysilicon layer on the first doped polysilicon layer by using an N-type dopant precursor and a silicon precursor in a carrier gas, wherein the volume of the N-type dopant precursor is in a second volume ratio relative to the volume of the carrier gas, and the second volume ratio is less than the first volume ratio. forming a conductive layer on the second doped polysilicon layer. forming a hard mask layer on the conductive layer. etching portions of the hard mask layer, the conductive layer, the second doped polysilicon layer, the first doped polysilicon layer, and the seed layer to form bit lines on the substrate.

[0012] In some implementations, the first volume ratio is 2% to 5%.

[0013] In some implementations, the silicon precursor and the N-type dopant precursor are each hydrides.

[0014] In some embodiments, the temperature for forming the first doped polysilicon layer is 440°C to 480°C, and the pressure is 1 Torr to 5 Torr; and the temperature for forming the second doped polysilicon layer is 440°C to 480°C, and the pressure is 1 Torr to 5 Torr.

[0015] In some embodiments, when forming the first doped polysilicon layer, the N-type dopant in the N-type dopant precursor reacts with the silicon in the silicon precursor, and the ratio of the amount of N-type dopant to the amount of silicon is 1 to 2; and when forming the second doped polysilicon layer, the N-type dopant in the N-type dopant precursor reacts with the silicon in the silicon precursor, and the ratio of the amount of N-type dopant to the amount of silicon is 0.04 to 0.09.

[0016] In some implementations, the thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer.

[0017] In some embodiments, the method further includes a thermal annealing process of the first doped polysilicon layer and the second doped polysilicon layer at a temperature of 900 °C to 1100 °C.

[0018] It should be understood that the general description above and the detailed description below are exemplary and intended to provide further explanation of the claimed invention. Attached Figure Description

[0019] When reading the detailed description of the embodiments below, please refer to the accompanying drawings for a better understanding of this disclosure.

[0020] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure according to some embodiments of this disclosure.

[0021] Figures 2 to 8 This is a cross-sectional schematic diagram of a structure during the formation of a semiconductor structure according to some embodiments of the present disclosure. Detailed Implementation

[0022] The embodiments of this disclosure will be described in detail below, examples of which are shown in the accompanying drawings. In some cases, the same reference numerals are used in the drawings and description to refer to the same or similar elements.

[0023] This disclosure provides semiconductor structures including bit lines, such as Figure 8 As shown. Figures 2 to 7 For reference, some implementation methods are provided through Figure 1 The diagram shows the structure of the intermediate process of forming a semiconductor structure using the method shown. Figure 1 The methods shown and their related Figures 2 to 7 The intermediate structure shown will be discussed later.

[0024] First, refer to Figure 8The semiconductor structure shown includes bit lines on a substrate 11, wherein the bit lines include a polysilicon contact 21, a conductive layer 41, and a hard masking layer 51. The polysilicon contact 21 directly contacts the active region 101 of the substrate 11. The polysilicon contact 21 includes a seed layer 201 that directly contacts the active region 101 of the substrate 11 and a doped polysilicon layer that directly contacts the seed layer 201 and includes a first portion 202 and a second portion 203, wherein the second portion 203 is on the first portion 202 on the seed layer 201. A first ratio of the total number of N-type dopants to the total number of silicon in the first portion 202 is greater than a second ratio of the total number of N-type dopants to the total number of silicon in the second portion 203, and a first thickness 202T of the first portion 202 is less than a second thickness 203T of the second portion 203. The conductive layer 41 is on the polysilicon contact 21, and the hard masking layer 51 is on the conductive layer 41. The higher concentration of N-type dopant (or a larger first quantity ratio) in the first portion 202 reduces the resistance of the bit lines, and the thinner first portion 202 also avoids the formation of voids and seams within it. The thicker second portion 203 provides the main structural support for the polysilicon contact 21 and has a relatively lower concentration of N-type dopant (or a smaller second quantity ratio) to reduce the formation of voids and seams within it. The distribution of N-type dopant in the first portion 202 and the second portion 203 with the aforementioned relative concentration and relative thickness (or relative space occupancy) allows the polysilicon contact 21 formed by including these two portions to have relatively straight sidewalls (e.g., by etching the precursor layers of the first portion 202 and the second portion 203, as described below, to form a relatively straight polysilicon contact 21). The reduced resistance, voids, and seams, and the formation of a nearly straight polysilicon contact 21, improve the electrical performance of the bit lines, thereby allowing more and / or smaller bit lines to be formed on the substrate 11. The semiconductor structure of this disclosure will be further described below according to some embodiments.

[0025] The substrate 11 can be any suitable semiconductor substrate and may include different regions. For example, the substrate 11 includes an active region 101 on which electrical elements (e.g., polysilicon contacts 21) can be disposed for electrical connection with the active region 101. In some embodiments, the active region 101 comprises silicon and is doped with an N-type dopant (e.g., phosphorus, arsenic, antimony, or combinations thereof) or a P-type dopant (e.g., boron, gallium, aluminum, indium, or combinations thereof) depending on the electrical type of the semiconductor element. In some embodiments, the substrate 11 provides a plurality of active regions 101 to provide a plurality of electrical elements (e.g., a plurality of bit lines) disposed thereon. In these embodiments, the substrate 11 is provided with an isolation region 102 such that adjacent active regions 101 are separated by the isolation region 102, thereby avoiding electrical interference between different electrical elements. In some embodiments, the isolation region 102 comprises any suitable electrically insulating material, such as silicon dioxide.

[0026] A polysilicon contact 21 is disposed on and directly contacts the active region 101 of the substrate 11. The polysilicon contact 21 includes a seed layer 201 directly contacting the active region 101 of the substrate 11. The seed layer 201 comprises undoped polysilicon and can be used to facilitate the formation of a doped polysilicon layer on the seed layer 201. In addition to the seed layer 201, the polysilicon contact 21 also includes a doped polysilicon layer on the seed layer 201, wherein the doped polysilicon layer comprises silicon doped with a dopant (e.g., an N-type dopant) to reduce resistance. Specifically, the doped polysilicon layer includes a first portion 202 directly contacting the seed layer 201 and a second portion 203 directly contacting the first portion 202, wherein the second portion 203 is separated from the seed layer 201 by the first portion 202. The dopant concentration of the first portion 202 is higher than that of the second portion 203 to effectively reduce contact resistance. On the other hand, the dopant concentration of the second portion 203 is lower than that of the first portion 202 to reduce the formation of voids and seams inside. More specifically, the first number of N-type dopants per unit volume in the first portion 202 is greater than the second number of N-type dopants per unit volume in the second portion 203, or the first ratio of the total number of N-type dopants in the first portion 202 to the total number of silicon is greater than the second ratio of the total number of N-type dopants in the second portion 203 to the total number of silicon. Furthermore, the second portion 203 occupies a larger space in the polysilicon contact 21 than the first portion 202 and the seed layer 201 to provide primary structural support. For example, in one dimension, the thickness 201T of the seed layer 201 (in the direction perpendicular to the substrate 11) and the first thickness 202T of the first portion 202 (in the direction perpendicular to the substrate 11) are smaller than the second thickness 203T of the second portion 203 (in the direction perpendicular to the substrate 11).

[0027] The first ratio of the total number of N-type dopants to the total number of silicon in the first portion 202 is 1 to 2, for example, 1, 1.2, 1.4, 1.6, 1.8, or 2. When the first ratio is too small, the contact resistance may increase. When the first ratio is too large, the voids and seams in the first portion 202 may increase. The second ratio of the total number of N-type dopants to the total number of silicon in the second portion 203 is 0.04 to 0.09, for example, 0.04, 0.05, 0.06, 0.07, 0.08, or 0.09. When the second ratio is too small, the resistance of the second portion 203 may increase. When the second ratio is too large, the voids and seams in the second portion 203 may increase, which may also lead to an increase in the resistance of the second portion 203 due to voids and seams, and may reduce the mechanical strength of the second portion 203, and may cause the upper layer material disposed on the second portion 203 to diffuse into the second portion 203. Besides defects caused by voids and seams, when the second quantity ratio is too large (i.e., too much dopant), the precursor layer of the second portion 203 may be etched at a faster rate during bit line formation, potentially leading to reduced mechanical strength. If the second portion 203 is etched at a faster rate, the sidewalls of the polysilicon contact 21 may neck, thus reducing mechanical strength (necked sidewalls may also affect the electrical performance and integration density of the bit lines). In other words, when the second quantity ratio is too large, it may be difficult to form polysilicon contacts 21 with relatively straight sidewalls. Methods for forming semiconductor structures including bit lines will be described in more detail below according to some embodiments. In some embodiments, the N-type dopant includes phosphorus, arsenic, antimony, or combinations thereof, with phosphorus being preferred.

[0028] In some embodiments, the first thickness 202T of the first portion 202 is 2 nm to 6 nm, such as 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, or 6 nm. When the first thickness 202T is too small, the amount of dopant provided by the first portion 202 may be insufficient to reduce the contact resistance. When the first thickness 202T is too large, the amount of dopant in the first portion 202 may be excessive, leading to the formation of voids and seams. In some embodiments, the second thickness 203T of the second portion 203 is 35 nm to 45 nm, such as 35 nm, 37.5 nm, 40 nm, 42.5 nm, or 45 nm. When the second thickness 203T is too small, the structural support provided by the second portion 203 may be reduced. When the second thickness 203T is too large, the cost may outweigh the practical benefits. In some embodiments, the thickness 201T of the seed layer 201 is from 0.5 nm to 1 nm, for example, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, or 1 nm. When the thickness 201T is too small, the benefits provided by the seed layer 201 may be reduced. When the thickness 201T is too large, the benefits provided by the doped polysilicon layer may be reduced.

[0029] In some embodiments, the sidewalls of the polysilicon contact 21 are substantially straight, or the sidewalls of the seed layer 201, the first portion 202, and the second portion 203 are substantially straight and extend to each other. In some embodiments, the absolute value of the difference between the bottom width (in the direction parallel to the substrate 11) and the top width (in the direction parallel to the substrate 11) of the polysilicon contact 21 is less than 1.2 nm, for example, less than 1.1 nm. In some embodiments, the width W3 (in the direction parallel to the substrate 11) of the second portion 203 is 6 nm to 12 nm, for example, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, or 12 nm. In some embodiments, the width W2 (in the direction parallel to the substrate 11) of the first portion 202 is 6 nm to 12 nm, for example, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, or 12 nm. In some embodiments, the width W1 of the seed layer 201 (in the direction parallel to the substrate 11) is 6 nm to 12 nm, for example, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm or 12 nm. In some embodiments, the difference between any two of the widths W1, W2 and W3 is less than 1.2 nm, for example less than 1.1 nm.

[0030] A conductive layer 41 is disposed on the polysilicon contact 21. The conductive layer 41, together with the polysilicon contact 21, serves to conduct the current for writing and reading data in the bit lines. In some embodiments, the conductive layer 41 is a metal layer. In some embodiments, the conductive layer 41 includes tungsten, titanium, tantalum, ruthenium, iridium, platinum, rhodium, molybdenum, aluminum, copper, or combinations thereof, wherein tungsten is preferred due to its lower resistance and contact resistance.

[0031] In some embodiments, the bit line further includes a barrier layer 31 disposed between the polysilicon contact 21 and the conductive layer 41. The barrier layer 31 has the function of reducing resistance and can provide adhesion between the conductive layer 41 and the polysilicon contact 21. In some embodiments, the barrier layer 31 includes a metal (e.g., Co, Cu, Ni, Ru, Mn, Ag, Au, Pt, Fe, Mo, Rh, Ti, Ta, W or combinations thereof); a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride or combinations thereof); a metal silicide (e.g., tungsten silicide, tantalum silicide, titanium silicide, molybdenum silicide, zirconium silicide, cobalt silicide, chromium silicide, nickel silicide or combinations thereof); or combinations thereof. In some embodiments, the barrier layer 31 is a single layer or includes multiple sublayers (not shown), wherein adjacent sublayers are made of different materials. In some embodiments, the material of the barrier layer 31 is different from the material of the conductive layer 41. In some embodiments, the barrier layer 31 directly contacts the conductive layer 41 and the polysilicon contact 21. In some implementations, the bit line does not include the barrier layer 31, and the conductive layer 41 directly contacts the polysilicon contact 21.

[0032] A hard mask layer 51 is disposed on the conductive layer 41. The hard mask layer 51 can provide electrical insulation for bit lines and can be used as a hard mask when forming bit lines. In some embodiments, the hard mask layer 51 includes a dielectric material, such as silicon nitride, silicon carbonitride, silicon carbide, silicon oxide, or combinations thereof. In some embodiments, the hard mask layer 51 is a single layer (not shown) or includes multiple sublayers, wherein adjacent sublayers are made of different materials. For example, in an embodiment where the hard mask layer 51 includes sublayers 501, 502, and 503, sublayer 501 includes silicon nitride, sublayer 502 includes silicon oxide, and sublayer 503 includes silicon nitride.

[0033] In some embodiments, the semiconductor structure further includes sidewall spacers (not shown) disposed on the sidewalls of the bit lines. The sidewall spacers can provide electrical insulation and mechanical protection for the bit lines and can also be used as process tolerances. In some embodiments, the sidewall spacers comprise dielectric materials such as SiCO, silicon nitride, silicon oxide, or combinations thereof. In some embodiments, the sidewall spacers are a single layer. In some embodiments, the sidewall spacers comprise multiple layers, and the layers in contact with each other are made of different materials. In some embodiments, the sidewall spacers also include air sandwiched between adjacent layers in the multilayer structure.

[0034] This disclosure also provides a semiconductor structure formed by thermal annealing the polysilicon contact 21 in the above-described semiconductor structure, wherein the concentration of the N-type dopant in the second portion 203 has a gradient increasing towards the interface between the first portion 202 and the second portion 203. In some embodiments, the average concentration of the N-type dopant in the first portion 202 and the second portion 203 is 2.5 × 10⁻⁶. 20 atoms / cm 3 Up to 5.0×10 20 atoms / cm 3 For example, 2.5 × 10 20 atoms / cm 3 3.0×10 20 atoms / cm 3 3.5×10 20 atoms / cm 3 4.0×10 20 atoms / cm 3 4.5×10 20 atoms / cm 3 Or 5.0×10 20 atoms / cm 3 .

[0035] In some implementations, the resistance of the bit lines (whether or not a thermal annealing process is performed) is 80 Ω / sq to 110 Ω / sq, for example 80 Ω / sq, 90 Ω / sq, 100 Ω / sq or 110 Ω / sq.

[0036] This disclosure also provides a method for forming the above-described semiconductor structure including bit lines. (Refer to...) Figure 1 The method includes operations 61 to 65, and Figures 2 to 8The diagram illustrates structural variations according to some embodiments of the method. Operation 61 includes forming a first doped polysilicon layer 202' on a seed layer 201' on a substrate 11 using an N-type dopant precursor and a silicon precursor in a carrier gas, wherein the volume of the N-type dopant precursor is in a first volume ratio relative to the volume of the carrier gas, the seed layer 201' contacts the active region 101 of the substrate 11, and the first doped polysilicon layer 202' contacts the seed layer 201'. Operation 62 includes forming a second doped polysilicon layer 203' on the first doped polysilicon layer 202' using an N-type dopant precursor and a silicon precursor in a carrier gas, wherein the volume of the N-type dopant precursor is in a second volume ratio relative to the volume of the carrier gas, and the second volume ratio is less than the first volume ratio. Operation 63 includes forming a conductive layer 41' on the second doped polysilicon layer 203'. Operation 64 includes forming a hard mask layer 51' on the conductive layer 41. Operation 65 includes etching multiple portions of the hard mask layer 51', conductive layer 41', second doped polysilicon layer 203', first doped polysilicon layer 202', and seed layer 201' to form bit lines including the hard mask layer 51, conductive layer 41, and polysilicon contact 21 on the active region 101 of the substrate 11. This method uses N-type dopant precursors of different concentrations to form the first doped polysilicon layer 202' and the second doped polysilicon layer 203' to form the first portion 202 and the second portion 203 of the polysilicon contact 21, respectively. The method disclosed herein will be further described below according to some embodiments.

[0037] In operation 61, refer to Figure 2 and Figure 3 A first doped polysilicon layer 202' is formed on a seed layer 201' in a trench 71 of the substrate 11, wherein the first doped polysilicon layer 202' directly contacts the seed layer 201' and the seed layer 201' directly contacts the active region 101 of the substrate 11. In some embodiments, prior to forming the first doped polysilicon layer 202', the method further includes etching the substrate 11 with any suitable etching process to form the trench 71, and forming the seed layer 201' on the substrate 11 and in the trench 71 with any suitable deposition process. In some embodiments, the seed layer 201' comprises undoped polysilicon. In some embodiments, the seed layer 201' and the first doped polysilicon layer 202' are conformally formed in the trench 71. In some embodiments, forming the seed layer 201' and forming the first doped polysilicon layer 202' further includes forming the seed layer 201' and the first doped polysilicon layer 202' on the substrate 11 outside the trench 71, for example, on the isolation region 102.

[0038] In operation 62, refer to Figure 3 , Figure 4 , Figure 5and Figure 6 A second doped polysilicon layer 203' is formed to fill the trench 71 and is located on top of the first doped polysilicon layer 202'. In some embodiments, the second doped polysilicon layer 203' completely fills the trench 71. In some embodiments, forming the second doped polysilicon layer 203' also includes forming the second doped polysilicon layer 203' on the substrate 11 outside the trench 71, for example, on the isolation region 102.

[0039] In operations 61 and 62, refer to Figures 2 to 6 The precursor materials for forming the first doped polysilicon layer 202' and the second doped polysilicon layer 203' include a silicon precursor stored in a carrier gas (e.g., in a cylinder) and an N-type dopant precursor stored in a carrier gas (e.g., in another cylinder). The carrier gas carries the silicon precursor and the N-type dopant precursor into a chamber for reaction to form the first doped polysilicon layer 202' and the second doped polysilicon layer 203'. For forming the first doped polysilicon layer 202', the N-type dopant precursor in the carrier gas has a first volume ratio, which is the volume of the N-type dopant precursor relative to the volume of the carrier gas. For forming the second doped polysilicon layer 203', the N-type dopant precursor in the carrier gas has a second volume ratio, which is the volume of the N-type dopant precursor relative to the volume of the carrier gas, and the second volume ratio is less than the first volume ratio. In some embodiments, the first volume ratio is 2% to 5%, for example, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, or 5%. In some embodiments, the second volume ratio is 0.5% to 1.5%, for example, 0.5%, 0.75%, 1.0%, 1.25%, or 1.5%. In some embodiments, when forming the first doped polysilicon layer 202', the N-type dopant in the N-type dopant precursor reacts with the silicon in the silicon precursor, and the first quantity ratio of the amount of N-type dopant reacting to the amount of silicon is 1 to 2, for example, 1, 1.2, 1.4, 1.6, 1.8, or 2. In some embodiments, when forming the second doped polysilicon layer 203', the N-type dopant in the N-type dopant precursor reacts with the silicon in the silicon precursor, and the second quantity ratio of the amount of N-type dopant reacting to the amount of silicon is 0.04 to 0.09, for example 0.04, 0.05, 0.06, 0.07, 0.08 or 0.09.

[0040] When the first volume ratio and the first quantity ratio are too small, the resistance of the formed first doped polysilicon layer 202' may increase. When the first volume ratio and the first quantity ratio are too large, the voids and seams in the formed first doped polysilicon layer 202' may increase. When the second volume ratio and the second quantity ratio are too small, the resistance of the formed second doped polysilicon layer 203' may increase. When the second volume ratio and the second quantity ratio are too large, the voids and seams in the formed second doped polysilicon layer 203' may increase, which may also lead to an increase in the resistance of the second doped polysilicon layer 203' due to voids and seams, and reduce the mechanical strength of the second doped polysilicon layer 203', and may cause the material disposed on the upper layer of the second doped polysilicon layer 203' to diffuse into the second doped polysilicon layer 203'. Besides defects caused by voids and seams, when the second volume ratio and the second number ratio are too large (i.e., too much dopant), the etching rate of the second doped polysilicon layer 203' in operation 65 may increase, potentially leading to a decrease in mechanical strength. If the second doped polysilicon layer 203' is etched too quickly, the sidewalls of the formed polysilicon contact 21 may become necked, thus reducing mechanical strength (this necked sidewall may also affect the electrical performance of the bit lines and the integration density). In other words, when the second volume ratio and the second number ratio are too large, it may be difficult to form polysilicon contacts 21 with relatively straight sidewalls.

[0041] In some embodiments, the silicon precursor is a hydride, such as silane. In some embodiments, the N-type dopant precursor is a hydride, such as PH3, AsH3, SbH3, or combinations thereof, wherein PH3 is preferred due to its easier diffusion. In some embodiments, the temperature for forming the first doped polysilicon layer 202' is 440°C to 480°C (e.g., 440°C, 450°C, 460°C, 470°C, or 480°C), and the pressure is 1 Torr to 5 Torr (e.g., 1 Torr, 2 Torr, 3 Torr, 4 Torr, or 5 Torr); and the temperature for forming the second doped polysilicon layer 203' is 440°C to 480°C (e.g., 440°C, 450°C, 460°C, 470°C, or 480°C), and the pressure is 1 Torr to 5 Torr (e.g., 1 Torr, 2 Torr, 3 Torr, 4 Torr, or 5 Torr). In some embodiments, the first doped polysilicon layer 202' is formed by chemical vapor deposition (CVD). In some embodiments, the second doped polysilicon layer 203' is formed by chemical vapor deposition (CVD).

[0042] In operations 61 and 62, refer to Figures 2 to 6The thickness of the first doped polysilicon layer 202' (in the direction perpendicular to the substrate 11) is less than the thickness 74 of the second doped polysilicon layer 203' (in the direction perpendicular to the substrate 11). The thickness of the first doped polysilicon layer 202' is substantially the same as the first thickness 202T described above. In some embodiments, the thickness 74 of the second doped polysilicon layer 203' is substantially the same as the second thickness 203T described above, or in some embodiments, the thickness 74 of the second doped polysilicon layer 203' is slightly larger than the second thickness 203T described above, and the second thickness 203T is formed after a polishing process. For example, in some embodiments, after forming the second doped polysilicon layer 203' in operation 62 and before forming the conductive layer 41' in operation 63 (or before forming the barrier layer 31' in some embodiments), the method further includes forming a sacrificial cap layer 75 on the second doped polysilicon layer 203' and performing a polishing process (e.g., a chemical mechanical polishing process, CMP) on the sacrificial cap layer 75 to remove the sacrificial cap layer 75 and give the second doped polysilicon layer 203' the aforementioned second thickness 203T. The formation of the sacrificial cap layer 75 and the corresponding polishing process help to planarize the surface of the second doped polysilicon layer 203'.

[0043] In operation 63, refer to Figure 7 The conductive layer 41' is formed on the second doped polysilicon layer 203' using any suitable deposition process. In some embodiments, a barrier layer 31' is first formed on the second doped polysilicon layer 203' using any suitable deposition process before forming the conductive layer 41'. The conductive layer 41' and the barrier layer 31' will be formed in an etching process (e.g., the etching process in operation 65) by removing multiple portions of the conductive layer 41' and the barrier layer 31' as described above. The material and structure of the barrier layer 31' are substantially the same as those of the barrier layer 31 described above, and will not be repeated here; details can be found above.

[0044] In operation 64, refer to Figure 7 The hard mask layer 51' is formed on the conductive layer 41' using any suitable deposition process. The hard mask layer 51' will be formed by removing portions of the hard mask layer 51' during an etching process (e.g., the etching process in operation 65). For example, sublayers 501', 502', and 503' of the hard mask layer 51' will be formed after the etching process, respectively. The material and structure of the hard mask layer 51' are substantially the same as those of the hard mask layer 51 described above, and will not be repeated here; details can be found above.

[0045] In operation 65, refer to Figure 7 and Figure 8 Multiple portions of the hard mask layer 51', conductive layer 41', second doped polysilicon layer 203', first doped polysilicon layer 202', and seed layer 201' (and barrier layer 31' in some embodiments) are etched using any suitable etching process to form the hard mask layer 51, conductive layer 41, second portion 203 of polysilicon contact 21, first portion 202 of polysilicon contact 21, and seed layer 201 of polysilicon contact 21 (and barrier layer 31 in some embodiments) on the active region 101 of substrate 11, respectively. In some embodiments, the etching of the hard mask layer 51', conductive layer 41', second doped polysilicon layer 203', first doped polysilicon layer 202', and seed layer 201' (and barrier layer 31' in some embodiments) is completed by a single etching process (i.e., an all-in-one etching process). The dopant concentration and thickness in the first doped polysilicon layer 202' and the second doped polysilicon layer 203' help the first doped polysilicon layer 202' and the second doped polysilicon layer 203' to have better etching rates, so as to form polysilicon contacts 21 with straighter sidewalls.

[0046] In some embodiments, after forming the bit line in operation 65, the method further includes forming sidewall spacers (not shown) on the sidewalls of the bit line using any suitable deposition process. The material and structure of the sidewall spacers are substantially the same as those described above, and will not be repeated here; details can be found above.

[0047] In some embodiments, after forming the first doped polysilicon layer 202' and the second doped polysilicon layer 203', the method further includes thermally annealing the polysilicon contact 21 at a temperature of 900°C to 1100°C, for example, 900°C, 950°C, 1000°C, 1050°C, or 1100°C, so that the second portion 203 includes the concentration gradient of the aforementioned N-type dopant. In some embodiments, the method does not include high-temperature processing of the bit lines (e.g., processes above 900°C) and does not perform thermal annealing on the polysilicon contact 21.

[0048] The polysilicon contact disclosed herein includes a first portion with a higher dopant concentration and a smaller thickness, and a second portion with a lower dopant concentration and a larger thickness on the first portion, to reduce the resistance of the polysilicon contact and reduce voids and seams within the polysilicon contact. Furthermore, the sidewalls of the polysilicon contact are straight and do not have necking. Overall, the electrical performance and mechanical strength of the bit lines are improved, which helps to reduce the size of the bit lines and increase the integration density of multiple bit lines.

[0049] This disclosure has described some embodiments in detail, but other embodiments may also exist. This disclosure is not intended to limit the scope of the appended patent applications with respect to the embodiments contained herein.

[0050] Various modifications and variations can be readily made to this disclosure without departing from its scope and spirit. Therefore, this disclosure is intended to cover such modifications and variations when they fall within the scope of the appended claims.

[0051] [Symbol Explanation] 11: Substrate 21: Polycrystalline silicon contact 31: Barrier Layer 41: Conductive layer 51: Hard mask layer 61: Operation 62: Operation 63: Operation 64: Operation 65: Operation 71: Trench 74: Thickness 75: Sacrifice Hat Layer 101: Active Region 102: Quarantine Area 201: Seed layer 202: Part One 203: Part Two 501: Sub-layer 502: Sublayer 503: Sub-layer 201': Seed layer 201T: Thickness 202': The first doped polycrystalline silicon layer 202T: First Thickness 203': Second doped polycrystalline silicon layer 203T: Second Thickness 31': Barrier layer 41': Conductive layer 501': Sublayer 502': Sublayer 503': Sublayer 51': Hard mask layer W1: Width W2: Width W3: Width.

Claims

1. A semiconductor structure, characterized in that, include: A bit line is on the substrate, wherein the bit line includes: Polycrystalline silicon contacts, including: The seed layer directly contacts the active region of the substrate; and A doped polysilicon layer is directly in contact with the seed layer, wherein the doped polysilicon layer includes a first portion and a second portion on the first portion, wherein a first ratio of the total number of N-type dopants to the total number of silicon in the first portion is greater than a second ratio of the total number of N-type dopants to the total number of silicon in the second portion, and the first thickness of the first portion is less than the second thickness of the second portion. A conductive layer is present on the polysilicon contact; and A hard masking layer is placed on the conductive layer.

2. The semiconductor structure according to claim 1, wherein the first quantity ratio is 1 to 2, and the second quantity ratio is 0.04 to 0.

09.

3. The semiconductor structure according to claim 1, wherein the first thickness is 2 nm to 6 nm and the second thickness is 35 nm to 45 nm.

4. The semiconductor structure according to claim 1, wherein the thickness of the seed layer is 0.5 nm to 1 nm.

5. The semiconductor structure of claim 1, wherein the first width of the first portion is 6 nm to 12 nm, and the second width of the second portion is 6 nm to 12 nm.

6. The semiconductor structure according to claim 1, wherein the difference between the bottom width and the top width of the polysilicon contact is less than 1.2 nm.

7. A semiconductor structure, characterized in that, Formed by a thermal annealing process on the polysilicon contact in the semiconductor structure according to claim 1, wherein the concentration of the N-type dopant in the second portion has a gradient increasing toward the interface between the first portion and the second portion.

8. The semiconductor structure according to claim 7, wherein the average concentration of the N-type dopant in the first portion and the second portion is 2.5 × 10⁻⁶. 20 atoms / cm 3 Up to 5.0×10 20 atoms / cm 3 .

9. A method for forming a semiconductor structure, characterized in that, include: A first doped polysilicon layer is formed on a seed layer on a substrate by using an N-type dopant precursor and a silicon precursor in a carrier gas, wherein the volume of the N-type dopant precursor is in a first volume ratio relative to the volume of the carrier gas, the seed layer contacts the active region of the substrate, and the first doped polysilicon layer contacts the seed layer. A second doped polysilicon layer is formed on the first doped polysilicon layer by using the N-type dopant precursor and the silicon precursor in the carrier gas, wherein the volume of the N-type dopant precursor is a second volume ratio relative to the volume of the carrier gas, and the second volume ratio is less than the first volume ratio. A conductive layer is formed on the second doped polysilicon layer; A hard masking layer is formed on the conductive layer; and Multiple portions of the hard mask layer, the conductive layer, the second doped polysilicon layer, the first doped polysilicon layer, and the seed layer are etched to form bit lines on the substrate.

10. The method of claim 9, wherein the first volume ratio is 2% to 5%.

11. The method of claim 9, wherein the silicon precursor and the N-type dopant precursor are each hydrides.

12. The method according to claim 9, wherein: The first doped polycrystalline silicon layer is formed at a temperature of 440 °C to 480 °C and a pressure of 1 Torr to 5 Torr; and The temperature for forming the second doped polycrystalline silicon layer is 440 °C to 480 °C, and the pressure is 1 Torr to 5 Torr.

13. The method according to claim 9, wherein: When the first doped polycrystalline silicon layer is formed, the N-type dopant in the N-type dopant precursor reacts with the silicon in the silicon precursor, and the ratio of the amount of N-type dopant to the amount of silicon is 1 to 2. as well as When forming the second doped polysilicon layer, the N-type dopant in the N-type dopant precursor reacts with the silicon in the silicon precursor, and the ratio of the amount of N-type dopant to the amount of silicon is 0.04 to 0.

09.

14. The method of claim 9, wherein the thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer.

15. The method according to claim 9, wherein, It also includes a thermal annealing process for the first doped polysilicon layer and the second doped polysilicon layer at a temperature of 900 °C to 1100 °C.

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