Semiconductor structure and method of manufacturing the same

Abstract

The present invention relates to a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a substrate, a bit line, a bit line capacitor, a transistor and a metal line. The substrate has a memory region and a peripheral region. The bit line is located above the memory region of the substrate. The bit line capacitor is located above the bit line and connected to the bit line. The transistor is located above the peripheral region of the substrate. The metal line is located above the transistor. A top surface of the bit line is higher than a bottom surface of the metal line. A dielectric layer is located above the metal line and contacts the metal line. The dielectric layer and the bit line capacitor are made of the same material. The method of the present invention can form the first metal line and the bit line simultaneously, so as to improve the flexibility of layout and routing of the semiconductor structure. Since the first metal line can be electrically connected to the gate structure and its related interconnection structure, more flexible layout and routing design can be achieved.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] For 10-nanometer process node dynamic random access memory (DRAM) technology, the core area, including the sense amplifier and sub-word line driver circuitry, has extremely high metal wiring density, and due to insufficient area, interconnect layout configuration is extremely difficult. Therefore, a reliable semiconductor structure and its manufacturing method are urgently needed. Summary of the Invention

[0003] This invention relates to a semiconductor structure comprising a substrate, bit lines, bit line capacitors, transistors, a first metal line, and a dielectric layer. The substrate includes a memory region and a peripheral region. The bit lines are located above and electrically connected to a first active region of the memory region on the substrate. The bit line capacitors are located above and in contact with the bit lines. The transistors are located above the peripheral region of the substrate. The first metal line is located above the transistor. The top surface of the bit lines is higher than the bottom surface of the metal line, and the first metal line and the bit lines are made of the same material. The dielectric layer is located above and in contact with the first metal line. The dielectric layer and the bit line capacitors are made of the same material.

[0004] In some implementations, the top surface of the bit line is located between the top and bottom surfaces of the first metal line.

[0005] In some implementations, the top surface of the bit line capacitor is flush with the top surface of the dielectric layer.

[0006] In some implementations, the bottom surface of the dielectric layer is located between the top and bottom surfaces of the bit line capacitor.

[0007] In some embodiments, the semiconductor structure further includes a second metal line, a first via contact window, and a second via contact window. The second metal line is located above the dielectric layer. The first via contact window is located between the first metal line and the source / drain regions of the transistor. The second via contact window is located between the first metal line and the second metal line.

[0008] In some embodiments, the second via contact window electrically connects the source / drain regions of the transistor and the ground doped region of the substrate.

[0009] In some embodiments, the semiconductor structure further includes an interlayer dielectric layer disposed along the sidewalls of the first metal line and the sidewalls of the dielectric layer.

[0010] In some embodiments, the semiconductor structure further includes a second metal line disposed along the top surface of the dielectric layer and the interlayer dielectric layer.

[0011] In some implementations, the first metal line is in contact with the top surface of the transistor's gate structure.

[0012] In some embodiments, the semiconductor structure further includes a bit line spacer layer, a cell contact window, and a capacitor. The bit line spacer layer is disposed along the bit lines and the bit line capacitor. The cell contact window is adjacent to the bit line spacer layer and electrically connected to a second active region of the memory region of the substrate. The capacitor is electrically connected to the cell contact window.

[0013] The present invention also relates to a method for manufacturing a semiconductor structure, comprising: forming bit line contact windows and transistors on a memory region and a peripheral region of a substrate; forming a conductive layer that spans the bit line contact windows and transistors; forming a dielectric layer on the conductive layer; forming a spacer material extending through a portion of the dielectric layer and a portion of the conductive layer in the memory region; patterning the conductive layer and the dielectric layer in the memory region to form bit lines and bit line capacitors, respectively; and forming a first interlayer dielectric layer extending through a portion of the dielectric layer and the conductive layer in the peripheral region; and patterning the conductive layer in the peripheral region to form a first metal line.

[0014] In some implementations, the top surface of the bit line is higher than the bottom surface of the metal line.

[0015] In some implementations, the top surface of the bit line is located between the top and bottom surfaces of the first metal line.

[0016] In some implementations, the top surface of the bit line capacitor is flush with the top surface of the dielectric layer.

[0017] In some implementations, the bottom surface of the dielectric layer is located between the top and bottom surfaces of the bit line capacitor.

[0018] In some embodiments, the method for manufacturing a semiconductor further includes: forming a semiconductor layer on a substrate, wherein bit line contact windows are formed to extend through the semiconductor layer; etching portions of the semiconductor layer and portions of the bit line contact windows in a memory region; forming a protective layer on portions of the semiconductor layer to cover the bit line contact windows; and patterning portions of the semiconductor layer in a peripheral region to form the gate of a transistor.

[0019] In some embodiments, the method for manufacturing a semiconductor further includes: forming a second interlayer dielectric layer on a peripheral region of a substrate; and removing a protective layer to expose bit line contact windows before forming a conductive layer.

[0020] In some implementations, a portion of the conductive layer in the memory region has a top surface that is lower than a portion of the conductive layer in the peripheral region.

[0021] In some embodiments, the method for manufacturing a semiconductor further includes forming a second metal line disposed along the top surface of the dielectric layer and the first interlayer dielectric layer, wherein the second metal line is electrically connected to the first metal line.

[0022] In some embodiments, the method for manufacturing a semiconductor further includes forming a capacitor after forming a first interlayer dielectric layer. The capacitor is electrically connected to an active region in a memory region of the substrate.

[0023] In summary, the method of the present invention can simultaneously form a first metal line and a bit line, thereby improving the flexibility of semiconductor structure layout and wiring. The semiconductor structure manufactured by the method of the present invention allows for more flexible layout and wiring design because the first metal line can be electrically connected to the gate structure and its associated interconnect structures.

[0024] These and other features, aspects and advantages of the present invention will become clearer with reference to the following description, claims and drawings.

[0025] It should be understood that the above general description and the following detailed description are merely examples and are intended to further explain the claimed invention. Attached Figure Description

[0026] A more complete understanding of the invention can be achieved by referring to the following detailed description of the embodiments herein: Figure 1 This is a circuit diagram of a memory array according to some embodiments of the present invention.

[0027] Figure 2 for Figure 1 A partially enlarged view of the memory array shown.

[0028] Figure 3 This is a schematic top view of a semiconductor structure according to some embodiments of the present invention.

[0029] Figure 4 This is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

[0030] Figure 5 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0031] Figure 6 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0032] Figure 7 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0033] Figure 8This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0034] Figure 9 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0035] Figure 10 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0036] Figure 11 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0037] Figure 12 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0038] Figure 13 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0039] Figure 14 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention.

[0040] Figure 15 This is a cross-sectional view of a semiconductor structure during the manufacturing stage according to some embodiments of the present invention. Detailed Implementation

[0041] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0042] The following disclosure provides many different implementations or examples for achieving different functions of the provided subject matter. To simplify the content of the invention, specific examples of elements and arrangements are described below. These examples are, of course, merely illustrative and not intended to be limiting. For example, the description of a first feature formed on or on the surface of a second feature may include implementations where the first and second features are in direct contact, or implementations where other features are formed between the first and second features without direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples; such repetition is for simplification and clarity and is not intended to indicate, in itself, a relationship between the various implementations and / or configurations discussed.

[0043] Furthermore, for ease of description, spatially related terms such as "below," "below," "bottom," "above," and "top" may be used in this invention to describe the relationship of one element or feature relative to another, as shown in the accompanying drawings. These spatially related terms are intended to cover different orientations of the device during use or operation, and are not limited to the orientations shown in the drawings. For example, the device may operate in different orientations (such as rotating 90 degrees or other orientations), therefore the spatially related descriptive terms in this document should be interpreted accordingly.

[0044] The terms "about," "approximately," "approximately," or "substantially" as used in this specification generally indicate a range of 20%, 10%, or 5% error within a specific value or range. All values ​​listed in this invention are approximate, meaning that even if not explicitly stated, the terms "about," "approximately," "approximately," or "substantially" can be inferred to apply. However, those skilled in the art should understand that the values ​​or ranges mentioned in the specification are merely examples, and as integrated circuits shrink, their values ​​or ranges may decrease or change accordingly.

[0045] This invention describes embodiments with reference to cross-sectional schematic diagrams, which are simplified representations of idealized embodiments (and intermediate structures). Therefore, actual structures may differ from the schematic shape due to manufacturing techniques and / or tolerances. Thus, the illustrated embodiments should not be construed as limited to the specific shapes of the illustrated areas, but should include shape deviations due to manufacturing factors. For example, the figures show rectangular doped regions whose edges typically exhibit rounded corners or curves, and whose doping concentration shows a gradual distribution, rather than a binary abrupt change between undoped and non-doped regions. Similarly, embedded regions formed by doping may allow dopant to penetrate into the transition zone between the embedded region and the doped surface. Therefore, the areas in the figures are merely illustrative, and their shapes are not intended to represent the actual form of the device areas, nor should they be considered as limiting the scope of this invention.

[0046] The embodiments will be described in detail below with reference to the accompanying drawings.

[0047] Please see Figure 1 , Figure 1 This is a circuit diagram of a memory array MA according to some embodiments of the present invention. The memory array MA includes a plurality of memory cells 101 arranged in a rectangular matrix. Each row of memory cells 101 is connected by word lines, and each column of memory cells 101 is connected by bit lines. Figure 1 In this process, sixteen memory cells 101 are organized and accessed through word lines WL0, WL1, WL2 and WL3, and bit lines BL0, BL1, BL2 and BL3.

[0048] Please see Figure 2 , Figure 2 yes Figure 1 A partially enlarged view. Memory cell 101 consists of access transistor 101T and storage capacitor 101C electrically connected to access transistor 101T. Specifically, access transistor 101T is typically an n-type metal-oxide-semiconductor field-effect transistor (NMOS), which controls the channel to memory cell 101 by turning its gate on or off. Storage capacitor 101C stores information based on the charge state stored within it. A storage capacitor 101C in an empty state (i.e., no charge) represents a logic value of 0. A storage capacitor 101C in a fully charged state represents a logic value of 1. Memory cell 101 stores one bit of data through the two extreme states of charge in storage capacitor 101C.

[0049] Please refer to it again. Figure 2 The word line WL0, connected to the access transistor 101T, is used to control the gate of the access transistor 101T by applying a voltage to it. Bit line BL2 is arranged perpendicular to word line WL0 and is also connected to the access transistor 101T. When the gate of the access transistor 101T is turned on, the access transistor 101T connects the storage capacitor 101C to bit line BL2, so that the logic value stored in the storage capacitor 101C is transferred to bit line BL2.

[0050] Please see Figure 3 , Figure 3 This is a schematic top view of a semiconductor structure 100 according to some embodiments of the present invention. The semiconductor structure 100 includes a substrate 110. The substrate 110 may include a memory region R10, an edge array region R20, and a peripheral region R30. The edge array region R20 may surround the memory region R10. The peripheral region R30 may surround the edge array region R20.

[0051] Please see Figure 4 , Figure 4 This is a cross-sectional view of a semiconductor structure 100 according to some embodiments of the present invention. The semiconductor structure 100 includes a substrate 110, a bit line structure located above a memory region R10 of the substrate 110, and a transistor T located above a peripheral region R30 of the substrate 110. The substrate 110 includes a memory region R10, an edge array region R20, and a peripheral region R30.

[0052] In some embodiments, the bit line structure includes a bit line contact window BT1, a bit line BT2, and a bit line capacitor BT3. The bit line contact window BT1 is located above the memory region R10 of the substrate 110. The bit line BT2 is located above and in contact with the bit line contact window BT1. The bit line capacitor BT3 is located above and in contact with the bit line BT2. The bit structure is located above and electrically connected to the first active region AR1 of the memory region R10 of the substrate 110.

[0053] In some embodiments, the transistor T includes a gate structure GT and two source / drain regions S / D located on both sides of the gate structure GT. The gate structure GT may include a gate dielectric layer GT1 and a gate electrode GT2 located above the gate dielectric layer GT1. Gate spacer layers GT3 are provided on both sides of the gate dielectric layer GT1 and the gate electrode GT2.

[0054] In some embodiments, the semiconductor structure 100 includes a first metal line 134 located above the transistor T. The top surface of the bit line BT2 may be higher than the bottom surface of the first metal line 134. The top surface of the bit line BT2 may be located between the top and bottom surfaces of the first metal line 134. Figure 4 In other embodiments not shown, the top surface of bit line BT2 may be flush with the top surface of the first metal line 134. The first metal line 134 and bit line BT2 may be made of the same material. The first metal line 134 may be in contact with the top surface of the gate structure GT of transistor T.

[0055] In some embodiments, the semiconductor structure 100 includes a dielectric layer 140. The dielectric layer 140 is located on and in contact with the first metal line 134. The top surface of the bit line capacitor BT3 may be flush with the top surface of the dielectric layer 140. The bottom surface of the dielectric layer 140 may be located between the top and bottom surfaces of the bit line capacitor BT3. The dielectric layer 140 and the bit line capacitor BT3 may be made of the same material.

[0056] In some embodiments, the semiconductor structure 100 includes a second metal line 164, a second metal line 168, a first via contact window 125, and a second via contact window 145. The second metal lines 164 and 168 are located above the dielectric layer 140. The first via contact window 125 may be located between and in contact with the first metal line 134 and the source / drain region S / D of one of the transistors T. The second via contact window 145 may be located between and in contact with the first metal line 134 and the second metal line 164.

[0057] In some embodiments, the first via contact window 125 may extend through the first interlayer dielectric layer 120. The first interlayer dielectric layer 120 may be located above the peripheral region R30 of the substrate 110.

[0058] In some embodiments, the second via contact window 145 extends through the dielectric layer 140. The second via contact window 145 can electrically connect the source / drain region (S / D) of the transistor T to the ground doped region (GR) in the substrate 110. The second metal lines 164 and 168 are located on the dielectric layer 140.

[0059] In some embodiments, the semiconductor structure 100 includes a second interlayer dielectric layer 160 disposed along the sidewalls of the first metal line 134 and the sidewalls of the dielectric layer 140. The second metal line 164 and the second metal line 168 are disposed along the top surfaces of the dielectric layer 140 and the second interlayer dielectric layer 160.

[0060] In some embodiments, the semiconductor structure 100 includes a third via contact window 182 and a fourth via contact window 185. The third via contact window 182 penetrates the third interlayer dielectric layer 170 and the fourth interlayer dielectric layer 180. The fourth via contact window 185 penetrates the fourth interlayer dielectric layer 180. The third interlayer dielectric layer 170 is located above the dielectric layer 140, the second metal line 164, and the bit line capacitor BT3. The fourth interlayer dielectric layer 180 is located above the third interlayer dielectric layer 170.

[0061] In some embodiments, the semiconductor structure 100 includes a third metal line 184 and a third metal line 188 located above a fourth interlayer dielectric layer 180. A third via contact window 182 is located between and in contact with the third metal line 184 and the second metal line 168. The second metal line 168 is located above the dielectric layer 140.

[0062] In some embodiments, the semiconductor structure 100 includes a bit line spacer layer 150, a cell contact window 152, and a capacitor 172. The bit line spacer layer 150 extends along bit line BT2 and bit line capacitor BT3. The cell contact window 152 is adjacent to the bit line spacer layer 150 and electrically connected to a second active region AR2 in the memory region R10 of the substrate 110. The capacitor 172 is electrically connected to the cell contact window 152. A fourth via contact window 185 may be located between and contact the third metal line 188 and the capacitor 172. The capacitor 172 may extend through the third interlayer dielectric layer 170 and contact the cell contact window 152 in the memory region R10 of the substrate 110.

[0063] Please see Figures 5 to 15 , Figures 5 to 15 Cross-sectional views of a semiconductor structure 100 according to some embodiments of the present invention are shown at various manufacturing stages.

[0064] exist Figure 5In this method, the semiconductor structure 100 is manufactured by forming an isolation structure 111 (e.g., shallow trench isolation) in a memory region R10, an edge array region R20, and a peripheral region R30 of a substrate 110. A dielectric layer 112 and a semiconductor layer 113 are then formed on the substrate 110. The dielectric layer 112 may be located between the semiconductor layer 113 and the substrate 110. In some embodiments, the substrate 110 may be made of a semiconductor material, such as silicon (Si). In some embodiments, the dielectric layer 112 may be made of silicon oxide, for example. In some embodiments, the semiconductor layer 113 may be made of polysilicon, for example.

[0065] like Figure 6 As shown, a method of manufacturing a semiconductor structure 100 includes forming a bit line contact window BT1. The bit line contact window BT1 extends through a portion of the semiconductor layer 113 and a portion of the dielectric layer 112 in the memory region R10 and the first active region AR1 of the substrate 110. The region between the isolation structures 111 in the memory region R10 can be defined as the first active region AR1 and the second active region AR2, respectively. The region between the isolation structures 111 in the peripheral region R30 can be defined as the ground doped region GR. In some embodiments, the first active region AR1 and the second active region AR2 can serve as the source / drain regions of an access transistor. In some embodiments, the first active region AR1 and the second active region AR2 can contain a conductivity type opposite to that of the substrate 110. For example, if the substrate 110 is doped with a p-type dopant, the first active region AR1 and the second active region AR2 can be doped with an n-type dopant, and vice versa. In some embodiments, the ground doped region GR and the substrate 110 can contain the same type of dopant.

[0066] like Figure 7 As shown, the method for manufacturing the semiconductor structure 100 includes etching (or recessing) a portion of the semiconductor layer 113 and a portion of the bit line contact window BT1 within the memory region R10 and the edge array region R20. Next, a protective layer 114 is formed on the recessed portion of the semiconductor layer 113 in the memory region R10 and the edge array region R20, covering the recessed portion of the bit line contact window BT1.

[0067] like Figure 8As shown, the method of manufacturing the semiconductor structure 100 includes patterning a portion of the semiconductor layer 113 and a portion of the dielectric layer 112 in the peripheral region R30 to form a gate structure GT. Simultaneously, a portion of the semiconductor layer 113 and a portion of the dielectric layer 112 in the memory region R10 are protected by a protective layer 114. The gate electrode GT2 of the transistor T is formed by patterning a portion of the semiconductor layer 113 in the peripheral region R30. Subsequently, a gate spacer layer GT3 is formed on the opposite sidewalls of each gate structure GT, and source / drain regions S / D are formed in the substrate 110 on opposite sides of the gate structure GT. Next, the transistor T is formed on the peripheral region R30 of the substrate 110. In some embodiments, the patterned semiconductor layer 113 and the patterned dielectric layer 112 in the peripheral region R30 constitute the gate dielectric layer GT1 and the gate electrode GT2 of the gate structure GT, respectively.

[0068] exist Figure 9 In this process, a method for manufacturing a semiconductor structure 100 includes forming a first interlayer dielectric layer 120 over a peripheral region R30 of a substrate 110. Then, a first via contact window 125 is formed, penetrating the first interlayer dielectric layer 120. The first via contact window 125 can make S / D contacts with and be electrically connected to the source / drain regions.

[0069] exist Figure 10 In this process, the method of manufacturing semiconductor structure 100 includes removing protective layer 114 to expose bit line contact window BT1 and the remainder of semiconductor layer 113 in memory region R10. At this stage, the top surface of semiconductor layer 113 is lower than the top surface of first interlayer dielectric layer 120.

[0070] exist Figure 11 In this method of manufacturing a semiconductor structure 100, a conductive layer 130 is formed, the conductive layer 130 spanning a bit line contact window BT1 and a transistor T. Subsequently, a dielectric layer 140 is formed over the conductive layer 130. In other words, the conductive layer 130 is formed over a first interlayer dielectric layer 120 and a semiconductor layer 113. At this stage, the top surface of the conductive layer 130 within the memory region R10 is lower than the top surface of the conductive layer 130 in the peripheral region R30. A portion of the top surface of the conductive layer 130 in the memory region R10 is lower than a portion of the top surface of the conductive layer 130 in the peripheral region R30. In some embodiments, the dielectric layer 140 may be selectively planarized, such that the top surface of the dielectric layer 140 is flat. In some embodiments, the conductive layer 130 may be made of, for example, tungsten (W). In some embodiments, the dielectric layer 140 may be made of, for example, silicon nitride (SiN).

[0071] like Figure 12As shown, a method for manufacturing a semiconductor structure 100 includes forming a bit line spacer layer 150 in a memory region R10, penetrating a portion of a dielectric layer 140 and a portion of a conductive layer 130, thereby etching the conductive layer 130 and the dielectric layer 140 in the memory region R10 into bit lines BT2 and bit line capacitors BT3, respectively. Next, a cell contact window 152 is formed, extending through a portion of the dielectric layer 140 and a portion of the conductive layer 130 within the memory region R10. The cell contact window 152 is located on and electrically connected to a second active region AR2 of the substrate 110. In some embodiments, the cell contact window 152 may be made of, for example, polysilicon.

[0072] exist Figure 13 In this process, a method of manufacturing a semiconductor structure 100 includes forming a second interlayer dielectric layer 160. The second interlayer dielectric layer 160 extends through a portion of the dielectric layer 140 and a portion of the conductive layer 130 in a peripheral region R30, thereby etching the conductive layer 130 in the peripheral region R30 into first metal lines 134 and 136. In other words, the first metal lines 134 and 136 are located on opposite sides of the second interlayer dielectric layer 160. The top surface of bit line BT2 may be higher than the bottom surface of the first metal lines 134 and 136. The top surface of bit line BT2 may be located between the top and bottom surfaces of the first metal lines 134 and 136. The first metal lines 134, 136, and BT2 may, for example, be made of the same material. The dielectric layer 140 covers and contacts the first metal lines 134 and 136. The dielectric layer 140 and the bit line capacitor BT3 may, for example, be made of the same material. The top surface of the bit line capacitor BT3 can be flush with the top surface of the dielectric layer 140. The bottom surface of the dielectric layer 140 can be located between the top and bottom surfaces of the bit line capacitor BT3. In the process of this invention, the first metal line 134 and the bit line BT2 are formed simultaneously, which enhances the flexibility of the wiring layout of the semiconductor structure 100.

[0073] like Figure 14As shown, a method of manufacturing a semiconductor structure 100 includes forming a second metal line 164 and a second metal line 168 over a dielectric layer 140. The second metal lines 164 and 168 extend along the top surface of the dielectric layer 140 and the second interlayer dielectric layer 160. Next, a second via contact window 145 is formed, penetrating the dielectric layer 140. The second via contact window 145 may be located between and in contact with the first metal line 134 and the second metal line 164, and / or located between and in contact with the first metal line 136 and the second metal line 164. In some embodiments, at least one source / drain region S / D of transistor T can be electrically connected to the ground doped region GR via a first via contact window 125 (which contacts the source / drain region S / D), a first metal line 134, a second via contact window 145 (which contacts the first metal line 134 and the second metal line 164), a second metal line 164, a second via contact window 145 (which contacts the first metal line 136 and the second metal line 164), a first metal line 136, and a first via contact window 125 (which contacts the ground doped region GR).

[0074] like Figure 15 As shown, a method for manufacturing a semiconductor structure 100 includes forming a third interlayer dielectric layer 170 on a dielectric layer 140, a second metal line 164, and a bit line capacitor BT3. Subsequently, a capacitor 172 is formed, penetrating the third interlayer dielectric layer 170. The capacitor 172 is electrically connected to a second active region AR2 of the substrate 110 in the memory region R10. Next, a fourth interlayer dielectric layer 180 is formed on the third interlayer dielectric layer 170. Subsequently, a third via contact window 182 is formed, penetrating both the fourth interlayer dielectric layer 180 and the third interlayer dielectric layer 170. Next, a fourth via contact window 185 is formed, penetrating the fourth interlayer dielectric layer 180. Subsequently, third metal lines 184 and 188 are formed on the fourth interlayer dielectric layer 180. The capacitor 172 can contact and be electrically connected to a cell contact window 152. The fourth via contact window 185 can be located between and contact the capacitor 172 and the third metal line 188. The third through-hole contact window 182 can be located between and in contact with the second metal wire 168 and the third metal wire 184.

[0075] In summary, the method of the present invention can simultaneously form a first metal line and a bit line, thereby improving the flexibility of semiconductor structure layout and wiring. The semiconductor structure manufactured by the method of the present invention allows for more flexible layout and wiring design because the first metal line can be electrically connected to the gate structure and its associated interconnect structures.

[0076] Although the invention has been described in detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.

[0077] Those skilled in the art will understand that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover the modifications and variations within the scope of the claims.

[0078] [Symbol Explanation] 100: Semiconductor Structure 101: Memory Unit 101T: Access Transistor 101C: Storage capacitor 110:Substrate 111: Isolation Structure 112: Dielectric layer 113: Semiconductor layer 114: Protective layer 120: First interlayer dielectric layer 125: First through-hole contact window 130: Conductive layer 134: First Metal Wire 136: First Metal Wire 140: Dielectric layer 145: Second through-hole contact window 150: Bit line spacer layer 152: Unit Contact Window 160: Second interlayer dielectric layer 164: Second metal wire 168: Second metal wire 170: Third interlayer dielectric layer 172: Capacitor 180: Fourth interlayer dielectric layer 182: Third through-hole contact window 184: Third Metal Wire 185: Fourth through-hole contact window 188: Third Metal Wire AR1: First active region AR2: Second active region BT1: Bitline Contact Window BT2: Bitline BT3: Bit line capacitor BL0: Bitline BL1: Bitline BL2: Bitline BL3: Bitline GR: Grounding doped region GT: Gate structure GT1: Gate Dielectric Layer GT2: Gate electrode GT3: Gate spacer layer MA: Memory Array R10: Memory area R20: Edge Array Region R30: Surrounding Area S / D: Source / Drain Region T: Transistor WL0: Character Line WL1: Character Line WL2: Character Line WL3: Character line.

Claims

1. A semiconductor structure, characterized in that, Include: The substrate includes the memory area and the peripheral area; Bit lines are located above and electrically connected to the first active region of the memory region of the substrate. Bit line capacitor, above and in contact with the bit line; A transistor is located above the peripheral region of the substrate; A first metal line is located above the transistor, wherein the top surface of the bit line is higher than the bottom surface of the first metal line, and the first metal line and the bit line are made of the same material; and A dielectric layer is located above and in contact with the first metal line, wherein the dielectric layer and the bit line capacitor are made of the same material.

2. The semiconductor structure according to claim 1, characterized in that, The top surface of the bit line is located between the top surface and the bottom surface of the first metal line.

3. The semiconductor structure according to claim 1, characterized in that, The top surface of the bit line capacitor is flush with the top surface of the dielectric layer.

4. The semiconductor structure according to claim 1, characterized in that, The bottom surface of the dielectric layer is located between the top and bottom surfaces of the bit line capacitor.

5. The semiconductor structure according to claim 1, characterized in that, Further includes: The second metal line is located above the dielectric layer; The first through-hole contact window is located between the first metal line and the source / drain region of the transistor; as well as The second through-hole contact window is located between the first metal wire and the second metal wire.

6. The semiconductor structure according to claim 5, characterized in that, The second through-hole contact window electrically connects the source / drain region of the transistor to the ground doped region of the substrate.

7. The semiconductor structure according to claim 1, characterized in that, It further includes an interlayer dielectric layer disposed along the sidewalls of the first metal line and the sidewalls of the dielectric layer.

8. The semiconductor structure according to claim 7, characterized in that, It further includes a second metal line disposed along the top surface of the dielectric layer and the interlayer dielectric layer.

9. The semiconductor structure according to claim 1, characterized in that, The first metal line is in contact with the top surface of the gate structure of the transistor.

10. The semiconductor structure according to claim 1, characterized in that, Further includes: Bit line spacer layer is disposed along the bit line and the bit line capacitance; Cell contact window, a second active region adjacent to the bit line spacer layer and electrically connected to the memory region of the substrate; as well as The capacitor is electrically connected to the unit's contact window.

11. A method for manufacturing a semiconductor structure, characterized in that, Include: Bit line contact windows and transistors are formed on the memory region and surrounding region of the substrate. A conductive layer is formed that spans the bit line contact window and the transistor; A dielectric layer is formed on the conductive layer; In the memory region, a spacer layer material is formed extending through a portion of the dielectric layer and a portion of the conductive layer. The conductive layer and the dielectric layer in the memory region are patterned to form bit lines and bit line capacitors, respectively. as well as A first interlayer dielectric layer is formed in the peripheral region, extending through the dielectric layer and the conductive layer, and the conductive layer in the peripheral region is patterned to form a first metal line.

12. The method according to claim 11, characterized in that, The top surface of the bit line is higher than the bottom surface of the first metal line.

13. The method according to claim 11, characterized in that, The top surface of the bit line is located between the top and bottom surfaces of the first metal line.

14. The method according to claim 11, characterized in that, The top surface of the bit line capacitor is flush with the top surface of the dielectric layer.

15. The method according to claim 11, characterized in that, The bottom surface of the dielectric layer is located between the top and bottom surfaces of the bit line capacitor.

16. The method according to claim 11, characterized in that, Further includes: A semiconductor layer is formed on the substrate, wherein the bit line contact window is formed to extend through the semiconductor layer; Etching is performed on a portion of the semiconductor layer and a portion of the bit line contact window in the memory region; A protective layer is formed on this portion of the semiconductor layer to cover the bit line contact window; as well as A portion of the semiconductor layer in the surrounding area is patterned to form the gate of the transistor.

17. The method according to claim 16, characterized in that, Further includes: A second interlayer dielectric layer is formed on the peripheral region of the substrate; and Before forming the conductive layer, the protective layer is removed to expose the bit line contact window.

18. The method according to claim 17, characterized in that, The portion of the conductive layer in the memory region has a top surface that is lower than the portion of the conductive layer in the peripheral region.

19. The method according to claim 11, characterized in that, It further includes forming a second metal line along the top surface of the dielectric layer and the first interlayer dielectric layer, wherein the second metal line is electrically connected to the first metal line.

20. The method according to claim 11, characterized in that, The process further includes forming a capacitor after the formation of the first interlayer dielectric layer, the capacitor being electrically connected to the active region in the memory region of the substrate.

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