1.5t otp memory and methods of making the same

Abstract

The application provides a 1.5T OTP memory and a preparation method thereof. Without increasing process steps, only the appearance of a gate structure mask plate is changed, the programming gate is transferred to an STI structure, and the two sides of a single programming gate are programmed respectively, so that higher density 1.5T programming is realized, the integration of the OTP is improved, miniaturization and high-density integration are realized. In addition, the anti-fuse structure of the OTP utilizes the electric field between the single-sided active area and the programming gate, so that the programming efficiency and stability are improved. Furthermore, the physical position of the anti-fuse is concentratedly distributed in the active recessed area, so that the area of the anti-fuse breakdown is more convergent and controllable.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology and relates to a 1.5T OTP memory and its preparation method. Background Technology

[0002] One-time programmable (OTP) memory is a type of non-volatile memory (NVM) and is generally used for storing encryption keys, code, and parameter correction. Common OTP memories use an anti-fuse logic architecture for programming. This involves using two conductors and a dielectric layer sandwiched between them to form an anti-fuse. The anti-fuse is non-conductive in the unprogrammed state. During programming, a high voltage is applied between the two conductors, causing the dielectric layer to break down and allowing current to flow, thus making the memory conductive.

[0003] like Figure 1 This diagram illustrates a cross-sectional structure of a 2T OTP memory in the prior art. Figure 2 The dashed box illustrates a top-view structural diagram of a 2×2T OTP memory array in the prior art. Figure 1 and Figure 2 It is known that the existing 2TOTP memory includes a semiconductor substrate 110, a select gate 210, a programming gate 220 and an active region 310. The antifuse formed by the programming gate 220 can only be programmed once, which restricts the miniaturization and high-density integration of OTP memory.

[0004] Therefore, it is necessary to provide a 1.5T OTP memory and its fabrication method. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a 1.5T OTP memory and its fabrication method, so as to solve the problem that it is difficult to achieve miniaturization and high-density integration of OTP memory in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a 1.5T OTP memory, the 1.5T OTP memory comprising:

[0007] A semiconductor substrate, the semiconductor substrate comprising an STI structure;

[0008] A gate structure located on the semiconductor substrate includes a select gate and a programming gate, wherein the programming gate is located on the STI structure and the edge of the programming gate is connected to the active region corresponding to the select gate through an active recess region.

[0009] Optionally, the programming gate and the active region have an overlapping area.

[0010] Optionally, the programming gate and the active region have a spacing region.

[0011] Optionally, the length of the active recess region is within 200 nm.

[0012] Optionally, in the vertical direction, the axis of symmetry of the programming gate coincides with the axis of symmetry of the STI structure, and the selection gate is symmetrically arranged along the axis of symmetry of the programming gate.

[0013] Optionally, a plurality of programming gates are connected to form at least one programming gate line, a plurality of select gates are connected to form at least two word lines, and the drain regions corresponding to the plurality of select gates are connected to form at least one bit line.

[0014] This invention also provides a method for fabricating a 1.5T OTP memory, comprising the following steps:

[0015] Provide semiconductor substrates;

[0016] An STI structure is formed in the semiconductor substrate;

[0017] A gate structure is formed on the semiconductor substrate. The gate structure includes a select gate and a programming gate, wherein the programming gate is located on the STI structure, and the edge of the programming gate is connected to the active region corresponding to the select gate through an active recess region.

[0018] Optionally, when the programming gate is patterned, the edge of the programming gate overlaps with the active region; or the edge of the programming gate is spaced apart from the active region.

[0019] Optionally, when forming the gate structure, the gate dielectric layer includes a silicon oxide layer, a silicon oxynitride layer, or a hafnium oxide layer.

[0020] Optionally, when forming the gate structure, the gate dielectric layer is prepared by thermal oxidation.

[0021] As described above, the 1.5T OTP memory and its fabrication method of the present invention, without increasing the process steps, only need to change the morphology of the gate structure mask to transfer the programming gate onto the STI structure, and can program both sides of a single programming gate separately, thereby achieving higher density 1.5T programming, improving the integration of OTP, and realizing miniaturized high-density integration; in addition, the antifuse structure of the OTP utilizes the electric field between the active region on one side and the programming gate, which can improve programming efficiency and stability; furthermore, the physical position of the antifuse can be concentrated in the active recess region, thereby making the antifuse breakdown area more convergent and controllable. Attached Figure Description

[0022] Figure 1The diagram shows a cross-sectional structure of a 2T OTP memory in the prior art.

[0023] Figure 2 The diagram shown is a top view of a 2T OTP memory array in the prior art.

[0024] Figure 3 The diagram shows the fabrication process flow of the 1.5T OTP memory in an embodiment of the present invention.

[0025] Figure 4 The diagram shown is a cross-sectional structural schematic of a 1.5T OTP memory in an embodiment of the present invention.

[0026] Figure 5 Displayed as Figure 4 A magnified view of a portion of region A in the middle.

[0027] Figure 6 The image shown is a magnified view of a portion of the spaced area in an embodiment of the present invention.

[0028] Figure 7 The diagram shown is a top view of the 1.5T OTP memory array in an embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures

[0030] 110 and 100 semiconductor substrates

[0031] 210, 201 Select gate

[0032] 220, 202 Programmable Gates

[0033] 310, 300 active areas

[0034] 400 STI structure Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0038] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] See Figure 4 This embodiment provides a 1.5T OTP memory, which includes:

[0040] Semiconductor substrate 100, the semiconductor substrate 100 including STI structure 400;

[0041] A gate structure located on the semiconductor substrate 100 includes a select gate 201 and a programming gate 202, wherein the programming gate 202 is located on the STI structure 400, and the edge of the programming gate 202 is connected to the active region 300 corresponding to the select gate 201 through an active recessed region.

[0042] The semiconductor substrate 100 defines a plurality of active regions 300 (AA) through the STI structure 400. The semiconductor substrate 100 may be a silicon substrate or other suitable substrate, such as an N-type doped silicon substrate or a P-type doped silicon substrate. N-type doped or P-type doped well regions may also be selectively formed within the semiconductor substrate 100.

[0043] This embodiment uses a transistor with an N-channel formed on its surface and a P-type doped silicon substrate 100 as an example. It can be understood that a P-channel transistor can also be obtained by interchangeing the N-type and P-type substrates.

[0044] The gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer. The gate dielectric layer may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a hafnium oxide layer. The gate conductive layer may include, for example, a polysilicon gate conductive layer or a metal gate conductive layer. The specific structure, material, and fabrication of the gate structure are not limited here.

[0045] Regarding the gate structure, see [link / reference]. Figure 4 and Figure 5 ,in Figure 5 Indicated as Figure 4 A partial enlarged view of region A. In this embodiment, the gate structure includes a select gate 201 and a programming gate 202 located on the STI structure 400, and the edge of the programming gate 202 passes through an active recessed region (AA divot), i.e. Figure 5 The ΔX region in the selection gate 201 is connected to the active region 300.

[0046] It should be noted that the active recessed region (AA divot) is a defect existing in the prior art when fabricating the gate structure. That is, as in this embodiment, the ΔX region where the active region 300 contacts the STI structure 400 has a gate dielectric layer thickness that is smaller than that in other regions. Therefore, the antifuse structure of the OTP in this embodiment can utilize the electric field between the active region 300 on one side and the programming gate 202 to improve programming efficiency and stability. Furthermore, the physical location of the antifuse can be concentrated in the active recessed region, thereby making the antifuse breakdown area more convergent and controllable.

[0047] In another embodiment, see Figure 6 The programming gate 202 and the active region 300 can also have a morphological distribution with spaced regions, that is, the active recessed region can be as follows: Figure 6 The ΔX region in the OTP allows the antifuse structure to utilize the electric field between the active region 300 on one side and the programming gate 202, thereby improving programming efficiency and stability. Furthermore, it allows the physical location of the antifuse to be concentrated in the active recessed region, thus making the antifuse breakdown area more convergent and controllable.

[0048] Furthermore, regarding the length of the active recessed region, as... Figure 5 and Figure 6 The value of ΔX can be controlled within 200nm, such as 0nm, 50nm, 100nm, 150nm, 200nm, etc. The value of ΔX is not excessively restricted here; it is specifically defined according to the range of the active recess region.

[0049] The specific structure, material, and fabrication of the STI structure 400 are not limited here, and may include, for example, an STI structure 400 filled with silicon oxide. In this embodiment, the programming gate 202 is transferred to the STI structure 400, so that one side of a single programming gate 202 can be programmed, thereby enabling the programming of a 1.5T OTP memory, which includes one select gate 201 and half of the programming gate 202. Since the programming gate 202 is disposed on the STI structure 400, the integration density of the OTP can be improved, achieving miniaturized high-density integration.

[0050] Furthermore, in this embodiment, as Figures 4-6 In the vertical direction, the axis of symmetry of the programming gate 202 is set to coincide with the axis of symmetry of the STI structure 400, and the selection gate 201 is symmetrically arranged along the axis of symmetry of the programming gate 202, thereby further reducing the device size and enabling programming on both sides of a single programming gate 202, thereby achieving higher density 1.5T programming and realizing the miniaturization and high-density integration of OTP memory.

[0051] like Figure 7 This diagram illustrates a top view of the 1.5T OTP memory in this embodiment, in which at least one programming gate line (PL) is formed by connecting multiple programming gates 202, at least two word lines (WL) are formed by connecting multiple select gates 201, and at least one bit line (BL) is formed by connecting the drain regions corresponding to the multiple select gates 201.

[0052] The programming gate line located on the STI structure 400, together with the two adjacent word lines and the bit lines, constitutes the symmetrically arranged 1.5T OTP memory, thereby enabling both sides of a single programming gate 202 to be programmed separately.

[0053] Of course, in another embodiment, the 1.5T OTP memory can also be an asymmetric structure, as needed, such as combining... Figure 5 and Figure 6 The 1.5T OTP memory is configured in the structure to expand its application range.

[0054] See Figures 3-7 This embodiment also provides a method for preparing a 1.5T OTP memory, wherein the 1.5T OTP memory can be prepared using the following process, but is not limited thereto.

[0055] In this embodiment, the 1.5T OTP memory is directly prepared using the following method. Therefore, in the following description of the preparation method of the 1.5T OTP memory, the specific structure, material, and beneficial effects of the prepared 1.5T OTP memory can be found in the above description of the 1.5T OTP memory.

[0056] In this embodiment, the method for fabricating the 1.5T OTP memory includes the following steps:

[0057] S1: Provides semiconductor substrate 100;

[0058] S2: An STI structure 400 is formed in the semiconductor substrate 100;

[0059] S3: A gate structure is formed on the semiconductor substrate 100. The gate structure includes a select gate 201 and a programming gate 202. The programming gate 202 is located on the STI structure 400, and the edge of the programming gate 202 is connected to the active region 300 corresponding to the select gate 201 through an active recessed region.

[0060] In this embodiment, without adding process steps, the programming gate 202 can be transferred to the STI structure 400 simply by changing the morphology of the gate structure mask. Furthermore, it allows programming on both sides of a single programming gate 202, thereby achieving higher density 1.5T programming, improving the integration of OTP, and realizing miniaturized high-density integration.

[0061] Furthermore, the antifuse structure of the OTP utilizes the electric field between the active region 300 on one side and the programming gate 202, which can improve programming efficiency and stability; moreover, it can make the physical location of the antifuse concentrated in the active recessed region, thereby making the antifuse breakdown area more convergent and controllable.

[0062] Specifically, during the patterning of the programming gate 202, the edge of the programming gate 202 may overlap with the active region 300, or the edge of the programming gate 202 may have a gap between it and the active region 300. For a description of the overlapping and gap regions, please refer to the above description of the ΔX region; it will not be repeated here.

[0063] In forming the gate structure, the gate dielectric layer can be prepared by thermal oxidation, such as by preparing a silicon oxide layer, a silicon oxynitride layer, or a hafnium oxide layer.

[0064] In summary, the 1.5T OTP memory and its fabrication method of the present invention, without increasing the process steps, only require changing the morphology of the gate structure mask to transfer the programming gate onto the STI structure. Furthermore, it allows for programming on both sides of a single programming gate, thereby achieving higher-density 1.5T programming, improving the integration density of the OTP, and realizing miniaturized high-density integration. In addition, the antifuse structure of the OTP utilizes the electric field between the active region on one side and the programming gate, which can improve programming efficiency and stability. Moreover, the physical location of the antifuse can be concentrated in the active recess region, thereby making the antifuse breakdown area more convergent and controllable.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A 1.5T OTP memory, characterized in that, The 1.5T OTP memory includes: A semiconductor substrate, the semiconductor substrate comprising an STI structure; A gate structure located on the semiconductor substrate includes a select gate and a programming gate, wherein the programming gate is located on the STI structure and the edge of the programming gate is connected to the active region corresponding to the select gate through an active recess region.

2. The 1.5T OTP memory according to claim 1, characterized in that: The programming gate and the active region have an overlapping area.

3. The 1.5T OTP memory according to claim 1, characterized in that: The programming gate and the active region are separated by a gap.

4. The 1.5T OTP memory according to claim 1, characterized in that: The length of the active recess region is within 200 nm.

5. The 1.5T OTP memory according to claim 1, characterized in that: In the vertical direction, the axis of symmetry of the programming gate coincides with the axis of symmetry of the STI structure, and the selection gate is symmetrically arranged along the axis of symmetry of the programming gate.

6. The 1.5T OTP memory according to any one of claims 1 to 5, characterized in that: The plurality of programming gates are connected to form at least one programming gate line, the plurality of select gates are connected to form at least two word lines, and the drain regions corresponding to the plurality of select gates are connected to form at least one bit line.

7. A method for fabricating a 1.5T OTP memory, characterized in that, Includes the following steps: Provide semiconductor substrates; An STI structure is formed in the semiconductor substrate; A gate structure is formed on the semiconductor substrate. The gate structure includes a select gate and a programming gate, wherein the programming gate is located on the STI structure, and the edge of the programming gate is connected to the active region corresponding to the select gate through an active recess region.

8. The method for fabricating a 1.5T OTP memory according to claim 7, characterized in that: When the programming gate is patterned, the edge of the programming gate overlaps with the active region; or the edge of the programming gate is spaced apart from the active region.

9. The method for fabricating a 1.5T OTP memory according to claim 7, characterized in that: When forming the gate structure, the gate dielectric layer includes a silicon oxide layer, a silicon oxynitride layer, or a hafnium oxide layer.

10. The method for fabricating a 1.5T OTP memory according to claim 7, characterized in that: When forming the gate structure, the gate dielectric layer is prepared by thermal oxidation.

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