Semiconductor device and method of manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device includes a gate structure disposed in a chip region and including conductive layers and first insulating layers alternately stacked, a dummy structure disposed in a chip protection region surrounding the chip region and including second insulating layers and third insulating layers alternately stacked, and a chip protection structure in the chip protection region including a polysilicon layer disposed in the dummy structure and a wire surrounding the polysilicon layer and extending through the dummy structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing a semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices for forming memory cells in a single layer on a substrate has reached its limit, three-dimensional semiconductor devices for stacking memory cells on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] In one embodiment, a semiconductor device may include: a gate structure disposed in a chip region and including alternating layers of conductive layers and a first insulating layer; a dummy structure disposed in a chip protection region surrounding the chip region and including alternating layers of a second insulating layer and a third insulating layer; and a chip protection structure located in the chip protection region, including a polysilicon layer disposed in the dummy structure and wires surrounding the polysilicon layer and extending through the dummy structure.

[0004] In one embodiment, a semiconductor device may include: a dummy structure including alternating layers of a first insulating layer and a second insulating layer; a stop layer including a first sub-stop layer located in the dummy structure and a second sub-stop layer surrounding the first sub-stop layer; a buffer layer surrounding the stop layer; and a conductor surrounding the buffer layer and having a closed curve shape extending through the dummy structure.

[0005] In one embodiment, a method of manufacturing a semiconductor device may include the steps of: forming a stack in a chip region and a chip protection region surrounding the chip region, the stack including alternating layers of first and second materials; forming a trench in the chip protection region of the stack, the trench surrounding the chip region; forming a buffer layer in the trench, the buffer layer including voids; and forming a slit in the buffer layer, the slit connecting to the voids to define an air gap within the voids and the slit, wherein the air gap is configured to prevent crack propagation from the chip region toward the chip protection region.

[0006] In one embodiment, a method of manufacturing a semiconductor device may include the steps of: forming a stack in a chip region and a chip protection region surrounding the chip region, the stack including alternating layers of first and second materials; forming a trench in the chip protection region of the stack, the trench surrounding the chip region; forming a buffer layer in the trench, the buffer layer including voids; forming a slit in the buffer layer, the slit connecting to the voids; and forming a stop layer in the voids and the slits, wherein the stop layer is configured to prevent crack propagation from the chip region toward the chip protection region. Attached Figure Description

[0007] The above and other objects, features and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings:

[0008] Figure 1A and Figure 1B This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0009] Figures 2A to 2C This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0010] Figures 3A to 3C This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0011] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0012] Figure 5 This is a cross-sectional view showing the structure of a semiconductor device including a chip region and a chip protection region according to an embodiment of the present disclosure.

[0013] Figure 6 This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0014] Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B ,as well as Figure 7C , Figure 8C , Figure 9C , Figure 10C and Figure 11C This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0015] Figure 12A , Figure 13A and Figure 14A as well as Figure 12B , Figure 13B and Figure 14B This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0016] Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A as well as Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B and Figure 25B This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0017] Figures 26A to 26D This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0018] Figure 27 This is a configuration diagram of a semiconductor device according to one embodiment of the present disclosure.

[0019] Figure 28 This is a configuration diagram of a semiconductor device according to one embodiment of the present disclosure. Detailed Implementation

[0020] Various embodiments relate to a semiconductor device having a stable structure and improved properties, as well as a method of manufacturing the semiconductor device.

[0021] In the following description, various embodiments of the present disclosure are illustrated with reference to the accompanying drawings. The advantages and features of the present disclosure, as well as methods of implementing them, will become apparent from the embodiments described in detail below with reference to the accompanying drawings. However, this is not intended to limit the present disclosure to specific embodiments.

[0022] This disclosure may be implemented in various different forms, and is not limited to one implementation, and should be understood to include various modifications, equivalents and / or alternatives to the implementation of this disclosure.

[0023] Furthermore, when adding reference numerals to components in each figure, it should be noted that the same components are represented by the same numbers, even if they are shown in other figures.

[0024] In this specification, unless otherwise stated, the singular form includes the plural form. The terms “comprising” and / or “including” as used in this specification indicate the presence of components, steps, operations, and / or elements, but do not exclude the presence or addition of one or more other components, steps, and / or elements.

[0025] In the following description, by stacking memory cells in three dimensions, embodiments of this disclosure provide the ability to increase the integration density of semiconductor devices. Embodiments of this disclosure also provide a semiconductor device with a stable structure and improved reliability.

[0026] Hereinafter, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0027] Figure 1A and Figure 1B This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0028] Reference Figure 1A The semiconductor device may include a wafer (WF), and the wafer (WF) may include chips and scribing regions (SCRs). Chips may be arranged along a first direction I and a second direction II intersecting the first direction I. SCRs may be located between chips and may surround chips. SCRs may be portions cut by a dicing process used to separate chips from each other.

[0029] A chip chip may include a chip region CHR and a chip protection region CGR surrounding the chip region CHR. The chip region CHR is the area in which elements operating within the chip chip are formed. The chip protection region CGR is the area used to protect the elements and may be an area where no said elements are formed or where dummy elements are formed. When a dicing process is performed, the chip region CHR may be protected by the chip protection region CGR.

[0030] Reference Figure 1B The chip (CHIP) may include multiple memory planes (PLs) arranged along a first direction (I) and a second direction (II). For example, the memory planes (PLs) may be arranged in a matrix within the chip region (CHR). The memory planes (PLs) may include multiple memory blocks (MBs), and the memory blocks (MBs) may be units of erase operations. For example, the memory planes (PLs) may include two or more memory blocks (MBs) arranged along the first direction (I).

[0031] A chip protection structure (CG) can be located at the edge of the chip. The inner region of the chip protection structure (CG) can be the chip region (CHR), while the outer region of the chip protection structure (CG) can be the chip protection region (CGR). The chip protection structure (CG) can extend along the edge of the chip and can have a closed curve shape. For example, the chip protection structure (CG) can have a rectangular shape. Because the chip protection structure (CG) has a shape surrounding the chip region (CHR), using the chip protection structure (CG) can prevent crack propagation and detect cracks.

[0032] Cracks can occur during the manufacturing process of semiconductor devices. Stress can arise due to voids, layer shrinkage, etc., caused during manufacturing, and this stress can lead to defects such as poor oxidation and cracks. Cracks can occur at the interface between the interlayer insulating layer and the laminate, and the cracks can propagate along the interface in one direction. As an example, cracks are likely to occur and propagate at the interface between the interlayer insulating layer and the laminate, located at the boundary A between memory blocks MB or the boundary B between memory planes PL. Cracks can propagate from the inside of a chip to the outside of the chip, or between adjacent chips. Therefore, by using a chip protection structure CG to prevent crack propagation, the disclosed embodiments can reduce crack propagation between chips.

[0033] Figures 2A to 2C This is a diagram illustrating the structure of a semiconductor device according to one embodiment. Figure 2A and Figure 2B It is a floor plan, and Figure 2C It is along Figure 2A A cross-sectional view taken by line A-A'. In the following text, content overlapping with the previously described content may be omitted.

[0034] Reference Figure 2A The semiconductor device may include a dummy structure DST and a chip protection structure CG. The dummy structure DST may be located within the chip protection region CGR. The dummy structure DST may include alternating layers of a first insulating layer 21 and a second insulating layer 22 (e.g., ...). Figure 2C (As shown). The first insulating layer 21 may each comprise a material that has high etch selectivity relative to the second insulating layer 22. As an example, the first insulating layer 21 may each comprise a nitride, and the second insulating layer 22 may each comprise an oxide.

[0035] The chip protection structure CG can be located within the chip protection region CGR. As an example, the chip protection structure CG can be located at the boundary between the chip region CHR and the chip protection region CGR. The chip protection structure CG can have a linear shape or a closed curve shape such as a quadrilateral. In a plane defined by a first direction I and a second direction II intersecting the first direction I, the chip protection structure CG can extend through the dummy structure DST in the first direction I and / or the second direction II. The chip protection structure CG can include a first portion CGA having a first width W1 and a second portion CGB having a second width W2. The first width W1 and the second width W2 can be different from each other, and the first width W1 can be greater than the second width W2. The chip protection structure CG can include alternating first portions CGA and second portions CGB. The chip protection structure CG can include sidewalls with irregular shapes.

[0036] Reference Figure 2B and Figure 2C The semiconductor device may include a dummy structure (DST) and a chip protection structure (CG), and may also include wiring (ML) and an interlayer insulating layer (IL). The chip protection structure (CG) may include conductors 24 and a stop layer 25. The stop layer 25 may be located inside the conductors 24. In a plan view, the stop layer 25 may be located in a portion of the conductors 24. As an example, the stop layer 25 may be located in a region where cracking is frequent (or most likely). The stop layer 25 may be located at the boundary between memory blocks or the boundary between memory planes, and may not be located in other regions. In a plan view, the stop layer 25 may be located throughout the entire region of the conductors 24. For example, the stop layer 25 may be positioned along the edge of the chip.

[0037] The wire 24 can be part of a crack detection circuit and can be used as a detection line for detecting cracks. Furthermore, the wire 24 can be used to prevent crack propagation. The wire 24 can comprise a conductive material having a higher density and / or elastic modulus (Young's modulus) compared to silicon oxide. As an example, the wire 24 can comprise a metal such as tungsten (W), copper (Cu), or aluminum (Al). The stop layer 25 is used to prevent crack propagation and can comprise a material having a higher density and / or elastic modulus (Young's modulus) compared to silicon oxide. As an example, the stop layer 25 can comprise silicon nitride, polycrystalline silicon, etc.

[0038] In the plan view, conductor 24 may extend through the dummy structure DST along the first direction I and / or the second direction II, and stop layer 25 may extend through conductor 24 along the first direction I or the second direction II.

[0039] In cross-section, conductor 24 may extend along a third direction III through the dummy structure DST. As an example, conductor 24 may penetrate the dummy structure DST and may be electrically connected to wiring ML located below the dummy structure DST. Conductor 24 may have a bow-shaped cross-section. As an example, the width of the lower surface of conductor 24 may be less than the width of its upper surface, and may have its maximum width at a bowing level BL between the upper and lower surfaces. In cross-section, stop layer 25 may be located only at a portion of the levels of conductor 24. The upper surface of stop layer 25 may be positioned lower than the upper surface of conductor 24. As an example, stop layer 25 may be positioned from the lower surface of conductor 24 to the bowing level BL. Alternatively, stop layer 25 may be positioned from the lower surface of conductor 24 to a level above or below the bowing level BL but lower than the upper surface of conductor 24. Stop layer 25 may comprise polysilicon, silicon nitride, etc.

[0040] The conductor 24 may surround the upper surface and sidewalls of the stop layer 25. The conductor 24 may include a first portion 24A located on the upper part of the stop layer 25 and a second portion 24B surrounding the sidewalls of the stop layer 25. The second portion 24B may protrude from the lower surface of the first portion 24A and may extend along the sidewalls of the stop layer 25. Because the conductor 24 surrounds the upper surface and sidewalls of the stop layer 25, the stop layer 25 can be separated from the dummy structure DST.

[0041] Based on the above structure, since the chip protection structure CG includes a stop layer 25, it can be used to prevent crack propagation. Because the chip protection structure CG includes a conductor 24 with a closed curve shape, it can be used as a detection line in a crack detection circuit.

[0042] Figures 3A to 3C This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 3A It is a floor plan, and Figure 3B and Figure 3C It is along Figure 3A The cross-sectional view taken by line B-B'. In the following text, content overlapping with the previously described content may be omitted.

[0043] Reference Figures 3A to 3C The semiconductor device may include a dummy structure DST and a chip protection structure CG. The dummy structure DST may include alternating layers of a first insulating layer 31 and a second insulating layer 32. In a plan view, the chip protection structure CG may extend through the dummy structure DST along a first direction I. In a cross-section, the chip protection structure CG may extend through the dummy structure DST along a third direction III and may be electrically connected to wiring ML.

[0044] The chip protection structure CG may include a conductor 34 and a stop layer 35 located within the conductor 34. In a plan view, the stop layer 35 may include a line portion 35L and at least one protruding portion 35P. As an example, the stop layer 35 may have irregularly shaped sidewalls. The line portion 35L may extend through the conductor 34 along a first direction I. The protruding portion 35P may protrude from the line portion 35L along a second direction II. The protruding portion 35P may be positioned corresponding to a first portion CGA of the chip protection structure CG. The chip protection structure CG may also include a buffer layer 36 surrounding the stop layer 35.

[0045] Stop layer 35 may include a first stop layer 35A (e.g., a first sub-stop layer) and a second stop layer 35B (e.g., a second sub-stop layer). The second stop layer 35B may surround the first stop layer 35A, and a buffer layer 36 may surround the second stop layer 35B. The first stop layer 35A may include a semiconductor layer or a conductive layer, and may include a material having a higher density and / or elastic modulus (Young's modulus) than the second stop layer 35B and the buffer layer 36. The second stop layer 35B and the buffer layer 36 may each include a dielectric material, and the second stop layer 35B may include a material having a higher density and / or elastic modulus (Young's modulus) than the buffer layer 36. As an example, the first stop layer 35A may include polysilicon, the second stop layer 35B may include an oxide or a nitride, and the buffer layer 36 may include an oxide. For reference, when both the second stop layer 35B and the buffer layer 36 include oxides, the interface between the second stop layer 35B and the buffer layer 36 may not be identifiable.

[0046] In cross-section, the first stop layer 35A may include a first portion 35AA and a second portion 35AB. The first portion 35AA may be a portion that fills voids created during the manufacturing process and may include a curved surface. The second portion 35AB may be a portion that fills slits formed during the manufacturing process and may have a smaller width than the first portion 35AA.

[0047] The upper surfaces of the first stop layer 35A, the second stop layer 35B, and the buffer layer 36 can be located at substantially the same height or at different heights. Figure 3B In the example, the upper surfaces of the first stop layer 35A, the second stop layer 35B, and the buffer layer 36 can be at substantially the same height. Figure 3CIn the example, the upper surfaces of the first stop layer 35A, the second stop layer 35B, and the buffer layer 36 may be located at different heights. The height difference between the upper surfaces may be due to differences in etch rates. The upper surfaces of the second stop layer 35B and the buffer layer 36 may be located at a lower height than the upper surface of the first stop layer 35A. As an example, a first portion 35AA of the first stop layer 35A may protrude from the upper surfaces of the second stop layer 35B and the buffer layer 36. The upper surfaces of the second stop layer 35B and the buffer layer 36 may be located at substantially the same height or at different heights.

[0048] According to the above structure, the chip protection structure CG may include a conductor 34, a stop layer 35, and a buffer layer 36, and the stop layer 35 may have a multilayer structure. By combining material layers having various densities and / or elastic moduli to form the stop layer 35, the disclosed embodiments provide the ability to prevent crack propagation in semiconductor devices.

[0049] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to one embodiment. In the following text, content overlapping with the previously described content may be omitted.

[0050] Reference Figure 4 The semiconductor device may include a wafer (WF), and the wafer (WF) may include a chip and a scribing region (SCR). The chip may include components located as shown in the image. Figure 1A The memory plane PL in the chip region CHR shown, and may include memory located in, for example Figure 1A The chip protection structure CG is shown in the chip protection region CGR. As an example, the chip protection structure CG can be located at the boundary between the chip region CHR and the chip protection region CGR.

[0051] During the manufacturing process of semiconductor devices, cracks may occur due to processes such as oxidation, and cracks appearing in the chip region CHR can propagate towards the chip protection region CGR. Cracks can propagate from the chip protection region CGR to the scribe line region SCR, and can also propagate to adjacent chip edges. As an example, cracks may appear at boundary A between memory blocks MB or boundary B between adjacent memory planes PL. Cracks can be induced at the interface between the laminates and the interlayer insulating layer at boundaries (regions) A and / or B, and the cracks can propagate along the interface in one direction.

[0052] Therefore, to prevent crack propagation, a chip protection structure CG including a stop layer can be provided (e.g., positioned) at the edge of the chip. The stop layer may be located only in a portion of the edge of the chip. As an example, the stop layer may be located only in a portion of the edge of the chip extending along the second direction II from region A and / or region B. In an alternative embodiment, the stop layer may be located entirely at the edge of the chip.

[0053] Based on the above structure, even if cracks occur during manufacturing, their propagation can be prevented by the chip protection structure CG. Therefore, cracks can prevent propagation to adjacent chips.

[0054] Figure 5 This is a cross-sectional view illustrating the structure of a semiconductor device including a chip region CHR and a chip protection region CGR according to one embodiment of the present disclosure. In the following, content overlapping with the previously described material may be omitted.

[0055] Reference Figure 5 The semiconductor device may include a substrate 50, a gate structure GST, a channel structure CH, a source structure S, a slit structure SLS, a dummy structure DST, a first transistor TRA, a second transistor TRB, a chip protection structure CG, first interlayer insulating layers IL1A and IL1B, second interlayer insulating layers IL2A and IL2B, first interconnect structures IC1A and IC1B, and a second interconnect structure IC2.

[0056] The second transistor TRB can be located in the chip region CHR of substrate 50. The second transistor TRB can belong to the peripheral circuitry used to drive the memory cell array. The peripheral circuitry can include page buffers, row decoders, logic circuits, input / output circuits, etc. The first interconnect structure IC1B can include vias, wiring, etc., and can be located in the first interlayer insulating layer IL1B. The first interconnect structure IC1B can be connected to the second transistor TRB.

[0057] In the chip region CHR, the source structure S can be located on the first interlayer insulating layer IL1B. The source structure S can be composed of a single layer or multiple layers. The source structure S can include conductive materials such as polysilicon or metal.

[0058] The gate structure GST can be located on the source structure S. The gate structure GST may include alternating layers of conductive layers 51 and insulating layers 52. The conductive layers 51 may be gate lines such as drain select lines, source select lines, and word lines. Each conductive layer 51 may comprise a conductive material such as polysilicon or metal. The insulating layers 52 are used to insulate the stacked conductive layers 51 from each other and may each comprise an insulating material such as oxide, nitride, or air gap.

[0059] The channel structure CH can extend through the gate structure GST into the source structure S. The channel structure CH may include a channel layer 55, a memory layer 56, and an insulating core 57. The channel layer 55 can be connected to the source structure S. The memory layer 56 may include at least one of a tunneling layer, a data storage layer, and a barrier layer. The data storage layer may include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance material, etc.

[0060] A source contact plug SCT may extend through the gate structure GST into the source structure S. The source contact plug SCT may be electrically connected to the source structure S. An insulating spacer SP may surround the sidewalls of the source contact plug SCT. A slit structure SLS may extend through the gate structure GST. As an example, the slit structure SLS may have a depth sufficient to penetrate the conductive layer 51 corresponding to the drain select line. The slit structure SLS may comprise an insulating material such as an oxide or nitride.

[0061] The second interlayer insulating layer IL2B can be located on the gate structure GST, and the second interconnect structure IC2 can be located within the second interlayer insulating layer IL2B. The second interconnect structure IC2 can be connected to the channel structure CH, the gate structure GST, etc., and can include vias, wiring, etc.

[0062] The first transistor TRA can be located in the chip protection region CGR of the substrate 50. The first transistor TRA can belong to the crack detection circuit. The first interconnect structure IC1A can include vias, wiring, etc., and can be located in the first interlayer insulating layer IL1A. The first interconnect structure IC1A can be connected to the first transistor TRA.

[0063] In the chip protection region (CGR), the dummy structure DST can be located on the first interlayer insulating layer IL1A. The dummy structure DST can be located at a height corresponding to the gate structure GST. The dummy structure DST may include alternating layers of a first insulating layer 53 and a second insulating layer 54. The second insulating layer 54 can be connected as a single layer to the insulating layer 52. The second interlayer insulating layer IL2A can be located on the dummy structure DST.

[0064] The chip protection structure CG can extend through the dummy structure DST and can be connected to the first interconnect structure IC1A. The chip protection structure CG may include a conductor 59 and a stop layer 58 located within the conductor 59. The stop layer 58 may include a semiconductor material, a conductive material, a dielectric material, etc. The chip protection structure CG, the first interconnect structure IC1A connected to the chip protection structure CG, and the first transistor TRA can be part of a crack detection circuit. Because chip cracks primarily occur on the outside of the chip, the chip protection structure CG can be formed as a closed-loop circuit extending along the outside of the chip. Current can be applied to the closed-loop circuit, and cracks can be detected based on whether current flows through the closed-loop circuit.

[0065] According to the above structure, by positioning the peripheral circuitry below the memory cell array, the disclosed embodiment can improve the integration density of the semiconductor device. A crack detection circuit including a chip protection structure CG can be used to detect cracks, and the chip protection structure CG can be used to prevent crack propagation.

[0066] Figure 6 This is a diagram illustrating the structure of a semiconductor device according to one embodiment. In the following text, content overlapping with the previously described content may be omitted.

[0067] Reference Figure 6 The semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a bonding structure BS located between the first semiconductor structure S1 and the second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 may be formed by separate processes and may be electrically connected to each other through the bonding structure BS. As an example, the first semiconductor structure S1 may include peripheral circuitry and crack detection circuitry, while the second semiconductor structure S2 may include a memory cell array.

[0068] The first semiconductor structure S1 may include a chip region CHR and a chip protection region CGR, and may include a substrate 60, a first transistor TRA, a second transistor TRB, first interconnect structures IC1A and IC1B, and first interlayer insulating layers IL1A and IL1B.

[0069] The second transistor TRB can be located in the chip region CHR of the substrate 60. The second transistor TRB can belong to the peripheral circuitry used to drive the memory cell array. The first interconnect structure IC1B can include vias, wiring, etc., and can be located in the first interlayer insulating layer IL1B. The first interconnect structure IC1B can be connected to the second transistor TRB.

[0070] The first transistor TRA can be located in the chip protection region CGR of the substrate 60. The first transistor TRA can be part of a crack detection circuit. The first interconnect structure IC1A can include vias, wiring, etc., and can be located in the first interlayer insulating layer IL1A. The first interconnect structure IC1A can be connected to the first transistor TRA. The first transistor TRA and the first interconnect structure IC1B connected to the first transistor TRA can be part of a crack detection circuit.

[0071] The second semiconductor structure S2 may include a source structure S, a gate structure GST, a dummy structure DST, a chip protection structure CG, second interconnect structures IC2A and IC2B, second interlayer insulating layers IL2A and IL2B, and a third interlayer insulating layer IL3.

[0072] The source structure S, gate structure GST, and channel structure CH can be located in the chip region CHR. The source structure S can be located above or below the gate structure GST. The source structure S can include a conductive material such as polysilicon or metal. The gate structure GST can include alternating layers of conductive layer 61 and insulating layer 62. The conductive layer 61 can be a gate line such as a source select line, drain select line, and word line. The channel structure CH can extend through the gate structure GST and can be connected to the source structure S. The channel structure CH can include a channel layer 65, a memory layer 66, and an insulating core 67.

[0073] The second interconnect structure IC2B can be located in the second interlayer insulating layer IL2B, and can include vias, wiring, etc. The second interconnect structure IC2B can be connected to the channel structure CH, the gate structure GST, etc.

[0074] The dummy structure DST and the chip protection structure CG can be located within the chip protection region CGR. The dummy structure DST can be located at a height corresponding to the gate structure GST. The dummy structure DST may include alternating layers of a first insulating layer 63 and a second insulating layer 64. The second insulating layer 64 can be connected as a single layer to the insulating layer 62. The second interlayer insulating layer IL2A can be located below the dummy structure DST. The third interlayer insulating layer IL3 can be located above the dummy structure DST.

[0075] The chip protection structure CG can extend through the dummy structure DST and can be connected to the second interconnect structure IC2A. The chip protection structure CG may include a conductor 69 and a stop layer 68 located in the conductor 69. The stop layer 68 may include a semiconductor material, a conductive material, a dielectric material, etc. The chip protection structure CG and the second interconnect structure IC2A connected to the chip protection structure CG may be part of a crack detection circuit.

[0076] The bonding structure BS may include a first bonding layer BL1, a second bonding layer BL2, a first bonding pad BP1, and a second bonding pad BP2. The first bonding layer BL1 and the second bonding layer BL2 may be in contact with each other. The first bonding pad BP1 and the second bonding pad BP2 may each include silicon carbide (SiCN), tetraethyl orthosilicate (TEOS), etc. The first bonding pad BP1 may be electrically connected to the first interconnect structures IC1A and IC1B. The second bonding pad BP2 may be electrically connected to the second interconnect structures IC2A and IC2B. The memory cell array and peripheral circuitry can be electrically connected to each other through the first bonding pad BP1 and the second bonding pad BP2.

[0077] According to the above structure, the chip protection structure CG and the first transistor TRA can be connected to each other through the bonding structure BS. A crack detection circuit including the chip protection structure CG can be used to detect cracks, and the chip protection structure CG can be used to prevent crack propagation.

[0078] Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B ,as well as Figure 7C , Figure 8C , Figure 9C , Figure 10C and Figure 11C This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A yes Figure 7C , Figure 8C , Figure 9C , Figure 10C and Figure 11C Plan view at the first elevation LV1 Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B yes Figure 7C , Figure 8C , Figure 9C , Figure 10C and Figure 11C Plan view at the second elevation LV2.

[0079] Reference Figures 7A to 7CA laminate ST comprising alternating layers of first material layers 71 and second material layers 72 can be formed. Each of the first material layers 71 may comprise a material with high etch selectivity relative to the second material layer 72. As an example, each of the first material layers 71 may comprise a nitride, and each of the second material layers 72 may comprise an oxide.

[0080] Subsequently, a groove T can be formed in the laminate ST. In a plan view, the groove T can extend through the laminate ST along a first direction I and / or a second direction II. For example, the groove T can have a closed curve shape. The groove T can include a first portion TA having a first width W1A and a second portion TB having a second width W1B. The first width W1A and the second width W1B can be substantially the same as or different from each other. When the first width W1A and the second width W1B are substantially the same as each other, the groove T can have a linear shape. When the first width W1A and the second width W1B are different from each other, the groove T can have an irregular shape. As an example, the first width W1A can be greater than the second width W1B.

[0081] In cross-section, the groove T can extend through the laminate ST along the third direction III and can have an arch shape. Along the third direction III, the first height LV1 can be the height corresponding to the upper surface, and the second height LV2 can be the height with the maximum width and can be a bow level. The width of the groove T at the second height LV2 can be greater than the width at the first height LV1. At the second height LV2, the first portion TA can have a first width W2A greater than the first width W1A, and the second portion TB can have a second width W2B greater than the second width W1B.

[0082] Subsequently, a buffer layer 73 can be formed in the trench T. The buffer layer 73 can be a sacrificial layer and can include oxides. The buffer layer 73 can have a shape transferred from the trench T. In a plan view, the buffer layer 73 can have a linear shape or an irregular shape. In a cross-section, the buffer layer 73 can have an arc shape.

[0083] The buffer layer 73 can be formed by a deposition method. During the deposition of the buffer material in the trench T, the trench T may be sealed before the buffer material is completely filled into the trench T, and voids V may be created. Voids V can be empty spaces in which no buffer material is deposited, and may be filled with air.

[0084] Reference Figures 8A to 8CA slit SL can be formed in the buffer layer 73. In a plan view, the slit SL can extend along the buffer layer 73 in a first direction I and / or a second direction II. The slit SL can have a shape similar to that of the trench T. When the trench T has a linear shape, the slit SL can also have a linear shape. When the trench T has an irregular shape, the slit SL can also have an irregular shape. When both the trench T and the slit SL have irregular shapes, the first portion SL1 of the slit SL can be positioned to correspond to the first portion TA of the trench T, and the second portion SLb of the slit SL can be positioned to correspond to the second portion TB of the trench T.

[0085] As an example, the slit SL can be partially formed in the buffer layer 73. The slit SL can be formed only in areas where cracking may occur, such as the boundary between adjacent memory blocks or the boundary between adjacent memory planes. As an example, the slit SL can be entirely formed in the buffer layer 73. The slit SL can be formed as a closed curve along the edge of the chip.

[0086] In cross-section, the slit SL can extend along the buffer layer 73 in the third direction III. The slit SL can be formed with a depth that does not completely penetrate the buffer layer, and the bottom surface of the slit SL can be located at a higher height than the bottom surface of the buffer layer 73. The slit SL can connect to the void V. The material layer may not fill the interior of the slit SL and the void V, and air gaps may exist in the slit SL and the void V.

[0087] Subsequently, cracks may arise and propagate due to stress generated during the manufacturing process. For example, stress and cracks may be caused by oxidation processes. Cracks may arise at the interface between the laminate and the interlayer insulation and may propagate in one direction along the interface to reach the buffer layer 73. Cracks that have reached the buffer layer 73 may come into contact with air gaps, and because air gaps are empty spaces where no material propagates cracks, they can prevent crack propagation. As an example, air gaps may exist in the buffer layer 73 extending along a first direction I, and cracks propagating along a second direction II may be stopped by the air gaps.

[0088] Reference Figures 9A to 9C An insulating spacer 74 can be formed in the slit SL and the gap V. The insulating spacer 74 may include an oxide. Subsequently, a conductive layer 75 can be formed on the insulating spacer 74. The conductive layer 75 can be used to form a source contact plug and may include a polysilicon layer. The slit SL and the gap V may be filled by the conductive layer 75.

[0089] Reference Figures 10A to 10CThe opening OP can be formed by etching the buffer layer 73, the insulating spacer 74, and the conductive layer 75. The opening OP can also be formed by reopening a portion of a previously formed trench T. Portions of the buffer layer 73, the insulating spacer 74, and the conductive layer 75 can be etched to retain the buffer layer 73A, the insulating spacer 74A, and the conductive layer 75A, respectively. The remaining conductive layer 75A may include a first portion 75AA with a curved surface and a second portion 75AB with a width smaller than that of the first portion 75AA. The first portion 75AA may be a portion filling the void V, and the second portion 75AB may be a portion filling the slit SL.

[0090] The etching rates of the buffer layer 73A, the insulating spacer 74A, and the conductive layer 75A can be different from each other. As an example, the etching rate of the buffer layer 73A can be greater than that of the conductive layer 75A. The shapes of the remaining buffer layer 73A, the insulating spacer 74A, and the conductive layer 75A, as well as the shape of the opening OP, can be changed according to the difference in etching rates.

[0091] Reference Figures 11A to 11C A conductor 77 can be formed within the opening OP. For example, the conductor 77 can be a detection line of a crack detection circuit and can comprise a metal such as tungsten (W), copper (Cu), or aluminum (Al). The conductor 77 can include a first portion 77A located above the buffer layer 73A, the insulating spacer 74A, and the conductive layer 75A, and a second portion 77B surrounding the sidewall of the buffer layer 73A. When the opening OP has an irregular shape, the probability of forming a linear void within the conductor 77 can be reduced, and the occurrence of cracks due to thermal stress can be decreased.

[0092] According to the above method, even if cracks are caused during the manufacturing process of a semiconductor device, the propagation of the cracks can be prevented by the air gaps in the slit SL and the void V.

[0093] Figure 12A , Figure 13A and Figure 14A as well as Figure 12B , Figure 13B and Figure 14B This is a diagram used to describe a method of manufacturing a semiconductor device according to one embodiment. Figure 12B , Figure 13B and Figure 14B They are along Figure 12A , Figure 13A and Figure 14A The cross-sectional view taken from line C-C'.

[0094] Reference Figure 12A and Figure 12BA laminate ST comprising alternating layers of first material layer 81 and second material layer 82 can be formed. Subsequently, a trench T can be formed in the laminate ST, and a buffer layer 83 including a void V can be formed in the trench T. A slit SL can then be formed in the buffer layer 83. The slit SL can be connected to the void V.

[0095] Reference Figure 13A and Figure 13B A second stop layer 84 can be formed in the slit SL and the void V. The second stop layer 84 may comprise a material having a higher elastic modulus (Young's modulus) than the buffer layer 83, and may comprise a nitride. Subsequently, a first stop layer 85 may be formed on the second stop layer 84. The first stop layer 85 may be a conductive layer for forming the source layer, and may comprise a material having a higher elastic modulus (Young's modulus) than the buffer layer 83 and the second stop layer 84. As an example, the first stop layer 85 may comprise a conductive material such as polysilicon.

[0096] Subsequently, cracks may form and propagate due to stress generated during the manufacturing process. For example, stress and cracks may be caused by oxidation processes. Cracks may form at the interface between the laminate and the interlayer insulation and may propagate in one direction along the interface to reach the buffer layer 83. Cracks that have reached the buffer layer 83 may come into contact with the second stop layer 84, and the propagation of the crack may be stopped by the second stop layer 84 and the first stop layer 85.

[0097] Reference Figure 14A and Figure 14B An opening OP can be formed by etching a buffer layer 83, a second stop layer 84, and a first stop layer 85. Buffer layers 83A, second stop layers 84A, and first stop layers 85A can be retained. Subsequently, a wire 87 can be formed in the opening OP. The wire 87 can surround the buffer layers 83A, second stop layers 84A, and first stop layers 85A. The wire 87 can include a metal such as tungsten (W).

[0098] According to the above method, even if cracks are caused by oxidation or other processes during the manufacturing of a semiconductor device, the propagation of the cracks can be prevented by the second stop layer 84 and the first stop layer 85.

[0099] Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A as well as Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B and Figure 25B This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A It is a cross-sectional view of the chip protection region (CGR), and Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B and Figure 25B This is a cross-sectional view of the chip region CHR.

[0100] Reference Figure 15A and Figure 15B A preliminary source structure PS, including a source sacrificial layer 93, can be formed on an interlayer insulating layer 90 including wiring 99. Wiring 99 may be part of a crack detection circuit. The preliminary source structure PS may be located in a chip region CHR and may include a first source layer 92, a second source layer 94, and a source sacrificial layer 93 located between the first source layer 92 and the second source layer 94. The preliminary source structure PS may also include a first protective layer 96 located between the first source layer 92 and the source sacrificial layer 93, and a second protective layer 97 located between the source sacrificial layer 93 and the second source layer 94. The preliminary source structure PS may also include a sub-source layer 91 and an insulating layer 95 located between the sub-source layer 91 and the first source layer 92. As an example, the first source layer 92, the second source layer 94, and the sub-source layer 91 may each include polysilicon, and the first protective layer 96, the second protective layer 97, and the insulating layer 95 may each include oxide.

[0101] Subsequently, a stacked element ST can be formed in the chip region CHR and the chip protection region CGR. The stacked element ST may include alternating layers of first material layer 101 and second material layer 102. Each of the first material layer 101 may include a material with high etch selectivity relative to the second material layer 102. As an example, each of the first material layer 101 may include a sacrificial material such as a nitride or a conductive material such as polysilicon or a metal. Each of the second material layer 102 may include an insulating material such as an oxide.

[0102] For reference, an etch stop pattern 98 may be formed on the preliminary source structure PS prior to forming the stacked component ST. The etch stop pattern 98 may be a pattern to be used as an etch stop layer in a subsequent process that forms the slot. The etch stop pattern 98 may include a material with high etch selectivity relative to the first material layer 101 and the second material layer 102, and may include tungsten.

[0103] Subsequently, a channel structure CH can be formed in the chip region CHR. The channel structure CH can extend through the stack ST into the initial source structure PS. As an example, the channel structure CH can penetrate the second source layer 94, the second protective layer 97, the source sacrificial layer 93, and the first protective layer 96, and can extend into the first source layer 92. The channel structure CH may include a channel layer 103, a memory layer 104 surrounding the channel layer 103, and an insulating core 105 located in the channel layer 103. The memory layer 104 may include a barrier layer, a data storage layer, and a tunneling layer. Subsequently, a second material layer 102 can be additionally formed on the stack ST to cover the upper surface of the channel structure CH.

[0104] Subsequently, a trench T can be formed in the chip protection region CGR surrounding the chip region CHR. The trench T can extend through the stacked assembly ST and can expose wiring 99. As an example, the trench T can have sidewalls that are linear or irregularly shaped. Subsequently, a buffer layer 106 including voids V can be formed in the trench T. The buffer layer 106 can extend along the upper surface of the stacked assembly ST. The buffer layer 106 can include oxide.

[0105] Reference Figure 16A and Figure 16BA slot SLA located in the chip protection region CGR and a slot SLB located in the chip region CHR can be formed. When the trench T has an irregular shape, the slot SLA can also have an irregular shape corresponding to the trench T. The slot SLA and slot SLB can be formed simultaneously. The slot SLA can be formed by etching the buffer layer 106 and can be connected to the void V. The bottom surface of the slot SLA can be located at a higher height than the bottom surface of the buffer layer 106 and can not expose the wiring 99. The slot SLA can have a width smaller than the width of the trench T and can not expose the stack-up ST. The slot SLB can be located between the channel structures CH and can extend through the stack-up ST to expose the etch stop pattern 98. Subsequently, the etch stop pattern 98 can be removed by the slot SLB.

[0106] Reference Figure 17A and Figure 17B A liner 108 can be formed in the slits SLA and SLB. The liner 108 can be formed along the inner surfaces of the slits SLA and SLB, and the central regions of the slits SLA and SLB can be opened.

[0107] The substrate 108 can be used to protect the stacked layer ST in subsequent processes of etching the memory layer 104. The substrate 108 can be composed of a single layer or multiple layers. As an example, the substrate 108 may include a first nitride layer 108A, an oxide layer 108B, and a second nitride layer 108C. The first nitride layer 108A can be formed, the oxide layer 108B can be formed on the first nitride layer 108A, and the second nitride layer 108C can be formed on the oxide layer 108B.

[0108] Reference Figure 18A and Figure 18B The first opening OP1 can be formed by removing the source sacrificial layer 93 via the slit SLB. Subsequently, the memory layer 104 can be etched to expose the channel layer 103. As an example, a dry etching cleaning process or a wet etching process can be used to etch the barrier layer, data storage layer, and tunneling layer. For example, the etching can be performed using a dry cleaning process. In this process, the first protective layer 96 and the second protective layer 97 can be etched, and the first source layer 92 and the second source layer 94 can be exposed in the first opening OP1. Furthermore, the second nitride layer 108C and the oxide layer 108B in the slits SLA and SLB can be etched, and the first nitride layer 108A in the slits SLA and SLB can be exposed. Through this process, the second nitride layer 108C and the oxide layer 108B in the slits SLA and SLB can be removed, while the first nitride layer 108A in the slits SLA and SLB can be retained.

[0109] Reference Figure 19A and Figure 19BA conductive layer 109 can be formed. The conductive layer 109 can fill the first opening OP1 and can extend along the slit SLB. The conductive layer 109 can extend along the slit SLA and can also be formed on the upper surface of the laminate ST. The slit SLA may not be completely filled by the conductive layer 109.

[0110] Reference Figure 20A and Figure 20B The third source layer 109A can be formed in the first opening OP1 by etching the conductive layer 109. As an example, a wet etching process can be used to etch the conductive layer 109. Through this process, a source structure S including a first source layer 92, a second source layer 94, a third source layer 109A, a sub-source layer 91, and an insulating layer 95 can be formed.

[0111] During the etching of conductive layer 109, conductive layer 109 in slit SLA can be removed, and buffer layer 106 can be exposed. When slit SLA has an irregular shape, the inflow channel of wet etching chemicals can be ensured, and conductive layer 109 can be left out of slit SLA. The interior of buffer layer 106 can be empty, and air gaps can be located inside buffer layer 106. Subsequently, the first nitride layer 108A in slit SLA and SLB can be removed.

[0112] Reference Figure 21A and Figure 21B The protective pattern 111 can be formed using an oxidation process. The surfaces of the first source layer 92, the second source layer 94, and the third source layer 109A exposed through the slit SLB can be oxidized, and the protective pattern 111 can be formed.

[0113] Oxidation processes can induce stress and potentially lead to cracks. Cracks can occur at boundaries between adjacent memory blocks, boundaries between adjacent memory planes, or at the edges of the chip. As an example, cracks can occur at the interface between the stack-up ST and the interlayer insulating layer and can propagate along the interface in one direction. When a crack reaches the buffer layer 106 of the chip protection region CGR, its propagation can be prevented by an air gap.

[0114] Reference Figure 22A and Figure 22BThe first material layer 101 can be removed, and then the conductive layer 112 can be formed. Because the first material layer 101 is exposed through the slot SLB in the chip protection region CGR, it can be selectively etched. When the first material layer 101 is etched, the source structure S can be protected by the protective pattern 111. The conductive layer 112 can fill the area where the first material layer 101 is etched and can extend along the inner surface of the slot SLB. Because the first material layer 101 is covered by the buffer layer 106 in the chip protection region CGR, it is not exposed through the slot SLA. The first material layer 101 remains intact, and the conductive layer 112 can be formed in the slot SLA.

[0115] Reference Figure 23A and Figure 23B The gate line 112A can be formed by etching the conductive layer 112. When the slit SLA has an irregular shape, the inflow channel of wet etching chemicals can be ensured, and the conductive layer 112 may not remain in the slit SLA. Through this process, a gate structure GST comprising alternating layers of a second material layer 102 and the gate line 112A can be formed. Because the first material layer 101 of the chip protection region CGR is not replaced by the gate line 112A, the stacked structure ST can remain in the chip protection region CGR, and the remaining stacked structure ST can be a dummy structure.

[0116] Subsequently, insulating spacers 113A and conductive layers 114A can be formed in the chip protection region CGR. Insulating spacers 113B and source contact plugs 114B can be formed in the chip region CHR. Insulating spacers 113A and 113B can be formed simultaneously. Source contact plugs 114B can be formed simultaneously with the conductive layer 114A. Insulating spacers 113A and 113B may each comprise oxide, and conductive layers 114A and source contact plugs 114B may each comprise polysilicon.

[0117] Reference Figure 24A and Figure 24B A sealing layer 115 can be formed in the chip protection region CGR and the chip region CHR. The sealing layer 115 can be used to cover the upper surface of the source contact plug of the chip region CHR. An interlayer insulating layer 116 can be formed on the sealing layer 115.

[0118] Subsequently, an opening OPA can be formed by etching the conductive layer 114A, insulating spacer 113A, and buffer layer 106 of the chip protection region CGR. The etching rates of the conductive layer 114A, insulating spacer 113A, and buffer layer 106 can be different from each other. The etching rate of the insulating spacer 113A and buffer layer 106 can be greater than the etching rate of the conductive layer 114A, and the conductive layer 114A and buffer layer 106A can be retained.

[0119] An opening OPB exposing the channel structure CH can be formed by etching the interlayer insulating layer 116 and buffer layer 106 of the chip region CHR. An opening OPB can be formed when an opening OPA is formed.

[0120] Reference Figure 25A and Figure 25B A conductive layer can be formed in the openings OPA and OPB. The conductive layer may include a metal such as tungsten. Through this process, a wire 117A can be formed in the chip protection region CGR. The wire 117A may be part of a crack detection circuit. A contact plug 117B can be formed in the chip region CHR. The contact plug 117B can be formed while the wire 117A is being formed.

[0121] According to the above method, even in the event of cracking due to oxidation processes, crack propagation can be prevented by the air gap in the slit SLA. The air gap can serve as a stop layer. The contact plugs of the chip region CHR and the conductors of the chip protection region CGR can be formed simultaneously.

[0122] Figures 26A to 26D This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment, and shows the chip protection region CGR. In the following description, content overlapping with the previously described material may be omitted.

[0123] Reference Figure 26A The slit SLAA can be formed by etching the buffer layer 106. Figure 26A This can correspond to the above references. Figure 16A and Figure 16B The described processing steps. Slit SLAA can have a higher... Figure 16A The slit SLA has a smaller width. The bottom surface of the slit SLAA can be located at a higher height than the bottom surface of the buffer layer 106, and the wiring 99 can be left unexposed.

[0124] Subsequently, as mentioned above. Figure 17A and Figure 17B As described above, a liner 108 comprising a first nitride layer 108A, an oxide layer 108B, and a second nitride layer 108C can be formed in the slit SLAA. Subsequently, as described above... Figure 18A and Figure 18B The second nitride layer 108C and oxide layer 108B in the slit SLAA can be etched.

[0125] Reference Figure 26B A conductive layer 109 can be formed on the first nitride layer 108A. Figure 26B This can correspond to the above references. Figure 19A and Figure 19BThe described processing steps. Because the slit SLAA has a smaller width than the slit SLA, the conductive layer 109 can completely fill the slit SLAA. The conductive layer 109 may comprise polysilicon.

[0126] Subsequently, as mentioned above. Figure 20A and Figure 20B The conductive layer 109 can be etched. Because the slit SLAA is completely filled with the conductive layer 109, the conductive layer 109 inside the slit SLAA does not need to be etched.

[0127] Subsequently, as mentioned above. Figure 21A and Figure 21B The oxidation process can be performed. The oxidation process may induce stress and potentially lead to cracks. Cracks can occur at the boundaries between adjacent memory blocks, the boundaries between adjacent memory planes, or the edges of the chip. As an example, cracks can occur at the interface between the stack-up ST and the interlayer insulating layer and can propagate along said interface in one direction. The first nitride layer 108A and the conductive layer 109 can each comprise a material having a higher elastic modulus (Young's modulus) than the buffer layer 106 and can serve as stop layers. The conductive layer 109 can be the first stop layer, and the first nitride layer 108A can be the second stop layer. When a crack reaches the buffer layer 106 of the chip protection region CGR, the propagation of the crack can be stopped by the first nitride layer 108A and the conductive layer 109.

[0128] Subsequently, as referred to Figure 22A , Figure 22B , Figure 23A and Figure 23B The conductive layer 112 can be formed and etched. Because the conductive layer 109 is in a state of filling the slit SLAA, the conductive layer 112 can be formed over the laminate ST and then removed. Subsequently, the insulating spacer 113A and the conductive layer 114A can be formed over the laminate ST and then removed.

[0129] Reference Figure 26C A sealing layer 115 and an interlayer insulation layer 116 can be formed on the buffer layer 106, and an opening OPAA can be formed. Figure 26C This can correspond to the above references. Figure 24A and Figure 24B The described processing steps are as follows: The opening OPAA can be formed by etching the conductive layer 109, the first nitride layer 108A, and the buffer layer 106. The etching rates of the conductive layer 109, the first nitride layer 108A, and the buffer layer 106 can be different from each other. The etching rate of the buffer layer 106 can be greater than the etching rate of the conductive layer 109 and the first nitride layer 108A, and the conductive layer 109AA and the first nitride layer 108AA can be retained.

[0130] Reference Figure 26D Wire 117A can be formed in the open OPAA. Figure 26D This can correspond to the above references. Figure 25A and Figure 25B The processing steps are described. Wire 117A may include a metal such as tungsten.

[0131] According to the above method, even in the event of cracking due to oxidation processes, crack propagation can be prevented by the first nitride layer 108A and the conductive layer 109 in the slit SLAA. The first nitride layer 108A and the conductive layer 109 can be used as stop layers.

[0132] The structure and manufacturing method according to the above embodiments can be applied to semiconductor devices with various structures. Figure 27 and Figure 28 A schematic configuration of a semiconductor device to which the above embodiments can be applied is shown.

[0133] Figure 27 This is a configuration diagram of a semiconductor device according to one embodiment of the present disclosure.

[0134] Reference Figure 27 The semiconductor device may include a substrate SUB, peripheral circuitry PC, and memory cell array CA. Here, the peripheral circuitry PC and the memory cell array CA may be formed on the same substrate.

[0135] The substrate SUB can be made of or comprise a semiconductor material. In one embodiment, the semiconductor material can include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Here, group IV semiconductors can include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon germanium (SiGe). Group III-V compound semiconductors can include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), gallium indium arsenide phosphide (GaInAsP), aluminum arsenide (AlAs), aluminum gallium (AlGa), indium phosphide (InP), indium antimonide (InSb), or indium gallium arsenide (InGaAs). Group II-VI compound semiconductors can include zinc sulfide (ZnS), zinc oxide (ZnO), or cadmium sulfide (CdS).

[0136] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. In one embodiment, the substrate SUB may include graphene.

[0137] The substrate SUB can be a bulk wafer or an epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB can include group II, III, IV, V, or VI impurities. In one embodiment, the substrate SUB can include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0138] The peripheral circuitry PC can be disposed between the substrate SUB and the memory cell array CA. The peripheral circuitry PC may include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. In one embodiment, the peripheral circuitry PC may include N-channel metal-oxide-semiconductor (NMOS) transistors, P-channel metal-oxide-semiconductor (PMOS) transistors, resistors, capacitors, etc. The peripheral circuitry PC may further include interconnect structures. The interconnect structures can serve as paths for transmitting operating voltages and may include contact plugs, wires, etc.

[0139] A memory cell array (CA) may include memory cells. In one embodiment, the memory cell array (CA) may include memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. In another embodiment, the memory cell array (CA) may include memory cells connected between word lines and bit lines. The memory cell array (CA) may further include interconnect structures.

[0140] Figure 28 This is a configuration diagram of a semiconductor device according to one embodiment of the present disclosure.

[0141] Reference Figure 28 The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may further include a support substrate SP_B.

[0142] The substrate SUB can serve as a support during the formation of the peripheral circuit PC. The support substrate SP_B can serve as a support during the formation of the memory cell array CA. In one embodiment, after fabricating a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC, the first and second wafers can be electrically connected via a bonding structure BS. After bonding, at least a portion of the support substrate SP_B of the first wafer can be removed. The support substrate SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0143] The supporting substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The supporting substrate SP_B can be a bulk wafer, an epitaxial layer grown using selective epitaxial growth (SEG), or a layer formed using metal-induced lateral crystallization (MILC). The supporting substrate SP_B can be single-crystal, polycrystalline, or amorphous. The supporting substrate SP_B can include group II, III, IV, V, or VI impurities.

[0144] The bonding structure BS can be used to connect the memory cell array CA and the peripheral circuit PC. In one embodiment, the memory cell array CA and the peripheral circuit PC can be bonded using wafer-on-wafer bonding, chip-on-wafer bonding, chip-on-chip bonding, etc. The bonding structure BS may include bonding pads, bonding layers, bonding interfaces, etc. The bonding pads may include metals such as copper and aluminum, and / or alloys. The bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array CA and the peripheral circuit PC can be electrically connected through the bonding structure BS.

[0145] For reference, interconnect structures included in the memory cell array (CA) and / or peripheral circuitry (PC) can be directly connected without the need for bonding pads. In one embodiment, bonding layers included in the memory cell array (CA) and bonding layers included in the peripheral circuitry (PC) can be bonded to form a bonding interface, and interconnect structures included in the memory cell array (CA) and interconnect structures included in the peripheral circuitry (PC) can be directly connected. In this way, contact plugs, wires, etc., formed on different wafers can be electrically connected without separate bonding pads.

[0146] Other configurations can be equivalent to or similar to those described above. Figure 27 The implementation method described above.

[0147] In a further embodiment, the semiconductor device may have incorporated the above references. Figure 27 and Figure 28 The described implementation scheme may have a structure that is partially modified. (Refer to...) Figure 27 and Figure 28 In the described implementation, the positions of the memory cell array CA and the peripheral circuit PC can be changed. At least one memory cell array CA and / or at least one peripheral circuit PC can be additionally coupled to the reference. Figure 27 and Figure 28 The described implementation method. In one implementation, a portion of the peripheral circuitry PC may be located in the memory cell array CA.

[0148] Although embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is only for explaining embodiments based on the concept of this disclosure, and this disclosure is not limited to the above embodiments. Those skilled in the art to which this disclosure pertains may make various types of substitutions, modifications, alterations, and combinations to the embodiments without departing from the technical concept of this disclosure as defined in the appended claims, and such substitutions, modifications, alterations, and combinations should be interpreted as falling within the scope of this disclosure.

[0149] Cross-references to related applications

[0150] This application claims priority to Korean Patent Application No. 10-2025-0043565, filed on April 3, 2025, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure disposed in a chip region and comprising alternating layers of conductive layers and a first insulating layer; A dummy structure is disposed in a chip protection region surrounding the chip region and includes alternating layers of a second insulating layer and a third insulating layer; as well as A chip protection structure located in the chip protection region, and including a polysilicon layer disposed in the dummy structure and wires surrounding the polysilicon layer and extending through the dummy structure.

2. The semiconductor device according to claim 1, wherein, The chip protection structure further includes an oxide layer disposed in the wire and surrounding the polysilicon layer.

3. The semiconductor device according to claim 2, wherein, The chip protection structure further includes a nitride layer disposed between the polysilicon layer and the oxide layer.

4. The semiconductor device according to claim 2, wherein, The wire includes: A first portion, the first portion being disposed above the oxide layer; and The second part extends from the first part along the sidewall of the oxide layer.

5. The semiconductor device according to claim 1, wherein, The polycrystalline silicon layer includes: The first part includes a curved surface; and The second part has a width smaller than that of the first part.

6. The semiconductor device according to claim 1, wherein, The polysilicon layer is disposed between adjacent memory blocks.

7. The semiconductor device according to claim 1, wherein, The polysilicon layers are disposed between adjacent memory planes.

8. The semiconductor device of claim 1, further comprising a metal wiring disposed below the dummy structure and electrically connected to the wire.

9. The semiconductor device according to claim 1, wherein, The chip protection structure is included in the chip crack detection circuit, and the wire is used as the detection line of the chip crack detection circuit.

10. A semiconductor device, the semiconductor device comprising: A dummy structure comprising alternating layers of a first insulating layer and a second insulating layer; A stop layer, comprising a first sub-stop layer located in the dummy structure and a second sub-stop layer surrounding the first sub-stop layer; A buffer layer surrounding the stop layer; and A conductor that surrounds the buffer layer and has a closed curve shape extending through the dummy structure.

11. The semiconductor device according to claim 10, wherein, The first sub-stop layer comprises polysilicon, the second sub-stop layer comprises nitride, and the buffer layer comprises oxide.

12. The semiconductor device according to claim 10, wherein, The upper surface of the stop layer is positioned at a lower height than the upper surface of the conductor.

13. The semiconductor device according to claim 12, wherein, The upper surface of the buffer layer is positioned at a lower height than the upper surface of the conductor.

14. The semiconductor device according to claim 10, wherein, The wire is used as the detection line of the crack detection circuit.

15. A method for manufacturing a semiconductor device, the method comprising the following steps: A stack is formed in a chip region and a chip protection region surrounding the chip region, the stack comprising alternating layers of first and second materials; A trench is formed in the chip protection region of the stacked assembly, the trench surrounding the chip region; A buffer layer is formed in the trench, the buffer layer including voids; and A slit is formed in the buffer layer, the slit connecting to the void to define an air gap within the void and the slit. The air gap prevents cracks from propagating from the chip region toward the chip protection region.

16. The method of claim 15, further comprising the following steps: A polycrystalline silicon layer is formed in the voids and the slits; as well as Remove a portion of the polycrystalline silicon layer.

17. The method of claim 16, further comprising the following steps: During the formation of the polysilicon layer, a source layer is formed in the chip region.

18. The method of claim 15, further comprising the following steps: A metal layer is formed in the voids and the slits; as well as Remove a portion of the metal layer.

19. The method of claim 18, further comprising the following steps: During the formation of the metal layer, gate lines are formed in the chip region.

20. The method of claim 15, further comprising the following steps: Insulating spacers are formed in the gaps and slits; as well as A polycrystalline silicon layer is formed on the insulating spacer.

21. The method of claim 20, further comprising the following steps: During the formation of the polysilicon layer, source contact plugs are formed in the chip region.

22. The method of claim 20, further comprising the following steps: An opening is formed by etching the buffer layer, the insulating spacer, and the polysilicon layer; and A wire is formed in the opening.

23. The method according to claim 22, further comprising the following steps: During the formation of the wire, a contact plug is formed in the chip region.

24. The method according to claim 22, wherein, The step of forming the opening includes the following steps: forming the opening to expose the sidewalls of the polysilicon layer.

25. The method according to claim 22, wherein, When the opening is formed, the etch rate of the buffer layer is greater than the etch rate of the polysilicon layer.

26. The method according to claim 15, wherein, The cracks were caused by the oxidation process.

27. A method for manufacturing a semiconductor device, the method comprising the following steps: A stack is formed in a chip region and a chip protection region surrounding the chip region, the stack comprising alternating layers of first and second materials; A trench is formed in the chip protection region of the stacked assembly, the trench surrounding the chip region; A buffer layer is formed in the trench, the buffer layer including voids; A slit is formed in the buffer layer, and the slit connects to the gap; as well as A stop layer is formed in the gap and the slit, wherein the stop layer prevents cracks from propagating from the chip region toward the chip protection region.

28. The method according to claim 27, wherein, The steps for forming the stop layer include: A nitride layer is formed in the voids and the slits; and A polycrystalline silicon layer is formed on the nitride layer.

29. The method of claim 28, further comprising the following steps: During the formation of the polysilicon layer, a source layer is formed in the chip region.

30. The method of claim 28, further comprising the following steps: An opening is formed by etching the polysilicon layer, the nitride layer, and the buffer layer; and A wire is formed in the opening.

31. The method according to claim 30, further comprising the following steps: During the formation of the wire, a contact plug is formed in the chip region.

32. The method according to claim 30, wherein, The step of forming the opening includes the following steps: forming the opening to expose the nitride layer.

33. The method according to claim 30, wherein, When the opening is formed, the etch rate of the buffer layer is greater than the etch rate of the nitride layer and the polysilicon layer.

34. The method according to claim 27, wherein, The cracks were caused by the oxidation process.

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