Semiconductor structure and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips, and aims to solve the problem of side bending of the gate stack structure on both sides of the gate isolation structure. The semiconductor structure comprises a gate stack structure and a gate isolation structure. The gate isolation structure penetrates the gate stack structure along a first direction, and the gate isolation structure comprises a plurality of first isolation structures and at least one second isolation structure. The plurality of first isolation structures are arranged along a third direction, and the second isolation structure is located between two adjacent first isolation structures. The second isolation structure has a first end and a second end arranged along the third direction. The semiconductor structure further comprises a first insulating layer and a second insulating layer arranged along the third direction. The first insulating layer is located between the first isolation structure and the first end, and the second insulating layer is located between the first isolation structure and the second end. Through the above arrangement, the first insulating layer and the second insulating layer can strengthen the support of the gate stack structure and improve the side bending problem of the gate stack structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a semiconductor structure is provided. The semiconductor structure includes a gate stack structure and a gate isolation structure. The gate stack structure includes a plurality of gate layers and a plurality of dielectric layers alternately arranged along a first direction; the gate isolation structure extends through the gate stack structure along the first direction, the gate stack structure is located on both sides of the gate isolation structure along a second direction, and the gate isolation structure extends along a third direction; the gate isolation structure includes a plurality of first isolation structures and at least one second isolation structure, the plurality of first isolation structures are arranged along the third direction, the second isolation structure is located between two adjacent first isolation structures along the third direction, and the second isolation structure has a first end and a second end arranged along the third direction; the gate isolation structure further includes a first insulating layer and a second insulating layer arranged along the third direction, the first insulating layer is located between the first isolation structure and the first end, and the second insulating layer is located between the first isolation structure and the second end; wherein the second direction is perpendicular to the third direction, and the first direction intersects the plane containing the second direction and the third direction.

[0007] In some embodiments, the first insulating layer includes a first arcuate surface and a second arcuate surface arranged along the third direction, wherein the bending direction of the first arcuate surface and the bending direction of the second arcuate surface are the same; the second insulating layer includes a third arcuate surface and a fourth arcuate surface arranged along the third direction, wherein the bending direction of the third arcuate surface and the fourth arcuate surface are the same, and the bending direction of the third arcuate surface is opposite to that of the first arcuate surface.

[0008] In some embodiments, the first insulating layer and the second insulating layer have a minimum spacing in the third direction, and the end of the first insulating layer in the second direction and the end of the second insulating layer in the second direction have a first spacing in the third direction, the first spacing being greater than the minimum spacing.

[0009] In some embodiments, the first insulating layer and the second insulating layer are symmetrically arranged with respect to the second isolation structure.

[0010] In some embodiments, the first insulating layer, the second isolation structure, and the second insulating layer together constitute an insulating structure, and the gate isolation structure includes a plurality of the insulating structures spaced apart along the third direction.

[0011] In some embodiments, both the first end and the second end have concave surfaces.

[0012] In some embodiments, the maximum dimension of the second isolation structure in the second direction is greater than the maximum dimension of the first isolation structure in the second direction.

[0013] In some embodiments, the second isolation structure includes a body and an isolation layer, the body penetrating the gate stack structure along the first direction, the isolation layer being located between the body and the gate stack structure, and the isolation layer also being located between the body and the first insulating layer, the isolation layer being disposed around the body; the semiconductor structure further includes a plurality of channel structures penetrating the gate stack structure along the first direction, the plurality of channel structures being arranged in multiple rows and columns along the third direction and the second direction, and the isolation layer contacting the sidewalls of a portion of the channel structures.

[0014] In some embodiments, the semiconductor structure includes a core region and a connection region adjacent to each other along the third direction, a portion of the channel structure is located in the core region, a portion of the channel structure is located in the connection region, and the number of rows of the channel structure located in the core region is greater than the number of rows of the channel structure located in the connection region; the first insulating layer and the second insulating layer are located in the core region.

[0015] In some embodiments, the gate isolation structure includes a plurality of first insulating layers and a plurality of second insulating layers, with portions of the first insulating layers and portions of the second insulating layers located in the connection region.

[0016] In some embodiments, the method includes: forming a gate stack structure, the gate stack structure including a plurality of gate layers and a plurality of dielectric layers alternately arranged along a first direction; forming a gate isolation structure, the gate isolation structure extending through the gate stack structure along the first direction and extending along a third direction; the gate isolation structure including a plurality of first isolation structures and at least one second isolation structure, the plurality of first isolation structures being arranged along the third direction, the second isolation structure being located between two adjacent first isolation structures along the third direction, the second isolation structure having a first end and a second end arranged along the third direction; the gate isolation structure further includes a first insulating layer and a second insulating layer arranged along the third direction, the first insulating layer being located between the first isolation structure and the first end, and the second insulating layer being located between the first isolation structure and the second end; wherein the second direction is perpendicular to the third direction, and the first direction intersects the plane containing the second direction and the third direction.

[0017] In some embodiments, forming a plurality of gate stack structures includes: forming a first stack structure, the first stack structure including a plurality of sacrificial layers and a plurality of dielectric layers alternately disposed along a first direction; forming a gate spacer, the gate spacer penetrating the first stack structure along the first direction and extending along the third direction; and replacing a portion of the sacrificial layers with the gate layers through the gate spacer.

[0018] In some embodiments, forming a gate spacer includes: forming a plurality of vias spaced apart along a third direction, the vias penetrating the first stacked structure along the first direction; injecting an etchant into a portion of the vias to connect the vias, thereby forming a first spacer and a second spacer spaced apart along the third direction; filling the first spacer and the second spacer with sacrificial material to form a first sacrificial structure and a second sacrificial structure, respectively; injecting an etchant into the vias located between the first spacer and the second spacer to form a third spacer, the third spacer exposing a portion of the sidewall of the first sacrificial structure and a portion of the sidewall of the second sacrificial structure; and using an anode oxidation process, forming a first insulating layer on the sidewall of the first sacrificial structure and a second insulating layer on a portion of the sidewall of the second sacrificial structure through the third spacer.

[0019] In some embodiments, injecting etchant into the through-hole located between the first and second partitions further includes: injecting etchant into a portion of the through-hole to connect a portion of the through-hole to form a fourth partition, the fourth partition exposing a portion of the sidewall of the second sacrificial structure, the first partition, the second partition, and the fourth partition together constituting the gate partition; the anode oxidation process further includes: forming an insulating layer on a portion of the sidewall of the second sacrificial structure through the fourth partition.

[0020] In some embodiments, forming a gate isolation structure includes: depositing an isolation material and a semiconductor material sequentially in the gate trench through the gate trench to form an isolation layer and a body, the body penetrating the gate stack structure along the first direction, the isolation layer being located between the body and the gate stack structure, and the isolation layer being disposed around the body.

[0021] In another aspect, a storage system is provided, comprising: a semiconductor structure as described above, and a controller coupled to the semiconductor structure to control the semiconductor structure to store data.

[0022] On the other hand, an electronic device is provided, including the storage system described above. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0025] Figure 2 A top view of a semiconductor structure according to some embodiments Figure 1 ;

[0026] Figure 3 for Figure 2 Cross-sectional view of AA;

[0027] Figure 4 A schematic diagram of the gate isolation structure according to some embodiments Figure 1 ;

[0028] Figure 5 A schematic diagram of the gate isolation structure according to some embodiments Figure 2 ;

[0029] Figure 6 A schematic diagram of the gate isolation structure according to some embodiments Figure 3 ;

[0030] Figure 7 A top view of a semiconductor structure according to some embodiments Figure 2 ;

[0031] Figure 8 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0032] Figure 9 This is a schematic diagram of the structure after the formation of the first stacked structure according to some embodiments;

[0033] Figure 10 This is a top view after the through hole has been formed according to some embodiments;

[0034] Figure 11 This is a top view after the sacrificial column has been formed according to some embodiments;

[0035] Figure 12 for Figure 11 A composite image of cross-sections at positions AA, BB, and CC;

[0036] Figure 13 This is a partial top view after the through-hole has been formed according to some embodiments;

[0037] Figure 14 This is a partial top view after the formation of the first and second partitions according to some embodiments;

[0038] Figure 15 A partial top view after forming a plurality of first partitions and a plurality of second partitions according to some embodiments;

[0039] Figure 16 A partial top view after the formation of the first and second sacrificial structures according to some embodiments. Figure 1 ;

[0040] Figure 17 A partial top view after the formation of the first and second sacrificial structures according to some embodiments. Figure 2 ;

[0041] Figure 18 for Figure 17 splicing of AA section and BB section Figure 1 ;

[0042] Figure 19 for Figure 17 splicing of AA section and BB section Figure 2 ;

[0043] Figure 20 This is a partial top view after the removal of the sacrificial column according to some embodiments;

[0044] Figure 21 for Figure 20 BB section in Figure 1 ;

[0045] Figure 22 for Figure 20 BB section in Figure 2 ;

[0046] Figure 23 This is a partial top view after the third partition has been formed according to some embodiments;

[0047] Figure 24 for Figure 23 BB section in Figure 1 ;

[0048] Figure 25 for Figure 23 BB section in Figure 2 ;

[0049] Figure 26 for Figure 23 BB section in Figure 3 ;

[0050] Figure 27 for Figure 23 BB section in Figure 4 ;

[0051] Figure 28 This is a partial top view after the formation of the first insulating layer and the second insulating layer according to some embodiments;

[0052] Figure 29 for Figure 28 BB section in Figure 1 ;

[0053] Figure 30 for Figure 28 BB section in Figure 2 ;

[0054] Figure 31 This is a partial top view of the third compartment after sacrificial material has been filled according to some embodiments;

[0055] Figure 32 for Figure 31 BB section in Figure 1 ;

[0056] Figure 33 for Figure 31BB section in Figure 2 ;

[0057] Figure 34 This is a top view after the trench structure has been formed according to some embodiments;

[0058] Figure 35 for Figure 34 A composite image of cross-sections at positions AA, BB, and CC;

[0059] Figure 36 This is a top view after forming a partial gate spacer according to some embodiments;

[0060] Figure 37 for Figure 36 A composite image of cross-sections at positions AA, BB, and CC;

[0061] Figure 38 A top view after forming the second sacrificial structure according to some embodiments;

[0062] Figure 39 for Figure 38 A composite image of cross-sections at positions AA, BB, and CC;

[0063] Figure 40 This is a top view after removing the sacrificial column located in the connection area according to some embodiments;

[0064] Figure 41 for Figure 40 A composite image of cross-sections at positions AA, BB, and CC;

[0065] Figure 42 This is a top view after the fourth partition has been formed according to some embodiments;

[0066] Figure 43 for Figure 42 A composite image of cross-sections at positions AA, BB, and CC;

[0067] Figure 44 This is a top view after the first filled space has been formed according to some embodiments;

[0068] Figure 45 for Figure 44 A composite image of cross-sections at positions AA, BB, and CC;

[0069] Figure 46 This is a top view after the insulating layer has been formed according to some embodiments;

[0070] Figure 47 for Figure 46 A composite image of cross-sections at positions AA, BB, and CC;

[0071] Figure 48 A top view after the first filling space has been filled with sacrificial material according to some embodiments;

[0072] Figure 49 for Figure 48 A composite image of cross-sections at positions AA, BB, and CC;

[0073] Figure 50 This is a top view after the fourth compartment has been filled with sacrificial material, according to some embodiments;

[0074] Figure 51 for Figure 50 A composite image of cross-sections at positions AA, BB, and CC;

[0075] Figure 52 This is a top view after the second filling space has been formed according to some embodiments;

[0076] Figure 53 for Figure 52 A composite image of cross-sections at positions AA, BB, and CC;

[0077] Figure 54 This is a block diagram of a storage system according to some embodiments;

[0078] Figure 55 This is a block diagram of a storage system according to some other embodiments.

[0079] Reference numerals: X, first direction; Y, second direction; Z, third direction; 200, semiconductor structure; 10, gate stack structure; 11, gate layer; 12, dielectric layer; 20, gate isolation structure; 21, first isolation structure; 22, second isolation structure; 221, first end; 222, second end; 223, concave surface; 224, main body; 225, isolation layer; 23, first insulating layer; 231, first arcuate surface; 232, second arcuate surface; 24, second insulating layer; 241, third arcuate surface; 242, fourth arcuate surface ; d1, minimum pitch; d2, first pitch; 25, insulating structure; 30, channel structure; 40, semiconductor layer; 50, first stacked structure; 51, substrate; 52, sacrificial layer; 53, via; 54, sacrificial pillar; 55, gate spacer; 551, first spacer; 5511, first sacrificial structure; 552, second spacer; 5521, second sacrificial structure; 553, third spacer; 554, fourth spacer; 555, second sacrificial layer; 561, first fill space; 562, second fill space; 57, insulating layer. Detailed Implementation

[0080] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0081] In the description of this disclosure, it should be understood that the terms "upper", "lower", "front", "rear", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0082] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0083] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0084] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0085] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0086] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0087] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0088] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0089] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0090] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0091] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0092] The term "three-dimensional memory" refers to a semiconductor structure formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0093] Figure 1 This is a cross-sectional view of a three-dimensional memory according to some embodiments. It should be noted that... Figure 1 In this context, the three-dimensional memory 1000 is located in the XYZ three-dimensional coordinate system. The three-dimensional memory 1000 extends in the YZ plane. The second direction Y and the third direction Z are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (e.g., the plane where the source layer SL is located): the second direction Y is, for example, the extension direction of the bit line, and the third direction Z is, for example, the extension direction of the word line. The first direction X is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the YZ plane.

[0094] As used in embodiments of this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of semiconductor structure 200 (e.g., a three-dimensional memory) is determined relative to the substrate or source layer of semiconductor structure 200 in the first direction X, when the substrate or source layer SL is located in the lowest plane of semiconductor structure 200 in the first direction X. The same concepts are applied throughout the embodiments of this disclosure to describe spatial relationships.

[0095] In order to show the structure of the device more clearly, in Figure 1 The image shows a view of the core region CA and a view of the connecting region SS. The view of the core region CA is based on the left coordinate system, while the view of the connecting region SS is based on the right coordinate system. That is, the view of the core region CA shows the cross-sectional structure along the Z direction, while the view of the connecting region SS shows the cross-sectional structure along the X direction.

[0096] See Figure 1 Some embodiments of this disclosure provide a three-dimensional memory 1000. The three-dimensional memory 1000 may include a semiconductor structure 200. The semiconductor structure 200 may include a source layer SL and an array interconnect layer 290. The three-dimensional memory 1000 may also include peripheral devices 100 coupled to the semiconductor structure 200. The peripheral devices 100 may be disposed on the side of the array interconnect layer 290 away from the source layer SL.

[0097] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0098] Semiconductor structure 200 may include arrayed strings of memory cell transistors (referred to herein as “memory cell string 400”, such as NAND memory cell strings). Source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0099] See also Figure 1 In some embodiments, the array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor in the memory cell string 400.

[0100] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT, drain select gate contacts, and gate line contacts. The bit line contacts BL-CNT are coupled to bit lines, the drain select gate contacts are coupled to drain select gates, and the gate line contacts are coupled to the gate layer. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of interconnect lines, such as bit lines, and word line interconnect lines coupled to word lines. The materials of the first interconnect conductor layers 291 and the contacts may include conductive materials, such as tungsten, cobalt, copper, aluminum, and one or more combinations of metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, or other suitable materials.

[0101] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device (e.g., semiconductor structure 200), including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0102] For example, in some embodiments, peripheral device 100 may include substrate 110, transistor 120 disposed on substrate 110, and peripheral interconnect layer 130 disposed on substrate 110. Peripheral circuitry may include transistor 120. The material of substrate 110 may include monocrystalline silicon, or other suitable materials, such as silicon-germanium, germanium, or silicon-on-insulator thin film.

[0103] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may include conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 includes insulating materials, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0104] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor structure 200 and the peripheral device 100. In some examples, because the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, peripheral circuitry in the peripheral device 100 can be coupled to the memory cell string in the semiconductor structure 200 to enable the transmission of electrical signals between the peripheral circuitry and the memory cell string. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, allowing the peripheral interconnect layer 130 and the array interconnect layer 290 to be bonded and coupled together.

[0105] This disclosure also provides a semiconductor structure 200 in some embodiments, which can serve as the semiconductor structure 200 in the aforementioned three-dimensional memory 1000, or the semiconductor structure 200 can serve as the aforementioned three-dimensional memory 1000. In the embodiments of this disclosure, a first direction X, a second direction Y, and a third direction Z are defined, wherein the second direction Y is perpendicular to the third direction Z, and the first direction X intersects the plane containing the second direction Y and the third direction Z. For ease of explanation, this disclosure establishes a coordinate system in which the first direction X, the second direction Y, and the third direction Z are mutually perpendicular. The following description, in conjunction with... Figures 2 to 8 The semiconductor structures 200 and 200 in some embodiments are explained and described.

[0106] Figure 2 This is a top view of a semiconductor structure 200 according to some embodiments. Figure 3 for Figure 2 Cross-sectional view of AA. Please refer to... Figure 1 , Figure 2 and Figure 3 In some embodiments, the semiconductor structure 200 includes a gate stack structure 10 and a gate isolation structure 20. The gate stack structure 10 includes a plurality of gate layers 11 and a plurality of dielectric layers 12 alternately stacked along a first direction X.

[0107] Here, alternating stacking means that the gate layer 11 and the dielectric layer 12 are stacked and arranged alternately. For example, along the direction from the bottom layer to the top layer of the gate stack structure 10, a dielectric layer 12 is first disposed, then a gate layer 11 is disposed on the dielectric layer 12, and then another dielectric layer 12 is disposed on the gate layer 11, and so on, to form the gate stack structure 10.

[0108] The specific number of stacked gate layer 11 / dielectric layer 12 can be set according to the actual situation. Gate layer 11 can be made of conductive material, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide, or other suitable conductive material.

[0109] The dielectric layer 12 may be made of an insulating material, which may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride and high dielectric constant insulating materials, or other suitable insulating materials.

[0110] Continue to refer to Figure 2 and Figure 3 The gate isolation structure 20 is located along the first direction X through the gate stack structure 10, the gate stack structure 10 is located on both sides of the gate isolation structure 20 along the second direction Y, and the gate isolation structure 20 extends along the third direction Z. The gate isolation structure 20 includes a plurality of first isolation structures 21 and at least one second isolation structure 22. For example, the gate isolation structure 20 may include a plurality of first isolation structures 21 and a second isolation structure 22, or the gate isolation structure 20 may include a plurality of first isolation structures 21 and a plurality of second isolation structures 22.

[0111] In this configuration, multiple first isolation structures 21 are arranged at intervals along the third direction Z. A second isolation structure 22 is located between two adjacent first isolation structures 21 along the third direction Z. For example, when the gate isolation structure 20 includes multiple second isolation structures 22, each second isolation structure 22 is located between two adjacent first isolation structures 21 along the third direction Z, and only one second isolation structure 22 is disposed between two adjacent first isolation structures 21 along the third direction Z. This can be understood as the multiple first isolation structures 21 and the multiple second isolation structures 22 being alternately arranged along the third direction Z.

[0112] In some examples, the first isolation structure 21 can be made of an insulating material, and the first isolation structure 21 can be a pillar-like structure extending through the gate stack structure 10 along the first direction X. In this case, the first isolation structure 21 can be integrally formed, meaning that a complete structure is formed in a single process. In other examples, the first isolation structure 21 can be made of an insulating material and a semiconductor material. For example, the first isolation structure 21 may include a semiconductor pillar extending through the gate stack structure 10 along the first direction X and a third insulating layer, the third insulating layer being located between the semiconductor pillar and the gate stack structure 10, and the third insulating layer being disposed around the semiconductor pillar. The constituent material of the semiconductor pillar may, for example, include polysilicon. The constituent material of the third insulating layer may, for example, include silicon oxide. Since semiconductor materials generally have greater stress than insulating materials, when the first isolation structure 21 is composed of a semiconductor pillar and a third insulating layer, it is beneficial to improve the structural stability and structural strength of the first isolation structure 21.

[0113] The composition of the second isolation structure 22 can be referenced from the example of the first isolation structure 21 described above, and will not be repeated here.

[0114] The second isolation structure 22 has a first end 221 and a second end 222 arranged along the third direction Z. That is, the two ends of the second isolation structure 22 along the third direction Z are the first end 221 and the second end 222, respectively.

[0115] The gate isolation structure 20 also includes a first insulating layer 23 and a second insulating layer 24 arranged along the third direction Z. The first insulating layer 23 is located between the first isolation structure 21 and the first end 221, and the second insulating layer 24 is located between the first isolation structure 21 and the second end 222. Furthermore, both the first insulating layer 23 and the second insulating layer 24 can penetrate the gate stack structure 10 along the first direction X.

[0116] For example, the constituent materials of the first insulating layer 23 / second insulating layer 24 may include insulating materials, which may be as described in the above embodiments and will not be repeated here. Furthermore, the constituent materials of the first insulating layer 23 and the second insulating layer 24 may be the same; for example, both the first insulating layer 23 and the second insulating layer 24 may be composed of silicon oxide.

[0117] In this embodiment, both the first insulating layer 23 and the second insulating layer 24 penetrate the gate stack structure 10 along the first direction X. The spacing between the first insulating layer 23 and the second insulating layer 24 can be adjusted according to structural requirements. The first insulating layer 23 and the second insulating layer 24 can prevent the gate stack structure 10 located on both sides of the gate isolation structure 20 along the second direction Y from bending towards the gate isolation structure 20. The first insulating layer 23 and the second insulating layer 24 can provide support for the gate stack structure 10, thereby supporting and reinforcing the gate stack structure 10, thus improving the bending or tilting problem of the gate stack structure 10, which is beneficial for reinforcing the semiconductor structure 200 and improving the stability of the semiconductor structure 200.

[0118] Furthermore, the semiconductor structure 200 may include a plurality of first insulating layers 23 and a plurality of second insulating layers 24. The number of first insulating layers 23 and the number of second insulating layers 24 may be the same or different. This disclosure does not limit the number of first insulating layers 23 / second insulating layers 24. When the semiconductor structure 200 includes a plurality of first insulating layers 23 and a plurality of second insulating layers 24, the gate stack structure 10 can be further strengthened, which is beneficial to improving the stability of the semiconductor structure 200.

[0119] In some embodiments, reference Figure 2 , Figure 3 and Figure 4 The first insulating layer 23 includes a first arcuate surface 231 and a second arcuate surface 232 arranged along a third direction Z. The bending direction of the first arcuate surface 231 and the bending direction of the second arcuate surface 232 are the same. Therefore, the first insulating layer 23 is a curved structure extending along a first direction X and bending along a third direction Z. For example... Figure 4 In the middle, the first insulating layer 23 is bent along the third direction Z, thereby forming a first arc-shaped surface 231 and a second arc-shaped surface 232 with the same bending direction.

[0120] Continue to refer to Figure 4 The second insulating layer 24 includes a third arcuate surface 241 and a fourth arcuate surface 242 arranged along the third direction Z. The bending directions of the third arcuate surface 241 and the fourth arcuate surface 242 are the same, and the bending direction of the third arcuate surface 241 is opposite to that of the first arcuate surface 231. Therefore, the second insulating layer 24 is also a curved structure extending along the first direction X and bending along the third direction Z. For example... Figure 4 In the middle, the second insulating layer 24 is bent along the third direction Z, thereby forming a third arcuate surface 241 and a fourth arcuate surface 242 with the same bending direction. The bending direction of the third arcuate surface 241 and the fourth arcuate surface 242 is opposite to the bending direction of the first arcuate surface 231 and the second arcuate surface 232.

[0121] For example, in the YZ plane, it can be observed that the first insulating layer 23 has a certain thickness, and the thickness of the first support can be approximately uniform at various points. Therefore, the first insulating layer 23, bent along the third direction Z, has a first arcuate surface 231 and a second arcuate surface 232 arranged along the third direction Z and bending in the same direction. Similarly, in the YZ plane, the second insulating layer 24 also has a certain thickness, and the thickness of the second insulating layer 24 can be approximately uniform at various points. Therefore, the second insulating layer 24, bent along the third direction Z, has a third arcuate surface 241 and a fourth arcuate surface 242 arranged along the third direction Z and bending in the same direction. The bending direction of the first insulating layer 23 is opposite to the bending direction of the second insulating layer 24, and the bending directions of the third arcuate surface 241 and the fourth arcuate surface 242 are opposite to the bending directions of the first arcuate surface 231 and the second arcuate surface 232.

[0122] In some examples, Figure 4 The diagram shows a first isolation structure 21 (left), a second isolation structure 22, and a third isolation structure 21 (right) sequentially configured towards Z. Based on... Figure 4 As shown in the orientation or positional relationship, the two first isolation structures 21 are located on the left and right sides of the second isolation structure 22 along the third direction Z. The curvature direction of the first arc-shaped surface 231 and the second arc-shaped surface 232 is from the left first isolation structure 21 towards the second isolation structure 22, and the center of the arc of the first arc-shaped surface 231 and the center of the arc of the second arc-shaped surface 232 are both located within the left first isolation structure 21. The curvature direction of the third arc-shaped surface 241 and the fourth arc-shaped surface 242 is from the right first isolation structure 21 towards the second isolation structure 22, and the center of the arc of the third arc-shaped surface 241 and the center of the arc of the fourth arc-shaped surface 242 are both located within the right first isolation structure 21. This forms a first insulating layer 23 and a second insulating layer 24 with opposite curvature directions.

[0123] In other examples, Figure 5 The diagram shows a first isolation structure 21 (left), a second isolation structure 22, and a third isolation structure 21 (right) sequentially configured towards Z. Based on... Figure 5As shown in the orientation or positional relationship, the two first isolation structures 21 are located on the left and right sides of the second isolation structure 22 along the third direction Z. The curvature direction of the first arc-shaped surface 231 and the second arc-shaped surface 232 is from the second isolation structure 22 towards the first isolation structure 21 on the left, and the centers of the arcs of the first and second arc-shaped surfaces 231 and 232 are both located within the second isolation structure 22. The curvature direction of the third and fourth arc-shaped surfaces 241 and 242 is from the second isolation structure 22 towards the first isolation structure 21 on the right, and the centers of the arcs of the third and fourth arc-shaped surfaces 241 and 242 are both located within the second isolation structure 22. The first insulating layer 23 and the second insulating layer 24 are located on the two sides of the second isolation structure 22 along the third direction Z, and the centers of the arcs of the first, second, third, and fourth arc-shaped surfaces 231, 232, 241, and 242 are all located within the second isolation structure 22, thus forming first insulating layers 23 and 24 with opposite curvature directions.

[0124] In this embodiment, the first insulating layer 23 and the second insulating layer 24 can support and reinforce the gate stack structure 10, thereby improving the bending or tilting problem of the gate stack structure 10, which is beneficial to strengthening the semiconductor structure 200 and improving the stability of the semiconductor structure 200.

[0125] In some embodiments, reference Figure 4 The first insulating layer 23 and the second insulating layer 24 have a minimum spacing d1 in the third direction Z, and the ends of the first insulating layer 23 and the second insulating layer 24 in the second direction Y have a first spacing d2 in the third direction Z, the first spacing d2 being greater than the minimum spacing d1.

[0126] The first insulating layer 23 has two ends in the second direction Y, and the second insulating layer 24 also has two ends in the second direction Y. In this embodiment, the ends of the first insulating layer 23 and the ends of the second insulating layer 24 in the second direction Y are located on the same side of the first isolation structure 21 in the second direction Y. For example, in Figure 4 On the YZ plane shown, the first spacing d2 can be the spacing between the lower end of the first insulating layer 23 and the lower end of the second insulating layer 24, or the first spacing d2 can be the spacing between the upper end of the first insulating layer 23 and the upper end of the second insulating layer 24. Alternatively, it can be understood that the end of the first insulating layer 23 in the second direction Y and the end of the second insulating layer 24 in the second direction Y correspond to each other in the third direction Z, then the spacing between these two ends is the first spacing d2.

[0127] In this embodiment, d2 is greater than d1. Therefore, both the first insulating layer 23 and the second insulating layer 24 can be curved structures, and both the first insulating layer 23 and the second insulating layer 24 are bent inwards towards the second isolation structure 22 to better fit the sidewall shape of the first isolation structure 21. This facilitates the attachment of the first insulating layer 23 / second insulating layer 24 to the sidewall of the first isolation structure 21. The close fit between the structural shapes of the first isolation structure 21, the first insulating layer 23, and the second insulating layer 24 helps improve the stability of the semiconductor structure 200.

[0128] Furthermore, the first insulating layer 23 and the second insulating layer 24 can also support and reinforce the gate stack structure 10, thereby improving the bending or tilting problem of the gate stack structure 10, which is beneficial to strengthening the semiconductor structure 200 and further improving the stability of the semiconductor structure 200.

[0129] In some embodiments, the first insulating layer 23 and the second insulating layer 24 are symmetrically arranged with respect to the second isolation structure 22.

[0130] "Symmetrical arrangement" refers to the absolute or approximate symmetry between the first insulating layer 23 and the second insulating layer 24 with respect to the second isolation structure 22. Approximate symmetry can be understood as the first insulating layer 23 and the second insulating layer 24 exhibiting a symmetrical trend with respect to the second isolation structure 22. Local variations exist between the first insulating layer 23 and the second insulating layer 24; for example, the dimensions of the first insulating layer 23 and the second insulating layer 24 along their bending direction may differ, and the fluctuation range of this difference should not exceed an error threshold. This error threshold is determined by the limitations of measurement systems in this field, and this disclosure does not limit the specific value of the error threshold.

[0131] In this embodiment, by setting a symmetrical first insulating layer 23 and a second insulating layer 24, it is beneficial to improve the supporting and reinforcing effect on the gate stack structure 10, thereby improving the bending or tilting problem of the gate stack structure 10, which is beneficial to strengthening the semiconductor structure 200 and further improving the stability of the semiconductor structure 200.

[0132] In some embodiments, such as Figure 4 and Figure 6 As shown, the first insulating layer 23 and the second insulating layer 24 are symmetrically arranged about the second isolation structure 22, and the first insulating layer 23, the second isolation structure 22, and the second insulating layer 24 can together form an insulating structure 25. The gate isolation structure 20 includes a plurality of insulating structures 25 arranged at intervals along the third direction Z.

[0133] It should be noted that the spacing between adjacent insulating structures 25 along the third direction Z can be the same, or the spacing between adjacent insulating structures 25 along the third direction Z can be different, and this disclosure does not impose any restrictions on this.

[0134] The gate isolation structure 20, by setting multiple insulating structures 25 arranged at Z intervals along the third direction, helps to strengthen the support of the gate stack structure 10, thereby improving the bending or tilting problem of the gate stack structure 10, which helps to strengthen the semiconductor structure 200 and further improve the stability of the semiconductor structure 200.

[0135] In some embodiments, reference Figure 4 Both the first end 221 and the second end 222 of the second isolation structure 22 have concave surfaces 223. This can be understood as both the first end 221 and the second end 222 having curved surfaces that are recessed into the second isolation structure 22. The first insulating layer 23 is located between the concave surface 223 of the first end 221 and the first isolation structure 21, and the second insulating layer 24 is located between the concave surface 223 of the second end 222 and the first isolation structure 21. The first insulating layer 23 can cover the concave surface 223 of the first end 221, thus the first insulating layer 23 can have a first arcuate surface 231 and a second arcuate surface 232 with the same bending direction. The second insulating layer 24 can cover the concave surface 223 of the second end 222, thus the second insulating layer 24 can have a third arcuate surface 241 and a fourth arcuate surface 242 with the same bending direction.

[0136] For example, the concave surface 223 of the first end 221 and the concave surface 223 of the second end 222 can be centrally symmetrically arranged. In this case, the first insulating layer 23 and the second insulating layer 24 can also be symmetrically arranged with respect to the second isolation structure 22.

[0137] With the above configuration, the first insulating layer 23 and the second isolation structure 22 can be tightly bonded, and the second insulating layer 24 and the second isolation structure 22 can also be tightly bonded, which is beneficial to improving the structural stability of the gate isolation structure 20.

[0138] In some embodiments, the maximum dimension d3 of the second isolation structure 22 in the second direction Y is greater than the maximum dimension d4 of the first isolation structure 21 in the second direction Y.

[0139] In this embodiment, the maximum dimension d3 of the second isolation structure 22 in the second direction Y can be understood as the maximum width of the second isolation structure 22 in the second direction Y. The maximum dimension d4 of the first isolation structure 21 in the second direction Y can be understood as the maximum width of the first isolation structure 21 in the second direction Y.

[0140] With the above settings, it can be ensured that the first isolation structure 21, the first insulating layer 23, the second isolation structure 22 and the second insulating layer 24 are all connected from top to bottom along the first direction X, so that the gate isolation structure 20 penetrates the gate stack structure 10 along the first direction X, thereby dividing the gate stack structure 10 into two regions. The two regions are not connected, which is beneficial for the semiconductor structure 200 to read / store data in different regions.

[0141] In some embodiments, reference Figure 3 The second isolation structure 22 includes a main body 224 and an isolation layer 225. The main body 224 penetrates the gate stack structure 10 along the first direction X. The isolation layer 225 is located between the main body 224 and the gate stack structure 10. The isolation layer 225 is also located between the main body 224 and the first insulating layer 23, and the isolation layer 225 is disposed around the main body 224. Similarly, the first isolation structure 21 can also refer to the structural composition of the second isolation structure 22.

[0142] For example, the material comprising the isolation layer 225 may include an insulating material, such as silicon oxide. The material comprising the body 224 may include a semiconductor material, such as polysilicon. Since the strength of a semiconductor material is greater than that of an insulating material, the structural strength of the second isolation structure 22 composed of the isolation layer 225 and the body 224 is greater than that of the second isolation structure 22 composed of a single insulating material, which is beneficial to improving the stability of the gate isolation structure 20.

[0143] In this embodiment, the semiconductor structure 200 may include a core region CA and a connection region SS adjacent along a third direction Z. The core region CA has a storage function. Exemplarily, the semiconductor structure 200 may include multiple channel structures 30, which penetrate the gate stack structure 10 along a first direction X. The multiple channel structures 30 are arranged in multiple rows and columns along a third direction Z and a second direction Y, and each channel structure 30 penetrates the gate stack structure 10 along the first direction X. Exemplarily, some channel structures 30 may be located in the core region CA, and some channel structures 30 may be located in the connection region SS.

[0144] In some embodiments, the channel structure 30 located in the core region CA can be used to store data. For example, the channel structure 30 can be generally columnar, such as an oxide-nitride-oxide-polysilicon (OxiDe-NitriDe-OxiDe-Poly, ONOP) structure stacked sequentially. In this case, the material of the channel barrier layer can include, for example, silicon oxide, the material of the storage layer can include, for example, silicon nitride, the material of the tunneling layer can include, for example, silicon oxide, and the material of the channel layer can include, for example, polysilicon. In the above steps, thin film deposition processes such as CVD, PVD, or ALD can also be used to form a filling layer, such as silicon oxide, in the channel holes where the storage layer and the channel layer are formed. The channel structure 30 having the channel barrier layer, storage layer, tunneling layer, channel layer, and filling layer can be called an "ONOPO" structure. The gate layer 11 is used to control the channel structure 30. The gate layer 11 can be led out to the corresponding control circuit in the connection region SS to realize functions such as read, erase, write, and program.

[0145] For example, the number of rows of the channel structure 30 located in the core region CA can be greater than the number of rows of the channel structure 30 located in the connection region SS, so as to facilitate the semiconductor structure 200 to read and write data.

[0146] In some other embodiments, the channel structure 30 located in the connection region SS may include a virtual channel structure 30. Of course, in other embodiments, multiple virtual channel structures 30 may also be located in the core region CA; this embodiment does not impose such limitations. The virtual channel structure 30 may be the same as or different from the channel structure 30; this embodiment does not impose such limitations. It should be noted that the virtual channel structure 30 may not actually be used as a storage unit, but rather serves to provide mechanical support and / or load balancing for the semiconductor structure 200.

[0147] In this embodiment, the gate isolation structure 20 extends along the third direction Z and penetrates the gate stack structure 10 located in the core region CA and the gate stack structure 10 located in the connection region SS, thereby isolating the gate stack structure 10 to facilitate reading / storing data in different regions.

[0148] In this embodiment, the isolation layer 225 of the second isolation structure 22 contacts part of the sidewall of the channel structure 30. The first isolation structure 21 does not contact the channel structure 30. Therefore, the maximum dimension d3 of the second isolation structure 22 in the second direction Y is greater than the maximum dimension d4 of the first isolation structure 21 in the second direction Y. This ensures that the first isolation structure 21, the first insulating layer 23, the second isolation structure 22, and the second insulating layer 24 are all connected from top to bottom along the first direction X. This allows the gate isolation structure 20 to penetrate the gate stack structure 10 along the first direction X and penetrate the core region CA and the connection region SS of the semiconductor structure 200 along the third direction Z, thereby dividing the gate stack structure 10 into two regions that are not connected. This facilitates the semiconductor structure 200 to read / store data in separate regions.

[0149] In some embodiments, the first insulating layer 23 and the second insulating layer 24 are located only in the core region. By providing the first insulating layer 23 and the second insulating layer 24, the bending phenomenon of the gate stack structure 10 located in the core region is improved, thereby strengthening the gate stack structure 10 and improving the stability of the semiconductor structure 200.

[0150] In other embodiments, the semiconductor structure 200 includes a plurality of first insulating layers 23 and a plurality of second insulating layers 24, with portions of the first insulating layers 23 and portions of the second insulating layers 24 located in the core region and portions of the first insulating layers 23 and portions of the second insulating layers 24 located in the connection region.

[0151] Exemplarily, the first insulating layer 23 and the second insulating layer 24 may appear in pairs. For example, a first insulating layer 23, a second isolation structure 22, and a second insulating layer 24 may constitute an insulating structure 25. The semiconductor structure 200 may include a plurality of insulating structures 25 spaced apart along a third direction Z. Some insulating structures 25 are located in the core region, and some insulating structures 25 are located in the connection region.

[0152] With the above configuration, the first insulating layer 23 and the second insulating layer 24 can improve the bending phenomenon of the gate stack structure 10 located in the core region and the connection region, thereby strengthening the gate stack structure 10 and improving the stability of the semiconductor structure 200.

[0153] In some embodiments, reference Figure 3The semiconductor structure 200 further includes a semiconductor layer 40, which may be located on one side of the gate stack structure 10 along the first direction X. The gate isolation structure 20 also penetrates the semiconductor layer 40 along the first direction X, and the channel structure 30 also penetrates the semiconductor layer 40 along the first direction X. In this case, the semiconductor layer 40 also penetrates part of the gate isolation structure 20. In this embodiment, the gate isolation structure 20 has sidewalls arranged along the second direction Y. The sidewalls of the gate isolation structure 20 have recesses, and the semiconductor layer 40 extends to the recesses. The orthographic projection of the semiconductor layer 40 in the first direction X overlaps with the orthographic projection of the gate isolation structure 20 in the first direction X.

[0154] By providing a semiconductor layer 40 on one side of the gate stack structure 10 along the first direction X, it is beneficial to protect the gate stack structure 10 from damage when the channel structure 30 is led out.

[0155] In other embodiments, the semiconductor structure 200 does not have a semiconductor layer 40. In this case, the gate isolation structure 20 has sidewalls arranged along the second direction Y, and the sidewalls of the gate isolation structure 20 extend along the first direction X. The sidewalls of the gate isolation structure 20 are flat and do not have depressions. This helps to improve the regularity of the gate isolation structure 20, thereby improving the stability of the semiconductor structure 200.

[0156] This disclosure also provides a method for fabricating a semiconductor structure 200 in some embodiments, which will be described below in conjunction with... Figures 8 to 53 The preparation method of a semiconductor structure 200 is explained.

[0157] like Figure 8 As shown, the method for fabricating the semiconductor structure 200 includes: S1 to S2.

[0158] S1. Forming multiple gate stack structures, the gate stack structures including multiple gate layers and multiple dielectric layers alternately arranged along a first direction, the multiple gate stack structures being arranged along a second direction.

[0159] refer to Figure 9 The first stacked structure 50 can be formed by sequentially depositing multiple sacrificial layers 52 and multiple dielectric layers 12 alternately arranged along the first direction X on the substrate 51 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0160] "Alternating arrangement" means that after forming a dielectric layer 12, a sacrificial layer 52 is formed on the dielectric layer 12, and then a dielectric layer 12 is formed on the sacrificial layer 52, and so on, the dielectric layer 12 and the sacrificial layer 52 are formed alternately to form the first stacked structure 50.

[0161] For example, the substrate 51 may be a single-crystal silicon (Si) substrate 51, a single-crystal germanium (Ge) substrate 51, a silicon-on-insulator (SOI) substrate 51, or a germanium-on-insulator (GOI) substrate 51, etc. Alternatively, the material of the substrate 51 may also be a compound semiconductor. For example, the substrate 51 may be a gallium arsenide (GaAs) substrate 51, an indium phosphide (InP) substrate 51, or a silicon carbide (SiC) substrate 51, etc. Or, the substrate 51 may also be made of other semiconductor materials commonly used in the art, which is not limited in this embodiment.

[0162] For example, both the constituent materials of the dielectric layer 12 and the constituent materials of the sacrificial layer 52 can be insulating materials. The insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride), and this disclosure is not limited to these embodiments.

[0163] It is worth noting that the dielectric layer 12 is made of a different material than the sacrificial layer 52. For example, the dielectric layer 12 may be made of silicon oxide, while the sacrificial layer 52 may be made of silicon nitride. This arrangement allows for the selective removal of a portion of the sacrificial layer 52 in subsequent process steps.

[0164] In this embodiment, the substrate 51 can provide support for the fabrication of the first stacked structure 50. Alternatively, the substrate 51 can be removed in subsequent fabrication processes, thereby enabling the fabrication of other processes on the exposed first stacked structure 50.

[0165] In other embodiments, reference continues. Figure 9 Before forming the first stacked structure 50, a semiconductor layer 40 can be formed on the substrate 51 using CVD, PVD, ALD, or any combination thereof thin film deposition processes. The constituent materials of the semiconductor layer 40 may include semiconductor materials, such as any suitable semiconductor material such as polycrystalline silicon.

[0166] refer to Figures 10 to 33 After the first stacked structure 50 is formed, a gate spacer 55 can be formed (see reference). Figure 31 The gate spacer 55 extends through the first stacked structure 50 along the first direction X, and the gate spacer 55 extends along the third direction Z.

[0167] In some embodiments, reference Figure 9 and Figure 10 A photoresist is applied to one side surface of the prepared first stacked structure 50 to form a photoresist pattern, and an etching pattern is formed on the first stacked structure 50 using the photoresist pattern. The first stacked structure 50 is etched using the etching pattern to form a plurality of vias 53 penetrating the first stacked structure 50 along the first direction X, and the plurality of vias 53 are spaced apart along the third direction Z.

[0168] For example, photoresist can be applied using suitable methods such as static spin coating or dynamic spray coating. Alternatively, a dry etching process can be used to etch the first stacked structure 50.

[0169] refer to Figure 10 , Figure 11 and Figure 12 Insulating material can be deposited in the via 53 using CVD, PVD, ALD or any combination thereof thin film deposition processes to form sacrificial pillars 54, and a portion of the sacrificial pillars 54 can be replaced with channel structures 30.

[0170] As a feasible implementation method, continue to refer to Figure 10 , Figure 11 and Figure 12 The sacrificial pillars 54 can be partially removed using either dry etching or wet etching to expose the vias 53. Furthermore, a channel barrier layer, a storage layer, a tunneling layer, a channel layer, and a filling layer can be sequentially deposited within the partially exposed vias 53 using CVD, PVD, ALD, or any combination thereof thin film deposition processes to form the channel structure 30.

[0171] In this step, the channel structure 30 and the sacrificial pillar 54 can be fabricated in the same fabrication process, which can reduce the number of masks required in the fabrication process, thereby improving the fabrication efficiency and reducing the fabrication cost of the semiconductor structure 200.

[0172] refer to Figure 10 , Figure 11 , Figure 12 and Figure 13 After forming the channel structure 30, a photoresist layer can be applied to one side surface of the first stacked structure 50 using a suitable method such as static spin coating or dynamic spray coating to form a photoresist pattern. An etching pattern is then formed on the first stacked structure 50 using the photoresist pattern. The remaining sacrificial pillars 54 are etched using the etching pattern to expose the remaining vias 53. For example, when the sacrificial pillars 54 are composed of carbon, the process for removing all sacrificial pillars 54 within the vias 53 may include ashing to remove all sacrificial pillars 54 within the vias 53.

[0173] refer to Figure 13 and Figure 14 An etchant is injected into some of the through-holes 53, making them interconnected to form a first partition 551 and a second partition 552 spaced apart along a third direction Z. For example, an acidic substance can be selected as the etchant. The etchant is injected into some of the through-holes 53, and the etchant can uniformly etch the hole walls (i.e., the first stacked structure 50), thereby connecting adjacent through-holes 53. It is worth noting that in this step, not all through-holes 53 are connected; some through-holes 53 need to be retained.

[0174] By injecting an etchant into some of the through holes 53, the first layered structure 50 between adjacent through holes 53 is removed, forming a first partition 551 and a second partition 552. Since the etchant removes the first layered structure 50 at a relatively uniform rate, it helps maintain the uniformity of the edges of the first partition 551 and the second partition 552. One or more through holes 53 are retained between the first partition 551 and the second partition 552.

[0175] In this step, refer to Figure 15 Multiple first partitions 551 and multiple second partitions 552 can be formed. The embodiments of this disclosure are explained by taking the formation of one first partition 551 and one second partition 552 as an example, but the number of first partitions 551 and second partitions 552 can be adapted to increase, and the embodiments of this disclosure do not limit this.

[0176] refer to Figure 14 , Figure 16 and Figure 17 After forming the first partition 551 and the second partition 552, sacrificial material can be filled into the first partition 551 and the second partition 552 using CVD, PVD, ALD, or any combination thereof thin film deposition processes to form the first sacrificial structure 5511 and the second sacrificial structure 5521, respectively. In this step, the sacrificial material is a semiconductor material, such as polycrystalline silicon.

[0177] refer to Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 After the first sacrificial structure 5511 and the second sacrificial structure 5521 are formed, the sacrificial pillar 54 in the through hole 53 located between the first partition 551 and the second partition 552 can be removed. (Refer to...) Figure 22 Since in some embodiments a semiconductor layer 40 is formed before the first stacked structure is formed, a portion of the semiconductor layer may also be exposed in the via 53.

[0178] Continue to refer to Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 and combined Figure 23 , Figure 24 , Figure 25 , Figure 26 and Figure 27 An etchant is injected into the through-hole 53 to form a third septum 553. The third septum 553 exposes a portion of the sidewall of the first sacrificial structure 5511, and also exposes a portion of the sidewall of the second sacrificial structure 5521. In some examples, refer to... Figure 25 and Figure 27 Part of the semiconductor layer 40 is also exposed in the third spacer 553.

[0179] Additionally, refer to Figure 24 and Figure 25 In some embodiments, before forming the first sacrificial structure in the first partition 551, a thin-film deposition process can be used to form a second sacrificial layer 555 on the sidewall of the first partition to protect the morphology of the first stacked structure. To expose the sidewalls of the first sacrificial structure 5511 and the second sacrificial structure 5521 in the third partition 553, refer to... Figure 24 , Figure 25 , Figure 26 and Figure 27 It is necessary to remove the second sacrificial layer 555 exposed in the third partition 553, so that the sidewalls of the first sacrificial structure 5511 and the sidewalls of the second sacrificial structure 5521 are exposed in the third partition 553.

[0180] In this step, an etching solution is injected into the through-hole 53 located between the first partition 551 and the second partition 552. For example, an acidic substance can be selected as the etching solution, which can uniformly etch the hole wall (i.e., the first stacked structure 50) of the through-hole 53, thereby enlarging the hole diameter of the through-hole 53. In some examples, because the etching solution uniformly etches the hole wall of the through-hole 53, in order to enable the third partition 553 to communicate with the first partition 551 and the second partition 552, the maximum dimension of the third partition 553 formed after this hole enlargement step in the second direction Y is greater than the maximum dimension of the first partition 551 in the second direction Y, and the maximum dimension of the third partition 553 in the second direction Y is greater than the maximum dimension of the second partition 552 in the second direction Y. Since the first partition 551 and the second partition 552 are formed in the same wet etching step, the maximum dimensions of the first partition 551 and the second partition 552 in the second direction Y are the same or approximately the same.

[0181] refer to Figure 28 , Figure 29 and Figure 30After the third partition 553 is formed, an anode oxidation process can be used to form a first insulating layer 23 on the sidewall of the first sacrificial structure 5511 and a second insulating layer 24 on a portion of the sidewall of the second sacrificial junction 5521 through the third partition 553. For example, oxygen is introduced into the third partition 553, and the oxygen reacts with the first sacrificial structure 5511 (polycrystalline silicon) to generate a silicon oxide film, thereby forming the first insulating layer 23. The oxygen also reacts with the second sacrificial structure 5521 (polycrystalline silicon) to generate a silicon oxide film, thereby forming the second insulating layer 24.

[0182] It should be noted that, generally, the through-hole 53 is a circular through-hole 53. During the hole enlargement step, the etching solution uniformly etches the hole wall of the through-hole 53. After the multiple circular through-holes 53 are enlarged and connected together, the hole walls of the first partition 551 and the second partition 552 formed after hole enlargement are similar in shape to a wave. Therefore, the sidewalls of the first sacrificial structure 5511 and the second sacrificial structure 5521 formed by filling the first partition 551 and the second partition 552 with sacrificial material are composed of multiple arc-shaped surfaces. Therefore, the first insulating layer 23 formed on the sidewall of the first sacrificial structure 5511 by the anodizing process is a curved structure, and the second insulating layer 24 formed on part of the sidewall of the second sacrificial structure 5521 is also a curved structure. Furthermore, the bending directions of the first insulating layer 23 and the second insulating layer 24 are opposite, and the first insulating layer 23 and the second insulating layer 24 can also be arranged in a centrally symmetrical manner.

[0183] In this step, refer to Figure 28 , Figure 29 and Figure 30 The first insulating layer 23 and the second insulating layer 24 are formed using anodizing, which allows for the formation of a certain thickness of the first insulating layer 23 and the second insulating layer 24 at specific locations. The via 53 has a relatively deep depth in the first direction X, meaning the third slot 553 also has a relatively deep depth in the first direction X. A combination of deposition and etching processes is used to form the first support layer and the second insulating layer 24, which is technically challenging and costly. The above steps help reduce the number of process steps, simplify the process, and lower the fabrication cost of the semiconductor structure 200.

[0184] In this embodiment, reference Figure 28 , Figure 29 and Figure 30 The first partition 551, the second partition 552, and the third partition 553 can form the gate partition 55, or together form a portion of the gate partition 55. Since the gate partition 55 penetrates the first stacked structure 50 along the first direction X, and the gate partition 55 penetrates the core region CA and the connection region SS along the third direction Z... Figure 28Only the gate spacer 55 located in the core region CA is shown. Therefore, the first stacked structure 50 located on both sides of the gate spacer 55 along the second direction Y may be subject to risks such as bending, tilting, or even short circuits towards the gate spacer 55. However, some embodiments of this disclosure prepare a first insulating layer 23 and a second insulating layer 24, both of which penetrate the first stacked structure 50 along the first direction X, thereby supporting the first stacked structure 50. In subsequent fabrication processes, this prevents the first stacked structure 50 from bending or tilting towards the gate spacer 55, which is beneficial to improving the stability and reliability of the first stacked structure 50.

[0185] In addition, in this embodiment, the spacing between the first insulating layer 23 and the second insulating layer 24 can be adjusted by changing the number of through holes 53 retained between the first partition 551 and the second partition 552. Adjusting the spacing between the first insulating layer 23 and the second insulating layer 24 according to process requirements helps to strengthen the support of the first stacked structure 50. Furthermore, the number of the first partition 551, the second partition 552, and the third partition 553 can be increased, thereby increasing the number of the first insulating layer 23 and the second insulating layer 24. By preparing multiple first insulating layers 23 and multiple second insulating layers 24, the support of the first stacked structure 50 is further strengthened, which helps to improve the stability and reliability of the first stacked structure 50.

[0186] refer to Figure 31 , Figure 32 and Figure 33 For example, after the first insulating layer 23 and the second insulating layer 24 are formed, sacrificial material can be filled in the third septum using CVD, PVD, ALD or any combination thereof thin film deposition process to facilitate the subsequent processing of other regions.

[0187] In other embodiments, reference is made to... Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 34 and Figure 35 After the first stacked structure 50 is formed, the first stacked structure 50 can be divided into a core region CA and a connecting region SS, and the core region CA and the connecting region SS are adjacent to each other along the third direction Z.

[0188] A portion of the first stacked structure 50 is removed using a wet etching process or a dry etching process, thereby forming multiple vias 53. The multiple vias 53 are arranged at intervals along the third direction Z, with some vias 53 located in the core region CA and some vias 53 located in the connection region SS.

[0189] After forming multiple vias 53, insulating material can be deposited in the vias 53 using CVD, PVD, ALD or any combination thereof thin film deposition processes to form sacrificial pillars 54, and some of the sacrificial pillars 54 can be replaced with channel structures 30 or virtual channel structures 30.

[0190] refer to Figure 34 , Figure 35 , Figure 36 , Figure 37 After the sacrificial pillar 54 is formed, a portion of the sacrificial pillar 54 can be removed. Then, the through hole 53 is enlarged to form the first partition groove 551 and the second partition groove 552. Specifically, refer to the embodiments described above; details will not be repeated here. For example, the first partition groove 551 (refer to...) Figure 31 ) and second partition 552 (reference) Figure 31 They can all be located in the core area CA.

[0191] refer to Figure 31 After the first sacrificial structure and the second sacrificial structure are formed in the first partition 551 and the second partition 552 respectively, an etching solution is injected into the through hole 53 located between the first partition 551 and the second partition 552 to form a third partition 553. The first insulating layer 23 and the second insulating layer 24 are formed through the third partition 553 and by a cathodic oxidation process. For details, please refer to some of the embodiments mentioned above, which will not be repeated here.

[0192] refer to Figure 38 , Figure 39 , Figure 40 and Figure 41 and combined Figure 31 After the sacrificial material is filled into the third septum 553, the sacrificial pillar 54 located in the connection area can be removed by etching process, thereby exposing the through hole 53.

[0193] Continue to refer to Figure 40 , Figure 41 , Figure 42 and Figure 43 An etchant is injected into the through-holes 53 located in the connection region, thereby connecting the multiple through-holes 53 in the connection region SS to form a fourth partition 554. The fourth partition 554 exposes part of the sidewall of the second sacrificial structure 5521.

[0194] In some embodiments, refer to 42. Figure 43 , Figure 44 and Figure 45A small amount of etching solution can be injected into the fourth partition 554 to remove a small amount of dielectric layer 12, thereby reducing the thickness of the dielectric layer 12 located on the wall of the fourth partition 554. This can be understood as the thickness of the end of the dielectric layer 12 exposed in the fourth partition 554 being reduced, thus forming a larger opening between adjacent dielectric layers 12, thereby exposing more of the sacrificial layer 52 in the fourth partition 554, so that the sacrificial layer 52 can be removed in subsequent fabrication processes.

[0195] Continue to refer to Figure 42 , Figure 43 , Figure 44 and Figure 45 After the fourth partition 554 is formed, a wet etching process can be used to remove part of the sacrificial layer 52 located in the connection region SS to form the first filling space 561. For example, a wet etching process can be used to inject etching solution into the fourth partition 554 to remove part of the sacrificial layer 52 located in the connection region SS.

[0196] In this embodiment, reference Figure 46 and Figure 47 After the fourth partition 554 is formed, an insulating layer 57 can be formed on a portion of the sidewall of the second sacrificial structure 5521 by using an anode oxidation process through the fourth partition 554. For example, oxygen can be introduced into the fourth partition 554, and the oxygen reacts with the second sacrificial structure 5521 to form silicon oxide, which forms the insulating layer 57.

[0197] In this step, an anode oxidation process is used to form the insulating layer 57, which can form an insulating layer 57 of a certain thickness at a specific location. The via 53 has a relatively deep depth in the first direction X, meaning the fourth spacer 554 also has a relatively deep depth in the first direction X. Forming the insulating layer 57 using a combination of deposition and etching processes is more difficult and costly. The above steps help reduce the number of process steps, simplify the process, and lower the fabrication cost of the semiconductor structure 200.

[0198] In this embodiment, reference Figure 31 and Figure 48 The first partition 551, the second partition 552, the third partition 553, and the fourth partition 554 are connected and together constitute the gate partition 55. As discussed above, the first stacked structure 50 located on both sides of the gate partition 55 along the second direction Y may be subject to risks such as bending, tilting, or even short circuits in the direction closer to the gate partition 55. However, some embodiments of this disclosure, by preparing the first insulating layer 23 and the second insulating layer 24, and further preparing the insulating layer, can further strengthen the support of the first stacked structure 50. In the subsequent preparation process, this prevents the first stacked structure 50 from bending or tilting in the direction closer to the gate partition 55, which is beneficial for reinforcing the semiconductor structure 200 and improving the stability and reliability of the first stacked structure 50.

[0199] It should be noted that the first insulating layer 23 and the second insulating layer 24 may be located in the core region CA, or the first insulating layer 23 and the second insulating layer 24 may be located in the connection region SS, or a portion of the first insulating layer 23 and a portion of the second insulating layer 24 may be located in the core region CA, and a portion of the first insulating layer 23 and a portion of the second insulating layer 24 may be located in the connection region SS.

[0200] In some other embodiments, reference is made to Figure 44 , Figure 45 , Figure 46 and Figure 47 A semiconductor layer 40 is disposed between the substrate 51 and the first stacked structure 50, and a portion of the semiconductor layer 40 is exposed in the fourth spacer 554. When oxygen is introduced into the fourth spacer 554, the surface of the semiconductor layer 40 exposed in the fourth spacer 554 is also oxidized, thereby forming a protective layer on the surface of the semiconductor layer 40. The material of the protective layer includes, for example, silicon oxide, to protect the semiconductor layer 40 from damage in subsequent fabrication processes.

[0201] It is worth noting that when the material of the protective layer is the same as that of the dielectric layer 12, for example, when both the material of the protective layer and the material of the dielectric layer 12 include silicon oxide, the step of forming the protective layer on the surface of the semiconductor layer 40 should be performed after the step of thinning the thickness of the dielectric layer 12, in order to prevent the protective layer from being accidentally removed.

[0202] refer to Figure 46 , Figure 47 , Figure 48 and Figure 49 After forming the first filling space 561, sacrificial material can be filled into the first filling space 561 and the fourth partition 554 using CVD, PVD, ALD, or any combination thereof thin film deposition processes. The sacrificial material can be, for example, carbon or polycrystalline silicon with doped ions. Experiments have shown that phosphorus-doped polycrystalline silicon can be selected as the sacrificial material. Phosphorus-doped polycrystalline silicon has a different etching rate than polycrystalline silicon, thus allowing the structural morphology of the semiconductor layer 40 to be removed without damaging it.

[0203] refer to Figure 48 , Figure 49 , Figure 50 and Figure 51 After the first filling space 561 is filled with sacrificial material, the fourth slot can be filled with sacrificial material, such as photoresist, to facilitate subsequent etching of other areas.

[0204] refer to Figure 50 , Figure 51 , Figure 53 and Figure 53 and combined Figure 31 After the first filling space 561 is filled with sacrificial material, an etching process can be used to remove the first sacrificial structure 5511 and the second sacrificial structure 5521, thereby exposing the first septum 551, the second septum 552, and the third septum 553. Further etching is then used through the first septum 551, the second septum 552, and the third septum 553 to remove the sacrificial layer 52 located in the core region CA (see reference). Figure 12 ), to form a second filling space 562.

[0205] For example, a wet etching process can be used in this step to remove the sacrificial layer 52 located in the core region CA by injecting etching solution into the first septum 551, the second septum 552 and the third septum 553.

[0206] It should be noted that the sacrificial material filling the first filling space 561 is different from the material of the sacrificial layer 52. For example, the sacrificial material filling the first filling space 561 may include polysilicon or carbon, while the material of the sacrificial layer 52 may include nitrides, such as silicon nitride. With this configuration, the sacrificial material filling the first filling space 561 in this step can protect the sacrificial layer 52 located in the connection region SS from being removed.

[0207] Continue to refer to Figure 50 , Figure 51 , Figure 53 and Figure 53 After the second filling space 562 is formed, a wet etching process can be used to remove the sacrificial material located in the fourth partition. Then, the sacrificial material located in the first filling space 561 is removed through the fourth partition 554, so that the first filling space 561, the second filling space 562 and the gate partition 55 are connected.

[0208] For example, when the sacrificial material located in the first filling space 561 includes carbon, the process for removing the sacrificial material located in the first filling space 561 may include ashing.

[0209] refer to Figure 52 and combined Figure 3 After removing the sacrificial material located in the first filling space 561, a gate layer 11 is formed in the first filling space 561 and the second filling space 562 through the gate spacer 55.

[0210] For example, conductive materials, such as tungsten metal, can be deposited in the first filled space 561 and the second filled space 562 using CVD, PVD, ALD, or any combination thereof thin film deposition processes to form the gate layer 11, thereby forming the gate stack structure 10.

[0211] Through the above process steps, the sacrificial layer 52 can be removed in sections, and the gate layer 11 can be formed through a single filling process. This facilitates the formation of different gate layer 11 morphologies in the core region CA and the connection region SS, enabling the formation of a memory array in the core region CA and facilitating the extraction of the gate layer 11 in the connection region SS. Furthermore, during the above process, the first insulating layer 23 and the second insulating layer 24 can provide support for the first stacked structure 50, preventing the first stacked structure 50 from bending and improving the stability of the first stacked structure 50.

[0212] S2. A gate isolation structure is formed, which extends through the gate stack structure along a first direction and extends along a third direction. The gate isolation structure includes a plurality of first isolation structures and at least one second isolation structure. The plurality of first isolation structures are arranged along the third direction, and the second isolation structure is located between two adjacent first isolation structures along the third direction. The second isolation structure has a first end and a second end arranged along the third direction. The gate isolation structure also includes a first insulating layer and a second insulating layer arranged along the third direction. The first insulating layer is located between the first isolation structure and the first end, and the second insulating layer is located between the first isolation structure and the second end. The second direction is perpendicular to the third direction, and the first direction intersects the plane containing the second direction and the third direction.

[0213] In this step, refer to Figure 52 and combined Figure 2 and Figure 3 An isolation layer 225 and a body 224 can be formed by sequentially depositing an isolation material and a semiconductor material in the gate spacer 55 using CVD, PVD, ALD, or any combination thereof thin film deposition processes. The body 224 penetrates the gate stack structure 10 along the first direction X. The isolation layer 225 is located between the body 224 and the gate stack structure 10, and is disposed around the body 224. The isolation layer 225 and the body 224 located in the first spacer 551, the second spacer 552, and the fourth spacer 554 together constitute the first isolation structure 21. The isolation layer 225 and the body 224 located in the third spacer 553 together constitute the second isolation structure 22.

[0214] The first insulating layer 23 and the second insulating layer 24 formed in step S1 are retained in the final structure. The first insulating layer 23 is located between the first isolation structure 21 and the first end 221, and the second insulating layer 24 is located between the first isolation structure 21 and the second end 222.

[0215] The semiconductor structure 200 prepared through the above embodiments has its first isolation structure 21 and second isolation structure 22 of the gate isolation structure 20 prepared in a single process, which helps to reduce preparation steps and improve preparation efficiency. Furthermore, during the preparation of the semiconductor structure 200, the preparation of the first insulating layer 23 and the second insulating layer 24 helps to prevent the first stacked structure 50 from bending towards the gate trench 55 during preparation, thus improving the stability and reliability of the first stacked structure 50.

[0216] Furthermore, in addition to the first insulating layer 23 and the second insulating layer 24, additional insulating layers can be added to further prevent the first stacked structure 50 from bending, tilting, and short-circuiting, thereby improving the stability and reliability of the semiconductor structure 200. Moreover, the above fabrication process does not require additional board opening or additional processes, which helps reduce fabrication difficulty and offers a cost advantage.

[0217] Figure 54 This is a block diagram of a storage system according to some embodiments. Figure 55 This is a block diagram of a storage system according to some other embodiments.

[0218] Please see Figure 54 and Figure 55 Some embodiments of this disclosure also provide a storage system 2000. The storage system 2000 includes a controller 2100 and a three-dimensional memory 1000 as described in some of the embodiments above. The controller 2100 is coupled to the three-dimensional memory 1000 to control the three-dimensional memory 1000 to store data. The three-dimensional memory 1000 includes the semiconductor structure 200 as described in some of the embodiments above.

[0219] The storage system 2000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 2000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0220] In some embodiments, see Figure 54The storage system 2000 includes a controller 2100 and a three-dimensional memory 1000, and the storage system 2000 can be integrated into a memory card.

[0221] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0222] In other embodiments, see Figure 55 The storage system 2000 includes a controller 2100 and multiple three-dimensional storage devices 1000, and the storage system 2000 is integrated into a solid state drive (SSD).

[0223] In some embodiments of the storage system 2000, the controller 2100 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0224] In other embodiments, the controller 2100 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0225] In some embodiments, controller 2100 may be configured to manage data stored in 3D memory 1000 and communicate with external devices (e.g., a host). In some embodiments, controller 2100 may also be configured to control operations of 3D memory 1000, such as read, erase, and program operations. In some embodiments, controller 2100 may also be configured to manage various functions relating to data stored or to be stored in 3D memory 1000, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 2100 is also configured to process error correction codes relating to data read from or written to 3D memory 1000.

[0226] Of course, the controller 2100 can also perform any other suitable functions, such as formatting the three-dimensional memory 1000; for example, the controller 2100 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0227] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0228] Since the three-dimensional memory 1000 includes the semiconductor structure 200 provided in some of the above embodiments, the memory system 2000 also has good stability and reliability.

[0229] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0230] The electronic device may include the storage system 2000 described above, and may also include at least one of a central processing unit (CPU) and a cache. If the electronic device includes the storage system 2000 described above, then the electronic device also possesses good stability and reliability.

[0231] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A gate stack structure and a gate isolation structure, wherein the gate stack structure includes a plurality of gate layers and a plurality of dielectric layers alternately arranged along a first direction; The gate isolation structure extends through the gate stack structure along the first direction, the gate stack structure is located on both sides of the gate isolation structure along the second direction, and the gate isolation structure extends along the third direction; The gate isolation structure includes a plurality of first isolation structures and at least one second isolation structure. The plurality of first isolation structures are arranged along the third direction. The second isolation structure is located between two adjacent first isolation structures along the third direction. The second isolation structure has a first end and a second end arranged along the third direction. The gate isolation structure further includes a first insulating layer and a second insulating layer arranged along the third direction, wherein the first insulating layer is located between the first isolation structure and the first end, and the second insulating layer is located between the first isolation structure and the second end; Wherein, the second direction is perpendicular to the third direction, and the first direction intersects the plane containing the second direction and the third direction.

2. The semiconductor structure according to claim 1, characterized in that, The first insulating layer includes a first arcuate surface and a second arcuate surface arranged along the third direction, wherein the bending direction of the first arcuate surface and the bending direction of the second arcuate surface are the same; The second insulating layer includes a third arcuate surface and a fourth arcuate surface arranged along the third direction, the third arcuate surface and the fourth arcuate surface having the same bending direction, and the third arcuate surface having the opposite bending direction to the first arcuate surface.

3. The semiconductor structure according to claim 1, characterized in that, The first insulating layer and the second insulating layer have a minimum spacing in the third direction, and the end of the first insulating layer in the second direction and the end of the second insulating layer in the second direction have a first spacing in the third direction, the first spacing being greater than the minimum spacing.

4. The semiconductor structure according to claim 1, characterized in that, The first insulating layer and the second insulating layer are symmetrically arranged with respect to the second isolation structure.

5. The semiconductor structure according to claim 4, characterized in that, The gate isolation structure includes a plurality of insulating structures spaced apart along the third direction, the insulating structures including: the first insulating layer, the second isolation structure and the second insulating layer.

6. The semiconductor structure according to claim 5, characterized in that, Both the first end and the second end have concave surfaces.

7. The semiconductor structure according to claim 1, characterized in that, The maximum dimension of the second isolation structure in the second direction is greater than the maximum dimension of the first isolation structure in the second direction.

8. The semiconductor structure according to claim 1, characterized in that, The second isolation structure includes a main body and an isolation layer. The main body extends through the gate stack structure along the first direction. The isolation layer is located between the main body and the gate stack structure. The isolation layer is also located between the main body and the first insulating layer. The isolation layer is disposed around the main body. The semiconductor structure further includes multiple channel structures that penetrate the gate stack structure along the first direction. The multiple channel structures are arranged in multiple rows and columns along the third direction and the second direction. The isolation layer is in contact with the sidewalls of a portion of the channel structures.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure includes a core region and a connection region adjacent to each other along the third direction, a portion of the channel structure is located in the core region, a portion of the channel structure is located in the connection region, and the number of rows of the channel structure located in the core region is greater than the number of rows of the channel structure located in the connection region; The first insulating layer and the second insulating layer are located in the core area.

10. The semiconductor structure according to claim 9, characterized in that, The gate isolation structure includes a plurality of first insulating layers and a plurality of second insulating layers, with portions of the first insulating layers and portions of the second insulating layers located in the connection region.

11. A method for fabricating a semiconductor structure, characterized in that, include: A gate stack structure is formed, the gate stack structure comprising a plurality of gate layers and a plurality of dielectric layers alternately arranged along a first direction; A gate isolation structure is formed, the gate isolation structure extending through the gate stack structure along a first direction and extending along a third direction; the gate isolation structure includes a plurality of first isolation structures and at least one second isolation structure, the plurality of first isolation structures are arranged along the third direction, the second isolation structure is located between two adjacent first isolation structures along the third direction, and the second isolation structure has a first end and a second end arranged along the third direction; the gate isolation structure further includes a first insulating layer and a second insulating layer arranged along the third direction, the first insulating layer is located between the first isolation structure and the first end, and the second insulating layer is located between the first isolation structure and the second end; wherein, the second direction is perpendicular to the third direction, and the first direction intersects the plane containing the second direction and the third direction.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The formation of multiple gate stack structures includes: A first stacked structure is formed, the first stacked structure comprising a plurality of sacrificial layers and a plurality of dielectric layers alternately arranged along the first direction; A gate spacer is formed, the gate spacer extending through the first stacked structure along the first direction and extending along the third direction; The gate spacer replaces a portion of the sacrificial layer with the gate layer.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The formation of the gate spacer includes: Multiple through holes are formed, the multiple through holes are arranged at intervals along the third direction, and the through holes penetrate the first stacked structure along the first direction; Etching liquid is injected into a portion of the through holes to connect the portions of the through holes, thereby forming a first and a second partition groove spaced apart along the third direction; Sacrificial material is filled into the first and second septa to form a first sacrificial structure and a second sacrificial structure, respectively. Etching fluid is injected into the through hole located between the first and second partitions to form a third partition, the third partition exposing a portion of the sidewall of the first sacrificial structure and a portion of the sidewall of the second sacrificial structure. Using an anode oxidation process, the first insulating layer is formed on the sidewall of the first sacrificial structure through the third partition, and the second insulating layer is formed on a portion of the sidewall of the second sacrificial structure.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The step of injecting corrosive liquid into the through hole located between the first partition and the second partition further includes: Etching solution is injected into a portion of the vias to connect the vias and form a fourth partition, the fourth partition exposing a portion of the sidewall of the second sacrificial structure, the first partition, the second partition and the fourth partition together constituting the gate partition; The process employing anode oxidation also includes: An insulating layer is formed on a portion of the sidewall of the second sacrificial structure through the fourth slot.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The formation of the gate isolation structure includes: An isolation material and a semiconductor material are sequentially deposited in the gate trench to form an isolation layer and a body. The body extends through the gate stack structure along the first direction. The isolation layer is located between the body and the gate stack structure and is disposed around the body.

16. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-10; A controller coupled to the semiconductor structure to control the semiconductor structure to store data.

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