Semiconductor memory device and electronic system including the same

Abstract

A semiconductor memory device and an electronic system are provided. The semiconductor memory device according to some embodiments of the present disclosure includes a substrate extending in a first direction and a second direction intersecting each other, and including a first region and a second region spaced apart from the first region in the first direction around the first region; a gate stack structure including first insulating layers and gate electrode layers stacked alternately with each other in the first region; a channel structure penetrating the gate stack structure; a molding structure including first insulating layers and second insulating layers stacked alternately with each other and having materials different from each other in the second region, each of the second insulating layers extending from each of the gate electrode layers in a horizontal direction; a separation structure separating the first region and the second region in the first direction and extending in the second direction; and a first gate contact penetrating at least a portion of the molding structure and connected to a first one of the gate electrode layers.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0046298, filed on April 9, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor memory devices and electronic systems including such semiconductor memory devices. Background Technology

[0003] There is a need to increase the integration level of semiconductor memory devices to meet consumers' demands for superior performance and low prices. In the case of semiconductor memory devices, increased integration is particularly necessary because it is a crucial factor in determining product price.

[0004] Meanwhile, in the case of two-dimensional or planar semiconductor memory devices, the integration density is mainly determined by the area occupied by a single memory cell, and is therefore greatly affected by the level of fine patterning technology. However, due to the need for extremely expensive equipment to miniaturize the patterns, the integration density of two-dimensional semiconductor devices is still limited, although it is increasing. Therefore, three-dimensional semiconductor devices incorporating memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0005] Various aspects of this disclosure provide a semiconductor memory device with improved electrical characteristics and reliability.

[0006] This disclosure also provides an electronic system including a semiconductor memory device with improved electrical characteristics and reliability.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0008] A semiconductor memory device according to some embodiments of the present disclosure includes: a substrate extending in a first direction and a second direction intersecting each other, and including a first region and a second region spaced apart from the first region in the first direction; a gate stack structure including a first insulating layer and a gate electrode layer alternately stacked in the first region; a channel structure penetrating the gate stack structure; a molding structure including a first insulating layer and a second insulating layer alternately stacked in the second region and having different materials from each other, each of the second insulating layers extending in a horizontal direction from each of the gate electrode layers; a separation structure separating the first region and the second region in the first direction and extending in the second direction; and a first gate contact penetrating at least a portion of the molding structure and connected to the first gate electrode layer in the gate electrode layer.

[0009] A semiconductor memory device according to some embodiments of the present disclosure includes: a substrate extending in a first direction and a second direction intersecting each other, and including a first region, a second region, and a third region that are different from each other, the second region being spaced apart from the first region in the first direction; a gate stack structure including a first insulating layer and a gate electrode layer that are alternately stacked in the first region; a channel structure penetrating the gate stack structure; a bit line connected to the channel structure and extending in the first direction; a dummy gate stack structure including a second insulating layer and a dummy gate electrode layer that are alternately stacked in the second region; a first dummy channel structure penetrating the dummy gate stack structure; a separation structure separating the first region and the second region in the first direction and extending in the second direction between the channel structure and the first dummy channel structure; a molding structure including a third insulating layer and a fourth insulating layer that are alternately stacked in the third region and have different materials from each other, and further including a first pad portion connecting one of the third insulating layers to one of the gate electrode layers; and a first gate contact penetrating at least a portion of the molding structure and connected to the first pad portion.

[0010] An electronic system according to some embodiments of the present disclosure includes: a motherboard; a semiconductor memory device on the motherboard; and a controller electrically connected to the semiconductor memory device on the motherboard, wherein the semiconductor memory device includes: a substrate extending in each of a first direction and a second direction intersecting each other, and including a first region, a second region, and a third region that are different from each other, the second region being spaced apart from the first region in the first direction; a gate stack structure including a first insulating layer and a gate electrode layer that are alternately stacked in the first region; a channel structure penetrating the gate stack structure; a dummy gate stack structure including a second insulating layer and a dummy gate electrode layer that are alternately stacked in the second region; a dummy channel structure penetrating the dummy gate stack structure; a separation structure separating the first region and the second region in the first direction and extending in the second direction; a molding structure including a third insulating layer and a fourth insulating layer having different materials and being alternately stacked in the third region, and a pad portion connecting one of the third insulating layers and one of the gate electrode layers; and a gate contact penetrating at least a portion of the molding structure and connected to the pad portion.

[0011] A method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure includes: providing a substrate extending in each of a first direction and a second direction intersecting each other and including a first region and a second region, the second region being spaced apart from the first region in the first direction; forming a first pre-stacked structure on the substrate including a first insulating layer and a sacrificial layer stacked alternately on each other; removing the sacrificial layer to form a second pre-stacked structure on the first region including a first insulating layer and a gate electrode layer stacked alternately on each other; forming a pre-molded structure on the second region including a first insulating layer and a second insulating layer stacked alternately on each other; forming a separation structure separating the first region and the second region in the first direction and extending in the second direction; forming a gate contact hole penetrating at least a portion of the pre-molded structure, and forming a contact insulating layer and a sacrificial insulating layer within the gate contact hole; removing the sacrificial insulating layer to form a first recess exposing any one of the second insulating layers; using the first recess to form a second recess in any one of the second insulating layers; and forming a contact conductive layer filling the second recess.

[0012] Specific details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0013] The above and other aspects and features of this disclosure will become more apparent from the detailed description of illustrative embodiments with reference to the accompanying drawings, in which: Figure 1 This is an exemplary block diagram illustrating a semiconductor memory device according to some embodiments; Figure 2These are exemplary circuit diagrams of semiconductor memory devices according to some embodiments; Figure 3 This is an exemplary layout diagram used to illustrate a semiconductor memory device according to some embodiments; Figure 4 This is an exemplary layout diagram used to illustrate the memory cell block region and the dummy cell block region of a semiconductor memory device according to some embodiments; Figure 5 yes Figure 4 A magnified view of region P1; Figure 6 It is along Figure 4 A cross-sectional view taken from AA; Figure 7 yes Figure 6 A magnified view of region Q1; Figure 8 yes Figure 6 A magnified view of region Q2; Figure 9 It is along Figure 4 A cross-sectional view of BB; Figure 10 and Figure 11 These are exemplary diagrams illustrating the capacitor structure of a semiconductor memory device according to some embodiments; Figure 12 These are exemplary diagrams illustrating the capacitor structure of a semiconductor memory device according to some embodiments; Figures 13 to 22 These are exemplary diagrams used to illustrate semiconductor memory devices according to some embodiments; Figure 23 and Figure 24 This is an exemplary cross-sectional view used to illustrate a semiconductor memory device according to some embodiments; Figures 25 to 29 This is an intermediate diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments; Figure 30 These are exemplary block diagrams used to illustrate electronic systems according to some embodiments; Figure 31 This is an exemplary perspective view used to illustrate an electronic system according to some embodiments. Detailed Implementation

[0014] Figure 1 This is an exemplary block diagram used to illustrate a semiconductor memory device according to some embodiments.

[0015] Reference Figure 1 According to some embodiments, the semiconductor memory device 10 includes a memory cell array 20 and peripheral circuitry 30.

[0016] The memory cell array 20 may include multiple memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include multiple memory cells. The memory cell array 20 can be connected to peripheral circuitry 30 via bit line BL, word line WL, at least one serial select line SSL, and at least one ground select line GSL. Specifically, the memory cell blocks BLK1 to BLKn can be connected to the row decoder 33 via word line WL, serial select line SSL, and ground select line GSL. Furthermore, the memory cell blocks BLK1 to BLKn can be connected to the page buffer 35 via bit line BL.

[0017] Peripheral circuitry 30 can receive address ADDR, command CMD, and control signal CTRL from the external device of semiconductor memory device 10, and can send data DATA to and receive data DATA from the external device of semiconductor memory device 10. Peripheral circuitry 30 may include a row decoder 33, a page buffer 35, and control logic 37. Peripheral circuitry 30 may also include various sub-circuits, such as input / output circuits, voltage generation circuits for generating various voltages required for the operation of semiconductor memory device 10, and error correction circuits for correcting errors in the data DATA read from memory cell array 20.

[0018] Control logic 37 can be connected to line decoder 33, page buffer 35, input / output circuits, voltage generation circuits, etc. Control logic 37 can control the overall operation of the semiconductor memory device 10. Control logic 37 can generate various internal control signals used within the semiconductor memory device 10 in response to the control signal CTRL. For example, control logic 37 can adjust the voltage levels supplied to word line WL and bit line BL during memory operations such as programming or erasing operations.

[0019] The row decoder 33 can select at least one of a plurality of memory cell blocks BLK1 to BLKn in response to address ADDR, and can select at least one word line WL, at least one serial select line SSL, and at least one ground select line GSL of the selected memory cell block BLK1 to BLKn. The row decoder 33 can transmit the voltage used to perform memory operations to the word line WL of the selected memory cell block BLK1 to BLKn.

[0020] Page buffer 35 can be connected to memory cell array 20 via bit line BL. Page buffer 35 can operate as a writer driver or a sense amplifier. Specifically, during a programming operation, page buffer 35 can operate as a writer driver to apply a voltage to bit line BL according to the data DATA to be stored in memory cell array 20. On the other hand, during a read operation, page buffer 35 can operate as a sense amplifier to sense the data DATA stored in memory cell array 20.

[0021] Figure 2 This is an exemplary circuit diagram of a semiconductor memory device according to some embodiments.

[0022] Reference Figure 2 According to some embodiments, a memory cell array of a semiconductor memory device (e.g., Figure 1 (20) may include a common source line CSL, multiple bit lines BL and multiple cell strings CSTR.

[0023] The common source line (CSL) can extend in the first direction X. In some embodiments, multiple common source lines (CSLs) can be arranged two-dimensionally. For example, multiple common source lines (CSLs) can be spaced apart from each other and each extends in the first direction X. The same voltage can be applied to the common source lines (CSLs), or different voltages can be applied to the common source lines (CSLs), and the common source lines (CSLs) can be controlled individually.

[0024] Multiple bit lines BL can be arranged in two dimensions. For example, the bit lines BL can be spaced apart from each other and can each extend in a second direction Y intersecting the first direction X. Multiple cell strings CSTR can be connected in parallel to each bit line BL. The cell strings CSTR can be connected together to a common source line CSL. That is, multiple cell strings CSTR can be arranged between the bit line BL and the common source line CSL.

[0025] Each cell string (CSTR) may include a ground select transistor (GLT) connected to the common source line (CSL), a string select transistor (SST) connected to the bit line (BL), and multiple memory cell transistors (MCTs) disposed between the ground select transistor (GLT) and the string select transistor (SST). Each memory cell transistor (MCT) may include a data storage element. The ground select transistor (GLT), the string select transistor (SST), and the memory cell transistors (MCTs) may be connected in series.

[0026] The common source line CSL can be commonly connected to the source of the ground select transistor GLT. Furthermore, the ground select line GSL, multiple word lines WL1 to WLn, and the serial select line SSL can be positioned between the common source line CSL and the bit line BL. The ground select line GSL can be used as the gate electrode of the ground select transistor GLT, the word lines WL1 to WLn can be used as the gate electrodes of the memory cell transistor MCT, and the serial select line SSL can be used as the gate electrode of the serial select transistor SST.

[0027] In some embodiments, the erase control transistor ECT can be positioned between the common source line CSL and the ground select transistor GLT. The common source line CSL can be commonly connected to the source of the erase control transistor ECT. Furthermore, the erase control line ECL can be positioned between the common source line CSL and the ground select line GSL. The erase control line ECL can serve as the gate electrode of the erase control transistor ECT. The erase control transistor ECT can generate gate-induced drain leakage (GIDL) to perform an erase operation on the memory cell array.

[0028] Figure 3 This is an exemplary layout diagram used to illustrate a semiconductor memory device according to some embodiments.

[0029] Reference Figure 3 A semiconductor memory device according to some embodiments includes a plurality of memory array blocks MAT1, MAT2, MAT3, and MAT4. The plurality of memory array blocks MAT1, MAT2, MAT3, and MAT4 can be arranged in rows and columns along a first direction X and a second direction Y. The first direction X can be a word line (…). Figure 1 The extension direction of each of the WL lines, and the second direction Y can be a bit line ( Figure 1 The extension direction of each of the multiple memory array blocks MAT1, MAT2, MAT3, and MAT4. Each of these blocks may include multiple memory cells.

[0030] Each of the plurality of memory array blocks MAT1, MAT2, MAT3, and MAT4 may include at least one memory cell block MBK and at least one dummy cell block DBK disposed around the periphery of the memory cell block MBK. The dummy cell block DBK may be disposed in the outermost region of each of the plurality of memory array blocks MAT1, MAT2, MAT3, and MAT4. In a single memory array block MAT1, the dummy cell block DBK may be disposed at both ends of the single memory array block MAT1, compared to the memory cell block MBK. In a single memory array block MAT1, the memory cell block MBK may be disposed inside the dummy cell block DBK. Within a single memory array block MAT1, the dummy cell block DBK may be spaced apart from the memory cell block MBK in a second direction Y.

[0031] The third memory array block MAT3 can be adjacent to the first memory array block MAT1 in the second direction Y. In the second direction Y, the dummy cell block DBK of the first memory array block MAT1 closest to the third memory array block MAT3 can be spaced apart from the dummy cell block DBK of the third memory array block MAT3 closest to the first memory array block MAT1. The second memory array block MAT2 can be adjacent to the first memory array block MAT1 in the first direction X. In the first direction X, the dummy cell block DBK of the first memory array block MAT1 closest to the second memory array block MAT2 can be spaced apart from the dummy cell block DBK of the second memory array block MAT2 closest to the first memory array block MAT1. However, the embodiment is not limited to this, and the dummy cell block DBK of the first memory array block MAT1 closest to the second memory array block MAT2 can be connected to the dummy cell block DBK of the second memory array block MAT2 closest to the first memory array block MAT1.

[0032] although Figure 3 The illustration shows only four memory array blocks arranged in a 2×2 configuration along the first direction X and the second direction Y, but the number and arrangement of memory array blocks are not limited to this. For example, in addition to four, the number of memory array blocks can also be, but is not limited to, six, or even eight. Furthermore, multiple memory array blocks can be arranged in a 1×4 or 4×1 configuration, but the technical concept of this disclosure is not limited to these.

[0033] Multiple memory cells in multiple memory array blocks MAT1, MAT2, MAT3, and MAT4 can be electrically connected to external circuitry. Figure 1 30). Although not specifically shown, the peripheral circuitry ( Figure 1 (30) can be configured to be spaced apart from multiple memory array blocks MAT1, MAT2, MAT3, and MAT4 in the second direction Y. Peripheral circuitry ( Figure 1 (30) can be configured to be adjacent to multiple memory array blocks MAT1, MAT2, MAT3, and MAT4 in the second direction Y. However, the peripheral circuitry ( Figure 1 The location of 30 is not limited to this, and the peripheral circuit ( Figure 1 30) can be set above and / or below multiple memory array blocks MAT1, MAT2, MAT3 and MAT4 on a third party Z.

[0034] Data storage, erasure, and / or retrieval operations can be performed within the memory cell block MBK. Data storage, erasure, and / or retrieval operations can also be performed outside of the dummy cell block DBK.

[0035] Figure 4 This is an exemplary layout diagram used to illustrate the memory cell block region and the dummy cell block region of a semiconductor memory device according to some embodiments. Figure 5 yes Figure 4 A magnified view of region P1. Figure 6 It is along Figure 4 The cross-sectional view taken from AA. Figure 7 yes Figure 6 A magnified view of region Q1. Figure 8 yes Figure 6 A magnified view of region Q2. Figure 9 It is along Figure 4 A cross-sectional view of BB.

[0036] A semiconductor memory device according to some embodiments may include a substrate 102, a gate stack structure GST, a molded structure MST, a channel structure CH, a dummy channel structure DCH, a discrete structure WLC, and a gate contact GC.

[0037] Substrate 102 may include a memory cell block region (MBR) and a dummy cell block region (DBR) surrounding the MBR. The memory cell block region (MBR) may correspond to... Figure 3 A memory cell block MBK is located within a memory array block (e.g., MAT1), and a dummy cell block region DBR can correspond to a dummy cell block DBK located within that memory array block (e.g., MAT1) that is spaced apart from the memory cell block MBK in the second direction Y. The dummy cell block region DBR can include an electrode region ER and a molding region IR. The electrode region ER can be disposed between the memory cell block region MBR and the molding region IR. The memory cell block region MBR, the electrode region ER, and the molding region IR can refer to different regions on the substrate 102.

[0038] Substrate 102 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, substrate 102 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In some embodiments, substrate 102 may include polycrystalline silicon (poly Si).

[0039] The substrate 102 may include a first side 102a and a second side 102b opposite to each other. In the following description, the first side 102a may also be referred to as the front side, and the second side 102b may also be referred to as the rear side. The first side 102a of the substrate 102 may extend over each of a first direction X and a second direction Y that intersect each other. Each of the first direction X and the second direction Y may refer to a horizontal direction aligned with the first side 102a. The first direction X and the second direction Y may be directions that intersect each other perpendicularly. A third direction Z may be a height direction perpendicular to each of the first direction X and the second direction Y.

[0040] In some embodiments, substrate 102 may include a conductive material, such as polysilicon doped with impurities, a metal, or a metal silicide. As an example, substrate 102 may include polysilicon (poly-Si) doped with N-type impurities (e.g., phosphorus (P) or arsenic (As)). According to some embodiments, such substrate 102 may be provided as a common source line for a semiconductor memory device.

[0041] A gate stack structure (GST) can be disposed in the memory cell block region (MBR) and the electrode region (ER). The gate stack structure (GST) may include a first insulating layer 110_11…110_1n and a second insulating layer 115_21…115_2n that are stacked alternately with each other, as well as gate electrodes GE11…GE1n and GE21…GE2n.

[0042] The gate stack structure GST may include a first stack structure SS1 and a second stack structure SS2. The first stack structure SS1 and the second stack structure SS2 may be stacked sequentially on a first side 102a of the substrate 102.

[0043] The first stacked structure SS1 may include a plurality of first insulating layers 110_11…110_1n and a plurality of first gate electrodes GE11…GE1n, alternately stacked along a third direction Z. Each of the first insulating layers 110_11…110_1n and each of the first gate electrodes GE11…GE1n may have a layered structure extending along a horizontal plane (e.g., an XY plane). The first gate electrodes GE11…GE1n are spaced apart from each other by the first insulating layers 110_11…110_1n and may be stacked sequentially.

[0044] In some embodiments, the first gate electrode GE11…GE1n may include at least one ground selection line stacked on the substrate 102 (e.g., Figure 1 GSL) and multiple word lines (e.g., Figure 1 (Part of WL). Although not shown, the first gate electrodes GE11…GE1n may also include at least one erase control line. The number and thickness of the first insulating layers 110_11…110_1n and the first gate electrodes GE11…GE1n are merely examples and are not limited to those shown in the figures.

[0045] The first interlayer insulating film 141 may cover the first stacked structure SS1 and the first molded structure MS1 described below. The first interlayer insulating film 141 may be, but is not limited to, at least one of silicon oxide, silicon oxynitride and / or a low dielectric constant (low k) material with a dielectric constant less than that of silicon oxide.

[0046] The second stacked structure SS2 may include a plurality of second insulating layers 115_21…115_2n and a plurality of second gate electrodes GE21…GE2n, alternately stacked along a third direction Z. Each of the second insulating layers 115_21…115_2n and each of the second gate electrodes GE21…GE2n may have a layered structure extending along a horizontal plane (e.g., an XY plane). The second gate electrodes GE21…GE2n are spaced apart from each other by the second insulating layers 115_21…115_2n and may be stacked sequentially.

[0047] In some embodiments, the second gate electrodes GE21…GE2n may include word lines sequentially stacked on the first stack structure SS1 (e.g., Figure 1 (part of the WL) and at least one string selection line (e.g., Figure 1 (SSL). The number and thickness of the second insulating layer 115_21…115_2n and the second gate electrode GE21…GE2n are merely exemplary and are not limited to those shown in the figures.

[0048] The second interlayer insulating film 142 may cover the second stacked structure SS2 and the second molded structure MS2, which will be described below. The second interlayer insulating film 142 may be, but is not limited to, at least one of silicon oxide, silicon oxynitride, and / or a low dielectric constant (low k) material with a dielectric constant less than that of silicon oxide.

[0049] Each of the gate electrodes GE11…GE1n and GE21…GE2n may include, but is not limited to, a conductive material (e.g., a metal such as tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nickel (Ni)) or a semiconductor material such as silicon. In some embodiments, each of the gate electrodes GE11…GE1n and GE21…GE2n may include a metal film. As an example, each of the gate electrodes GE11…GE1n and GE21…GE2n may include at least one of a tungsten (W) film, a molybdenum (Mo) film, and / or a ruthenium (Ru) film.

[0050] Each of the insulating layers 110_11…110_1n and 115_21…115_2n may include, but is not limited to, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride. As an example, each of the insulating layers 110_11…110_1n and 115_21…115_2n may include a silicon oxide film.

[0051] A channel structure CH can be formed on the substrate 102 of each memory cell block region MBR. The channel structure CH can extend in the third direction Z and penetrate at least a portion of the stacked structures SS1 and SS2. The channel structure CH can intersect with multiple gate electrodes GE11…GE1n and GE21…GE2n. For example, the channel structure CH can be a pillar (e.g., cylindrical) structure extending in the third direction Z.

[0052] In some embodiments, the multiple channel structures CH can be arranged in a zigzag pattern. For example, as... Figure 4 and Figure 5 As shown, the channel structures CH can be arranged alternately in the first direction X and the second direction Y. This channel structure CH can further improve the integration density of semiconductor memory devices. The number, arrangement, etc., of the channel structures CH are merely exemplary and are not limited to those shown in the figures.

[0053] Each channel structure CH may include a semiconductor film 130 and a data storage film 132.

[0054] Semiconductor film 130 extends in the Z-direction and may intersect with multiple gate electrodes GE11…GE1n and GE21…GE2n. Although semiconductor film 130 is only shown as a cup-shaped structure, this is merely exemplary. For example, semiconductor film 130 may have various shapes, such as cylindrical, rectangular barrel, and solid filler shapes. Semiconductor film 130 may include, for example, but not limited to, semiconductor materials such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0055] In some embodiments, the semiconductor film 130 may be electrically connected to the substrate 102. For example, one end (e.g., the lower end) of the semiconductor film 130 may be in contact with the substrate 102.

[0056] In some embodiments, the semiconductor film 130 may protrude beyond the first stacked structure SS1 and the data storage film 132. For example, one end (e.g., the lower end) of the semiconductor film 130 may be formed below the lower side of the first stacked structure SS1 and the lower side of the data storage film 132. The substrate 102 may contact the end (e.g., the lower end) of the semiconductor film 130 that protrudes beyond the first stacked structure SS1 and the data storage film 132.

[0057] The data storage film 132 can be interposed between the semiconductor film 130 and the plurality of gate electrodes GE11…GE1n and GE21…GE2n. For example, the data storage film 132 can extend along the outer side of the semiconductor film 130. The data storage film 132 can be, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material can include, for example, at least one of, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0058] In some embodiments, such as Figure 7 As shown, the data storage film 132 may include a tunnel insulating film 132a, a charge storage film 132b, and a barrier insulating film 132c, which are sequentially stacked on the outside of the semiconductor film 130.

[0059] The tunnel insulating film 132a may include, for example, silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)). The charge storage film 132b may include, for example, silicon nitride. The barrier insulating film 132c may include, for example, silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)).

[0060] In some embodiments, each channel structure CH may further include a filling insulating film 134. The filling insulating film 134 may be formed to fill the interior of the cup-shaped semiconductor film 130. The filling insulating film 134 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0061] In some embodiments, each of the channel structures CH may further include a channel pad 136. The channel pad 136 may be formed to connect to the other end (e.g., the upper end) of the semiconductor film 130. The channel pad 136 may include a conductive material, such as polysilicon doped with impurities, a metal, a metal silicide, etc. As an example, the channel pad 136 may include polysilicon (poly-Si) doped with N-type impurities (e.g., phosphorus (P) or arsenic (As)).

[0062] The separated structure WLC can cut the stacked structures SS1 and SS2. For example, as Figure 6 As shown, the uppermost side of the separation structure WLC can be formed to be the same as or higher than the upper side of the second stacked structure SS2, and the lowermost side of the separation structure WLC can be formed to be the same as or lower than the lower side of the first stacked structure SS1.

[0063] The separate structure WLC can extend in the first direction X. Although not shown, multiple separate structures WLC can be spaced apart from each other and arranged along the second direction Y. The stacked structures SS1 and SS2 can be divided by multiple separate structures WLC to form multiple memory cell blocks (e.g., Figure 1 (BLK1 to BLKn). The discrete structure WLC can be disposed between the memory cell block region MBR and the dummy cell block region DBR. The discrete structure WLC can be disposed between the channel structure CH and the dummy channel structure DCH, which will be described below. The discrete structure WLC can be disposed between the channel structure CH and the gate contact GC, which will be described below.

[0064] In some embodiments, the separated structure WLC may include an insulating material, such as at least one of silicon oxide, silicon nitride, and / or silicon oxynitride. As an example, the separated structure WLC may include a silicon oxide film.

[0065] Multiple dummy channel structures (DCHs) each extend in the third direction Z and can penetrate the second interlayer insulating film 142 and the stacked structures SS1 and SS2. Unlike the channel structure CH, the dummy channel structures (DCHs) are not used as channels for transistors. The dummy channel structures (DCHs) are not electrically connected to the first conductor 182 and the gate electrodes GE11…GE1n and GE21…GE2n, as will be described below. The dummy channel structures (DCHs) can be formed in a shape similar to that of the channel structure CH. The dummy channel structures (DCHs) can include the same film as the channel structure CH.

[0066] The molded structure MST can be set in the molded region IR of the dummy unit block region DBR. The molded structure MST may include a first insulating layer 110_11…110_1n and a second insulating layer 115_21…115_2n, and a third insulating layer SL11…SL1n and SL21…SL2n, which are alternately stacked along the third direction Z.

[0067] The molded structure MST may include a first molded structure MS1 and a second molded structure MS2. The first molded structure MS1 and the second molded structure MS2 may be stacked sequentially on a first side 102a of the substrate 102.

[0068] The first molded structure MS1 may include a plurality of first insulating layers 110_11…110_1n and a plurality of third insulating layers SL11…SL1n, alternately stacked along a third direction Z. Each of the first insulating layers 110_11…110_1n and each of the plurality of third insulating layers SL11…SL1n may have a layered structure extending along a horizontal plane (e.g., an XY plane). The plurality of third insulating layers SL11…SL1n are spaced apart from each other by the first insulating layers 110_11…110_1n and may be stacked sequentially.

[0069] The second molded structure MS2 may include a plurality of second insulating layers 115_21…115_2n and a plurality of third insulating layers SL21…SL2n, alternately stacked along a third direction Z. Each of the second insulating layers 115_21…115_2n and each of the third insulating layers SL21…SL2n may have a layered structure extending along a horizontal plane (e.g., an XY plane). The third insulating layers SL21…SL2n may be spaced apart from each other by the second insulating layers 115_21…115_2n and stacked sequentially.

[0070] Each of the third insulating layers SL11…SL1n and SL21…SL2n may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride. The third insulating layers SL11…SL1n and SL21…SL2n may have a different material than the first insulating layers 110_11…110_1n and the second insulating layers 115_21…115_2n. For example, the third insulating layers SL11…SL1n and SL21…SL2n may include a material with etch selectivity relative to the first insulating layers 110_11…110_1n and the second insulating layers 115_21…115_2n. As an example, each of the third insulating layers SL11…SL1n and SL21…SL2n may include silicon nitride.

[0071] Gate contacts GC can be formed on substrate 102 of molding region IR. Multiple gate contacts GC can be connected to each of the corresponding multiple gate electrodes GE11…GE1n and GE21…GE2n. For example, each gate contact GC can extend in the third direction Z and be connected to a corresponding one of gate electrodes GE11…GE1n and GE21…GE2n. Each gate contact GC can penetrate at least a portion of the molding structures MS1 and MS2 and be connected to a corresponding one of gate electrodes GE11…GE1n and GE21…GE2n (hereinafter, selected gate electrode).

[0072] Multiple gate contacts GC can be formed within each gate contact hole GCH extending into the molded structures MS1 and MS2. Each gate contact GC may include a contact insulating layer 162S and a contact conductive layer 162 inside the gate contact hole GCH. (Refer to...) Figure 5 From a planar perspective, the gate contacts GC can have a first center distance D1. The center distance between the gate contacts GC is not limited to this, and can be various center distances as described below.

[0073] The contact conductive layer 162 of the gate contact GC (e.g., the first gate contact GC13) can fill at least a portion of each gate contact hole GCH. The contact conductive layer 162 can contact the pad portion PD (e.g., the first pad portion PD13), a portion of which is exposed through the gate contact hole GCH.

[0074] The entire lower side of the contact conductive layer 162 may contact the pad portion PD (e.g., the first pad portion PD13). The width of the pad portion PD (e.g., the first pad portion PD13) may be greater than the width of the gate contact GC (e.g., the first gate contact GC13).

[0075] The contact conductive layer 162 may include a conductive material. The contact conductive layer 162 may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. One of the gate electrodes GE11…GE1n and GE21…GE2n (selected gate electrodes) may include a conductive material different from that of the contact conductive layer 162. For example, when one of the gate electrodes GE11…GE1n and GE21…GE2n (selected gate electrodes) includes molybdenum (Mo), the contact conductive layer 162 may include tungsten (W). However, the technical concept of this disclosure is not limited thereto, and one of the gate electrodes GE11…GE1n and GE21…GE2n (selected gate electrodes) and the contact conductive layer 162 may include the same conductive material.

[0076] A contact insulating layer 162S may surround the sidewalls of each contact conductive layer 162. The contact insulating layer 162S may conformally extend along the sidewalls of each contact conductive layer 162. The contact insulating layer 162S does not cover the pad portion PD (e.g., the first pad portion PD13), a portion of which is exposed by each gate contact via GCH. The contact insulating layer 162S may include an insulating material. The contact insulating layer 162S may include, for example, but not limited to, silicon oxide.

[0077] Each of the third insulating layers SL11…SL1n and SL21…SL2n may extend from each of the corresponding gate electrodes GE11…GE1n and GE21…GE2n in the second direction Y. Any of the third insulating layers SL11…SL1n and SL21…SL2n may be connected to the corresponding gate electrode GE11…GE1n and GE21…GE2n via a pad portion PD (e.g., a first pad portion PD13). Figure 8 SL23) can be connected to one of the gate electrodes GE11…GE1n and GE21…GE2n via the pad portion PD (e.g., the first pad portion PD13). Figure 8 GE23). The pad portion PD (e.g., the first pad portion PD13) is provided in any one of the third insulating layers SL11…SL1n and SL21…SL2n (e.g., Figure 8 SL23) and the corresponding one of the gate electrodes GE11…GE1n and GE21…GE2n (e.g., Figure 8 Between GE23), and connected to them. The pad portion PD (e.g., the first pad portion PD13) can be located between any one of the third insulating layers SL11…SL1n and SL21…SL2n (e.g., Figure 8 SL23) and the corresponding one of the gate electrodes GE11…GE1n and GE21…GE2n (e.g., Figure 8 At each of the same vertical and horizontal heights in GE23).

[0078] In some embodiments, the pad portion PD can connect the memory cell block region (MBR) and the dummy cell block region (DBR) and prevent the dummy cell block region (DBR) from collapsing.

[0079] The second gate contact GC23 penetrates at least a portion of the molded structures MS1 and MS2, and can be connected to a corresponding one of the gate electrodes GE11…GE1n and GE21…GE2n (e.g., Figure 8(GE23). The second gate contact GC23 can be located at the same vertical horizontal height as the first gate contact GC13. The second gate contact GC23 can be connected to the second pad portion PD23.

[0080] The second pad portion PD23 can accommodate any one of the third insulating layers SL11…SL1n and SL21…SL2n (for example, ...). Figure 8 SL23) is connected to one of the corresponding gate electrodes GE11…GE1n and GE21…GE2n (e.g., Figure 8 (GE23). The second pad portion PD23 may be spaced apart from the first pad portion PD13 in the first direction X. The second pad portion PD23 may be located at the same vertical horizontal height as the first pad portion PD13.

[0081] The description of the first gate contact GC13 described above can be similarly applied to the structure and materials of the second gate contact GC23. Similarly, the description of the first pad portion PD13 described above can be similarly applied to the structure and materials of the second pad portion PD23.

[0082] In other words, multiple gate contacts GC can be connected to one of the gate electrodes GE11…GE1n and GE21…GE2n. Multiple pads PD can be connected to one of the gate electrodes GE11…GE1n and GE21…GE2n. In some embodiments, since multiple gate contacts GC are connected to a single gate electrode, the resistance characteristics can be improved.

[0083] The third gate contact GC11 and the fourth gate contact GC21 penetrate at least a portion of the molded structures MS1 and MS2, and can be connected to a corresponding one of the gate electrodes GE11…GE1n and GE21…GE2n. Figure 10 (GE25). The third gate contact GC11 can be located at the same vertical horizontal height as the fourth gate contact GC21. Each of the third gate contact GC11 and the fourth gate contact GC21 can be connected to the third pad portion PD11 and the fourth pad portion PD21.

[0084] The third pad portion PD11 and the fourth pad portion PD21 can connect one of the insulating layers SL11…SL1n and SL21…SL2n (e.g., SL25) to the corresponding gate electrode among the gate electrodes GE11…GE1n and GE21…GE2n. Figure 10 (GE25). The third pad portion PD11 may be spaced apart from the fourth pad portion PD21 in the first direction X. The third pad portion PD11 may be located at the same vertical horizontal height as the fourth pad portion PD21.

[0085] The descriptions of the first gate contact GC13 and the second gate contact GC23 described above can be similarly applied to the structure and materials of the third gate contact GC11 and the fourth gate contact GC21. Similarly, the descriptions of the first pad portion PD13 and the second pad portion PD23 can be similarly applied to the structure and materials of the third pad portion PD11 and the fourth pad portion PD21.

[0086] The fifth gate contact GC12 and the sixth gate contact GC22 penetrate at least a portion of the molded structures MS1 and MS2, and can be connected to one of the corresponding gate electrodes GE11…GE1n and GE21…GE2n. Figure 10 (GE24). The fifth gate contact GC12 may be located at the same vertical horizontal height as the sixth gate contact GC22. Each of the fifth gate contact GC12 and the sixth gate contact GC22 may be connected to the fifth pad portion PD12 and the sixth pad portion PD22.

[0087] The fifth pad portion PD12 and the sixth pad portion PD22 can connect one of the third insulating layers SL11…SL1n and SL21…SL2n (e.g., SL24) to the corresponding gate electrode among the gate electrodes GE11…GE1n and GE21…GE2n. Figure 10 (GE24). The fifth pad portion PD12 may be spaced apart from the sixth pad portion PD22 in the first direction X. The fifth pad portion PD12 may be located at the same vertical horizontal height as the sixth pad portion PD22.

[0088] The descriptions of the first gate contact GC13 and the second gate contact GC23 described above can be similarly applied to the structure and materials of the fifth gate contact GC12 and the sixth gate contact GC22. Similarly, the descriptions of the first pad portion PD13 and the second pad portion PD23 described above can be similarly applied to the structure and materials of the fifth pad portion PD12 and the sixth pad portion PD22.

[0089] The seventh gate contact GC14 and the eighth gate contact GC24 penetrate at least a portion of the molded structures MS1 and MS2, and can be connected to a corresponding one of the gate electrodes GE11…GE1n and GE21…GE2n. The seventh gate contact GC14 can be located at the same vertical horizontal height as the eighth gate contact GC24. Each of the seventh gate contact GC14 and the eighth gate contact GC24 can be connected to the seventh pad portion PD14 and the eighth pad portion PD24.

[0090] The seventh pad portion PD14 and the eighth pad portion PD24 can connect one of the third insulating layers SL11…SL1n and SL21…SL2n (e.g., SL14) to a corresponding gate electrode among the gate electrodes GE11…GE1n and GE21…GE2n. The seventh pad portion PD14 can be spaced apart from the eighth pad portion PD24 in the first direction X. The seventh pad portion PD14 can be located at the same vertical horizontal height as the eighth pad portion PD24.

[0091] The descriptions of the first gate contact GC13 and the second gate contact GC23 described above can be similarly applied to the structure and materials of the seventh gate contact GC14 and the eighth gate contact GC24. Similarly, the descriptions of the first pad portion PD13 and the second pad portion PD23 described above can be similarly applied to the structure and materials of the seventh pad portion PD14 and the eighth pad portion PD24.

[0092] although Figure 9 Only the vertical horizontal position of the third pad portion PD11, the fifth pad portion PD12, and the first pad portion PD13 in the third direction Z is shown, but the embodiment is not limited to this. The vertical horizontal height of the third pad portion PD11, the fifth pad portion PD12, the first pad portion PD13, and the seventh pad portion PD14 is not limited to those shown in the figure.

[0093] In some embodiments, each gate contact GC may penetrate the second interlayer insulating film 142. For example, a third interlayer insulating film 143 may be formed on the second interlayer insulating film 142. Each gate contact GC penetrates at least a portion of the third interlayer insulating film 143, the second interlayer insulating film 142, and the molded structures MS1 and MS2, and may be connected to the select gate electrode.

[0094] In some embodiments, the width of each gate contact GC may decrease toward the substrate 102. This may be due to the etching process forming the gate contact GC being performed in a direction from the molded structures MS1 and MS2 toward the substrate 102.

[0095] The first contact pattern 181, the first wire 182, the second contact pattern 183, and the second wire 184 can be disposed within the third interlayer insulating film 143 and the fourth interlayer insulating film 144.

[0096] A first contact pattern 181 may be formed on the channel structure CH. The first contact pattern 181 may connect the channel pad 136 and the first conductor 182. The first conductor 182 may be electrically connected to the channel structure CH through the first contact pattern 181.

[0097] The first conductor 182 may extend in the second direction Y within the memory cell block region (MBR). Although not shown, the first conductors 182 may be spaced apart from each other in the first direction X and extend side-by-side in the second direction Y. The first conductors 182 may be electrically connected to a channel structure CH arranged along the second direction Y. The first conductors 182 may serve as bit lines ( Figure 1 (BL) is provided.

[0098] The second contact pattern 183 can be formed on the gate contact GC. The second contact pattern 183 can connect the gate contact GC and the second wire 184.

[0099] The second conductor 184 may extend in the molding region IR in the second direction Y. Although not shown, the second conductors 184 are spaced apart from each other in the first direction X, and may extend side by side in the second direction Y. The second conductors 184 may be electrically connected to gate contacts GC arranged along the second direction Y.

[0100] Each of the first contact pattern 181, the first wire 182, the second contact pattern 183, and the second wire 184 may include a conductive material, such as, but not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and their alloys.

[0101] Figure 10 and Figure 11 This is an exemplary diagram illustrating the capacitor structure of a semiconductor memory device according to some embodiments. For ease of explanation, the above descriptions will be brief or omitted. Figures 1 to 9 The repeated parts of the description.

[0102] Figure 11 It shows the use of Figure 10 The capacitor structure formed by some of the gate electrodes GE25, GE24 and GE23 in the described gate electrodes GE11…GE1n and GE21…GE2n and the insulating layer 115 between them.

[0103] Reference Figure 10 The third gate electrode GE25 is connected to the third gate contact GC11 via the third pad PD11. The fifth gate electrode GE24 is connected to the fifth gate contact GC12 via the fifth pad PD12. The first gate electrode GE23 is connected to the first gate contact GC13 via the first pad PD13.

[0104] The first capacitor C1 includes a third gate electrode GE25, a fifth gate electrode GE24, and an insulating layer 115 therebetween. The third gate electrode GE25 and the fifth gate electrode GE24 can constitute the capacitor electrodes of the first capacitor C1, and the insulating layer 115 can constitute the capacitor dielectric.

[0105] The second capacitor C2 includes a fifth gate electrode GE24, a first gate electrode GE23, and an insulating layer 115 therebetween. The fifth gate electrode GE24 and the first gate electrode GE23 can constitute the capacitor electrodes of the second capacitor C2, and the insulating layer 115 can constitute the capacitor dielectric.

[0106] Reference Figure 10 and Figure 11 The first capacitor C1 and the second capacitor C2 can be connected in parallel.

[0107] In some embodiments, the gate electrode of the dummy cell block region (DBR) can be used as a capacitor electrode. Therefore, the capacitance of the semiconductor memory device can be further ensured.

[0108] Figure 12 This is an exemplary diagram illustrating the capacitor structure of a semiconductor memory device according to some embodiments. For ease of explanation, the above descriptions will be brief or omitted. Figures 1 to 11 The repeated parts of the description.

[0109] Reference Figure 12 The first capacitor C1A and the second capacitor C2A can be connected in series. In this case, with Figure 10 Unlike other gate contacts, the fifth gate contact GC12 can be electrically floated.

[0110] Figures 13 to 22 This is an exemplary diagram used to illustrate a semiconductor memory device according to some embodiments. For ease of explanation, the above descriptions will be brief or omitted. Figures 1 to 12 The repeated parts of the description.

[0111] Reference Figure 13 Furthermore, multiple second dummy channel structures DCH2 can be set in the molding area IR. The second dummy channel structures DCH2 can be spaced apart from the first dummy channel structure DCH1 in the second direction Y, and the pad portion PD is inserted between the second dummy channel structures DCH2 and the first dummy channel structure DCH1.

[0112] Reference Figure 14 Multiple separation patterns SP can also be provided in the electrode region ER. The multiple separation patterns SP can be spaced apart from each other in the first direction X. The multiple separation patterns SP can be spaced apart from the separation structure WLC in the second direction Y. The dummy channel structures DCH can be spaced apart from each other in the second direction Y, and the separation patterns SP are interposed between the dummy channel structures DCH. The width of the separation pattern SP in the first direction X can be equal to, but not limited to, the width of the separation structure WLC in the first direction X. The separation pattern SP can include the same insulating material as the separation structure WLC.

[0113] Reference Figure 15 From a planar perspective, the gate contact GC can have a second center distance D2. The second center distance D2 can be less than... Figure 5 The first center distance D1.

[0114] Reference Figure 16 From a planar perspective, the gate contact GC can have a third center distance D3.

[0115] Reference Figure 17 and Figure 18 A portion of the lower side of the conductive contact layer 162 may contact the first pad portion PD13. For example, the lower side of the conductive contact layer 162 may include a first portion that contacts the first pad portion PD13 and a second portion that contacts the insulating layer SL23.

[0116] Reference Figure 19 A first dummy channel structure DCH1 can be provided in the electrode region ER, and a second dummy channel structure DCH2 can be provided in the molding region IR. The second dummy channel structure DCH2 can be spaced apart from the gate contact GC in the first direction X. The second dummy channel structure DCH2 can be disposed between the gate contacts GC in the first direction X. Multiple second dummy channel structures DCH2 can be disposed along the second direction Y in the region between the gate contacts GC.

[0117] Reference Figure 20 Multiple second dummy channel structures DCH2 can be disposed between gate contacts GC in the first direction X.

[0118] Reference Figure 21 The second dummy channel structure DCH2 can overlap with each of the electrode region ER and the molding region IR. The third dummy channel structure DCH3 can be disposed in the molding region IR. The first dummy channel structure DCH1, the second dummy channel structure DCH2, and the third dummy channel structure DCH3 can have different dimensions. The size of the second dummy channel structure DCH2 can be larger than the size of the first dummy channel structure DCH1. The length of the second dummy channel structure DCH2 in the second direction Y can be longer than the length of the first dummy channel structure DCH1 in the second direction Y. The size of the third dummy channel structure DCH3 can be larger than the size of the second dummy channel structure DCH2. The length of the third dummy channel structure DCH3 in the second direction Y can be longer than the length of the second dummy channel structure DCH2 in the second direction Y.

[0119] Reference Figure 22The third dummy channel structure DCH3 can be spaced apart from the gate contact GC in the first direction X. The third dummy channel structure DCH3 can be disposed between the gate contacts GC in the first direction X. Multiple third dummy channel structures DCH3 can be disposed along the second direction Y in the region between the gate contacts GC. The size of the third dummy channel structure DCH3 can be larger than the size of each of the first dummy channel structure DCH1 and the second dummy channel structure DCH2.

[0120] Figure 23 and Figure 24 This is an exemplary cross-sectional view used to illustrate a semiconductor memory device according to some embodiments. For ease of explanation, the above descriptions will be brief or omitted. Figures 1 to 22 The repeated parts of the description.

[0121] Reference Figure 23 and 24 According to some embodiments, a semiconductor memory device may include a memory cell region (CELL) and a peripheral circuit region (PERI).

[0122] Reference Figure 23 The memory cell region CELL may include a substrate 102, a gate stack structure GST, a molded structure MST, a channel structure CH, a first wire 182, a dummy channel structure DCH, a split structure WLC, a gate contact GC, and a first wiring insulating film 310.

[0123] The peripheral circuit area PERI may include peripheral circuit board 200, peripheral circuit element PT and wiring structure 260.

[0124] The peripheral circuit board 200 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the peripheral circuit board 200 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

[0125] Peripheral circuit element PT can be formed on the upper side of peripheral circuit board 200. Peripheral circuit element PT can constitute peripheral circuitry for controlling the operation of the semiconductor memory device (e.g., Figure 1 (30). For example, the peripheral circuit element PT may include control logic (e.g., Figure 1 37), line decoder (e.g., Figure 1 33), page buffer (e.g., Figure 1 (35), etc. In the following description, the surface of the peripheral circuit board 200 on which the peripheral circuit elements PT are disposed may be referred to as the front side of the peripheral circuit board 200. Conversely, the surface of the peripheral circuit board 200 opposite to the front side of the peripheral circuit board 200 may be referred to as the rear side of the peripheral circuit board 200.

[0126] Peripheral circuit elements PT may include, for example, but not limited to, transistors. For example, peripheral circuit elements PT may include not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, and inductors.

[0127] In a semiconductor memory device according to some embodiments, the back side of the substrate 102 may be opposite to the front side of the peripheral circuit board 200. For example, a second inter-wire insulating film 240 covering the peripheral circuit elements PT may be formed on the upper side of the peripheral circuit board 200. The substrate 102 may be stacked on the upper side of the second inter-wire insulating film 240.

[0128] Wiring structure 260 connected to peripheral circuit element PT can be formed within second wiring inter-insulation film 240. Wiring structure 260 may include conductive material, such as, but not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and alloys thereof. As an example, wiring structure 260 may include copper (Cu) wiring.

[0129] Reference Figure 24 In a semiconductor memory device according to some embodiments, the upper side of the substrate 102 is opposite to the front side of the peripheral circuit board 200.

[0130] For example, a semiconductor memory device according to some embodiments may have a C2C (chip-to-chip) structure. A C2C structure may refer to a structure in which an upper chip of the memory cell region CELL is fabricated on a first wafer (e.g., substrate 102), a lower chip including the peripheral circuit region PERI is fabricated on a second wafer (e.g., peripheral circuit board 200) different from the first wafer, and then the upper and lower chips are connected to each other by bonding.

[0131] As an example, the bonding method can be represented in such a way that a first bonding metal 190 (and / or a first bonding insulating film 146) formed on the uppermost metal layer of the upper chip is connected to a second bonding metal 290 (and / or a second bonding insulating film 246) formed on the uppermost metal layer of the lower chip. For example, when the first bonding metal 190 and the second bonding metal 290 are formed of copper (Cu), the bonding method can be a Cu-Cu bonding method. However, this is merely an example, and the first bonding metal 190 and the second bonding metal 290 can of course be formed of various other metals such as aluminum (Al) or tungsten (W).

[0132] When the first bonding metal 190 and the second bonding metal 290 are bonded, the first wiring structure 180 can be electrically connected to the second wiring structure 260. Therefore, multiple memory cells of the memory cell region CELL can be electrically connected to peripheral circuit elements PT.

[0133] The first wiring structure 180 may be formed on the fourth interlayer insulating film 144. The first wiring structure 180 may provide an electrical path for the operation of each memory cell. The first wiring structure 180 is formed on the fourth interlayer insulating film 144 and may be connected to the substrate 102, the channel structure CH and / or the gate contact GC. The number of layers and arrangement of the first wiring structure 180 are merely exemplary and are not limited to those shown in the figures.

[0134] The first wiring structure 180 may include a conductive material, such as, but not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and their alloys. As an example, the first wiring structure 180 may include copper (Cu) wiring.

[0135] Figures 25 to 29 This is an intermediate diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments. For ease of explanation, the above description will be briefly described or omitted. Figures 1 to 24 The repeated parts of the description.

[0136] Reference Figure 25 A substrate 102 is provided, comprising a memory cell block region (MBR) and a dummy cell block region (DBR). The dummy cell block region (DBR) may include an electrode region (ER) and a molding region (IR).

[0137] A first pre-stacked structure (not shown) comprising alternately stacked insulating layers 110_11…115_2n and sacrificial layers SL11…SL2n can be formed on substrate 102. The insulating layers 110_11…115_2n and sacrificial layers SL11…SL2n of the first pre-stacked structure (not shown) are formed in the memory block region MBR and the dummy block region DBR.

[0138] A channel structure CH is formed in the memory cell block region MBR that penetrates the first pre-stacked structure (not shown), and a dummy channel structure DCH can be formed in the electrode region ER.

[0139] The sacrificial layers SL11…SL2n of the first pre-stacked structure (not shown) are removed, and a second pre-stacked structure PSS1 and a second pre-stacked structure PSS2, comprising insulating layers 110_11…115_2n and gate electrodes GE11…GE2n stacked alternately, can be formed in the memory cell block region MBR.

[0140] In the memory cell block region MBR, a separation structure WLC can be formed in the separation structure hole WLCH that penetrates the first pre-stacked structure (not shown).

[0141] A pre-molded structure comprising alternating layers of insulating layers 110_11…115_2n and a third insulating layer SL11…SL2n can be formed in the molding region IR. The third insulating layer SL11…SL2n in the molding region IR may refer to the sacrificial layer that was not completely removed during the removal process of the sacrificial layer SL11…SL2n of the first pre-stacked structure (not shown) described above.

[0142] Subsequently, a gate contact hole GCH penetrating at least a portion of the pre-molded structure can be formed in the molding region IR. A contact insulating layer 162S and a sacrificial insulating layer P162 can be formed within the gate contact hole GCH. The contact insulating layer 162S can be conformally formed along the sidewalls and bottom of the gate contact hole GCH. The sacrificial insulating layer P162 can fill the remaining interior of the gate contact hole GCH after the contact insulating layer 162S is formed.

[0143] Reference Figure 26 The sacrificial insulating layer P162 of the molding region IR can be removed. With the removal of the sacrificial insulating layer P162, the contact insulating layer 162S can be exposed.

[0144] Reference Figure 27 Any one of the exposed third insulating layers SL11…SL2n can be formed in the molding region IR (e.g., Figure 8 The first recess RC1 of SL23. The first recess RC1 can be formed by removing a portion of one of the insulating layers 110-11…115-2n by, for example, an etch-back process.

[0145] Reference Figure 28 One of the third insulating layers SL11…SL2n can be removed using the first recess RC1 (e.g., Figure 8 At least a portion of SL23). That is, it can be one of the third insulating layers SL11…SL2n (e.g., Figure 8 A second recess RC2 extending in the horizontal direction is formed in the SL23. Therefore, one of the gate electrodes GE11…GE1n and GE21…GE2n can be formed in the molding region IR (e.g., Figure 8 The second recess RC2 adjacent to GE23).

[0146] Reference Figure 29 This allows the formation of a pad portion PD filling the second recess RC2 and a contact conductive layer 162. Therefore, it is possible to form a connection to any one of the gate electrodes GE11…GE1n and GE21…GE2n (e.g., Figure 8 The gate contact GC of GE23 can be formed in the same process as the pad portion PD and the contact conductive layer 162.

[0147] Then, a first contact pattern can be formed connecting to the channel structure CH. Figure 6 181) and the first conductor ( Figure 6 (182). A second contact pattern can be formed to connect to the gate contact GC. Figure 6 183) and the second conductor ( Figure 6 (of 184).

[0148] This process can be used to manufacture and use Figures 1 to 11 The semiconductor memory device described.

[0149] Figure 30 This is an exemplary block diagram used to illustrate an electronic system according to some embodiments. Figure 31 This is an exemplary perspective view used to illustrate an electronic system according to some embodiments. For ease of explanation, the above description will be brief or omitted. Figures 1 to 29 The repeated parts of the description.

[0150] Reference Figure 30 According to some embodiments, the electronic system 1000 may include a non-volatile memory device 1100 and a controller 1200 electrically connected to the non-volatile memory device 1100. The electronic system 1000 may be a storage device including one or more non-volatile memory devices 1100, or an electronic device including the storage device. For example, the electronic system 1000 may be an SSD (Solid State Drive), USB (Universal Serial Bus), computing system, medical device, or communication device including one or more non-volatile memory devices 1100.

[0151] The non-volatile memory device 1100 may be, for example, a NAND flash memory device, and may be, for example, the one described above. Figures 1 to 29 The semiconductor memory device described. The non-volatile memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0152] The first structure 1100F can be an external circuit structure, which includes a decoder circuit 1110 (e.g., Figure 1 The line decoder 33), page buffer 1120 (e.g., Figure 1 Page buffer 35) and logic circuit 1130 (e.g., Figure 1 Control logic 37).

[0153] The second structure 1100S may include the above-mentioned use Figure 1 and Figure 2The diagram describes the common source line CSL, multiple bit lines BL, and multiple cell strings CSTR. The cell strings CSTR can be connected to the decoder circuit 1110 via the word line WL, at least one string select line SSL, and at least one ground select line GSL. Additionally, the cell strings CSTR can be connected to the page buffer 1120 via the bit line BL.

[0154] In some embodiments, the common source line CSL and the cell string CSTR can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S.

[0155] In some embodiments, the bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S.

[0156] The non-volatile memory device 1100 can be electrically connected to the logic circuit 1130 (e.g., Figure 1 The I / O pads 1101 of the control logic 37 communicate with the controller 1200. The I / O pads 1101 can be electrically connected to the logic circuit 1130 via I / O connection wiring 1135 extending from the interior of the first structure 1100F to the second structure 1100S.

[0157] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of non-volatile memory devices 1100, and in this case, the controller 1200 may control the plurality of non-volatile memory devices 1100.

[0158] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access non-volatile memory device 1100. NAND controller 1220 may include NAND interface 1221, which handles communication with non-volatile memory device 1100. Control commands for controlling non-volatile memory device 1100, data to be recorded in memory cell transistors (MCTs) of non-volatile memory device 1100, and data to be read from memory cell transistors (MCTs) of non-volatile memory device 1100 can be sent through NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control non-volatile memory device 1100 in response to the control command.

[0159] Reference Figure 30 and Figure 31 According to some embodiments, the electronic system may include a motherboard 2001, a main controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the main controller 2002 via wiring patterns 2005 formed on the motherboard 2001.

[0160] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and placement of the pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host via any of the following interfaces: M-Phy for USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and UFS (Universal Flash Memory). In some embodiments, the electronic system 2000 may be operated by power supplied by the external host via the connector 2006. The electronic system 2000 may also include a PMIC (Power Management Integrated Circuit) that distributes power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

[0161] The main controller 2002 can record data in or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0162] DRAM 2004 can be a buffer memory used to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 can also operate as a high-speed cache memory and can also provide space for temporary data storage during control operations on the semiconductor package 2003. When the electronic system 2000 includes DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the main controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0163] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the underside of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0164] The package substrate 2100 may be a printed circuit board including pads 2130 on the package. Each semiconductor chip 2200 may include I / O pads 2210. The I / O pads 2210 may correspond to... Figure 30 I / O pad 1101.

[0165] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the I / O pad 2101 and the on-package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in the manner of bonding wires and may be electrically connected to the on-package pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including through-silicon vias (TSVs) instead of a bonding wire type connection structure 2400.

[0166] In some embodiments, the main controller 2002 and the semiconductor chip 2200 may also be included in a single package. In some embodiments, the main controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer substrate different from the motherboard 2001, and the main controller 2002 and the semiconductor chip 2200 may also be interconnected by wiring formed on the interposer substrate.

[0167] In an electronic system according to some embodiments, each of the semiconductor chips 2200 may include the features described above. Figures 1 to 29 The semiconductor memory device described herein. For example, each of the semiconductor chip 2200 may include a peripheral circuit region (PERI) and a memory cell region (CELL). As an example, the memory cell region (CELL) may include the components described above. Figures 1 to 29The substrate 102, gate stack structure GST, channel structure CH, dummy channel structure DCH, molded structure MST and gate contact GC are described.

[0168] Substrate 102 may include a memory cell block region (MBR) and a dummy cell block region (DBR). The dummy cell block region (DBR) may include an electrode region (ER) and a molding region (IR). In the memory cell block region (MBR) and the electrode region (ER), the gate stack structure (GST) may include insulating layers 110_11…115_2n and gate electrodes GE11…GE2n that are stacked alternately. In the memory cell block region (MBR), the channel structure (CH) may penetrate the gate stack structure (GST). In the electrode region (ER), the dummy channel structure (DCH) may penetrate the gate stack structure (GST). In the molding region (IR), the molding structure (MST) may include insulating layers 110_11…115_2n and third insulating layers SL11…SL2n that are stacked alternately, as well as pads (PD). The pads (PD) may be disposed in a specific insulating layer within the third insulating layers SL11…SL2n. The pads (PD) may be connected to a specific gate electrode within the gate electrodes GE11…GE2n. The gate contact GC penetrates at least a portion of the molded structure MST and can be connected to the pad portion PD. The gate contact GC can be connected to a specific gate electrode among the gate electrodes GE11…GE2n via the pad portion PD.

[0169] Although embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be made in various different forms. Those skilled in the art will understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, the above embodiments should be understood in all respects as illustrative and not restrictive.

Claims

1. A semiconductor memory device, comprising: A substrate extending in a first direction and a second direction intersecting each other, and including a first region and a second region spaced apart from the first region in the first direction surrounding the first region; A gate stack structure comprising, in the first region, a first insulating layer and a gate electrode layer stacked alternately on top of each other; A channel structure that penetrates the gate stack structure; A molded structure comprising, in the second region, a first insulating layer and a second insulating layer that are alternately stacked and have different materials from each other, each of the second insulating layers extending horizontally from each of the gate electrode layers; A separation structure that separates the first region and the second region in the first direction and extends in the second direction; as well as A first gate contact penetrates at least a portion of the molded structure and is connected to a first gate electrode layer in the gate electrode layer.

2. The semiconductor memory device according to claim 1, in, The first gate contact includes a first gate contact hole extending into the molded structure and a contact insulating layer and a contact conductive layer inside the first gate contact hole.

3. The semiconductor memory device according to claim 2, in, The entire lower side of the contact conductive layer is in contact with the first gate electrode layer.

4. The semiconductor memory device according to claim 2, in, A portion of the lower side of the contact conductive layer is in contact with the first gate electrode layer.

5. The semiconductor memory device according to claim 2, in, The first gate electrode layer comprises a material different from that of the contact conductive layer.

6. The semiconductor memory device according to claim 1, further comprising: A second gate contact, spaced apart from the first gate contact, penetrates at least a portion of the molded structure and is connected to the first gate electrode layer.

7. The semiconductor memory device according to claim 1, in, The separation structure is disposed between the channel structure and the first gate contact.

8. The semiconductor memory device according to claim 1, further comprising: A dummy gate stack structure includes a first insulating layer and a dummy gate electrode layer alternately stacked between a first region and a second region; as well as A dummy channel structure that penetrates the dummy gate stack structure.

9. The semiconductor memory device according to claim 8, in, The dummy channel structure includes the same material as the channel structure.

10. The semiconductor memory device of claim 1, further comprising: The peripheral circuit region on the substrate that is electrically connected to the first region.

11. The semiconductor memory device according to claim 1, in, Each of the gate electrode layers includes tungsten. Each of the first insulating layers comprises silicon oxide, and Each of the second insulating layers comprises silicon nitride.

12. A semiconductor memory device, comprising: A substrate extending in a first direction and a second direction that intersect each other, and comprising a first region, a second region and a third region that are distinct from each other, the second region being spaced apart from the first region in the first direction; A gate stack structure comprising, in the first region, a first insulating layer and a gate electrode layer stacked alternately on top of each other; A channel structure that penetrates the gate stack structure; Bit lines, which are connected to the channel structure and extend in the first direction; A dummy gate stack structure, which includes a second insulating layer and a dummy gate electrode layer stacked alternately in the second region; The first dummy channel structure penetrates the dummy gate stack structure; A separation structure that separates the first region and the second region in the first direction, and extends in the second direction between the channel structure and the first dummy channel structure; A molded structure comprising, in the third region, alternatingly stacked third and fourth insulating layers having different materials from each other, and further comprising a first pad portion connecting one of the third insulating layers to one of the gate electrode layers; and A first gate contact penetrates at least a portion of the molded structure and is connected to the first pad portion.

13. The semiconductor memory device according to claim 12, in, The width of the first pad portion is greater than the width of the first gate contact.

14. The semiconductor memory device according to claim 12, in, The molding structure further includes a second pad portion, which connects one of the third insulating layers and one of the gate electrode layers, and is spaced apart from the first pad portion; as well as A second gate contact penetrates at least a portion of the molded structure and is connected to the second pad portion.

15. The semiconductor memory device of claim 12, further comprising: A second dummy channel structure is spaced apart from the first dummy channel structure in the first direction in the third region, wherein the first pad portion is inserted between the first dummy channel structure and the second dummy channel structure.

16. The semiconductor memory device of claim 12, further comprising: Multiple separation patterns are spaced apart from the separation structure in the second region in the first direction.

17. The semiconductor memory device of claim 12, further comprising: A second dummy channel structure is spaced apart from the first gate contact in the second direction in the third region.

18. The semiconductor memory device of claim 12, further comprising: The second dummy channel structure overlaps with each of the second and third regions and has dimensions different from those of the first dummy channel structure.

19. The semiconductor memory device of claim 12, further comprising: The second dummy channel structure is spaced apart from the first gate contact in the second direction in the third region and has dimensions different from those of the first dummy channel structure.

20. An electronic system comprising: Motherboard; A semiconductor memory device on the motherboard; as well as A controller, electrically connected to the semiconductor memory device on the motherboard, The semiconductor memory device includes: The substrate extends in each of a first direction and a second direction that intersect each other, and includes a first region, a second region and a third region that are different from each other, the second region being spaced apart from the first region in the first direction; A gate stack structure comprising, in the first region, a first insulating layer and a gate electrode layer stacked alternately on top of each other; A channel structure that penetrates the gate stack structure; A dummy gate stack structure, which includes a second insulating layer and a dummy gate electrode layer stacked alternately in the second region; A dummy channel structure that penetrates the dummy gate stack structure; A separation structure that separates the first region and the second region in the first direction and extends in the second direction; A molded structure comprising, in the third region, a third insulating layer and a fourth insulating layer having different materials and stacked alternately, and a pad portion connected to one of the third insulating layers and one of the gate electrode layers; and A gate contact that penetrates at least a portion of the molded structure and is connected to the pad portion.

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