Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a barrier layer located at least between adjacent memory cell regions in a substrate, the barrier layer having second doped ions, wherein the type of the second doped ions is the same as the type of first doped ions, and the concentration of the second doped ions is greater than the concentration of the first doped ions; a stack gate structure located on a bit line of the memory cell region; an isolation layer located on the substrate exposed by the bit line, and the bottom of the isolation layer is in contact with the top of the barrier layer; in the embodiment, because the concentration of the second doped ions is greater than the concentration of the first doped ions, a built-in electric field is generated in the direction of the barrier layer pointing to the bit line, which is beneficial to the flow of electrons in the channel depletion layer in the barrier bit line from the bottom of the isolation layer to the adjacent memory cell region, accordingly reduces the probability of the flow of electrons in the channel depletion layer from the bottom of the isolation layer to the adjacent memory cell region, thereby reducing the leakage current at the bottom of the isolation layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] The main characteristics of flash memory are that it can retain stored information for a long time without applying voltage, and it has the advantages of high integration, fast access speed, and easy erasure and rewriting. Therefore, it has been widely used in many fields such as microcomputers and automation control.

[0003] Depending on their structure, flash memory can be divided into two types: NOR Flash and NAND Flash. NAND flash memory devices have advantages such as higher cell density, higher storage density, and faster write and erase speeds, and have gradually become the most commonly used structure in flash memory. Currently, they are mainly used in flash memory cards for digital cameras and MP3 players.

[0004] However, the performance of NAND flash memory devices still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the durability and service life of semiconductor devices.

[0006] To address the aforementioned problems, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate on which bit lines are formed, the bit lines having first doped ions, the substrate including adjacent spaced memory cell regions, the bit lines being located within the memory cell regions; a barrier layer located at least in the substrate between adjacent memory cell regions, the barrier layer having second doped ions, wherein the type of the second doped ions is the same as the type of the first doped ions, and the concentration of the second doped ions is greater than the concentration of the first doped ions; an isolation layer located on the substrate where the bit lines are exposed, and the bottom of the isolation layer contacting the top of the barrier layer; and a stacked gate structure located on the bit lines of the memory cell regions, the stacked gate structure including a tunneling oxide layer and a floating gate layer located on the tunneling oxide layer.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein bit lines are formed on the substrate, the bit lines having first doped ions, the substrate including adjacent spaced memory cell regions, the bit lines being located in the memory cell regions; forming a barrier layer in the substrate at least between adjacent memory cell regions, the barrier layer having second doped ions, the type of the second doped ions being the same as the type of the first doped ions, and the concentration of the second doped ions being greater than the concentration of the first doped ions; forming an isolation layer on the substrate where the bit lines are exposed, and the bottom of the isolation layer contacting the top of the barrier layer; and after forming the isolation layer, forming a stacked gate structure on the bit lines of the memory cell regions, the stacked gate structure including a tunneling oxide layer and a floating gate layer located on the tunneling oxide layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a semiconductor structure, comprising: a substrate on which bit lines are formed, the bit lines having first doped ions, the substrate including adjacent spaced memory cell regions, the bit lines being located within the memory cell regions; a barrier layer located at least in the substrate between adjacent memory cell regions, the barrier layer having second doped ions of the same type as the first doped ions, and the concentration of the second doped ions being greater than the concentration of the first doped ions; an isolation layer located on the substrate where the bit lines are exposed, the bottom of the isolation layer contacting the top of the barrier layer; and a stacked gate structure located within the memory cell regions. On the bit line of the domain, the stacked gate structure includes a tunneling oxide layer and a floating gate layer located on the tunneling oxide layer. In this embodiment, since a barrier layer is formed in the substrate, the barrier layer has a second doped ion, the top of the barrier layer is in contact with the bottom of the isolation layer, and the concentration of the second doped ion is greater than the concentration of the first doped ion, a built-in electric field is generated along the direction of the barrier layer pointing to the bit line. The built-in electric field facilitates the flow of electrons in the channel depletion layer in the barrier bit line from the bottom of the isolation layer to the adjacent memory cell region, thereby reducing the leakage current at the bottom of the isolation layer and thus improving the durability and lifespan of the semiconductor device (e.g., write and erase operations are increased to 8000 times).

[0010] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein bit lines are formed on the substrate, the bit lines having first doped ions, the substrate including adjacent spaced memory cell regions, the bit lines being located in the memory cell regions; forming a barrier layer in the substrate at least between adjacent memory cell regions, the barrier layer having second doped ions, the type of the second doped ions being the same as the type of the first doped ions, and the concentration of the second doped ions being greater than the concentration of the first doped ions; forming an isolation layer on the substrate where the bit lines are exposed, the bottom of the isolation layer being in contact with the top of the barrier layer; and after forming the isolation layer, forming a method for forming a semiconductor structure in the memory cell region. A stacked gate structure is formed on the bit line of the storage cell region. The stacked gate structure includes a tunneling oxide layer and a floating gate layer located on the tunneling oxide layer. In this embodiment, since a barrier layer is formed in the substrate, the barrier layer has a second doped ion. The top of the barrier layer is in contact with the bottom of the isolation layer, and the concentration of the second doped ion is greater than the concentration of the first doped ion. Therefore, a built-in electric field is generated along the direction of the barrier layer pointing to the bit line. The built-in electric field facilitates the flow of electrons in the channel depletion layer in the barrier bit line from the bottom of the isolation layer to the adjacent storage cell region, thereby reducing the leakage current at the bottom of the isolation layer and improving the durability and lifespan of the semiconductor device (e.g., write and erase operations are increased to 8000 times). Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a semiconductor structure.

[0012] Figure 2 yes Figure 1 The diagram shows the characteristic curves of the durability of the semiconductor structure.

[0013] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0014] Figure 4 yes Figure 3 A characteristic curve of the durability of a semiconductor structure according to an embodiment of the present invention;

[0015] Figures 5 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0016] Currently, the durability and lifespan of semiconductor devices still need improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a schematic diagram of a semiconductor structure as an example.

[0017] Figure 1 This is a schematic diagram of a semiconductor structure. Figure 2 yes Figure 1 Characteristic curves of the durability of semiconductor structures.

[0018] refer to Figure 1 The semiconductor structure includes: a substrate 10 on which bit lines 18 are formed, the bit lines 18 having first doped ions, the substrate 10 including a memory cell region i, the bit lines 18 being located in the memory cell region i; an isolation layer 12 located on the substrate 10 adjacent to the bit lines 18 exposed; and a stacked gate structure 11 located on the bit lines 18 of the memory cell region i, the stacked gate structure 11 including a tunneling oxide layer 13 located on the bit lines 18 of the memory cell region i, a floating gate layer 14 located on the tunneling oxide layer 13, an inter-gate dielectric layer 15 located on the top and sidewalls of the floating gate layer 14, and a control gate layer 16 located on the top and sidewalls of the inter-gate dielectric layer 15.

[0019] Reference Figure 2 , Figure 2 yes Figure 1 The graph shown represents the characteristic curves of the durability of the semiconductor structure, where the horizontal axis represents the threshold voltage (V) of the memory cell. T The vertical axis represents the number of failed memory cell regions. The curves within the solid boxes represent memory cells with threshold voltages within the normal range, while the curves within the dashed boxes represent memory cells with threshold voltages exceeding the normal range. Figure 2 As can be seen, there are a large number of storage units within the dashed box, meaning that a large number of storage units have program disturb problems.

[0020] Specifically, when only a voltage is applied to the stacked gate structure 11, a channel depletion layer 17 will be formed in the bit line 18 at the bottom of the stacked gate structure 11 due to the presence of first doped ions in the bit line 18 (e.g., Figure 1 As shown in the figure, the channel potential increases. With repeated write and erase operations, the tunneling oxide layer 13 in the stacked gate structure 11 is damaged, thereby weakening the ability of the tunneling oxide layer 13 to prevent electrons in the channel depletion layer 17 from entering the floating gate layer 14. At the same time, due to the potential difference between the channel (not shown) and the floating gate layer 14, electrons in the channel depletion layer 17 can more easily enter the floating gate layer 14, correspondingly reducing the thickness of the channel depletion layer 17, thereby reducing the channel potential. This can easily lead to programming interference problems, reducing the durability and lifespan of the semiconductor device.

[0021] Furthermore, there is a potential difference between the stacked gate structures 11 in adjacent memory cell regions i, which in turn causes a potential difference between the channel depletion layer 17 in any bit line 18 and the bit line 18 in the adjacent memory cell region i. This makes it easy for electrons in the channel depletion layer 17 in any bit line 18 to flow through the bottom of the isolation layer 12 to the adjacent memory cell region i, thereby increasing the leakage current at the bottom of the isolation layer 12 and reducing the durability and lifespan of the semiconductor device.

[0022] The substrate 10 and the adjacent bit line 18 form a groove (not shown) for accommodating the isolation layer. Currently, in order to reduce leakage current at the bottom of the isolation layer 12, the commonly used method is to increase the depth of the groove corresponding to the formation of the isolation layer. However, due to the limitations of existing process conditions, the morphology quality of the groove sidewalls is easily poor, which affects the performance of the semiconductor device and further reduces the durability and lifespan of the semiconductor device.

[0023] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate having bit lines formed thereon, the bit lines having first doped ions, the substrate including adjacent spaced memory cell regions, the bit lines being located within the memory cell regions; a barrier layer located at least in the substrate of adjacent memory cell regions, the barrier layer having second doped ions of the same type as the first doped ions, and the concentration of the second doped ions being greater than the concentration of the first doped ions; a stacked gate structure located on the bit lines of the memory cell regions, the stacked gate structure including a tunneling oxide layer and a floating gate layer located on the tunneling oxide layer; and an isolation layer located on the substrate where the bit lines are exposed, the bottom of the isolation layer being in contact with the top of the barrier layer.

[0024] In the scheme disclosed in the embodiments of the present invention, since a barrier layer is formed in the substrate, the barrier layer has a second doped ion, the top of the barrier layer is in contact with the bottom of the isolation layer, and the concentration of the second doped ion is greater than the concentration of the first doped ion, a built-in electric field is generated along the direction of the barrier layer pointing to the bit line. The built-in electric field facilitates the flow of electrons in the channel depletion layer in the barrier bit line from the bottom of the isolation layer to the adjacent memory cell region, thereby reducing the leakage current at the bottom of the isolation layer and thus improving the durability and lifespan of the semiconductor device (e.g., write and erase operations are increased to 8000 times).

[0025] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0027] refer to Figure 3 The semiconductor structure includes: a substrate 100, on which bit lines 109 are formed, the bit lines 109 having first doped ions, the substrate 100 including a memory cell region I, the bit lines 109 being located in the memory cell region I; a barrier layer 101, located at least between adjacent memory cell regions I in the substrate 100, the barrier layer 101 having second doped ions, the type of the second doped ions being the same as the type of the first doped ions, and the concentration of the second doped ions being greater than the concentration of the first doped ions; an isolation layer 103, located on the substrate 100 exposed by the bit lines 109, and the bottom of the isolation layer 103 contacting the top of the barrier layer 101; and a stacked gate structure 102, located on the bit lines 109 of the memory cell region I, the stacked gate structure 102 including a tunneling oxide layer 105 and a floating gate layer 106 located on the tunneling oxide layer 105.

[0028] refer to Figure 4 In conjunction with references Figure 2 , Figure 4 yes Figure 3 The present invention provides a characteristic curve of the durability of a semiconductor structure according to an embodiment of the present invention. The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of failed memory cell regions. Curves within solid lines represent memory cell threshold voltages within the normal range, while curves within dashed lines represent memory cell threshold voltages exceeding the normal range. Figure 4 and Figure 2 In comparison, from Figure 4 As can be seen from the curve within the dashed box, the number of memory cell regions I with programming interference problems is less than [a certain number]. Figure 2 The number of memory cell regions I with programming interference problems. Specifically, since a barrier layer 101 is formed in the substrate 100, the barrier layer 101 has second doped ions, the top of the barrier layer 101 is in contact with the bottom of the isolation layer 103, and the concentration of the second doped ions is greater than the concentration of the first doped ions, a built-in electric field is generated along the direction of the barrier layer 101 pointing to the bit line 109. The built-in electric field facilitates the flow of electrons in the channel depletion layer 104 in the barrier bit line 109 from the bottom of the isolation layer 103 to the adjacent memory cell region I, thereby reducing the leakage current at the bottom of the isolation layer 103, and thus improving the durability and lifespan of the semiconductor device (e.g., write and erase operations increased to 8000 times).

[0029] Substrate 100 serves as a process platform for subsequent flash memory fabrication processes. Specifically, substrate 100 is used to form NAND flash memory.

[0030] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0031] In this embodiment, the first doped ion in bit line 109 is a P-type doped ion.

[0032] As an example, the first dopant ion includes boron (B) ions. In other embodiments, the first dopant ion may also be other Group IIIA elements.

[0033] Specifically, when the first doped ion is a P-type ion, the concentration of the first doped ion is less than 3.4E13 atoms per cubic centimeter.

[0034] It should be noted that when a voltage is applied to the stacked gate structure, since the bit line 109 contains the first doped ions, a channel depletion layer 104 is generated in the bit line 109 at the bottom of the stacked gate structure 102. At this time, since the concentration of the first doped ions is less than 3.4E13 atoms per cubic centimeter, that is, the concentration of the first doped ions is reduced, the thickness of the channel depletion layer 104 in the bit line 109 can be increased, and the potential of the channel (not shown) is increased accordingly, thereby improving the programming interference problem and thus improving the durability and lifespan of the semiconductor device.

[0035] It should also be noted that the concentration of the first doped ion is less than 3.4E13 atoms per cubic centimeter, that is, the concentration of the first doped ion is reduced, which correspondingly increases the thickness of the channel depletion layer 104 in the bit line 109, thereby increasing the potential of the channel (not shown), and further enhancing the electric field strength along the direction of the channel pointing to the bit line 109 in the adjacent memory cell region I. However, since a barrier layer 101 is formed in the substrate 100, the barrier layer 101 has second doped ions, the top of the barrier layer 101 is in contact with the bottom of the isolation layer 103, and the concentration of the second doped ion is greater than the concentration of the first doped ion, a built-in electric field is generated along the direction of the barrier layer 101 pointing to the bit line 109. The built-in electric field facilitates the flow of electrons in the channel in the barrier bit line 109 from the bottom of the isolation layer 103 to the adjacent memory cell region I, thereby reducing the leakage current at the bottom of the isolation layer 103, and thus improving the durability and lifespan of the semiconductor device.

[0036] Specifically, the concentration of the first doped ion should not be too high or too low. If the concentration of the first doped ion is too high, the thickness of the channel depletion layer 104 will be reduced accordingly, thereby lowering the channel potential. If the concentration of the first doped ion is too low, it will easily affect the threshold voltage of the semiconductor structure, thereby easily causing the threshold voltage of the semiconductor structure to exceed the preset threshold voltage range. Therefore, when the first doped ion is a P-type ion, the concentration of the first doped ion is between 2.4E13 atoms per cubic centimeter and 3.4E13 atoms per cubic centimeter.

[0037] In another embodiment, the first dopant ion in the bit line is an N-type dopant ion. As an example, the first dopant ion includes a phosphorus (P) ion.

[0038] Accordingly, when the first doped ion is an N-type ion, the concentration of the first doped ion is less than 4.0 E13 atoms per cubic centimeter. As an example, when the first doped ion is an N-type ion, the concentration of the first doped ion is between 2.6 and 3.8 E13 atoms per cubic centimeter.

[0039] The memory cell region I is used to provide a process platform for forming the stacked gate structure 102 and the isolation layer 103.

[0040] Bit line 109 and stacked gate structure 102 work together to select memory cell region I for a specific operation.

[0041] In this embodiment, the barrier layer 101 is located at least in the substrate 100 between adjacent memory cell regions I, which helps the barrier layer 101 to prevent electrons in the channel depletion layer 104 from flowing from the bottom of the isolation layer 103 to the adjacent memory cell region I.

[0042] As an example, the barrier layer 101 extends along the arrangement direction of the memory cell region I, and the barrier layer 101 also extends into the substrate 100 of the memory cell region I. This is beneficial for the barrier layer 101 to further prevent electrons in the channel depletion layer 104 from flowing from the bottom of the isolation layer 103 to the adjacent memory cell region I, thereby improving the blocking effect.

[0043] In other embodiments, the barrier layer may also be located only in the substrate between adjacent memory cell regions.

[0044] In this embodiment, the type of the second doped ion is the same as that of the first doped ion, which helps to reduce the electromigration effect of the semiconductor structure and thus improve the durability of the semiconductor structure.

[0045] Therefore, when the first doped ion in bit line 109 is a P-type ion, the second doped ion is also a P-type ion.

[0046] Specifically, the second dopant ion comprises a Group IIIA element. In this embodiment, the second dopant ion comprises a boron ion. In other embodiments, the second dopant ion may also be another Group IIIA element of the same type as the first dopant ion.

[0047] When the second dopant ion is a P-type ion, its concentration should not be too high or too low. If the concentration is too high, it will not further enhance the ability of the barrier layer 101 to prevent electrons in the channel depletion layer 104 from flowing from the bottom of the isolation layer 103 to the adjacent memory cell region I, and will also waste resources. If the concentration is too low, the barrier layer 101 may not effectively prevent electrons in the channel depletion layer 104 from flowing from the bottom of the isolation layer 103 to the adjacent memory cell region I. Therefore, in this embodiment, when the second dopant ion is a P-type ion, its concentration is between 1.2E13 atoms per cubic centimeter and 1.4E13 atoms per cubic centimeter.

[0048] In another embodiment, when the first dopant ion is a group VA element, the corresponding second dopant ion of the barrier layer is also a group VA element.

[0049] Specifically, when the second doped ion is an N-type ion, the concentration of the second doped ion is from 8.0E12 atoms per cubic centimeter to 1.0E13 atoms per cubic centimeter.

[0050] In this embodiment, the thickness h of the barrier layer 101 should not be too large or too small. If the thickness h of the barrier layer 101 is too large, it will easily increase the process time for forming the barrier layer 101, thereby reducing the production capacity; if the thickness h of the barrier layer 101 is too small, the barrier layer 101 may not be effective in preventing electrons in the channel depletion layer 104 from flowing from the bottom of the isolation layer 103 to the adjacent memory cell region I. Therefore, in this embodiment, the thickness h of the barrier layer 101 is 20 nanometers to 50 nanometers.

[0051] In this embodiment, the distance L between the top surface of the barrier layer 101 and the top surface of the bit line 109 should not be too large or too small. If the distance L between the top surface of the barrier layer 101 and the top surface of the bit line 109 is too large, it will not further enhance the ability of the barrier layer 101 to prevent electrons in the channel depletion layer 104 from flowing from the bottom of the isolation layer 103 to the adjacent memory cell region I, and it will also cause a waste of resources. If the distance L between the top surface of the barrier layer 101 and the top surface of the bit line 109 is too small, the barrier layer 101 may not be effective in preventing electrons in the channel depletion layer 104 from flowing from the bottom of the isolation layer 103 to the adjacent memory cell region I. Therefore, in this embodiment, the distance L between the top surface of the barrier layer 101 and the top surface of the bit line 109 is 190 nanometers to 210 nanometers.

[0052] The stacked gate structure 102 is used as a cell structure for storing data in a memory.

[0053] In this embodiment, the stacked gate structure 102 includes: a tunneling oxide layer 105 located on the bit line 109 of the memory cell region I; and a floating gate layer 106 located on the tunneling oxide layer 105.

[0054] It should be noted that the tunneling oxide layer 105 serves as an insulating layer between the floating gate layer 106 and the substrate 100, allowing electrons to enter the floating gate layer 106 via the tunneling oxide layer 105 during NAND flash memory operation. In this embodiment, the material of the tunneling oxide layer 105 is silicon oxide. The floating gate layer 106 serves to store electrons during the formation of the NAND flash memory, thereby enabling the NAND flash memory to perform data storage functions. In this embodiment, the material of the floating gate layer 106 is polysilicon.

[0055] In this embodiment, the stacked gate structure 102 further includes: an inter-gate dielectric layer 107 located on the top and sidewalls of the floating gate layer 106; and a control gate layer 108 located on the top and sidewalls of the inter-gate dielectric layer 107.

[0056] It should be noted that the inter-gate dielectric layer 107 serves as an insulating layer between the floating gate layer 106 and the control gate layer 108. In this embodiment, the material of the inter-gate dielectric layer 107 includes silicon oxide or silicon nitride. The control gate layer 108 serves as part of the stacked gate structure 102 of the NAND memory. In this embodiment, the material of the control gate layer 108 is polysilicon.

[0057] The isolation layer 103 is used to isolate devices in adjacent memory cell regions I. Specifically, the isolation layer 103 is a shallow trench isolation (STI) structure.

[0058] The insulating layer 103 can be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. As an example, the insulating layer 103 is made of silicon oxide.

[0059] It should be noted that the bottom of the isolation layer 103 is in contact with the top of the barrier layer 101, which helps to further enhance the ability of the barrier layer 101 to prevent electrons in the channel depletion layer 104 from flowing from the bottom of the isolation layer 103 to the adjacent memory cell region I.

[0060] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0061] refer to Figures 5 to 9 A substrate 500 is provided, on which bit lines 512 (e.g.) are formed. Figure 9 As shown in the figure, the bit line 512 has a first doped ion, the substrate includes memory cell regions I' arranged at adjacent intervals, and the bit line 512 is located in the memory cell region I'.

[0062] The memory cell region I' is used to provide a process platform for forming the stacked gate structure and isolation layer.

[0063] Bit line 512 works in conjunction with the subsequently formed stacked gate structure to select memory cell region I' for a specific task.

[0064] Substrate 500 serves as a process platform for subsequent flash memory fabrication processes. Specifically, substrate 500 is used to form NAND flash memory.

[0065] In this embodiment, the substrate 500 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0066] In this embodiment, the step of providing the substrate 500 includes: referencing Figure 5 An initial substrate 513 is provided, a portion of the initial substrate 513 serving as a substrate 500, and the remaining portion of the initial substrate 513 above the substrate 500 serving as a bit line material layer 514; Continuing to refer to Figure 5 The initial substrate 513 is subjected to first ion doping, forming first doped ions in the initial substrate 513; Reference Figures 6 to 9After doping the first doped ions in the initial substrate 513, the bit line material layer 514 located between adjacent memory cell regions I' is removed, and the bit line material layer 514 is patterned as a bit line 512 located in the memory cell region I'.

[0067] The initial substrate 513 is used to form the substrate 500 and the bit line 512.

[0068] Bit line material layer 514 is used to form bit line 512.

[0069] It should be noted that performing first ion doping on the initial substrate 513 and removing the bit line material layer 514 located between adjacent memory cell regions I' after forming the first doped ions in the initial substrate 513 is beneficial to improving the uniformity of the concentration distribution of the first doped ions in the bit line 512 and the substrate 500, thereby improving the stability of the electrical performance of the semiconductor structure.

[0070] It should also be noted that after the first doped ions are doped in the initial substrate 513, the bit line material layer 514 located between adjacent memory cell regions I' is removed to prepare for the subsequent formation of an isolation layer between adjacent memory cell regions I'.

[0071] In this embodiment, the first doped ion in bit line 512 is a P-type doped ion.

[0072] As an example, the first dopant ion includes a boron ion. In other embodiments, the first dopant ion may also be other Group IIIA elements.

[0073] In another embodiment, the first dopant ion in the bit line is an N-type dopant ion. As an example, the first dopant ion includes a phosphorus (P) ion.

[0074] In this embodiment, in the step of providing the substrate 500, the first doped ions in the bit line 512 are obtained through a first ion implantation process.

[0075] Specifically, the first ion implantation process has advantages such as high resolution, precise control and no need for physical contact, and can be used to achieve highly controllable ion implantation, which is beneficial for the precise formation of the first dopant ion in the in-situ line 512.

[0076] In this embodiment, when the first doped ion is a P-type doped ion, the parameters of the first ion implantation process include: the implantation dose of the first doped ion is less than 3.6E13 atoms per square centimeter, and the implantation energy is 25,000 electron volts to 30,000 electron volts.

[0077] When a voltage is applied to the stacked gate structure, a channel depletion layer 504 is generated in the bit line 512 at the bottom of the stacked gate structure due to the presence of first doped ions in the bit line 512. At this time, since the implantation dose of the first doped ions is less than 3.6E13 atoms per square centimeter, that is, the concentration of the first doped ions is reduced, the thickness of the channel depletion layer 504 in the bit line 512 can be increased, and the potential of the channel (not shown) is increased accordingly, thereby improving the programming interference problem and thus improving the durability and lifespan of the semiconductor device.

[0078] It should also be noted that the concentration of the first doped ion is less than 3.4E13 atoms per cubic centimeter, that is, the concentration of the first doped ion is reduced, which correspondingly increases the thickness of the channel depletion layer 504 in the bit line 512, thereby increasing the potential of the channel (not shown), and thus enhancing the electric field strength along the direction of the channel pointing to the bit line 512 in the adjacent memory cell region I'. However, since a barrier layer is subsequently formed in the substrate 500, the barrier layer has a second doped ion, the top of the barrier layer is in contact with the bottom of the isolation layer, and the concentration of the second doped ion is greater than the concentration of the first doped ion. Therefore, a built-in electric field is generated along the direction of the barrier layer pointing to the bit line 512. The built-in electric field helps to prevent electrons in the channel of the bit line 512 from flowing from the bottom of the isolation layer to the adjacent memory cell region I', thereby reducing the leakage current at the bottom of the isolation layer and thus improving the durability and lifespan of the semiconductor device.

[0079] As an example, when the first dopant ion is a P-type dopant ion, the implantation dose of the first dopant ion ranges from 2.6E13 atoms per square centimeter to 3.6E13 atoms per square centimeter.

[0080] In this embodiment, the implantation energy of the first dopant ion should not be too high or too low. If the implantation energy of the first dopant ion is too high, the implantation depth of the first dopant ion is likely to be too deep, thereby reducing the carrier mobility and affecting the electrical performance of the channel. If the implantation energy of the first dopant ion is too low, the doped ion may not be able to be fully implanted into the bit line 512, thereby reducing the probability of channel formation. Therefore, in this embodiment, the implantation energy of the first dopant ion is 25,000 electron volts to 30,000 electron volts.

[0081] In another embodiment, when the first doped ion is an N-type doped ion, the parameters of the first ion implantation process include: the implantation dose of the first doped ion is less than 4.2E13 atoms per square centimeter, and the implantation energy is 25,000 electron volts to 30,000 electron volts.

[0082] Specifically, when the first doped ion is an N-type doped ion, the implantation dose of the first doped ion is 2.8E13 atoms per square centimeter to 4.0E13 atoms per square centimeter.

[0083] refer to Figures 6 to 8 At least in the substrate 500 between adjacent memory cell regions I', a barrier layer 501 is formed (e.g., Figures 7 to 8 As shown), the barrier layer 501 has a second doped ion, wherein the type of the second doped ion is the same as the type of the first doped ion, and the concentration of the second doped ion is greater than the concentration of the first doped ion.

[0084] It should be noted that, since a barrier layer 501 is formed in the substrate 500, the barrier layer 501 has second doped ions, the top of the barrier layer 501 is in contact with the bottom of the isolation layer, and the concentration of the second doped ions is greater than the concentration of the first doped ions, a built-in electric field is generated along the direction of the barrier layer 501 pointing to the bit line 512. The built-in electric field facilitates the flow of electrons in the channel depletion layer 504 in the barrier bit line 512 from the bottom of the isolation layer to the adjacent memory cell region I', thereby reducing the leakage current at the bottom of the isolation layer and thus improving the durability and lifespan of the semiconductor device (e.g., write and erase operations are increased to 8000 times).

[0085] In this embodiment, after doping the first doped ions in the initial substrate 513 and before removing the bit line material layer 514 located between adjacent memory cell regions I', the method further includes: forming a barrier layer 501 in the substrate 500 between adjacent memory cell regions I', which is beneficial to improve the uniformity of the concentration distribution of the second doped ions in the substrate 500, thereby generating a built-in electric field of uniform intensity along the direction of the barrier layer 501 pointing to the bit line 512.

[0086] In this embodiment, the barrier layer 501 is located at least in the substrate 500 between adjacent memory cell regions I', which helps the barrier layer 501 to prevent electrons in the channel depletion layer 504 from flowing from the bottom of the isolation layer to the adjacent memory cell region I'.

[0087] As an example, the barrier layer 501 extends along the arrangement direction of the memory cell region I', and the barrier layer 501 also extends into the substrate 500 of the memory cell region I'. This is advantageous because, in the process of forming the barrier layer 501, no additional photomask is needed, and the barrier layer 501 can be located in the substrate 500 of the memory cell region I' and in the substrate 500 between adjacent memory cell regions I', thereby reducing process costs.

[0088] In other embodiments, the barrier layer may also be located only in the substrate between adjacent memory cell regions.

[0089] In this embodiment, the step of forming a barrier layer 501 in the substrate 500 at least between adjacent memory cell regions I' includes: performing a second ion doping on the region of the substrate 500 where the barrier layer 501 is to be formed to form the barrier layer 501, wherein the region where the barrier layer is to be formed includes at least the region between adjacent memory cell regions I'.

[0090] It should be noted that by forming the barrier layer 501 through the second ion doping step, the function of preventing electrons in the channel depletion layer 504 from flowing from the bottom of the isolation layer to the adjacent memory cell region I' is achieved without the need for additional deposition or etching steps, thus simplifying the process flow.

[0091] Specifically, the step of performing a second ion doping on the region of the substrate 500 where the barrier layer is to be formed includes: (Referring to...) Figure 6 A mask layer 510 with a mask opening 515 is formed on the substrate 500, the mask opening 515 being located above the region of the substrate 500 where the barrier layer is to be formed; Reference Figure 7 Using the mask layer 510 as a mask, the substrate 500 at the bottom of the mask opening 515 is subjected to a second ion doping to form a barrier layer 501; Reference Figure 8 After forming the barrier layer 501, the process further includes removing the mask layer 510.

[0092] The mask layer 510 is used to protect areas that do not require ion doping.

[0093] In this embodiment, the mask layer 510 is made of photoresist. Specifically, the photoresist has high resolution, allowing for precise control over the area where the barrier layer 501 is formed; simultaneously, the photoresist is easy to remove, thereby reducing process complexity and improving production efficiency. In other embodiments, the mask layer may also be made of other materials that can serve as etching masks and are easy to remove, such as silicon oxide.

[0094] In this embodiment, the second ion doping process includes a second ion implantation process.

[0095] It should be noted that the second ion implantation process has advantages such as high resolution, precise control and no need for physical contact, and can be used to achieve highly controllable ion implantation, which is beneficial for accurately forming the barrier layer 501 in the substrate 500.

[0096] In this embodiment, the type of the second doped ion is the same as that of the first doped ion, which helps to reduce the electromigration effect of the semiconductor structure and thus improve the durability of the semiconductor structure.

[0097] Therefore, when the first doped ion in bit line 512 is a P-type ion, the second doped ion is also a P-type ion.

[0098] Specifically, the second dopant ion includes a Group IIIA element. In this embodiment, the second dopant ion includes a boron ion. In other embodiments, the second dopant ion may also be another Group IIIA element of the same type as the first dopant ion.

[0099] When the second doped ion is a P-type ion, the parameters of the second ion implantation process include: an implantation energy of 100 keV to 120 keV and an implantation dose of 1.4E13 atoms per square centimeter to 1.6E13 atoms per square centimeter.

[0100] When the second doped ion is a p-type ion, the implantation dose of the second ion implantation process should not be too high or too low. If the implantation dose of the second ion implantation process is too high, the concentration of the second doped ion will be too high, which will not further enhance the ability of the barrier layer 501 to prevent electrons in the channel depletion layer 504 from flowing from the bottom of the isolation layer to the adjacent memory cell region I', and will also cause a waste of resources. If the implantation dose of the second ion implantation process is too low, the concentration of the second doped ion will be too low, which will make the barrier layer 501 less effective in preventing electrons in the channel depletion layer 504 from flowing from the bottom of the isolation layer to the adjacent memory cell region I'. Therefore, in this embodiment, the implantation dose of the second ion implantation process is 1.4E13 atoms per square centimeter to 1.6E13 atoms per square centimeter.

[0101] In this embodiment, the implantation energy of the second ion implantation process should not be too high or too low. If the implantation energy of the second ion implantation process is too high, the distance between the barrier layer 501 and the top surface of the substrate 500 will be too large, resulting in an excessively deep groove corresponding to the formation of the isolation layer. This can lead to poor morphology quality of the groove sidewalls, affecting the performance of the semiconductor device and further reducing its durability and lifespan. If the implantation energy of the second ion implantation process is too low, the distance between the barrier layer 501 and the top surface of the substrate 500 will be too small, thus reducing the barrier layer 501's effectiveness in preventing electrons in the channel depletion layer 504 from flowing from the bottom of the isolation layer to the adjacent memory cell region I'. Therefore, in this embodiment, the implantation energy of the second ion implantation process is 100 keV to 120 keV.

[0102] In another embodiment, when the first doped ion is an N-type ion, the corresponding second doped ion of the barrier layer is also an N-type ion.

[0103] Specifically, when the second doped ion is an N-type ion, the parameters of the second ion implantation process include: an implantation dose of 1.0E13 atoms per square centimeter to 1.2E13 atoms per square centimeter, and an implantation energy of 100 keV to 120 keV.

[0104] In this embodiment, the thickness H of the barrier layer 501 should not be too large or too small. If the thickness H of the barrier layer 501 is too large, it will easily increase the process time for forming the barrier layer 501, thereby reducing the production capacity; if the thickness H of the barrier layer 501 is too small, the barrier layer 501 will not be able to effectively prevent electrons in the channel depletion layer from flowing from the bottom of the isolation layer to the adjacent memory cell region I'. Therefore, in this embodiment, the thickness H of the barrier layer 501 is 20 nanometers to 50 nanometers.

[0105] In this embodiment, the distance l between the top surface of the barrier layer 501 and the top surface of the bit line 512 should not be too large or too small. If the distance l between the top surface of the barrier layer 501 and the top surface of the bit line 512 is too large, it will not further enhance the ability of the barrier layer 501 to prevent electrons in the channel depletion layer from flowing from the bottom of the isolation layer to the adjacent memory cell region I', and it will also cause a waste of resources; if the distance l between the top surface of the barrier layer 501 and the top surface of the bit line 512 is too small, the barrier layer 501 may not be effective in preventing electrons in the channel depletion layer from flowing from the bottom of the isolation layer to the adjacent memory cell region I'. Therefore, in this embodiment, the distance l between the top surface of the barrier layer 501 and the top surface of the bit line 512 is 190 nanometers to 210 nanometers.

[0106] refer to Figure 10 An isolation layer 503 is formed on the substrate 500 exposed by the bit line 512, and the bottom of the isolation layer 503 is in contact with the top of the barrier layer 501.

[0107] The isolation layer 503 is used to isolate devices in adjacent memory cell regions I'. Specifically, the isolation layer 503 is a shallow trench isolation structure.

[0108] The insulating layer 503 can be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. As an example, the insulating layer 503 is made of silicon oxide.

[0109] It should be noted that the bottom of the isolation layer 503 is in contact with the top of the barrier layer 501, which helps to further enhance the ability of the barrier layer 501 to prevent electrons in the channel depletion layer 504 from flowing from the bottom of the isolation layer 503 to the adjacent memory cell region I'.

[0110] In this embodiment, after the barrier layer 501 is formed in the substrate 500 at least between adjacent memory cell regions I', an isolation layer 503 is formed on the substrate 500 exposed by the bit line 512, which is beneficial to ensure that the second doped ions forming the barrier layer 501 are located at the same depth.

[0111] In other embodiments, an isolation layer may be formed first, followed by the formation of the barrier layer in the substrate at least between adjacent memory cell regions.

[0112] refer to Figure 11 After the isolation layer 503 is formed, a stacked gate structure 502 is formed on the bit line 512 of the memory cell region I'. The stacked gate structure 502 includes a tunneling oxide layer 506 and a floating gate layer 507 located on the tunneling oxide layer 506.

[0113] The stacked gate structure 502 is used as a cell structure for storing data in a memory.

[0114] In this embodiment, the tunneling oxide layer 506 serves as an insulating layer between the floating gate layer 507 and the substrate 500, allowing electrons to enter the floating gate layer 507 via the tunneling effect during NAND flash memory operation. In this embodiment, the tunneling oxide layer 506 is made of silicon oxide. The floating gate layer 507 stores electrons during the formation of the NAND flash memory, enabling the NAND flash memory to function as a data storage device. In this embodiment, the floating gate layer 507 is made of polysilicon.

[0115] In this embodiment, the step of forming a stacked gate structure 502 on the bit line 512 of the memory cell region I' further includes: forming an inter-gate dielectric layer 508 on the top and sidewalls of the floating gate layer 507; and forming a control gate layer 509 on the top and sidewalls of the inter-gate dielectric layer 508.

[0116] It should be noted that the inter-gate dielectric layer 508 serves as an insulating layer between the floating gate layer 507 and the control gate layer 509. In this embodiment, the material of the inter-gate dielectric layer 107 includes silicon oxide or silicon nitride. The control gate layer 509 serves as part of the stacked gate structure 502 of the NAND memory. In this embodiment, the material of the control gate layer 509 is polysilicon.

[0117] It should be noted that the semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a description of the semiconductor structure of this embodiment, please refer to the relevant content in the foregoing formation method.

[0118] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having bit lines formed thereon, the bit lines having first doped ions, the substrate including memory cell regions disposed at adjacent intervals, the bit lines being located in the memory cell regions; A barrier layer, located at least in the substrate between adjacent memory cell regions, the barrier layer having a second doped ion of the same type as the first doped ion, and the concentration of the second doped ion being greater than the concentration of the first doped ion; An isolation layer is located on the substrate exposed by the bit line, and the bottom of the isolation layer is in contact with the top of the barrier layer; A stacked gate structure is located on the bit line of the memory cell region, the stacked gate structure including a tunneling oxide layer and a floating gate layer located on the tunneling oxide layer.

2. The semiconductor structure as described in claim 1, characterized in that, The barrier layer extends along the arrangement direction of the memory cell region, and the barrier layer is also located in the substrate at the bottom of the bit line.

3. The semiconductor structure as described in claim 1, characterized in that, When the first doped ion is an N-type ion, the concentration of the first doped ion is less than 4.0E13 atoms per cubic centimeter; Alternatively, if the first doped ion is a P-type ion, the concentration of the first doped ion is less than 3.4E13 atoms per cubic centimeter.

4. The semiconductor structure as described in claim 3, characterized in that, When the first doped ion is an N-type ion, the concentration of the first doped ion is from 2.6E13 atoms per cubic centimeter to 3.8E13 atoms per cubic centimeter. Alternatively, if the first doped ion is a P-type ion, the concentration of the first doped ion is between 2.4E13 atoms per cubic centimeter and 3.4E13 atoms per cubic centimeter.

5. The semiconductor structure as described in claim 1, characterized in that, When the second doped ion is an N-type ion, the concentration of the second doped ion is from 8.0E12 atoms per cubic centimeter to 1.0E13 atoms per cubic centimeter; Alternatively, if the second doped ion is a P-type ion, the concentration of the second doped ion is from 1.2E13 atoms per cubic centimeter to 1.4E13 atoms per cubic centimeter.

6. The semiconductor structure as described in claim 1, characterized in that, The thickness of the barrier layer is 20 nanometers to 50 nanometers.

7. The semiconductor structure as described in claim 1, characterized in that, The distance between the top surface of the barrier layer and the top surface of the bit line is 190 nanometers to 210 nanometers.

8. The semiconductor structure as described in claim 1, characterized in that, The stacked gate structure further includes: an inter-gate dielectric layer located on the top and sidewalls of the floating gate layer; and a control gate layer located on the top and sidewalls of the inter-gate dielectric layer.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which bit lines are formed, the bit lines having first doped ions, the substrate including memory cell regions disposed at adjacent intervals, the bit lines being located in the memory cell regions; A barrier layer is formed in the substrate between at least adjacent memory cell regions. The barrier layer has a second doped ion of the same type as the first doped ion, and the concentration of the second doped ion is greater than the concentration of the first doped ion. An isolation layer is formed on the substrate where the bit line is exposed, and the bottom of the isolation layer is in contact with the top of the barrier layer; After the isolation layer is formed, a stacked gate structure is formed on the bit line of the memory cell region. The stacked gate structure includes a tunneling oxide layer and a floating gate layer located on the tunneling oxide layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of providing the substrate includes: providing an initial substrate, a portion of the initial substrate thickness serving as a substrate, and the remaining portion of the initial substrate thickness located above the substrate serving as a bit line material layer; The initial substrate is subjected to first ion doping to form first doped ions in the initial substrate; After doping the first dopant ions in the initial substrate, the bit line material layer located between adjacent memory cell regions is removed, and the bit line material layer is patterned as a bit line located in the memory cell region.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, After the first dopant ions are doped in the initial substrate, and before the bit line material layer located between adjacent memory cell regions is removed, a barrier layer is formed in the substrate between adjacent memory cell regions.

12. The method for forming a semiconductor structure as described in claim 9 or 10, characterized in that, In the step of providing the substrate, the first doped ions in the bit line are obtained by a first ion implantation process.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, When the first doped ion is an N-type doped ion, the parameters of the first ion implantation process include: the implantation dose of the first doped ion is less than 4.2E13 atoms per square centimeter, and the implantation energy is 25,000 electron volts to 30,000 electron volts. Alternatively, if the first doped ion is a P-type doped ion, the parameters of the first ion implantation process include: the implantation dose of the first doped ion is less than 3.6E13 atoms per square centimeter, and the implantation energy is 25,000 electron volts to 30,000 electron volts.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, When the first dopant ion is an N-type dopant ion, the implantation dose of the first dopant ion is from 2.8E13 atoms per square centimeter to 4.0E13 atoms per square centimeter. Alternatively, if the first dopant ion is a P-type dopant ion, the implantation dose of the first dopant ion is 2.6E13 atoms per square centimeter to 3.6E13 atoms per square centimeter.

15. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the barrier layer in the substrate at least between adjacent memory cell regions, the barrier layer extends along the arrangement direction of the memory cell regions, and the barrier layer is also formed in the substrate at the bottom of the bit line.

16. The method for forming a semiconductor structure as described in claim 9, 11, or 15, characterized in that, The step of forming a barrier layer in a substrate at least between adjacent memory cell regions includes: performing a second ion doping on a region of the substrate in which the barrier layer is to be formed to form a barrier layer, wherein the region in which the barrier layer is to be formed includes at least the region between adjacent memory cell regions.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The step of performing a second ion doping on the region of the substrate to which a barrier layer is to be formed includes: forming a mask layer with a mask opening on the substrate, the mask opening being located above the region of the substrate to which a barrier layer is to be formed; Using the mask layer as a mask, the substrate at the bottom of the mask opening is subjected to a second ion doping to form a barrier layer; After forming the barrier layer, the process further includes: removing the mask layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The second ion doping process includes a second ion implantation process.

19. The method for forming a semiconductor structure as described in claim 17, characterized in that, When the second doped ion is an N-type ion, the parameters of the second ion implantation process include: an implantation dose of 1.0E13 atoms per square centimeter to 1.2E13 atoms per square centimeter, and an implantation energy of 100 keV to 120 keV. Alternatively, when the second doped ion is a P-type ion, the parameters of the second ion implantation process include: an implantation dose of 1.4E13 atoms per square centimeter to 1.6E13 atoms per square centimeter, and an implantation energy of 100 keV to 120 keV.

20. The method for forming a semiconductor structure as described in claim 9, characterized in that, After the barrier layer is formed at least in the substrate between adjacent memory cell regions, an isolation layer is formed on the substrate where the bit lines are exposed.

21. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming a stacked gate structure on the bit line of the memory cell region further includes: forming an inter-gate dielectric layer on the top and sidewalls of the floating gate layer; and forming a control gate layer on the top and sidewalls of the inter-gate dielectric layer.

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