Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor device comprises the following steps: forming a first stacked structure and a second initial stacked structure which are stacked and spaced on a substrate; forming a first source / drain electrode and a second source / drain electrode at two ends of a first channel structure along a first direction respectively; forming a first contact structure connected to the outside of each first source / drain electrode and a second contact structure connected to the outside of each second source / drain electrode; laterally etching a second initial sacrificial structure to obtain a second sacrificial structure; forming a third source / drain electrode and a fourth source / drain electrode at two ends of a second channel structure along the first direction respectively; forming a third contact structure connected to the outside of each third source / drain electrode and a fourth contact structure connected to the outside of each fourth source / drain electrode; forming a first metal structure on the first contact structure and a second metal structure on the second contact structure. The embodiments of the application can effectively improve the performance of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of semiconductor devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect the performance of semiconductor devices.

[0003] To minimize product costs, the goal is to fabricate as many semiconductor devices as possible on a substrate with limited area. Since the advent of Moore's Law, the industry has proposed various structural designs and process optimizations for semiconductor devices to meet current product demands. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device, its manufacturing method, and an electronic device, which can effectively improve the performance of the semiconductor device.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: A first stacked structure and a second initial stacked structure are formed on a substrate and spaced apart; the first stacked structure includes alternating layers of first channel structures and layers of first sacrificial structures, and the second initial stacked structure includes alternating layers of second channel structures and layers of second initial sacrificial structures. A first source and a second source and a third source are formed at the two ends of the first channel structure along a first direction, respectively; a first contact structure connected to the outside of each first source and a third contact structure connected to the outside of each second source and a third source are formed along the first direction; the first direction is parallel to the substrate. The second initial sacrificial structure is laterally etched to obtain the second sacrificial structure; the second insulating layer is backfilled on both sides of the second sacrificial structure along the first direction to obtain the second stacked structure. The third source and drain of the second transistor are formed at both ends of the second channel structure along the first direction, and the fourth source and drain are formed along the first direction, with a third contact structure connected to the outside of each third source and drain and a fourth contact structure connected to the outside of each fourth source and drain. A first metal structure that is insulated from the third contact structure is formed on the first contact structure, and a second metal structure that is insulated from the fourth contact structure is formed on the second contact structure.

[0006] In some embodiments, forming a first stacked structure and a second initial stacked structure that are stacked and spaced apart on a substrate includes: A first channel layer and a first sacrificial layer, a first isolation layer, a second channel layer and a second sacrificial layer, and a first mask structure are sequentially formed on a substrate in alternating layers. Based on the first mask structure, the first channel layer, the first sacrificial layer, the first isolation layer, the second channel layer, and the second sacrificial layer are etched to form the first channel structure, the first initial sacrificial structure, the first isolation structure, the second channel structure, and the second initial sacrificial structure, respectively. The first initial sacrificial structure is etched laterally to obtain the first sacrificial structure; the first insulating layer is backfilled on both sides of the first sacrificial structure along the first direction to obtain the first stacked structure. Replace the first isolation structure with the third insulation structure.

[0007] In some embodiments, the first isolation structure and the first sacrificial structure are made of the same material but have different mole fractions.

[0008] In some embodiments, before laterally etching the second initial sacrificial structure to obtain the second sacrificial structure, the method further includes: A second isolation layer is formed covering the first contact structure and the second contact structure; And, forming a third contact structure connected to the outside of each third source / drain electrode and a fourth contact structure connected to the outside of each fourth source / drain electrode, including: A third initial contact structure is formed that covers a portion of the second isolation layer and conformally covers the top, end, and bottom surfaces of each third source and drain electrode. At the same time, a fourth initial contact structure is formed that covers another portion of the second isolation layer and conformally covers the top, end, and bottom surfaces of each fourth source and drain electrode. The third initial contact structure is patterned into a third contact structure that is recessed within the first contact structure, and the fourth initial contact structure is patterned into a fourth contact structure that is recessed within the second contact structure.

[0009] In some embodiments, a first metal structure insulated from a third contact structure is formed on a first contact structure, and a second metal structure insulated from a fourth contact structure is formed on a second contact structure, including: On the second isolation layer, a fourth insulating layer is formed along the first direction on the outer side of the third contact structure and the fourth contact structure, respectively; Based on the self-aligned process, the second isolation layer exposed outside the fourth insulating layer of the third contact structure and the fourth contact structure along the first direction is etched away, exposing the edge regions of the first contact structure and the second contact structure. A first metal structure is formed on the edge region of the first contact structure, and a second metal structure is formed on the edge region of the second contact structure; along the second direction, the orthographic projection of the first metal structure onto the first contact structure does not exceed the range of the first contact structure, and the orthographic projection of the second metal structure onto the second contact structure does not exceed the range of the second contact structure; the second direction intersects the first direction and is parallel to the substrate.

[0010] In some embodiments, a third initial contact structure is formed covering a portion of the second isolation layer and conformally covering the top, end, and bottom surfaces of each third source / drain electrode; simultaneously, a fourth initial contact structure is formed covering another portion of the second isolation layer and conformally covering the top, end, and bottom surfaces of each fourth source / drain electrode, including: A second initial contact layer is formed, which covers the first mask structure, conformally covers the top, end, and bottom surfaces of each third source and drain electrode and the top, end, and bottom surfaces of each fourth source and drain electrode, and covers the second insulating layer. Based on the self-aligned process, the second initial contact layer covering the first mask structure is etched away, and the second initial contact layers on both sides are etched down to below the top surface of the first mask structure to obtain the third initial contact structure and the fourth initial contact structure.

[0011] In some embodiments, after forming a first metal structure insulated from a third contact structure on a first contact structure and forming a second metal structure insulated from a fourth contact structure on a second contact structure, the method further includes: The first sacrificial structure is replaced by the first gate insulating layer and the first gate sequentially wound around the first channel structure to obtain the first transistor, and the second sacrificial structure is replaced by the second gate insulating layer and the second gate sequentially wound around the second channel structure to obtain the second transistor; Remove the first mask structure to form a third isolation layer covering the second gate insulating layer and at least some of the fourth insulating layers. The third isolation layer has a first cutout exposing the first metal structure, a second cutout exposing the third contact structure, a third cutout exposing the fourth contact structure, and a fourth cutout exposing the second metal structure, arranged sequentially along the first direction. Simultaneously, a third metal structure is formed in the first hollow of the third isolation layer, a fourth metal structure is formed in the second hollow, a fifth metal structure is formed in the third hollow, and a sixth metal structure is formed in the fourth hollow.

[0012] In some embodiments, the third and fourth cutouts are connected, and the fifth and sixth metal structures are connected.

[0013] In some embodiments, laterally etching the first initial sacrificial structure to obtain the first sacrificial structure includes: Based on the designed channel length of the first transistor, the first initial sacrificial structure is etched along the first direction at a first designed distance to obtain the first sacrificial structure; And, the second initial sacrificial structure is laterally etched to obtain the second sacrificial structure, including: Based on the design channel length of the second transistor, the second initial sacrificial structure is etched along the first direction at a second design distance to obtain the second sacrificial structure.

[0014] Secondly, embodiments of this application also provide a semiconductor device, including: The first transistor and the second transistor are stacked on the substrate; The first transistor includes a multilayer first channel structure, a first source and drain, and a second source and drain; the first source and drain and the second source and drain are located at the two ends of the first channel structure along a first direction, respectively; The first contact structure is connected to the outside of each first source and drain electrode along the first direction; The second contact structure is connected to the outside of each second source / drain electrode along the first direction; The second transistor includes a multilayer second channel structure, a third source drain, and a fourth source drain; the third source drain and the fourth source drain are located at the two ends of the second channel structure along the first direction, respectively; The third contact structure is connected to the outside of each third source / drain electrode along the first direction; The fourth contact structure is connected to the outside of each fourth source / drain electrode along the first direction; A first metal structure is disposed on the first contact structure and is insulated from the third contact structure; The second metal structure is disposed on the second contact structure and is insulated from the fourth contact structure.

[0015] In some embodiments, along the second direction, the orthographic projection of the first metal structure onto the first contact structure does not exceed the range of the first contact structure, and the orthographic projection of the second metal structure onto the second contact structure does not exceed the range of the second contact structure.

[0016] In some embodiments, the exposed sides of the first metal structure and the first contact structure are flush with each other along the first direction; The exposed sides of the second metal structure and the second contact structure are flush with each other along the first direction.

[0017] In some embodiments, the semiconductor device further includes: The third isolation layer has a first hollow that exposes the first metal structure, a second hollow that exposes the third contact structure, a third hollow that exposes the fourth contact structure, and a fourth hollow that exposes the second metal structure, arranged sequentially along the first direction; The third, fourth, fifth, and sixth metal structures are located within the first, second, third, and fourth hollows, respectively.

[0018] In some embodiments, along the first direction, the third metal structure does not extend beyond the first contact structure, and the sixth metal structure does not extend beyond the second contact structure.

[0019] In some embodiments, a first metal connection layer is provided between the first contact structure and the first source / drain, and / or between the second contact structure and the second source / drain; A second metal connection layer is provided between the third contact structure and the third source / drain electrode, and / or between the fourth contact structure and the fourth source / drain electrode.

[0020] Thirdly, embodiments of this application provide an electronic device, including: a semiconductor device manufactured by any of the manufacturing methods provided in the first aspect above, or any of the semiconductor devices provided in the second aspect above.

[0021] The beneficial technical effects of the technical solutions provided in this application include: This application embodiment forms a first metal structure on a first contact structure to form a signal line leading out the first source and drain of a first transistor, and a second metal structure on a second contact structure to form a signal line leading out the second source and drain of a second transistor, such that the first metal structure, third contact structure, fourth contact structure, and second metal structure are arranged sequentially along a first direction. This application divides the high aspect ratio metal signal lines in related technologies into stacked first metal structures and first contact structures, as well as stacked second metal structures and second contact structures. The aspect ratios of the first metal structures and first contact structures, as well as the second metal structures and second contact structures, manufactured in stages are all lower, effectively solving the problem of high aspect ratios in related technologies, reducing manufacturing difficulty, and thus improving manufacturing efficiency and yield.

[0022] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0023] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 2 This is a top view schematic diagram of the film structure after forming a first mask layer on a substrate in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 3 for Figure 2 Schematic diagram of the cross section at point AA'; Figure 4A top view schematic diagram of the film structure after forming the first mask structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 5 for Figure 4 Schematic diagram of the cross section at point AA'; Figure 6 This is a schematic diagram of the film structure after the formation of the first protective layer in a semiconductor device manufacturing method provided in this application embodiment; Figure 7 This is a schematic diagram of the film structure after forming the first sacrificial structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 8 This is a schematic diagram of the film structure after forming the first stacked structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 9 This is a schematic diagram of the film structure after forming the third insulating structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 10 A schematic diagram of the film structure after forming the first source / drain and the second source / drain in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 11 This is a schematic diagram of the film structure after forming the first metal interconnect layer in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 12 This is a schematic diagram of the film structure after forming a first initial contact layer in a semiconductor device manufacturing method provided in this application embodiment; Figure 13 A schematic diagram of the film structure after forming the first contact structure and the second contact structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 14 This is a schematic diagram of the film structure after forming the second isolation layer in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 15 This is a schematic diagram of the film structure after forming the second stacked structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 16 A schematic diagram of the film structure after forming the third and fourth source / drain electrodes in a semiconductor device manufacturing method provided in this application embodiment; Figure 17 This is a schematic diagram of the film structure after forming the second metal interconnect layer in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 18 This is a schematic diagram of the film structure after forming the second initial contact layer in a semiconductor device manufacturing method provided in this application embodiment; Figure 19 This is a schematic diagram of the film structure after forming the third initial contact structure and the fourth initial contact structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 20 This is a schematic diagram of the film structure after forming the third mask structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 21 A schematic diagram of the film structure after forming the third contact structure and the fourth contact structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 22 This is a schematic diagram of the film structure after forming the fourth insulating layer in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 23 This is a schematic diagram of the film structure after removing the edge region of the second isolation layer in a semiconductor device manufacturing method provided in this application embodiment; Figure 24 A schematic diagram of the film structure after forming the first metal structure and the second metal structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 25 This is a schematic diagram of the film structure after forming the fourth mask structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 26 This is a schematic diagram of the film structure after forming an etching window in a semiconductor device manufacturing method provided in this application embodiment; Figure 27 A schematic diagram of the film structure after removing the first sacrificial structure and the second sacrificial structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 28 A schematic diagram of the film structure after forming a first gate insulating layer and a first gate electrode in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 29 This is a schematic diagram of the film structure during the formation of the third isolation layer in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 30 This is a schematic diagram of the film structure after forming the third isolation layer in a semiconductor device manufacturing method provided in this application embodiment; Figure 31 This is a schematic diagram of the film structure after forming a third metal structure in a semiconductor device manufacturing method provided in this application embodiment; Figure 32 for Figure 31 Schematic diagram of the cross section at point AA'; Figure 33 for Figure 31 A schematic diagram of the cross-section at point BB'.

[0024] Figure label: 100 - Substrate; 110 - Frame; 111 - Etching window; 120 - First mask layer; 130 - Fourth isolation layer; 140 - First protective layer; 150 - Hard mask layer; 200 - Buffer layer; 201 - First channel layer; 202 - First sacrificial layer; 203 - First isolation layer; 204 - Second channel layer; 205 - Second sacrificial layer; 206 - First mask structure; 207 - Third mask structure; 208 - Fourth mask structure; 209 - Fifth mask structure; 300 - First initial stacked structure; 310 - First channel structure; 320 - First initial sacrificial structure; 330 - First stacked structure; 331 - First sacrificial structure; 332 - First insulating layer; 340 - First transistor; 341 - First source / drain; 342 - Second source / drain; 343 - First gate insulating layer; 344 - First gate; 350 - First initial contact layer; 351 - First contact structure; 352 - Second contact structure; 353 - First metal connection layer; 410 - First insulating structure; 411 - Third insulating structure; 420 - Second insulating layer; 500 - Second initial stacked structure; 510 - Second channel structure; 520 - Second initial sacrificial structure; 530 - Second stacked structure; 531 - Second sacrificial structure; 532 - Second insulating layer; 540 - Second transistor; 541 - Third source / drain; 542 - Fourth source / drain; 543 - Second gate insulating layer; 544 - Second gate; 550 - Second initial contact layer; 551 - Third contact structure; 5510 - Third initial contact structure; 552 - Fourth contact structure; 5520 - Fourth initial contact structure; 553 - Second metal connection layer; 610 - First metal structure; 620 - Second metal structure; 630 - Fourth insulating layer; 700 - Third initial isolation layer; 710 - Third isolation layer; 711 - First cutout; 712 - Second cutout; 713 - Third cutout; 714 - Fourth cutout; 701 - Third metal structure; 702 - Fourth metal structure; 703 - Fifth metal structure; 704 - Sixth metal structure. Detailed Implementation

[0025] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0026] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0028] The research and development ideas of this application include: In recent years, integrated circuits have been continuously miniaturized and developed at the nanoscale. The development of semiconductor devices with architectures such as complementary field-effect transistors (CFETs) has enabled the limits of Moore's Law to be continuously broken and sustained.

[0029] As is widely known, CFET is considered by the industry to be a very promising transistor structure for transistors to reach the deep nanometer or even angstrom scale, and has been extensively studied by industry and research in recent years. However, the vertical stacking architecture of CFET faces practical process challenges such as high aspect ratio, high precision requirements, or the use of a large number of masks, which is extremely detrimental to the research and development of CFET.

[0030] For example, semiconductor devices in related technologies include double-layer transistors stacked one on top of the other. The source and drain of the lower transistor need to be led out to the top of the semiconductor device through a metal layer. Since the source and drain of the lower transistor are close to the bottom of the semiconductor device, a metal contact structure with a depth almost equal to the overall height of the double-layer transistor needs to be manufactured in the window area. This results in a high aspect ratio challenge in manufacturing the metal contact structure, making it difficult to manufacture, inefficient, and with a low yield.

[0031] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.

[0032] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0033] This application provides a method for manufacturing a semiconductor device, and the flowchart of the method is shown below. Figure 1 As shown, the method includes steps S101-S105: S101: A first stacked structure 330 and a second initial stacked structure 500 are formed on the substrate 100, with the stacked structures spaced apart. The first stacked structure 330 includes alternating layers of first channel structures 310 and multiple layers of first sacrificial structures 331, and the second initial stacked structure 500 includes alternating layers of second channel structures 510 and multiple layers of second initial sacrificial structures 520. Optionally, a schematic diagram of the film structure obtained after step S101 is shown below. Figure 8 As shown.

[0034] S102: A first source / drain electrode 341 and a second source / drain electrode 342 of a first transistor 340 are formed at both ends of the first channel structure 310 along a first direction; a first contact structure 351 connected to the outside of each first source / drain electrode 341 and a second contact structure 352 connected to the outside of each second source / drain electrode 342 are formed along the first direction; the first direction is parallel to the substrate 100. Optionally, a schematic diagram of the film structure obtained after step S102 is shown below. Figure 13 As shown.

[0035] S103: Laterally etch the second initial sacrificial structure 520 to obtain the second sacrificial structure 531; backfill the second insulating layer 532 on both sides of the second sacrificial structure 531 along the first direction to obtain the second stacked structure 530. Optionally, a schematic diagram of the film structure obtained after step S103 is shown below. Figure 15 As shown.

[0036] S104: Third source / drain electrodes 541 and fourth source / drain electrodes 542 of the second transistor 540 are formed at both ends of the second channel structure 510 along the first direction, respectively; along the first direction, a third contact structure 551 connected to the outside of each third source / drain electrode 541 and a fourth contact structure 552 connected to the outside of each fourth source / drain electrode 542 are formed. Optionally, a schematic diagram of the film structure obtained after step S104 is shown below. Figure 21 As shown.

[0037] S105: A first metal structure 610, which is insulated from the third contact structure 551, is formed on the first contact structure 351, and a second metal structure 620, which is insulated from the fourth contact structure 552, is formed on the second contact structure 352. Optionally, a schematic diagram of the film structure obtained after step S101 is shown below. Figure 24 As shown.

[0038] In this embodiment, a first metal structure 610 is formed on the first contact structure 351 to form a signal line leading out the first source-drain 341 of the first transistor 340, and a second metal structure 620 is formed on the second contact structure 352 to form a signal line leading out the second source-drain 342 of the first transistor 340. The first metal structure 610, the third contact structure 551, the fourth contact structure 552, and the second metal structure 620 are arranged sequentially along a first direction. This application divides the high aspect ratio metal signal lines in related technologies into stacked first metal structures 610 and 351, and stacked second metal structures 620 and 352. The first metal structures 610 and 351, and the second metal structures 620 and 352, manufactured in stages, all have lower aspect ratios, effectively solving the problem of high aspect ratios in related technologies, reducing manufacturing difficulty, and thus improving manufacturing efficiency and yield.

[0039] The specific steps of this application will be described in detail below with reference to the accompanying drawings.

[0040] This application provides a method for manufacturing a semiconductor device, which includes the following steps: Please refer to Figures 2-3 On the substrate 100, a first channel layer 201 and a first sacrificial layer 202, a first isolation layer 203, a second channel layer 204 and a second sacrificial layer 205, and a first mask layer 120 are sequentially formed in alternating layers.

[0041] like Figure 3 As shown, the direction perpendicular to the substrate is the third direction.

[0042] Optionally, such as Figure 2 As shown, based on actual process requirements, in Figure 2 The left and right sides may also be equipped with frames 110, which is not limited here.

[0043] Optionally, such as Figure 2 As shown, the region where each first mask layer 120 is located, i.e., the window region between the frames 110, forms a semiconductor structure within each window region through various manufacturing processes. The frames 110 serve to support the connected film layers. It should be noted that the number of window regions can be greater than or equal to one, and is not limited here.

[0044] Optionally, each window area is formed simultaneously through a self-alignment process. Specifically, in this embodiment, a master mask is used to define the window positions. This master mask can also be used in subsequent steps to manufacture other film layers, which can reduce the number of masks used. Please refer to the detailed description below for details.

[0045] Optionally, the above steps further include forming a buffer layer 200 on the substrate 100, and then sequentially forming alternating multilayer first channel layer 201 and first sacrificial layer 202, first isolation layer 203, alternating multilayer second channel layer 204 and second sacrificial layer 205, and first mask layer 120 on the protective layer.

[0046] It is understandable that, such as Figure 3 As shown, in the above steps, firstly, multiple layers of first channel layers 201 and multiple layers of first sacrificial layers 202 are alternately stacked on the buffer layer 200, the multiple layers including at least two layers; a first isolation layer 203 is formed on the first sacrificial layer 202; multiple layers of second channel layers 204 and multiple layers of second sacrificial layers 205 are alternately stacked on the first isolation layer 203, the multiple layers including at least two layers; and a first mask layer 120 is formed on the second sacrificial layer 205.

[0047] Optionally, the buffer layer 200 is made of oxide, the first channel layer 201 and the second channel layer 204 are made of silicon, and the first sacrificial layer 202 and the second sacrificial layer 205 are made of germanium-silicon.

[0048] Next, the first mask layer 120 is patterned to form the first mask structure 206.

[0049] Please refer to Figures 4-5 Based on the first mask structure 206, the first channel layer 201, the first sacrificial layer 202, the first isolation layer 203, the second channel layer 204, and the second sacrificial layer 205 are etched to form a first channel structure 310 and a first initial sacrificial structure 320, a first isolation structure 410, a second channel structure 510, and a second initial sacrificial structure 520, respectively. The first channel structure 310 and the first initial sacrificial structure 320 together form a first initial stacked structure 300.

[0050] Optionally, using the first mask structure 206, the first channel layer 201, the first sacrificial layer 202, the first isolation layer 203, the second channel layer 204, and the second sacrificial layer 205 are etched in one step to form a first channel structure 310 and a first initial sacrificial structure 320, a first isolation structure 410, a second channel structure 510, and a second initial sacrificial structure 520 with consistent planar dimensions.

[0051] Please refer to Figure 6Based on the self-aligned process, the fourth isolation layer 130 is filled in each window area, the upper part of the fourth isolation layer 130 is removed, and the remaining fourth isolation layer 130 is lower than the first isolation structure 410; a first protective layer 140 is formed on the outside of part of the first isolation structure 410, the alternately stacked second channel structure 510 and the second initial sacrificial structure 520, and the first mask structure 206.

[0052] Optionally, the material of the fourth isolation layer 130 includes oxides.

[0053] Please refer to Figure 7 Remove the fourth isolation layer 130; laterally etch the first initial sacrificial structure 320 to obtain the first sacrificial structure 331.

[0054] Optionally, the first initial sacrificial structure 320 is laterally etched to obtain the first sacrificial structure 331, including: based on the designed channel length of the first transistor 340, etching the first initial sacrificial structure 320 along the first direction at a first designed distance to obtain the first sacrificial structure 331.

[0055] In this embodiment, the designed channel length of the first transistor 340 is the overlap length along the first direction between the first channel structure 310 and the first gate 344 of the first transistor 340. Referring later, in this embodiment, the first sacrificial structure 331 will be replaced by the first gate insulating layer 343 and the first gate 344 in subsequent steps, while the length of the first channel structure 310 remains fixed. Therefore, based on the determined length of the first channel structure 310 in this embodiment, the etching distance of the first initial sacrificial structure 320 can be controlled by the pre-designed channel length of the first transistor 340, thereby controlling the length of the first gate 344, so that the first transistor 340 has the designed channel length.

[0056] Therefore, the embodiments of this application adjust the channel length of the first transistor 340 by controlling the etching length of the first initial sacrificial structure 320, thereby adjusting the device performance of the first transistor 340, which has wide applicability.

[0057] Similarly, the method for controlling the design channel length of the second transistor 540 is similar to that for the first transistor 340, and will be described in detail later.

[0058] Of course, in the above steps of this application, based on the first mask structure 206, the first channel layer 201, the first sacrificial layer 202, the first isolation layer 203, the second channel layer 204, and the second sacrificial layer 205 are etched to form the first channel structure 310 and the first initial sacrificial structure 320, the first isolation structure 410, the second channel structure 510, and the second initial sacrificial structure 520, respectively. Alternatively, different masks can be used to etch the first channel layer 201 and the first sacrificial layer 202, the second channel layer 204, and the second sacrificial layer 205 twice, respectively, so as to control the length of the first channel structure 310 and the second channel structure 510, and then control the etching length of the first initial sacrificial structure 320 and the second initial sacrificial structure 520, thereby adjusting the channel length of the first transistor 340 and the channel length of the second transistor 540 to adjust the performance of the semiconductor device.

[0059] Please refer to Figure 8 The first insulating layer 332 is backfilled on both sides of the first sacrificial structure 331 along the first direction to obtain the first stacked structure 330.

[0060] Please refer to Figure 9 The first isolation structure 410 is replaced with the third insulation structure 411.

[0061] Optionally, replacing the first insulating structure 410 with the third insulating structure 411 in the above steps includes: Remove the first isolation structure 410 and form a third insulation structure 411 in the area prior to the first isolation structure 410.

[0062] Optionally, the first isolation structure 410 and the first sacrificial structure 331 are made of the same material but have different mole fractions. That is, the first isolation layer 203 and the first sacrificial layer 202 are made of the same material but have different mole fractions, which facilitates the sequential epitaxial growth of the first isolation layer 203 and the first sacrificial layer 202, simplifying the formation steps of the stacked structure. Moreover, since the first isolation layer 203 and the first sacrificial layer 202 have different mole fractions, their etching solutions and etching rates are also different, which can improve the etching selectivity. This makes it easier to reduce the influence of the first sacrificial layer 202 during the subsequent etching of the first isolation layer 203, and also makes it easier to reduce the influence of the first isolation layer 203 during the subsequent etching of the first sacrificial layer 202.

[0063] Optionally, the material of the first isolation layer 203 includes silicon germanium with a germanium content of 2%, and the germanium content in the material of the first sacrificial layer 202 is different from that in the first isolation layer 203.

[0064] Please refer to Figure 10 The first source-drain electrode 341 and the second source-drain electrode 342 of the first transistor 340 are respectively formed at both ends of the first channel structure 310 along the first direction.

[0065] Optionally, one of the first source / drain 341 and the second source / drain 342 can be used as the source and the other as the drain.

[0066] Optionally, a first source / drain 341 and a second source / drain 342 may be formed at both ends of the first channel structure 310 along the first direction using an epitaxial growth process. The materials of the first source / drain 341 and the second source / drain 342 may include conductive materials such as silicon-germanium or silicon-phosphorus.

[0067] Please refer to Figure 11 Before forming the first contact structure 351 and the second contact structure 352, a first metal interconnect layer 353 is first formed to cover the exposed surfaces of the first source / drain electrode 341 and the second source / drain electrode 342. The first metal interconnect layer 353 can prevent metal from diffusing into the semiconductor material and provides good conductivity. The first metal interconnect layer 353 also has strong thermal stability and adhesion, which can improve the contact stability between the first source / drain electrode 341 and the second source / drain electrode 342 and the first contact structure 351 and the second contact structure 352, respectively.

[0068] Please refer to Figure 12 The first initial contact layer 350 is filled in the window area to cover the formed film layer.

[0069] Optionally, filling the window area with the first initial contact layer 350 can be achieved through a self-alignment process, forming the first initial contact layer 350 only within the window area, which can reduce the number of masks used.

[0070] Please refer to Figure 13 Along the first direction, the first initial contact layer is etched until the first protective layer 140 is fully exposed, forming a first contact structure 351 connected to the outside of each first source / drain electrode 341 and a second contact structure 352 connected to the outside of each second source / drain electrode 342.

[0071] Please refer to Figure 14 Remove the first protective layer 140; form a second isolation layer 420 covering the first contact structure 351 and the second contact structure 352.

[0072] Alternatively, this step can also be achieved through a self-alignment process, controlling the formation of the second isolation layer 420 within the window position.

[0073] Please refer to Figure 15 The second initial sacrificial structure 520 is etched laterally to obtain the second sacrificial structure 531; the second insulating layer 532 is backfilled on both sides of the second sacrificial structure 531 along the first direction to obtain the second stacked structure 530.

[0074] Optionally, the second initial sacrificial structure 520 is laterally etched to obtain the second sacrificial structure 531, including: based on the designed channel length of the second transistor 540, etching the second initial sacrificial structure 520 along the first direction at a second designed distance to obtain the second sacrificial structure 531.

[0075] In this embodiment, the designed channel length of the second transistor 540 is the overlap length along the first direction between the second channel structure 510 and the second gate 544 of the second transistor 540. In this embodiment, the second sacrificial structure 531 will be replaced by the second gate insulating layer 543 and the second gate 544 in subsequent steps, while the length of the second channel structure 510 remains fixed. Therefore, based on the determined length of the second channel structure 510 in this embodiment, the etching distance of the second initial sacrificial structure 520 can be controlled by the pre-designed channel length of the second transistor 540, thereby controlling the length of the second gate 544, so that the second transistor 540 has the designed channel length.

[0076] Therefore, the embodiments of this application adjust the channel length of the second transistor 540 by controlling the etching length of the second initial sacrificial structure 520, thereby adjusting the device performance of the second transistor 540, which has wide applicability.

[0077] Please refer to Figure 16 The third source-drain 541 and the fourth source-drain 542 of the second transistor 540 are formed at both ends of the second channel structure 510 along the first direction, respectively. Optionally, one of the third source / drain 541 and the fourth source / drain 542 can be used as a source and the other as a drain.

[0078] Optionally, a third source / drain 541 and a fourth source / drain 542 may be formed at both ends of the second channel structure 510 along the first direction using an epitaxial growth process. The materials of the third source / drain 541 and the fourth source / drain 542 may include conductive materials such as silicon-germanium or silicon-phosphorus.

[0079] Please refer to Figure 17 Before forming the third contact structure 551 and the fourth contact structure 552, a second metal interconnect layer 553 is first formed to cover the exposed surfaces of the third source / drain electrode 541 and the fourth source / drain electrode 542. The second metal interconnect layer 553 can prevent metal from diffusing into the semiconductor material and provides good conductivity. The second metal interconnect layer 553 also has strong thermal stability and adhesion, which can improve the contact stability between the third source / drain electrode 541 and the fourth source / drain electrode 542 and the third contact structure 551 and the fourth contact structure 552, respectively.

[0080] Please refer to Figure 18A second initial contact layer 550 is formed, which covers the first mask structure 206, conformally covers the top, end, and bottom surfaces of each third source / drain electrode 541 and the top, end, and bottom surfaces of each fourth source / drain electrode 542, and covers the second insulating layer 532.

[0081] Please refer to Figure 19 Based on the self-aligned process, the second initial contact layer 550 covering the first mask structure 206 is etched away, and the second initial contact layers 550 on both sides of the second stacked structure 530 are etched down to below the top surface of the first mask structure 206, to obtain the third initial contact structure 5510 and the fourth initial contact structure 5520 respectively.

[0082] Please refer to Figures 20-21 A hard mask layer 150 is deposited covering the third initial contact structure, the first mask structure 206, and the fourth initial contact structure, and then planarized. The planarized hard mask layer 150 is higher than the first mask structure 206. A third mask structure 207 is then disposed on the hard mask layer 150. Based on the third mask structure 207, the hard mask layer 150 is patterned to expose the edge regions of the third initial contact structure 5510 and the fourth initial contact structure 5520, which are then etched away to form the third contact structure 551 and the fourth contact structure 552, exposing the edge region of the second isolation layer 420.

[0083] Please refer to Figure 22 On the second insulating layer, a fourth insulating layer 630 is formed on the outer side of the third contact structure 551 and the fourth contact structure 552 along the first direction.

[0084] Please refer to Figure 23 The edge regions of the second isolation layer 420 exposed outside the fourth insulating layer 630 of the third contact structure 551 and the fourth contact structure 552 along the first direction are etched away, exposing the edge regions of the first contact structure 351 and the second contact structure 352.

[0085] Please refer to Figure 24 A first metal structure 610 is formed on the edge region of the first contact structure 351, and a second metal structure 620 is formed on the edge region of the second contact structure 352. Along the second direction, the orthographic projection of the first metal structure 610 on the first contact structure 351 does not exceed the range of the first contact structure 351, and the orthographic projection of the second metal structure 620 on the second contact structure 352 does not exceed the range of the second contact structure 352.

[0086] Optionally, along the second direction, the orthographic projection of the first metal structure 610 onto the first contact structure 351 coincides with the range of the first contact structure 351, and the orthographic projection of the second metal structure 620 onto the second contact structure 352 coincides with the range of the second contact structure 352.

[0087] It should be noted that in related technologies, because the source and drain of the lower-level transistors require additional, smaller contact holes to form a metal contact structure within the window area, the precision requirements are higher and the manufacturing process is more difficult. Furthermore, this increases the number of photomasks used, thus increasing manufacturing costs.

[0088] Optionally, in this embodiment, the first metal structure 610 and the second metal structure 620 can be formed based on a self-aligned process, such that the outer side of the first metal structure 610 is flush with the first contact structure 351, and the outer side of the second metal structure 620 is flush with the second contact structure 352. This is equivalent to forming the first metal structure 610 and the second metal structure 620 within the window area formed at the beginning, eliminating the need for additional contact holes of smaller size, enlarging the processing window, reducing precision requirements, and thus reducing manufacturing difficulty. Moreover, this embodiment can also save on the number and frequency of mask usage, reducing manufacturing costs.

[0089] Please refer to Figure 25 The fourth mask structure 208 is deposited and covers the first metal structure 610, the third contact structure 551, the first mask structure 206, the fourth contact structure 552, and the second metal structure 620, protecting the underlying film structure and defining the etching window 111.

[0090] Alternatively, please refer to Figure 26 An etching window 111 is formed on the frame 110 for injecting etching solution or etching gas to remove the first sacrificial structure 331 and the second sacrificial structure 531. The resulting film structure is shown in the schematic diagram below. Figure 27 As shown.

[0091] Please refer to Figure 28 The first sacrificial structure 331 is replaced with the first gate insulating layer 343 and the first gate 344 sequentially wound around the first channel structure 310 to obtain the first transistor 340, and the second sacrificial structure 531 is replaced with the second gate insulating layer 543 and the second gate 544 sequentially wound around the second channel structure 510 to obtain the second transistor 540.

[0092] Optionally, the step includes: sequentially depositing a first gate insulating layer 343 and a first gate 344 on the film surface exposed to the etching window 111, such that the first gate 344 fills the area where the first sacrificial structure 331 and the second sacrificial structure 531 were originally located; filling the etching window 111 located below the second transistor 540 in the vertical direction with insulating material; removing the first gate insulating layer 343 and the first gate 344 in the area where the second sacrificial structure 531 was originally located, and sequentially depositing a second gate insulating layer 543 and a second gate 544 in the area where the second sacrificial structure 531 was originally located.

[0093] Optionally, in this step, the residual insulating material, gate insulating material and gate material in the etched window 111 can also be removed based on the fourth mask structure 208 to expose the first gate 344 and the second gate 544.

[0094] Optionally, in this step, a metal material can also be deposited based on the fourth mask structure 208 to form a common gate connecting the first gate 344 and the second gate 544.

[0095] It should be noted that before this step, i.e. Figure 28 Before the corresponding membrane structure, the first mask structure 206 always exists above the second channel structure 510, protecting the membrane structure below. In this embodiment, keeping the first mask structure 206 used to form the first initial stacked structure 300 and the second initial stacked structure 500 intact and using it as a protective structure in the future can improve the utilization rate of the first mask structure 206 and reduce manufacturing costs.

[0096] Please refer to Figures 29-30 Remove the first mask structure 206, deposit a third initial isolation layer 700 in the window area, and set a fifth mask structure 209 above the third initial isolation layer 700.

[0097] Please refer to Figure 30 Based on the fifth mask structure 209, a third isolation layer 710 is formed covering the second gate insulating layer 543 and at least some of the fourth insulating layers 630. The third isolation layer 710 has a first cutout 711 exposing the first metal structure 610, a second cutout 712 exposing the third contact structure 551, a third cutout 713 exposing the fourth contact structure 552, and a fourth cutout 714 exposing the second metal structure 620, arranged sequentially along the first direction.

[0098] Please refer to Figures 31-33Meanwhile, a third metal structure 701 is formed in the first hollow 711 of the third isolation layer 710, a fourth metal structure 702 is formed in the second hollow 712, a fifth metal structure 703 is formed in the third hollow 713, and a sixth metal structure 704 is formed in the fourth hollow 714.

[0099] Optionally, a metal material can be formed using a full-surface film-forming process, allowing the metal material to fill all the openings in the third isolation layer 710. Then, the metal material is subjected to processes such as grinding to remove the residual metal material above the third isolation layer 710. The metal material retained in the first opening 711 is the third metal structure 701, the metal material retained in the second opening 712 is the fourth metal structure 702, the metal material retained in the third opening 713 is the fifth metal structure 703, and the metal material retained in the fourth opening 714 is the sixth metal structure 704.

[0100] In some embodiments, the third cutout 713 and the fourth cutout 714 are connected, and the fifth metal structure 703 and the sixth metal structure 704 are connected.

[0101] In this embodiment, the third cutout 713 and the fourth cutout 714 are actually different regions of the same cutout. When metal material is deposited simultaneously in the third cutout 713 and the fourth cutout 714, the formed fifth metal structure 703 and the sixth metal structure 704 are actually different parts of the metal material within the same cutout. Therefore, this embodiment forms the fifth metal structure 703 and the sixth metal structure 704 in one step, thereby electrically connecting the fourth contact structure 552 and the second metal structure 620, which in turn electrically connects the second source / drain 342 of the first transistor 340 and the fourth source / drain 542 of the second transistor 540, and further electrically connects the first transistor 340 and the second transistor 540.

[0102] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned by a patterning process to manufacture each corresponding film layer.

[0103] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.

[0104] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film of a certain material manufactured on a substrate 100 using a deposition or coating process. If the thin film does not require a patterning process or photolithography process during the entire manufacturing process, the thin film can also be called a layer. If the thin film requires a patterning process or photolithography process during the entire manufacturing process, it can be called a thin film before the patterning process and a layer after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern".

[0105] Based on the same inventive concept, embodiments of this application provide a semiconductor device, including: a first transistor 340, a second transistor 540, a first contact structure 351, a second contact structure 352, a third contact structure 551, a fourth contact structure 552, a first metal structure 610, and a second metal structure 620.

[0106] The first transistor 340 and the second transistor 540 are stacked on the substrate 100.

[0107] The first transistor 340 includes a multilayer first channel structure 310, a first source-drain 341, and a second source-drain 342; the first source-drain 341 and the second source-drain 342 are located at both ends of the first channel structure 310 along a first direction.

[0108] The first contact structure 351 is connected to the outside of each first source / drain electrode 341 along the first direction.

[0109] The second contact structure 352 is connected to the outside of each second source / drain electrode 342 along the first direction.

[0110] The second transistor 540 includes a multilayer second channel structure 510, a third source-drain 541, and a fourth source-drain 542; the third source-drain 541 and the fourth source-drain 542 are located at both ends of the second channel structure 510 along the first direction. The third contact structure 551 is connected along the first direction to the outside of each third source / drain electrode 541.

[0111] The fourth contact structure 552 is connected to the outside of each fourth source / drain electrode 542 along the first direction.

[0112] The first metal structure 610 is disposed on the first contact structure 351 and is insulated from the third contact structure 551.

[0113] The second metal structure 620 is disposed on the second contact structure 352 and is insulated from the fourth contact structure 552.

[0114] In this embodiment, a first metal structure 610 is formed on the first contact structure 351 to form a signal line leading out the first source-drain 341 of the first transistor 340, and a second metal structure 620 is formed on the second contact structure 352 to form a signal line leading out the second source-drain 342 of the second transistor 540. The first metal structure 610, the third contact structure 551, the fourth contact structure 552, and the second metal structure 620 are arranged sequentially along a first direction. This application divides the high aspect ratio metal signal lines in related technologies into stacked first metal structures 610 and 351, and stacked second metal structures 620 and 352. The first metal structures 610 and 351, and the second metal structures 620 and 352, manufactured in stages, all have lower aspect ratios, effectively solving the problem of high aspect ratios in related technologies, reducing manufacturing difficulty, and thus improving manufacturing efficiency and yield.

[0115] Optionally, the materials of the first channel structure 310 and the second channel structure 510 include metal oxide semiconductor materials or silicon-containing materials. Among them, the metal oxide semiconductor materials include IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), IWO (Indium Wolfram Oxide), InGaO (Indium Gallium Oxide), ZnO (Zinc Oxide), InO (Indium Oxide), InWO (Indium Tungsten Oxide), SnO (Tin Oxide), TiO (Titanium Oxide), InSnO (Indium Tin Oxide), ZnON (Nitrogen-Doped Zinc Oxide), Mg... ZnO (zinc magnesium oxide), InZnO (zinc indium oxide), InGaZnO (zinc indium gallium oxide), ZrInZnO (zinc zirconium oxide), HfInZnO (zinc hafnium oxide), SnInZnO (zinc tin oxide), AlZnO (zinc aluminum oxide), AlSnInZnO (zinc aluminum tin oxide), SiInZnO (zinc silicon oxide), ZnSnO (zinc tin oxide), AlZnSnO (zinc aluminum oxide), GaZnSnO (zinc gallium oxide), ZrZnSnO (zinc zirconium oxide), and InGaSiO (silicon indium gallium oxide), etc.

[0116] In some embodiments, along the second direction, the orthographic projection of the first metal structure 610 onto the first contact structure 351 does not exceed the range of the first contact structure 351, and the orthographic projection of the second metal structure 620 onto the second contact structure 352 does not exceed the range of the second contact structure 352.

[0117] In this embodiment, the orthographic projection of the first metal structure 610 onto the first contact structure 351 does not exceed the range of the first contact structure 351, and the orthographic projection of the second metal structure 620 onto the second contact structure 352 does not exceed the range of the second contact structure 352. Therefore, it does not need to occupy areas other than the first contact structure 351 and the second contact structure 352, which can reduce the planar size of the semiconductor device and is conducive to the miniaturization of the semiconductor device.

[0118] In some embodiments, the exposed sides of the first metal structure 610 and the first contact structure 351 are flush with each other along the first direction.

[0119] The second metal structure 620 and the second contact structure 352 are flush with the exposed sides along the first direction.

[0120] In this embodiment, the first metal structure 610 and the first contact structure 351, the second metal structure 620 and the second contact structure 352 can all be manufactured using a self-aligned process, without the need for additional mask plates, which can reduce the number of mask plates used and reduce manufacturing costs.

[0121] In some embodiments, the semiconductor device further includes: a third isolation layer 710, a third metal structure 701, a fourth metal structure 702, a fifth metal structure 703, and a sixth metal structure 704.

[0122] The third isolation layer 710 has a first cutout 711 exposing the first metal structure 610, a second cutout 712 exposing the third contact structure 551, a third cutout 713 exposing the fourth contact structure 552, and a fourth cutout 714 exposing the second metal structure 620, arranged sequentially along the first direction. The third metal structure 701, the fourth metal structure 702, the fifth metal structure 703, and the sixth metal structure 704 are respectively located within the first hollow 711, the second hollow 712, the third hollow 713, and the fourth hollow 714.

[0123] In this embodiment, the third metal structure 701, the fourth metal structure 702, the fifth metal structure 703 and the sixth metal structure 704 are arranged sequentially along the first direction, and the first source-drain 341 of the first transistor 340, the third source-drain 541 of the second transistor 540, the fourth source-drain 542 of the second transistor 540 and the second source-drain 342 of the first transistor 340 are led out sequentially.

[0124] In some embodiments, along the first direction, the third metal structure 701 does not extend beyond the first contact structure 351, and the sixth metal structure 704 does not extend beyond the second contact structure 352.

[0125] In this embodiment, the third metal structure 701 does not exceed the first contact structure 351, and the sixth metal structure 704 does not exceed the second contact structure 352. By controlling the planar dimensions of each metal structure within the window area, the overall size of the semiconductor device can be controlled, and the manufacturing difficulty can be reduced.

[0126] Optionally, the third metal structure 701 is flush with the first contact structure 351, and the sixth metal structure 704 is flush with the second contact structure 352. This can be manufactured through a self-aligned process, reducing the number and frequency of mask use and lowering manufacturing costs.

[0127] In some embodiments, a first metal interconnect layer 353 is provided between the first contact structure 351 and the first source / drain 341, and / or between the second contact structure 352 and the second source / drain 342; a second metal interconnect layer 553 is provided between the third contact structure 551 and the third source / drain 541, and / or between the fourth contact structure 552 and the fourth source / drain 542. In this embodiment, by adding a metal interconnect layer between the source / drain and the contact structure, not only can the contact stability between the source / drain and the contact structure be increased, but also the diffusion of metal into the semiconductor material can be prevented, and good conductivity can be provided, thereby improving device performance.

[0128] Based on the same inventive concept, this application provides an electronic device, including: a semiconductor device manufactured by any of the semiconductor device manufacturing methods provided in the foregoing embodiments, or any of the semiconductor devices provided in the foregoing embodiments.

[0129] In this embodiment, since the electronic device uses any of the semiconductor devices provided in the foregoing embodiments, the principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0130] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or power bank.

[0131] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the semiconductor devices provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.

[0132] Those skilled in the art will understand that the electronic devices provided in the embodiments of this application can be specifically designed and manufactured for a desired purpose, or may include known devices in general-purpose computers. These devices have any of the semiconductor devices provided in the various embodiments described above.

[0133] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0134] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0135] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0136] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A first stacked structure and a second initial stacked structure are formed on a substrate and spaced apart; the first stacked structure includes alternating layers of first channel structures and multiple layers of first sacrificial structures, and the second initial stacked structure includes alternating layers of second channel structures and multiple layers of second initial sacrificial structures. A first source / drain and a second source / drain of a first transistor are formed at both ends of the first channel structure along a first direction; a first contact structure connected to the outside of each first source / drain and a second contact structure connected to the outside of each second source / drain are formed along the first direction; the first direction is parallel to the substrate. The second initial sacrificial structure is laterally etched to obtain the second sacrificial structure; A second insulating layer is backfilled on both sides of the second sacrificial structure along the first direction to obtain a second stacked structure; The third source and drain of the second transistor are formed at both ends of the second channel structure along the first direction, respectively; Along the first direction, a third contact structure is formed connecting to the outside of each of the third source and drain electrodes, and a fourth contact structure is formed connecting to the outside of each of the fourth source and drain electrodes. A first metal structure that is insulated from the third contact structure is formed on the first contact structure, and a second metal structure that is insulated from the fourth contact structure is formed on the second contact structure.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Forming a first stacked structure and a second initial stacked structure on a substrate, which are stacked and spaced apart, includes: A first channel layer and a first sacrificial layer, a first isolation layer, a second channel layer and a second sacrificial layer, and a first mask structure are sequentially formed on a substrate in alternating layers. Based on the first mask structure, the first channel layer, the first sacrificial layer, the first isolation layer, the second channel layer, and the second sacrificial layer are etched to form the first channel structure and the first initial sacrificial structure, the first isolation structure, the second channel structure, and the second initial sacrificial structure, respectively. The first initial sacrificial structure is etched laterally to obtain the first sacrificial structure; a first insulating layer is backfilled on both sides of the first sacrificial structure along the first direction to obtain the first stacked structure. Replace the first isolation structure with the third insulation structure.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The first isolation structure and the first sacrificial structure are made of the same material, but have different mole fractions.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before obtaining the second sacrificial structure by laterally etching the second initial sacrificial structure, the process further includes: A second isolation layer is formed covering the first contact structure and the second contact structure; And, forming a third contact structure connected to the outside of each of the third source and drain electrodes and a fourth contact structure connected to the outside of each of the fourth source and drain electrodes, including: A third initial contact structure is formed that covers a portion of the second isolation layer and conformally covers the top, end, and bottom surfaces of each of the third source and drain electrodes; at the same time, a fourth initial contact structure is formed that covers another portion of the second isolation layer and conformally covers the top, end, and bottom surfaces of each of the fourth source and drain electrodes. The third initial contact structure is patterned into a third contact structure that is recessed within the first contact structure, and the fourth initial contact structure is patterned into a fourth contact structure that is recessed within the second contact structure.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, Forming a first metal structure that is insulated from the third contact structure on the first contact structure, and forming a second metal structure that is insulated from the fourth contact structure on the second contact structure, comprising: On the second isolation layer, a fourth insulating layer is formed on the outer side of the third contact structure and the fourth contact structure along the first direction; Based on the self-aligned process, the second isolation layer exposed outside the fourth insulating layer of the third contact structure and the fourth contact structure along the first direction is etched away, exposing the edge regions of the first contact structure and the second contact structure. The first metal structure is formed on the edge region of the first contact structure, and the second metal structure is formed on the edge region of the second contact structure; along the second direction, the orthographic projection of the first metal structure onto the first contact structure does not exceed the range of the first contact structure, and the orthographic projection of the second metal structure onto the second contact structure does not exceed the range of the second contact structure; the second direction intersects the first direction and is parallel to the substrate.

6. The method for manufacturing a semiconductor device according to claim 4, characterized in that, A third initial contact structure is formed, covering a portion of the second isolation layer and conformally covering the top, end, and bottom surfaces of each of the third source and drain electrodes. Simultaneously, a fourth initial contact structure is formed, covering another portion of the second isolation layer and conformally covering the top, end, and bottom surfaces of each of the fourth source and drain electrodes. This includes: A second initial contact layer is formed, which covers the first mask structure, conformally covers the top, end, and bottom surfaces of each of the third source and drain electrodes and the top, end, and bottom surfaces of each of the fourth source and drain electrodes, and covers the second insulating layer; Based on the self-aligned process, the second initial contact layer covering the first mask structure is etched away, and the second initial contact layers on both sides are etched down to below the top surface of the first mask structure to obtain the third initial contact structure and the fourth initial contact structure.

7. The method for manufacturing a semiconductor device according to claim 2, characterized in that, After forming a first metal structure insulated from the third contact structure on the first contact structure, and forming a second metal structure insulated from the fourth contact structure on the second contact structure, the method further includes: The first sacrificial structure is replaced with a first gate insulating layer and a first gate sequentially wound around the first channel structure to obtain a first transistor, and the second sacrificial structure is replaced with a second gate insulating layer and a second gate sequentially wound around the second channel structure to obtain a second transistor; The first mask structure is removed to form a third isolation layer covering the second gate insulating layer and at least some of the fourth insulating layers. The third isolation layer has a first cutout exposing the first metal structure, a second cutout exposing the third contact structure, a third cutout exposing the fourth contact structure, and a fourth cutout exposing the second metal structure, arranged sequentially along the first direction. Simultaneously, a third metal structure is formed in the first hollow of the third isolation layer, a fourth metal structure is formed in the second hollow, a fifth metal structure is formed in the third hollow, and a sixth metal structure is formed in the fourth hollow.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The third and fourth cutouts are connected, and the fifth and sixth metal structures are connected.

9. The method for manufacturing a semiconductor device according to claim 2, characterized in that, Laterally etching the first initial sacrificial structure to obtain the first sacrificial structure includes: Based on the designed channel length of the first transistor, the first initial sacrificial structure is etched along the first direction at a first designed distance to obtain the first sacrificial structure; And, laterally etching the second initial sacrificial structure to obtain the second sacrificial structure, including: Based on the designed channel length of the second transistor, the second initial sacrificial structure is etched along the first direction at a second designed distance to obtain the second sacrificial structure.

10. A semiconductor device, characterized in that, include: The first transistor and the second transistor are stacked on the substrate; The first transistor includes a multilayer first channel structure, a first source and drain, and a second source and drain; The first source and drain, and the second source and drain are respectively located at both ends of the first channel structure along the first direction; The first contact structure is connected to the outside of each of the first source and drain electrodes along the first direction; The second contact structure is connected to the outside of each of the second source and drain electrodes along the first direction; The second transistor includes a multilayer second channel structure, a third source drain, and a fourth source drain; the third source drain and the fourth source drain are respectively located at both ends of the second channel structure along a first direction; The third contact structure is connected to the outside of each of the third source and drain electrodes along the first direction; The fourth contact structure is connected to the outside of each of the fourth source and drain electrodes along the first direction; A first metal structure is disposed on the first contact structure and is insulated from the third contact structure; A second metal structure is disposed on the second contact structure and is insulated from the fourth contact structure.

11. The semiconductor device according to claim 10, characterized in that, Along the second direction, the orthographic projection of the first metal structure onto the first contact structure does not exceed the range of the first contact structure, and the orthographic projection of the second metal structure onto the second contact structure does not exceed the range of the second contact structure.

12. The semiconductor device according to claim 11, characterized in that, The exposed sides of the first metal structure and the first contact structure are flush with each other along the first direction; The exposed sides of the second metal structure and the second contact structure are flush with each other along the first direction.

13. The semiconductor device according to claim 10, characterized in that, Also includes: The third isolation layer has a first cutout that exposes the first metal structure, a second cutout that exposes the third contact structure, a third cutout that exposes the fourth contact structure, and a fourth cutout that exposes the second metal structure, arranged sequentially along the first direction; The third, fourth, fifth, and sixth metal structures are each located within the first, second, third, and fourth cutouts, respectively.

14. The semiconductor device according to claim 13, characterized in that, Along the first direction, the third metal structure does not extend beyond the first contact structure, and the sixth metal structure does not extend beyond the second contact structure.

15. The semiconductor device according to claim 10, characterized in that, A first metal connection layer is provided between the first contact structure and the first source / drain electrode, and / or between the second contact structure and the second source / drain electrode; A second metal connection layer is provided between the third contact structure and the third source / drain electrode, and / or between the fourth contact structure and the fourth source / drain electrode.

16. An electronic device, characterized in that, include: Semiconductor devices manufactured by any of the manufacturing methods described in claims 1-9 above, or semiconductor devices described in any of claims 10-15 above.

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