Storage device and method of manufacturing the same

Abstract

The present application provides a storage device and a manufacturing method thereof. The storage device includes a substrate, a first stack structure, a second stack structure, at least one transistor, and a metal wiring layer. The substrate includes an array region and a peripheral region. The first stack structure is located in the array region. The first stack structure includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer. The first conductive layer, the insulating layer, and the second conductive layer are stacked along a first direction. The second stack structure is located in the peripheral region. The at least one transistor is located in the second stack structure. The at least one transistor has a conductive film, a dielectric film, and a semiconductor film stacked along the first direction. The metal wiring layer is located above the first stack structure and the second stack structure. The metal wiring layer is electrically connected to the at least one transistor, the first conductive layer, and the second conductive layer.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods of manufacturing them, and more particularly to memory devices and methods of manufacturing them. Background Technology

[0002] Generally, a storage device comprises multiple storage cells located in an array region (forming a storage array) and peripheral circuitry located in a peripheral region. The peripheral circuitry is electrically connected to the storage array to operate the storage cells. The sequence of manufacturing steps in a storage device can impose limitations on its design. For example, process temperature may restrict the material selection for components in the storage device, leading to poor performance. Summary of the Invention

[0003] The present invention provides a storage device and a method for manufacturing the same, which allows for better integration of the peripheral area and the array area without limiting the design choices of the peripheral area and the array area due to process limitations, thereby improving the performance of the storage device.

[0004] According to some embodiments of the present invention, a storage device is provided. The storage device includes a substrate, a first stacked structure, a second stacked structure, at least one transistor, and a metal winding layer. The substrate includes an array region and a peripheral region. The first stacked structure is located in the array region. The first stacked structure includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer. The first conductive layer, the insulating layer, and the second conductive layer are stacked along a first direction. The second stacked structure is located in the peripheral region. At least one transistor is located in the second stacked structure. The at least one transistor has a conductive film, a dielectric film, and a semiconductor film stacked along the first direction. The metal winding layer is located above the first stacked structure and the second stacked structure. The metal winding layer is electrically connected to the at least one transistor, the first conductive layer, and the second conductive layer.

[0005] According to some embodiments of the present invention, a method for manufacturing a memory device is provided. The method includes: providing a substrate including an array region and a peripheral region; forming a layer stack in the array region, the layer stack including a semiconductor material layer, a dielectric layer, and an insulating layer between the semiconductor material layer and the dielectric layer; forming a channel pillar penetrating the layer stack; forming an extension adjacent to the layer stack, wherein the extension includes a plurality of semiconductor layers stacked and extending along a first direction and a second direction, the first direction being perpendicular to the second direction; and forming at least one transistor in the peripheral region, the at least one transistor including a stacked conductive film, a dielectric film, and a semiconductor film.

[0006] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1This is a schematic cross-sectional view of a storage device according to an embodiment of the present invention;

[0008] Figure 2A It is a drawing Figure 1 Circuit diagram of the storage device;

[0009] Figure 2B It is a drawing Figure 1 Threshold voltage distribution diagram of the storage device;

[0010] Figure 3 This is a schematic cross-sectional view of a storage device according to another embodiment of the present invention;

[0011] Figures 4 to 23 This is a structural cross-sectional schematic diagram illustrating multiple stages of a method for manufacturing a storage device according to some embodiments of the present invention; and

[0012] Figures 24 to 37 This is a structural cross-sectional schematic diagram illustrating multiple stages of a method for manufacturing a storage device according to some embodiments of the present invention.

[0013] Explanation of reference numerals in the attached figures:

[0014] 10,20: Storage devices

[0015] 72AU, 100U, 970U, 7221U, 7223U: Top surface

[0016] 100: Substrate

[0017] 101: Array Area

[0018] 102: Surrounding Area

[0019] 110, 120, 320: Stacked structure

[0020] 111,113,115,116,411,411A,413,413A,413B,415,415A,415B,1616: Insulation layer

[0021] 112, 114: Conductive layer

[0022] 117: Barrier Layer

[0023] 121,123,1621,1621A: Insulating film

[0024] 122: Derivative section

[0025] 130, 330: Transistors

[0026] 131: Source Extreme

[0027] 132: Drain

[0028] 133: Gate

[0029] 140: Metal winding layer

[0030] 141: Conductor

[0031] 142: Insulating materials

[0032] 150, 450, 550: Channel Columns

[0033] 150H, 171H, 172H, 178H: Altitude

[0034] 151: Insulating Post

[0035] 152,552: Channel layer

[0036] 153,553: Charge storage layer

[0037] 154,454: Seam Pad

[0038] 170: Shallow trench isolation

[0039] 171: Source contact structure

[0040] 172: Drain contact structure

[0041] 173: Gate contact structure

[0042] 174, 175: Conductive contact structure

[0043] 176: Channel Contact Structure

[0044] 177,1333,6771,6771A,6772,6772A: Dielectric film

[0045] 178: Conductive column

[0046] 181, 182: Spacer elements

[0047] 181S, 182S: Sidewall

[0048] 183, 1483, 1483A, 1483B: Overlay layer

[0049] 191, 192, 1891: Interlayer insulation

[0050] 324: Conductive part

[0051] 410, 410A, 410B, 410C: Layer stacking

[0052] 412, 412A: Semiconductor material layer

[0053] 414, 414A, 414B, 414C: Dielectric layers

[0054] 970, 970A: Isolation components

[0055] 1201,1501,1801,2001,2002,2003,2004,2601,3401,3402,3403,3404,4501,8501: Holes

[0056] 1221,1222,7221,7221A,7222,7222A: Semiconductor layer

[0057] 1331, 2431, 2431A, 3331: Conductive film

[0058] 1332: Semiconductor film

[0059] 1332A, 1332B: Semiconductor material films

[0060] 1711, 1721, 1731, 1781: Isolation elements

[0061] 1901, 1902: Space

[0062] 7223, 7223A: Filler element

[0063] 7224, 7224A, 7224B: Gate oxide layer

[0064] BL1, BL2: Bit lines

[0065] CSL: Common Source Line

[0066] D1: First Direction

[0067] D2: Second Direction

[0068] D3: Third direction

[0069] MG1, MG2: Word Lines

[0070] SG1, SG2: Select gate lines

[0071] TD1~TD4: Data storage transistors

[0072] TS1~TS4: Select transistors Detailed Implementation

[0073] The drawings are simplified to clearly illustrate the embodiments, and the dimensions in the drawings are not drawn to scale with the actual product. In the following manufacturing methods, one or more additional operations may be present between the operations, and the order of the operations may vary. Therefore, the specification and drawings are used only to describe embodiments and are not intended to limit the scope of protection of the invention. The following description uses the same / similar symbols to denote the same / similar elements.

[0074] The ordinal numbers used to modify elements in the specification and claims, such as "first," "second," etc., do not imply or represent a specific position, arrangement, or manufacturing order in the structure; these ordinal numbers are merely used to clearly distinguish multiple elements with the same name. Spatial terms used in the specification and claims, such as "above," "over," "above," "higher than," "top," "below," "below," "below," "lower than," "bottom," etc., describe the relative spatial or positional relationship between one element and another in the drawings, and these spatial or positional relationships can be direct or indirect (with other elements disposed between the two elements), unless otherwise specified. Spatial terms may cover structures shown in other orientations, not limited to the orientation shown in the drawings. Structures can be flipped or rotated at various angles, and the spatial terms used herein can be interpreted accordingly. The singular forms "a," "an," "the," and "the" used in the specification and claims are also intended to include the plural forms, unless the context clearly indicates otherwise. The use of "and / or" in the specification and claims includes any and all combinations of one or more of the listed items.

[0075] Furthermore, the term "electrical connection" used in the specification and appended claims can mean that multiple elements form an ohmic contact, that current flows between multiple elements, or that multiple elements have an operational relationship. An operational relationship can be, for example, one element driving another element, but the current may not flow directly between the two elements. The term "adjacent" used in the specification and appended claims means "adjacent and in contact." The term "deposition" used in the specification and appended claims includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and epitaxial growth. Depending on the type of material to be formed, those skilled in the art can select a suitable technique for forming the material. The terms "etching" and "etching back" used in the specification and appended claims include, but are not limited to, dry etching and wet etching. The term "polishing" used in the specification and appended claims includes, but is not limited to, chemical-mechanical planarization (CMP) and ion milling. The terms "etching," "etching back," and "polishing" used in the specification and appended claims are interchangeable, and those skilled in the art can select appropriate removal techniques based on the structure and materials.

[0076] Embodiments of the present invention can be applied to various types of three-dimensional storage devices. For example, multiple embodiments of the present invention can be applied to, but are not limited to, NAND flash memory devices, NOR flash memory devices, or any type of storage device. Embodiments of the present invention can be applied to storage devices employing a CMOS near array (CNA) architecture, that is, the array region (where the storage array is disposed in the array region) and the peripheral region (where the peripheral circuitry is disposed in the peripheral region) of the storage device are disposed side by side on the same wafer. The following describes various embodiments of the present invention using an NOR flash memory device as an example, but the present invention is not limited to a specific type of device.

[0077] Please refer to Figure 1 . Figure 1This is a cross-sectional schematic diagram illustrating a storage device 10 according to an embodiment of the present invention. The storage device 10 includes a substrate 100, at least one stacked structure 110, at least one stacked structure 120, at least one transistor 130, and at least one metal winding layer 140 located above the stacked structures 110 and 120. The substrate 100 includes an array region 101 and a peripheral region 102. The peripheral region 102 may be disposed near the array region 101. The peripheral region 102 may be adjacent to the array region 101. The array region 101 and the peripheral region 102 may be disposed along a second direction D2 and / or a third direction D3. The stacked structure 110 is located in the array region 101. The stacked structure 110 is disposed on the substrate 100 along a first direction D1. The stacked structure 110 may include a conductive layer 112, a conductive layer 114, and an insulating layer 113 disposed between the conductive layers 112 and 114. Conductive layer 112, insulating layer 113, and conductive layer 114 can be stacked along a first direction D1. A stacked structure 120 is located in the peripheral region 102. The stacked structure 120 is disposed on the substrate 100 along the first direction D1. The stacked structure 120 can be disposed on one side of the stacked structure 110 along a second direction D2 and / or a third direction D3. The stacked structure 120 can be adjacent to the stacked structure 110. A transistor 130 is located in the stacked structure 120. The transistor 130 has a conductive film 1331, a dielectric film 1333, and a semiconductor film 1332 stacked along the first direction D1. A metal winding layer 140 can electrically connect the transistor 130, conductive layer 112, and conductive layer 114. The first direction D1, the second direction D2, and the third direction D3 can be perpendicular to each other. For example, the first direction D1 may be the normal direction of the surface of the substrate 100 facing the stacked structures 110 and 120, and the second direction D2 and the third direction D3 may be parallel to the surface of the substrate 100. The transistor 130 may be part of the peripheral circuitry of the memory device 10. The peripheral circuitry of the memory device 10 may also include other active and / or passive semiconductor elements, such as transistors, diodes, capacitors, resistors, etc.

[0078] The stacked structure 110 may further include an insulating layer 111, an insulating layer 115, an insulating layer 116, and a barrier layer 117. The insulating layer 111, conductive layer 112, insulating layer 113, conductive layer 114, and insulating layer 115 may be sequentially stacked on the substrate 100 along a first direction D1. The insulating layer 111 may be disposed between the conductive layer 112 and the substrate 100. The conductive layer 112 is closer to the substrate 100 than the conductive layer 114. The barrier layer 117 may be disposed on or cover the upper surface, lower surface, and sidewalls of the conductive layer 112, the upper surface, lower surface, and sidewalls of the conductive layer 114. The lower surfaces of the conductive layers 112 and 114 face the substrate 100. The barrier layer 117 may be located between the insulating layer 111 and the conductive layer 112. Barrier layer 117 may be located between conductive layer 112 and insulating layer 113. Barrier layer 117 may be located between insulating layer 113 and conductive layer 114. Barrier layer 117 may be located between conductive layer 114 and insulating layer 115. Barrier layer 117 may be located between insulating layer 116 and conductive layer 112. Barrier layer 117 may be located between insulating layer 116 and conductive layer 114. Insulating layer 116 may be disposed on conductive layer 112 in a first direction D1. Insulating layer 116 may be disposed on one side of conductive layer 114 in a second direction D2 and / or a third direction D3. Insulating layer 116 may be adjacent to insulating layer 113 and insulating layer 115.

[0079] The stacked structure 120 may include an insulating film 121, a deflection 122, and an insulating film 123. The deflection 122 may be adjacent to one end of the conductive layer 112. The deflection 122 may include multiple semiconductor layers, such as semiconductor layer 1221 and semiconductor layer 1222, stacked and extending along a first direction D1 and a second direction D2. The number of semiconductor layers included in the deflection 122 is not limited to... Figure 1 As shown, the derivation portion 122 may contain two or more semiconductor layers. Semiconductor layers 1221 and 1222 may have an L-shaped cross-section on the plane formed by the first direction D1 and the second direction D2. Semiconductor layers 1221 and 1222 may extend on the plane formed by the second direction D2 and the third direction D3, and may also extend on the plane formed by the first direction D1 and the third direction D3. Semiconductor layer 1222 may be disposed on semiconductor layer 1221. An insulating film 123 may be disposed on semiconductor layer 1222. The insulating film 123 may be adjacent to the upper surface of semiconductor layer 1222 and the sidewall facing away from the stacked structure 110. Semiconductor layer 1221 may be adjacent to the sidewall of insulating layer 116, the sidewall of barrier layer 117, and the sidewall of insulating layer 111. The derivation portion 122 and the insulating film 123 may be located between the insulating film 121 and the stacked structure 110.

[0080] Transistor 130 has a source 131, a drain 132, and a gate 133. The gate 133 is disposed between the source 131 and the drain 132. The source 131 and the drain 132 are located in a substrate 100. The gate 133 is located on the substrate 100. The gate 133 may be formed of a conductive film 1331, a dielectric film 1333, and a semiconductor film 1332. The semiconductor film 1332 may be disposed between the conductive film 1331 and the dielectric film 1333. The dielectric film 1333, the semiconductor film 1332, and the conductive film 1331 may be stacked sequentially along a first direction D1. In this embodiment, the semiconductor film 1332 has a multilayer structure, comprising semiconductor material films 1332A and 1332B stacked along the first direction D1. However, the invention is not limited thereto; the semiconductor film 1332 may have three or more layers of semiconductor material films, or the semiconductor film 1332 may have a single-layer structure. In this embodiment, Figure 1 The dielectric film 1333 of the two transistors 130 shown has different heights in the first direction D1, but the present invention is not limited thereto.

[0081] The storage device 10 may further include at least one channel post 150, a plurality of storage cells MS, a plurality of shallow trench isolation (STI) structures 170, at least one source contact structure 171, at least one drain contact structure 172, at least one gate contact structure 173, at least one conductive contact structure 174, at least one conductive contact structure 175, at least one channel contact structure 176, at least one dielectric film 177, at least one conductive post 178, at least one spacer element 181, at least one spacer element 182, a capping layer 183, at least one isolation element 1711, at least one isolation element 1721, at least one isolation element 1731, at least one isolation element 1781, and interlayer insulating layers 191 and 192. Interlayer insulating layers 191 and 192 may extend on the plane formed by the second direction D2 and the third direction D3 and span the array region 101 and the peripheral region 102. Interlayer insulating layer 191 and interlayer insulating layer 192 can be disposed between stacked structure 110 and metal winding layer 140, and can also be disposed between stacked structure 120 and metal winding layer 140. Interlayer insulating layer 191 and interlayer insulating layer 192 can be stacked sequentially along the first direction D1.

[0082] Channel post 150 may extend along a direction opposite to the first direction D1 (e.g., a negative first direction D1) and penetrate the stack structure 110. Channel post 150 may be disposed in array region 101 and on substrate 100. Channel post 150 may include insulating post 151, channel layer 152, charge storage layer 153, and pad 154. Channel layer 152 may be tubular and surround insulating post 151. Charge storage layer 153 may be tubular and surround channel layer 152 and insulating post 151. Outer wall of charge storage layer 153 may contact insulating layer 111, insulating layer 113, insulating layer 115, and barrier layer 117. Barrier layer 117 may isolate channel post 150 from conductive layer 112 and conductive layer 114. Pad 154 may be disposed at or contact a first end of insulating post 151, a first end of channel layer 152, and a first end of charge storage layer 153. The second end of the insulating pillar 151 (relative to the first end), the second end of the channel layer 152 (relative to the first end), and the second end of the charge storage layer 153 (relative to the first end) are in contact with the substrate 100. A plurality of memory cells MS are located between the conductive layer 114 and the channel pillar 150.

[0083] Multiple shallow trench isolations 170 may be disposed in the substrate 100. The multiple shallow trench isolations 170 are disposed in the peripheral region 102 and below the stacked structure 120. The multiple shallow trench isolations 170 may be alternately distributed with transistors 130. The shallow trench isolations 170 can electrically isolate the multiple transistors 130 from each other.

[0084] Source contact structure 171 and drain contact structure 172 may extend to the surface of substrate 100 in a direction opposite to the first direction D1 (e.g., negative first direction D1). Source contact structure 171 may extend to the surface of source 131 of transistor 130 in a direction opposite to the first direction D1 (e.g., negative first direction D1). Drain contact structure 172 may extend to the surface of drain 132 of transistor 130 in a direction opposite to the first direction D1 (e.g., negative first direction D1). Gate contact structure 173 may extend to the surface of gate 133 of transistor 130 in a direction opposite to the first direction D1 (e.g., negative first direction D1). Source contact structure 171, drain contact structure 172 and gate contact structure 173 may be disposed separately on substrate 100. Source contact structure 171, drain contact structure 172 and gate contact structure 173 may penetrate stacked structure 120, interlayer insulating layer 191 and interlayer insulating layer 192. Source contact structure 171 is electrically connected to the source 131 of transistor 130. Drain contact structure 172 is electrically connected to the drain 132 of transistor 130. Gate contact structure 173 is electrically connected to the gate 133 of transistor 130. In this embodiment, the height 171H of source contact structure 171 from substrate 100 and the height 172H of drain contact structure 172 from substrate 100 are greater than the height 150H of channel pillar 150 from substrate. Heights 171H, 172H, and 150H are in the first direction D1. Height 171H can also be understood as the distance between the upper surface of source contact structure 171 and the upper surface of source 131. Height 172H can also be understood as the distance between the upper surface of drain contact structure 172 and the upper surface of drain 132. Height 150H can also be understood as the distance between the upper surface of pad 154 and the surface of substrate 100.

[0085] Isolating elements 1711, 1721, and 1731 are on substrate 100. Isolating elements 1711, 1721, and 1731 can penetrate the stacked structure 120 and the interlayer insulating layer 191. Isolating element 1711 can be disposed on the sidewall of source contact structure 171. Isolating element 1711 can surround source contact structure 171. Source contact structure 171 can extend beyond isolation element 1711. Isolating element 1721 can be disposed on the sidewall of drain contact structure 172. Isolating element 1721 can surround drain contact structure 172. Drain contact structure 172 can extend beyond isolation element 1721. Isolating element 1731 can be disposed on the sidewall of gate contact structure 173. Isolating element 1731 can surround gate contact structure 173. Gate contact structure 173 can extend beyond isolation element 1731. In this embodiment, the upper surfaces of isolation elements 1711, 1721 and 1731 can be at the same height as the upper surface of the interlayer insulating layer 191.

[0086] Spacer elements 181 and 182, and a capping layer 183 are disposed on substrate 100. Spacer elements 181, 182, and 183 are disposed in peripheral region 102. Spacer elements 181, 182, and 183 are disposed in stacked structure 120. Spacer element 181 may be located on the sidewall of gate 133 of transistor 130. Spacer element 181 may be disposed on opposite sidewalls of gate 133. Spacer element 181 may be located on the sidewalls of conductive film 1331 and semiconductor film 1332 of gate 133 of transistor 130. Spacer element 181 may be located above dielectric film 1333 of gate 133. Spacer element 181 may be located between source 131 and semiconductor film 1332. Spacer element 181 may be located between drain 132 and semiconductor film 1332. Spacer element 181 can contact dielectric film 1333, semiconductor film 1332, conductive film 1331, and isolation element 1731. In the first direction D1, one end of spacer element 181 may be higher than the upper surface of conductive film 1331. Spacer element 182 may be disposed on the sidewall of the deflection portion 122 and the sidewall of insulating film 123. Spacer element 182 may be located at the end of the deflection portion 122 away from conductive layer 112. Spacer element 182 may be disposed above dielectric film 177. The height of spacer element 181 in the first direction D1 may be substantially the same as the height of spacer element 182 in the first direction D1. Cover layer 183 may cover spacer element 181, spacer element 182, and shallow trench isolation 170. Cover layer 183 may cover dielectric film 177. Cover layer 183 may be located between insulating film 121 and spacer element 182. Cover layer 183 may be located between insulating film 121 and dielectric film 177. Cover layer 183 may be located between insulating film 121 and shallow trench isolation 170. Cover layer 183 may be located between insulating film 121 and spacer element 181.

[0087] A dielectric film 177 is disposed in the peripheral region 102 and below the stacked structure 120. The dielectric film 177 may extend from the boundary of the peripheral region 102 to the shallow trench isolation 170. In this embodiment, the height of the dielectric film 177 in the first direction D1 is the same as or substantially the same as the height of the dielectric film 1333 of the transistor 130 adjacent to the dielectric film 177 in the first direction D1, but the invention is not limited thereto.

[0088] Conductive pillars 178 are disposed on substrate 100. Conductive pillars 178 are disposed in array region 101. Conductive pillars 178 can penetrate stacked structure 110, interlayer insulating layer 191, and interlayer insulating layer 192. Conductive pillars 178 can extend to the surface of substrate 100 in a direction opposite to the first direction D1 (e.g., a negative first direction D1). Conductive pillars 178 can be electrically connected to substrate 100. Isolation element 1781 is on substrate 100. Isolation element 1781 can penetrate stacked structure 110 and interlayer insulating layer 191. Isolation element 1781 can be disposed on the sidewall of conductive pillar 178. Isolation element 1781 can surround conductive pillar 178. Conductive pillar 178 can extend beyond isolation element 1781.

[0089] Conductive contact structures 174 and 175 are disposed separately on the substrate 100. Conductive contact structures 174 and 175 are disposed in the array region 101. Conductive contact structure 174 is above conductive layer 112. Conductive contact structure 174 can land on or contact conductive layer 112. Conductive contact structure 174 can penetrate interlayer insulating layer 192, interlayer insulating layer 191, insulating layer 116, and a portion of barrier layer 117 on the upper surface of conductive layer 112 and is electrically connected to conductive layer 112. Conductive contact structure 175 is above conductive layer 114. Conductive contact structure 175 can land on or contact conductive layer 114. Conductive contact structure 175 can penetrate interlayer insulating layer 192, interlayer insulating layer 191, insulating layer 115, and a portion of barrier layer 117 on the upper surface of conductive layer 114 and is electrically connected to conductive layer 114. The height 171H of the source contact structure 171 from the substrate 100 and the height 172H of the drain contact structure 172 from the substrate 100 can be greater than the height 178H of the conductive pillar 178 from the substrate 100. The height 178H is in the first direction D1. The height 178H can also be understood as the distance between the upper surface of the conductive pillar 178 and the surface of the substrate 100.

[0090] Channel contact structure 176 is on substrate 100. Channel contact structure 176 is disposed in array region 101. Channel contact structure 176 is above channel pillar 150 and stack structure 110. Channel contact structure 176 may extend along a first direction D1 and penetrate interlayer insulating layer 191 and interlayer insulating layer 192. Channel contact structure 176 may be disposed between channel pillar 150 and metal winding layer 140.

[0091] The metal winding layer 140 may include an insulating material 142 and a plurality of wires 141 disposed in the insulating material 142. One of the plurality of wires 141 may be electrically connected to a source 131 via a source contact structure 171. One of the plurality of wires 141 may be electrically connected to a drain 132 via a drain contact structure 172. One of the plurality of wires 141 may be electrically connected to a gate 133 via a gate contact structure 173. One of the plurality of wires 141 may be electrically connected to a substrate 100 via a conductive post 178. Conductive contact structures 174 and 175 are electrically connected to the wires 141 of the metal winding layer 140. One of the plurality of wires 141 may be electrically connected to a conductive layer 112 via a conductive contact structure 174. One of the plurality of wires 141 may be electrically connected to a conductive layer 114 via a conductive contact structure 175. One of the plurality of wires 141 may be electrically connected to a channel post 150 via a channel contact structure 176.

[0092] The number of components included in storage device 10 is not limited to Figure 1 The quantities shown can be increased or decreased as needed.

[0093] The transistor formed at the intersection of conductive layer 112 and channel pillar 150 can serve as a select transistor, and conductive layer 112 can serve as a select gate line. The transistor formed at the intersection of conductive layer 114 and channel pillar 150 can serve as a data storage transistor, and conductive layer 114 can serve as a word line. The wire 141 electrically connected to channel pillar 150 in metal winding layer 140 can serve as a bit line.

[0094] Please refer to the following at the same time Figure 1 and Figure 2A . Figure 2A It is a drawing Figure 1 Circuit diagram of storage device 10. Figure 2AThis diagram shows four data storage transistors TD1-TD4 and four select transistors TS1-TS4. Data storage transistor TD1 is connected in series with select transistor TS1. Data storage transistor TD2 is connected in series with select transistor TS2. Data storage transistor TD3 is connected in series with select transistor TS3. Data storage transistor TD4 is connected in series with select transistor TS4. Data storage transistor TD1 and select transistor TS1 form a memory cell MS and are electrically connected between bit line BL1 and common source line CSL. Data storage transistor TD2 and select transistor TS2 form a memory cell MS and are electrically connected between bit line BL2 and common source line CSL. Data storage transistor TD3 and select transistor TS3 form a memory cell MS and are electrically connected between bit line BL1 and common source line CSL. Data storage transistor TD4 and select transistor TS4 form a memory cell MS and are electrically connected between bit line BL2 and common source line CSL. Data storage transistors TD1 and TD2 are electrically connected to word line MG1. Select transistors TS1 and TS2 are electrically connected to select gate line SG1. Data storage transistors TD3 and TD4 are electrically connected to word line MG2. Select transistors TS3 and TS4 are electrically connected to select gate line SG2. For example, the operation of the memory device 10 may include: applying a voltage to bit line BL1 and common source line CSL electrically connected to data storage transistor TD1 and select transistor TS1, applying a voltage to word line MG1 electrically connected to data storage transistor TD1, and applying a voltage to select gate line SG1 electrically connected to select transistor TS1 to perform read, write, or erase operations.

[0095] Please refer to Figure 2B . Figure 2B Showing the Figure 1 The threshold voltage distribution of the storage device 10 in the write and erase states. Figure 2B In the diagram, the horizontal axis represents the threshold voltage Vt, and the vertical axis represents the number of memory cells (count). Figure 2BThe read voltage Vread is applied to the word line during a read operation to identify the data stored in the memory cell. The read voltage Vread is typically set between the erase voltage and the write voltage. In a comparative example where the memory cell does not contain a select transistor, the erase voltage is set slightly higher than 0 V to prevent the data storage transistor from being normally ON, and the write voltage must be set to a higher value to ensure the memory device has sufficient sensing margin for read operations, thus requiring a charge pump circuit to boost the voltage. In the memory device of this invention, since the memory cell includes a data storage transistor and a select transistor, and the select transistor can be used to turn the data storage transistor on or off, the threshold voltage distribution of the data storage transistor in the erase state can be set to a lower value (compared to the comparative example), for example, the threshold voltage distribution of the data storage transistor in the erase state can be set to below 0 V (e.g., ...). Figure 2B As shown in the figure, the threshold voltage distribution of the data storage transistor in the write state can also be set to a lower value (compared to the comparative example); even if such a threshold voltage distribution setting may cause the data storage transistor to be in the normally on state, leakage can be avoided by turning off the select transistor. Therefore, the memory device of the present invention can achieve lower read voltage (e.g., the read voltage can be set to the supply voltage Vdd) and lower write voltage, eliminate the need for a charge pump circuit to boost the voltage, shorten the word line setup time, simplify circuit design, and speed up operation. The memory device of the present invention is advantageous for low-power, high-speed applications.

[0096] Please refer to Figure 3 . Figure 3 This is a schematic cross-sectional view illustrating a storage device 20 according to another embodiment of the present invention. Storage device 20 and Figure 1The difference between the storage device 10 shown is that the storage device 20 also includes a conductive part 324, and the storage device 20 uses a conductive film 3331 instead of the conductive film 1331 of the storage device 10. The storage device 20 may include a substrate 100, at least one stacked structure 110, at least one stacked structure 320, at least one transistor 330, at least one metal wire-wound layer 140 located above the stacked structures 110 and 320, at least one channel pillar 150, a plurality of memory cells MS, a plurality of shallow trench isolations 170, at least one source contact structure 171, at least one drain contact structure 172, at least one gate contact structure 173, at least one conductive contact structure 174, at least one conductive contact structure 175, at least one channel contact structure 176, at least one dielectric film 177, at least one conductive pillar 178, at least one spacer element 181, at least one spacer element 182, a capping layer 183, at least one isolation element 1711, at least one isolation element 1721, at least one isolation element 1731, at least one isolation element 1781, an interlayer insulating layer 191, and an interlayer insulating layer 192.

[0097] A stacked structure 320 is located in the peripheral region 102. The stacked structure 320 is disposed on the substrate 100 along a first direction D1. The stacked structure 320 may be disposed on one side of the stacked structure 110 along a second direction D2 and / or a third direction D3. The stacked structure 320 may be adjacent to the stacked structure 110. The stacked structure 320 includes an insulating film 121, a deflection portion 122, an insulating film 123, and a conductive portion 324. The conductive portion 324 is disposed between the insulating film 123 and the deflection portion 122. The conductive portion 324 may extend along the first direction D1 and the second direction D2 and is stacked on the deflection portion 122. The conductive portion 324 may have an L-shaped cross-section in the plane formed by the first direction D1 and the second direction D2. The conductive portion 324 may extend in the plane formed by the second direction D2 and the third direction D3, and may also extend in the plane formed by the first direction D1 and the third direction D3. A transistor 330 is located in the peripheral region 102. Transistor 330 is located in stacked structure 320. Transistor 330 includes a source 131, a drain 132, and a gate 333 disposed between the source 131 and the drain 132. Gate 333 includes a dielectric film 1333, a semiconductor film 1332, and a conductive film 3331 sequentially stacked along a first direction D1. Gate contact structure 173 may be disposed on conductive film 3331. Gate contact structure 173 may contact conductive film 3331. Metal winding layer 140 may be electrically connected to gate 333 of transistor 330 through gate contact structure 173. The material of conductive film 3331 of storage device 20 may be different from the material of conductive film 1331 of storage device 10. Conductive portion 324 and conductive film 3331 may contain the same material or different materials. Transistor 330 may be part of peripheral circuitry of storage device 20. Peripheral circuitry of storage device 20 may also include other active and / or passive semiconductor elements, such as transistors, diodes, capacitors, resistors, etc. The circuit diagram of storage device 20 and the threshold voltage distribution during operation are similar to those of storage device 10.

[0098] In one embodiment, in array region 101, the stacked structure of storage device 10 and storage device 20 may include only two stacked transistors (one data storage transistor and one select transistor) in the first direction D1, without including any additional transistors stacked along the first direction D1. In one embodiment, storage device 10 and storage device 20 may be low-power, high-efficiency, and low-density (compared to NAND flash memory devices) storage devices.

[0099] Figures 4 to 23 This is a structural cross-sectional schematic diagram illustrating multiple stages of a method for manufacturing a storage device according to some embodiments of the present invention. Figures 4 to 23 The steps shown can be performed sequentially or in other orders, and the present invention is not limited thereto.

[0100] Please refer to Figure 4 . Figure 4 This is a schematic cross-sectional view of a stage of a method for manufacturing a memory device. A substrate 100 is provided, comprising an array region 101 and a peripheral region 102. A layer stack 410 is formed in the array region 101 and the peripheral region 102. The layer stack 410 is disposed on the substrate 100 along a first direction D1. The layer stack 410 may extend in a plane formed by a second direction D2 and a third direction D3 and span the array region 101 and the peripheral region 102. The layer stack 410 may include an insulating layer 411, a semiconductor material layer 412, an insulating layer 413, a dielectric layer 414, and an insulating layer 415. The insulating layer 411 may be disposed between the substrate 100 and the semiconductor material layer 412. The insulating layer 413 may be disposed between the semiconductor material layer 412 and the dielectric layer 414. The insulating layer 415 may be disposed on the side of the layer stack 410 away from the substrate 100. An insulating layer 411, a semiconductor material layer 412, an insulating layer 413, a dielectric layer 414, and an insulating layer 415 can be sequentially formed on the upper surface 100U of a substrate 100 by a deposition process to form a layer stack 410. The substrate 100 may contain a semiconductor material, such as doped or undoped monocrystalline silicon, doped or undoped polycrystalline silicon, germanium, etc. In one embodiment, the substrate 100 contains doped or undoped monocrystalline silicon. The insulating layers 411, 413, and 415 may contain an insulating material, such as an oxide. In one embodiment, the insulating layers 411, 413, and 415 contain silicon oxide. The semiconductor material layer 412 may contain a semiconductor material, such as doped or undoped polycrystalline silicon. The dielectric layer 414 may contain a dielectric material, such as a nitride. In one embodiment, the dielectric layer 414 contains silicon nitride.

[0101] Next, at least one channel post 450 can be formed through the stacked layers 410. The channel post 450 is disposed in the array region 101 and on the substrate 100. A plurality of channel posts 450 may be disposed separately from each other. The channel post 450 may include an insulating post 151, a channel layer 152, a charge storage layer 153, and a pad 454. The outer sidewall of the charge storage layer 153 may contact the insulating layer 411, the semiconductor material layer 412, the insulating layer 413, the dielectric layer 414, and the insulating layer 415. The pad 454 may be disposed on or in contact with the first end of the insulating post 151, the first end of the channel layer 152, and the first end of the charge storage layer 153. The second end of the insulating post 151 (the second end relative to the first end), the second end of the channel layer 152 (the second end relative to the first end), and the second end of the charge storage layer 153 (the second end relative to the first end) may contact the substrate 100. The method of forming the channel pillar 450 may include: forming at least one hole 4501 in the layer stack 410 by etching, the hole 4501 extending along a first direction D1, the hole 4501 exposing the sidewalls of the insulating layer 411, the sidewalls of the semiconductor material layer 412, the sidewalls of the insulating layer 413, the sidewalls of the dielectric layer 414, the sidewalls of the insulating layer 415, and the upper surface 100U of the substrate 100; then, forming a charge storage layer 153, a channel layer 152 and an insulating pillar 151 sequentially in the hole 4501 by deposition; then, forming a pad 454 in the hole 4501 by deposition. In one embodiment, the deposition process used to form pad 454 causes the material of pad 454 to be formed in the aperture 4501 and on the insulating layer 415. The material of pad 454 on the insulating layer 415 (which can also be understood as the material of pad 454 outside the aperture 4501) can be removed by an etching back process, thereby forming pad 454.

[0102] The charge storage layer 153 may comprise a multilayer structure known in the field of memory technology, such as an ONO (oxide-nitride-oxide) structure, an ONONO (oxide-nitride-oxide-nitride-oxide) structure, an ONONONO (oxide-nitride-oxide-nitride-oxide-oxide) structure, a SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, a BE-SONOS (bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, a TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, a MA BE-SONOS (metal-high dielectric constant material bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, or a combination thereof. The channel layer 152 may comprise a semiconductor material, such as doped or undoped polysilicon. The insulating pillar 151 may comprise an insulating material, such as an oxide. In one embodiment, the insulating pillar 151 comprises silicon oxide. The pad 454 may contain semiconductor material, such as doped or undoped polysilicon.

[0103] The structure of the channel column is not limited to Figure 4 The channel post 450 is shown. For example, the channel post can be as follows: Figure 4A The channel pillar 550 is shown. The channel pillar 550 may include a channel layer 552 and a charge storage layer 553. The charge storage layer 553 may be tubular and surround the channel layer 552. The outer wall of the charge storage layer 553 may contact an insulating layer 411, a semiconductor material layer 412, an insulating layer 413, a dielectric layer 414, and an insulating layer 415. The channel pillar 550 may contact the substrate 100. A method for forming the channel pillar 550 may include: forming the charge storage layer 553 in a cavity 4501 by a deposition process; and then forming the channel layer 552 in the cavity 4501 by a deposition process or an epitaxial growth process. The charge storage layer 553 may comprise a multilayer structure known in the field of memory technology, such as an ONO (oxide-nitride-oxide) structure, an ONONO (oxide-nitride-oxide-nitride-oxide) structure, an ONONONO (oxide-nitride-oxide-nitride-oxide-oxide) structure, a SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, a BE-SONOS (bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, a TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, a MA BE-SONOS (metal-high dielectric constant material bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, or a combination thereof. The channel layer 552 may comprise a semiconductor material, such as doped or undoped single-crystal silicon, doped or undoped polycrystalline silicon, etc. In one embodiment, the channel layer 552 may comprise single-crystal silicon formed by an epitaxial growth process.

[0104] Please refer to Figure 5 . Figure 5 This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. The layer stack 410 with the removed portion is shown. Specifically, the portion of layer stack 410 located in the peripheral region 102 is removed, while the portion of layer stack 410 located in the array region 101 is retained; the retained portion is layer stack 410A. The upper surface 100U of the substrate 100 in the peripheral region 102 is exposed. A portion of insulating layer 411, a portion of semiconductor material layer 412, a portion of insulating layer 413, a portion of dielectric layer 414, and a portion of insulating layer 415 located in the peripheral region 102 can be removed by etching. The retained portion of insulating layer 411 is insulating layer 411A, the retained portion of semiconductor material layer 412 is semiconductor material layer 412A, the retained portion of insulating layer 413 is insulating layer 413A, the retained portion of dielectric layer 414 is dielectric layer 414A, and the retained portion of insulating layer 415 is insulating layer 415A. The insulating layer 411A, the semiconductor material layer 412A, the insulating layer 413A, the dielectric layer 414A and the insulating layer 415A form a stacked layer 410A.

[0105] Please refer to Figure 6 . Figure 6 This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. Dielectric films 6771 and 6772 are formed in a peripheral region 102. Dielectric films 6771 and 6772 may have different heights in the first direction D1, but the invention is not limited thereto. In this embodiment, the height of dielectric film 6771 in the first direction D1 is greater than the height of dielectric film 6772 in the first direction D1. Dielectric film 6771 can serve as a dielectric film for a high-voltage element, such as a gate dielectric film. Dielectric film 6772 can serve as a dielectric film for a low-voltage element, such as a gate dielectric film. The exposed substrate 100 may undergo one or more oxidation processes to form dielectric films 6771 and 6772. In one embodiment, the oxidation process used to form dielectric films 6771 and 6772 is a dry oxidation process.

[0106] Please refer to Figure 7 . Figure 7This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. A semiconductor layer 7221 and a filler element 7223 are formed. The semiconductor layer 7221 extends across the array region 101 and the peripheral region 102, in a plane formed by a second direction D2 and a third direction D3. A portion of the semiconductor layer 7221 is on the layer stack 410A, and another portion is on dielectric films 6771 and 6772. The semiconductor layer 7221 is in contact with the upper surface and sidewalls of the layer stack 410A. The semiconductor layer 7221 is in contact with dielectric films 6771 and 6772. The filler element 7223 is on the semiconductor layer 7221. The filler element 7223 is located in the peripheral region 102. In this embodiment, the semiconductor layer 7221 on the upper surface 7221U of the array region 101 and the fill element 7223 on the upper surface 7223U of the peripheral region 102 may be coplanar (or may have substantially the same height in the first direction D1). The semiconductor layer 7221 can be formed on the layer stack 410A and the substrate 100 by deposition, followed by deposition to form the fill element 7223 on the semiconductor layer 7221. In one embodiment, the deposition process for forming the fill element 7223 may cause the material of the fill element 7223 to cover the semiconductor layer 7221 in the array region 101 and the peripheral region 102. A polishing process can be used to remove a portion of the material of the fill element 7223, exposing the semiconductor layer 7221 on the upper surface 7221U of the array region 101, thereby forming the fill element 7223. The semiconductor layer 7221 may comprise a semiconductor material, such as doped or undoped polysilicon. The fill element 7223 may comprise an insulating material, such as an oxide. In one embodiment, the filling element 7223 comprises silicon oxide.

[0107] Please refer to Figure 8 . Figure 8This is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a storage device. At least one hole 8501 is formed in the peripheral region 102. Multiple holes 8501 may be arranged separately from each other. The holes 8501 may extend along a first direction D1. The holes 8501 may penetrate the filling element 7223A, the semiconductor layer 7221A, the dielectric film 177, the dielectric film 6771A, the dielectric film 6772A, and the substrate 100. The holes 8501 may expose the sidewalls of the filling element 7223A, the semiconductor layer 7221A, the dielectric film 6771A, the dielectric film 177, the dielectric film 6772A, the sidewalls of the substrate 100, and the surface of the substrate 100. The bottom of the hole 8501 may be lower than the upper surface 100U of the substrate 100. A portion of the filler element 7223, a portion of the semiconductor layer 7221, a portion of the dielectric film 6771, a portion of the dielectric film 6772, and a portion of the substrate 100 can be removed by etching to form a hole 8501. The portion of the filler element 7223 that is retained is the filler element 7223A. The portion of the semiconductor layer 7221 that is retained is the semiconductor layer 7221A. The portion of the dielectric film 6771 that is retained can be divided into dielectric film 6771A and 177, and the hole 8501 separates dielectric film 6771A and 177 from each other. The portion of the dielectric film 6772 that is retained is the dielectric film 6772A.

[0108] Please refer to Figure 9 . Figure 9 This is a structural cross-sectional schematic diagram of a stage of a method for manufacturing a memory device. At least one isolation element 970 is formed. The isolation element 970 can be formed in a via 8501 by a deposition process. In one embodiment, the deposition process for forming the isolation element 970 causes the material of the isolation element 970 to cover the semiconductor layer 7221A in the array region 101 and the filler element 7223A in the peripheral region 102. A polishing process can be used to remove the portion of the material of the isolation element 970 above the semiconductor layer 7221A and the filler element 7223A, leaving the portion of the material of the isolation element 970 within the via 8501, thereby forming the isolation element 970. The isolation element 970 may comprise an insulating material, such as an oxide. In one embodiment, the isolation element 970 comprises silicon oxide.

[0109] Please refer to Figure 10 . Figure 10This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. At least one isolation element 970A, a semiconductor layer 7222, and a gate oxide layer 7224 are formed. The isolation element 970A extends along a first direction D1 and penetrates the semiconductor layer 7221A, dielectric film 6771A, dielectric film 177, dielectric film 6772A, and substrate 100. The upper surface 970U of the isolation element 970A and the upper surface 72AU of the semiconductor layer 7221A are coplanar. The semiconductor layer 7222 and the gate oxide layer 7224 extend along a plane formed by a second direction D2 and a third direction D3, spanning the array region 101 and the peripheral region 102. The semiconductor layer 7222 and the gate oxide layer 7224 are disposed on the semiconductor layer 7221A. The semiconductor layer 7222 may be located between the gate oxide layer 7224 and the semiconductor layer 7221A. An etch-back process can be used to remove a portion of the fill element 7223A and the isolation element 970 above the upper surface 72AU of the semiconductor layer 7221A. The portion of the isolation element 970 retained is the isolation element 970A. After forming the isolation element 970A, a deposition process can be used to sequentially form a semiconductor layer 7222 and a gate oxide layer 7224 on the semiconductor layer 7221A. The semiconductor layer 7222 and the gate oxide layer 7224 can be conformally formed on the semiconductor layer 7221A. The semiconductor layer 7222 may contain a semiconductor material, such as doped or undoped polysilicon. The gate oxide layer 7224 may contain an insulating material, such as an oxide. In one embodiment, the gate oxide layer 7224 contains silicon oxide.

[0110] Please refer to Figure 11 . Figure 11 This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. Semiconductor layer 7221B, semiconductor layer 7222A, and gate oxide layer 7224A are formed. The upper surfaces of semiconductor layer 7221B, semiconductor layer 7222A, gate oxide layer 7224A, and the upper surface of the layer stack 410A are coplanar. The portions of semiconductor layer 7221A, semiconductor layer 7222A, and gate oxide layer 7224A above the upper surface of the layer stack 410A can be removed by etching. The portion of semiconductor layer 7221A remaining is semiconductor layer 7221B, the portion of semiconductor layer 7222A remaining is semiconductor layer 7222A, and the portion of gate oxide layer 7224A remaining is gate oxide layer 7224A.

[0111] Please refer to Figure 12 . Figure 12This is a schematic cross-sectional view of a stage of a method for manufacturing a memory device. In the peripheral region 102, an extension 122 comprising semiconductor layers 1221 and 1222, an insulating film 123, a semiconductor film 1332 comprising semiconductor material films 1332A and 1332B, a gate oxide layer 7224B, and a shallow trench isolation 170 are formed. At least one aperture 1201 is formed in the peripheral region 102. A plurality of apertures 1201 may be arranged separately from each other. One of the plurality of apertures 1201 may expose the upper surface of the dielectric film 177, the upper surface of the shallow trench isolation 170, the upper surface of the dielectric film 6771A, the sidewall of the extension 122, the sidewall of the insulating film 123, the sidewall of the semiconductor film 1332, and the sidewall of the gate oxide layer 7224B. One of the plurality of apertures 1201 may expose the upper surface of dielectric film 6771A, the upper surface of shallow trench isolation 170, the upper surface of dielectric film 6772A, the sidewall of semiconductor film 1332, and the sidewall of gate oxide layer 7224B. The upper surfaces of shallow trench isolation 170, dielectric film 177, dielectric film 6771A, and dielectric film 6772A may be coplanar. The deflection portion 122 may be adjacent to the layer stack 410A. The semiconductor layer 1222 in the deflection portion 122 may be located between semiconductor layer 1221 and insulating film 123. The deflection portion 122 may be disposed at the boundary of peripheral region 102, or the deflection portion 122 may serve as the boundary between array region 101 and peripheral region 102.

[0112] A portion of the isolation element 970A, a portion of the semiconductor layer 7221B, a portion of the semiconductor layer 7222A, and a portion of the gate oxide layer 7224A can be removed by etching, thereby forming a hole 1201. The portion of the isolation element 970A that is retained forms the shallow trench isolation 170. The portion of the semiconductor layer 7221B that is retained can be divided into semiconductor layer 1221 and semiconductor material film 1332B. The portion of the semiconductor layer 7222A that is retained can be divided into semiconductor layer 1222 and semiconductor material film 1332A. The portion of the gate oxide layer 7224A that is retained can be divided into insulating film 123 and gate oxide layer 7224B. The hole 1201 separates semiconductor layer 1221 from semiconductor material film 1332B. The hole 1201 separates semiconductor layer 1222 from semiconductor material film 1332A. The hole 1201 separates insulating film 123 from gate oxide layer 7224B.

[0113] Please refer to Figure 13 . Figure 13 This is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a storage device. A plurality of spacer elements 181 and at least one spacer element 182 are formed in the peripheral region 102. The spacer elements 181 and 182 are located in the aperture 1201. Figure 13Spacer element 181 and spacer element 182 are illustrated as having arcuate sidewalls 181S and 182S, respectively, but the invention is not limited thereto. Spacer element 181 may be adjacent to the sidewall of semiconductor film 1332 and the sidewall of gate oxide layer 7224B. Spacer element 182 may be adjacent to the sidewall of diffracted portion 122 and the sidewall of insulating film 123. Spacer element 181 and spacer element 182 are disposed separately from each other. Spacer element 181 and spacer element 182 may comprise an insulating material, such as an oxide or nitride. In one embodiment, spacer element 181 and spacer element 182 comprise silicon oxide or silicon nitride. Spacer element 181 and spacer element 182 may comprise the same material or different materials. An insulating material (i.e., the material of spacer element 181 and spacer element 182) can be formed in the hole 1201 by deposition process, and the insulating material can fill the hole 1201; then a portion of the insulating material can be removed by etching process, and the portion of the insulating material that is retained can be divided into spacer element 181 and spacer element 182.

[0114] In one embodiment, after forming spacer element 181 and spacer element 182, the spacer element 181 can be... Figure 13 The surface of the structure shown (e.g.) Figure 13 The surface indicated by the dashed line is subjected to ion implantation to introduce N-type or P-type dopants. Figure 13 The surface of the structure shown. Ion implantation can be performed simultaneously on the structure located in array region 101 and the structure located in peripheral region 102.

[0115] Please refer to Figure 14 . Figure 14 This is a structural cross-sectional schematic diagram of a stage of a method for manufacturing a memory device. A capping layer 1483 is formed. The capping layer 1483 extends on the plane formed by the second direction D2 and the third direction D3 and spans the array region 101 and the peripheral region 102. The capping layer 1483 may cover the upper surface of the layer stack 410A, the upper surface of the semiconductor layer 1221, the upper surface of the semiconductor layer 1222, the upper surface of the insulating film 123, the sidewall 182S of the spacer element 182, the upper surface of the dielectric film 177, the upper surface of the shallow trench isolation 170, the upper surface of the dielectric film 6771A, the sidewall 181S of the spacer element 181, the upper surface of the gate oxide layer 7224B, and the upper surface of the dielectric film 6772A. A capping layer 1483 can be conformally formed on the layer stack 410A, the diffracted portion 122, the insulating film 123, the spacer element 182, the dielectric film 177, the shallow trench isolation 170, the dielectric film 6771A, the spacer element 181, and the gate oxide layer 7224B by a deposition process. The capping layer 1483 may contain a dielectric material, such as a nitride.

[0116] Please refer to Figure 15 . Figure 15 This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. A hole 1501 is formed in the array region 101. The hole 1501 penetrates the capping layer 1483A, insulating layer 415B, dielectric layer 414B, and insulating layer 413B. The hole 1501 exposes the sidewalls of the capping layer 1483A, insulating layer 415B, dielectric layer 414B, insulating layer 413B, the upper surface of the semiconductor material layer 412A, and the sidewalls of the semiconductor layer 1221. The hole 1501 may be located at the boundary of the array region 101. The hole 1501 can be formed by etching to remove a portion of the capping layer 1483A, a portion of the insulating layer 415A, a portion of the dielectric layer 414A, and a portion of the insulating layer 413A. The portion of capping layer 1483 that is retained is capping layer 1483A, the portion of insulating layer 415A that is retained is insulating layer 415B, the portion of dielectric layer 414A that is retained is dielectric layer 414B, and the portion of insulating layer 413A that is retained is insulating layer 413B. Insulating layer 411A, semiconductor material layer 412A, insulating layer 413B, dielectric layer 414B, and insulating layer 415B form a stacked layer 410B.

[0117] Please refer to Figure 16 . Figure 16 This is a schematic cross-sectional view of a stage in a method for manufacturing a storage device. An insulating layer 1616 is formed in the array region 101. An insulating film 1621 is formed in the peripheral region 102. The insulating layer 1616 is disposed in the aperture 1501. The insulating film 1621 is disposed on the capping layer 1483A. The insulating layer 1616 and the insulating film 1621 can be formed by deposition and polishing processes. The insulating layer 1616 and the insulating film 1621 may contain an insulating material, such as an oxide. The insulating layer 1616 and the insulating film 1621 may contain the same material or different materials. In one embodiment, the insulating layer 1616 and the insulating film 1621 contain silicon oxide.

[0118] Please refer to Figure 17 . Figure 17 This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. An insulating film 1621A, a capping layer 1483B, and an insulating layer 116 are formed. The insulating film 1621A and the capping layer 1483B are located in the peripheral region 102. The insulating layer 116 is located in the array region 101. The portion of the capping layer 1483A located above the upper surface of the layer stack 410B, above the upper surface of the diffracted portion 122, above the upper surface of the insulating film 123, and above the upper surface of the gate oxide layer 7224B can be removed by an etch-back process, and the portions of the insulating layer 1616 and the insulating film 1621 above the upper surface of the layer stack 410B can be removed to form a structure as shown below. Figure 17The structure shown. The portion of the cover layer 1483A that is retained is the cover layer 1483B. The portion of the insulating layer 1616 that is retained is the insulating layer 116. The portion of the insulating film 1621 that is retained is the insulating film 1621A.

[0119] In other embodiments, Figure 17 The steps shown are optional.

[0120] Please refer to Figure 18 . Figure 18 This is a structural cross-sectional schematic diagram of a stage in a method for manufacturing a memory device. An interlayer insulating layer 1891 and a via 1801 penetrating the interlayer insulating layer 1891 are formed. The interlayer insulating layer 1891 extends along a plane formed by a second direction D2 and a third direction D3, spanning the array region 101 and the peripheral region 102. The via 1801 may be disposed in the array region 101. The via 1801 extends along a first direction D1 and penetrates the insulating layer 115, the dielectric layer 414C, and the insulating layer 113. The via 1801 exposes the sidewalls of the interlayer insulating layer 1891, the insulating layer 115, the dielectric layer 414C, the insulating layer 113, and the upper surface of the semiconductor material layer 412A. The via 1801 may be disposed between a plurality of channel pillars 450. An interlayer insulating layer 1891 can be formed over the layer stack 410B, the gate oxide layer 7224B, and the insulating film 1621A by deposition. Then, a portion of the interlayer insulating layer 1891, a portion of the insulating layer 415B, a portion of the dielectric layer 414B, and the insulating layer 413B can be removed by etching to form a via 1801. The retained portion of the insulating layer 415B is the insulating layer 115, the retained portion of the dielectric layer 414B is the dielectric layer 414C, and the retained portion of the insulating layer 413B is the insulating layer 113. The insulating layer 411A, the semiconductor material layer 412A, the insulating layer 113, the dielectric layer 414C, and the insulating layer 115 form a layer stack 410C. The interlayer insulating layer 1891 may contain an insulating material, such as an oxide. In one embodiment, the interlayer insulating layer 1891 may contain silicon oxide.

[0121] Please refer to Figure 19 . Figure 19This is a schematic cross-sectional view of a stage of a method for manufacturing a storage device. In array region 101, a stacked structure 110 is formed, comprising an insulating layer 111, a conductive layer 112, an insulating layer 113, a conductive layer 114, an insulating layer 115, an insulating layer 116, and a barrier layer 117; a conductive pillar 178 penetrating the stacked structure 110; and an isolation element 1781 disposed between the conductive pillar 178 and the barrier layer 117. Conductive layers 112 and 114 may comprise conductive materials, such as metals. Conductive layers 112 and 114 may comprise the same or different materials. In one embodiment, conductive layers 112 and 114 may comprise tungsten. The barrier layer 117 may comprise a multilayer structure, such as an oxide / nitride / oxide (ONO) multilayer structure. The conductive pillar 178 may comprise conductive materials, such as metals. In one embodiment, the conductive pillar 178 may comprise tungsten. The isolation element 1781 may comprise an insulating material, such as an oxide. In one embodiment, the isolation element 1781 may comprise silicon oxide.

[0122] The dielectric layer 414C and the semiconductor material layer 412A can be removed through the aperture 1801 by etching to form the space 1902 between the insulating layer 113 and the insulating layer 115, and the space 1901 between the insulating layer 113 and the insulating layer 411A. Next, a barrier layer 117 can be formed on the space 1902, the space 1901, the sidewall of the insulating layer 113 exposed by the aperture 1801, the sidewall of the insulating layer 115 exposed by the aperture 1801, and the sidewall of the interlayer insulating layer 1891 exposed by the aperture 1801 by deposition. Then, a conductive material can be formed in the remaining space of the space 1902 (i.e., the space not filled by the barrier layer 117), the remaining space of the space 1901 (i.e., the space not filled by the barrier layer 117), and the remaining space of the aperture 1801 (i.e., the space not filled by the barrier layer 117) by deposition. Next, a portion of the conductive material in the aperture 1801 can be removed by an etching process, and a portion of the insulating layer 411A can be removed by an etching process to expose the substrate 100; the portion of the insulating layer 411A retained is the insulating layer 111. The portion of the conductive material retained in the space 1902 is the conductive layer 114. The portion of the conductive material retained in the space 1901 is the conductive layer 112. The sidewalls of the conductive layer 114 exposed by the aperture 1801 can be recessed relative to the sidewalls of the barrier layer 117 exposed by the aperture 1801 to form a recess. The sidewalls of the conductive layer 112 exposed by the aperture 1801 can be recessed relative to the sidewalls of the barrier layer 117 exposed by the aperture 1801 to form a recess. Next, conductive pillars 178 and isolation elements 1781 can be formed in the aperture 1801 by deposition and etching processes. A portion of the isolation element 1781 can be formed in the recess.

[0123] In one embodiment, after the conductive pillar 178 and the isolation element 1781 are formed, a polishing process may be performed to make the upper surface of the conductive pillar 178, the upper surface of the isolation element 1781, the upper surface of the barrier layer 117 and the upper surface of the interlayer insulating layer 1891 coplanar.

[0124] Please refer to Figure 20 . Figure 20 This is a schematic cross-sectional view of a stage in a method for manufacturing a storage device. An interlayer insulating layer 191 is formed. A portion of the interlayer insulating layer 191 is in the array region 101, and another portion is in the peripheral region 102. A hole 2001 penetrating the interlayer insulating layer 191 is formed in the array region 101. Holes 2002 and 2003 penetrating the interlayer insulating layer 191, the insulating film 121, and the cover layer 183 are formed in the peripheral region 102. A hole 2004 penetrating the interlayer insulating layer 191 and the insulating film 121 is formed in the peripheral region 102. The number and location of the holes 2001 may correspond to the number and location of the channel posts 450. The holes 2001 expose the upper surface of the channel posts 450 (i.e., the upper surface of the pads 454) and the sidewalls of the interlayer insulating layer 191. Holes 2002 and 2003 may be located on opposite sides of the hole 2004. The number and location of the holes 2004 correspond to the number and location of the semiconductor film 1332. Holes 2002 and 2003 can extend along the first direction D1 to the upper surface of the substrate 100. Holes 2002 and 2003 can expose the substrate 100. Hole 2004 can expose the semiconductor material film 1332A of the semiconductor film 1332.

[0125] A portion of the interlayer insulating layer 1891 can be removed by etching to form vias 2001. A portion of the interlayer insulating layer 1891, a portion of the insulating film 1621A, a portion of the capping layer 1483B, a portion of the dielectric film 6771A, and a portion of the dielectric film 6772A can be removed by etching to form vias 2002 and 2003. A portion of the interlayer insulating layer 1891 and the gate oxide layer 7224B can be removed by etching to form vias 2004. After the etching processes used to form vias 2001 to 2004, the portion of the interlayer insulating layer 1891 that is retained is the interlayer insulating layer 191, the portion of the insulating film 1621A that is retained is the insulating film 121, the portion of the capping layer 1483B that is retained is the capping layer 183, and the portions of the dielectric films 6771A and 6772A that are retained are the dielectric films 1333. The insulating film 121, the diffracted portion 122 and the insulating film 123 can form a stacked structure 120.

[0126] Please refer to Figure 21 . Figure 21This is a schematic cross-sectional view of a stage of a method for manufacturing a memory device. At least one transistor 130 is formed in the peripheral region 102. Channel pillars 150 are formed in the array region 101. Metallic material can be formed in the holes 2001-2004 by deposition, followed by a rapid thermal process (RTP) to react the metallic material (e.g., titanium, tungsten, cobalt, or nickel) with an underlying semiconductor material (e.g., silicon) to form a pad 154 in hole 2001, a source 131 in hole 2002, a drain 132 in hole 2003, and a conductive film 1331 in hole 2004. In this embodiment, the pad 454 reacts with the metallic material to form the pad 154, a portion of the substrate 100 reacts with the metallic material to form the source 131, a portion of the substrate 100 reacts with the metallic material to form the drain 132, and a portion of the semiconductor film 1332 reacts with the metallic material to form the conductive film 1331. The conductive film 1331, the semiconductor film 1332, and the dielectric film 1333 can form the gate 133. The source 131, the drain 132, and the gate 133 can form the transistor 130. The insulating pillar 151, the channel layer 152, the charge storage layer 153, and the pad 154 can form the channel pillar 150.

[0127] In one embodiment, after the pad 154 and transistor 130 are formed, unreacted metal material can be removed by etching. The pad 154, source 131, drain 132, and conductive film 1331 may comprise metal silicides, such as titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, etc. In one embodiment, the pad 154, source 131, drain 132, and conductive film 1331 comprise cobalt silicide.

[0128] Please refer to Figure 22 . Figure 22 This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. An interlayer insulating layer 192 is formed. A portion of the interlayer insulating layer 192 is in the array region 101, and another portion is in the peripheral region 102. A channel contact structure 176 is formed in the array region 101. A source contact structure 171, an isolation element 1711 on the sidewall of the source contact structure 171, a drain contact structure 172, an isolation element 1721 on the sidewall of the drain contact structure 172, a gate contact structure 173, and an isolation element 1731 on the sidewall of the gate contact structure 173 are formed in the peripheral region 102.

[0129] Isolation element 1711 can be formed in via 2002, isolation element 1721 in via 2003, and isolation element 1731 in via 2004 by deposition. Next, interlayer insulating layer 192 can be formed over interlayer insulating layer 191 by deposition. Then, channel contact structure 176 penetrating interlayer insulating layers 191 and 192, source contact structure 171 penetrating interlayer insulating layer 192 and isolation element 1711, drain contact structure 172 penetrating interlayer insulating layer 192 and isolation element 1721, and gate contact structure 173 penetrating interlayer insulating layer 192 and isolation element 1731 can be formed by etching and deposition. Interlayer insulating layer 192 may comprise an insulating material, such as an oxide. In one embodiment, interlayer insulating layer 192 comprises silicon oxide. The channel contact structure 176, source contact structure 171, drain contact structure 172, and gate contact structure 173 may comprise a conductive material, such as a metal. These structures may comprise the same or different materials. In one embodiment, the channel contact structure 176, source contact structure 171, drain contact structure 172, and gate contact structure 173 comprise tungsten. Isolation elements 1711, 1721, and 1731 may comprise an insulating material, such as an oxide. In one embodiment, isolation elements 1711, 1721, and 1731 comprise silicon oxide.

[0130] Please refer to Figure 23 . Figure 23 This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. Conductive contact structures 175 and 174 are formed. A metal winding layer 140 comprising insulating material 142 and multiple conductive lines 141 is formed on an interlayer insulating layer 192. The insulating material 142 electrically isolates the multiple conductive lines 141 from each other. The positions of the conductive lines 141 may correspond to the positions of channel contact structure 176, conductive pillar 178, conductive contact structure 175, conductive contact structure 174, source contact structure 171, drain contact structure 172, and gate contact structure 173 to form electrical connections. The insulating material 142 may comprise an oxide, such as silicon oxide. The conductive lines 141 may comprise a conductive material, such as a metal. In one embodiment, the conductive lines 141 comprise tungsten. The conductive contact structures 175 and 174 can be formed in the array region 101 by etching and deposition processes. After forming conductive contact structures 175 and 174, a metal winding layer 140 can be formed in the array region 101 and the peripheral region 102 by etching and deposition processes. In one embodiment, Figure 22 and Figure 23The steps shown can be performed in the back-end-of-the-line (BEOL) process of semiconductor manufacturing.

[0131] In one embodiment, by performing an exemplary drawing... Figures 4 to 23 The method can yield results such as Figure 1 The storage device 10 shown.

[0132] Figures 24 to 37 This is a structural cross-sectional schematic diagram illustrating multiple stages of a method for manufacturing a storage device according to some embodiments of the present invention. Figures 24 to 37 The steps shown can be performed sequentially or in other orders, and the present invention is not limited thereto. In some embodiments, references can be made. Figures 4 to 9 After the manufacturing steps described above, refer to Figures 24 to 37 The manufacturing steps described above.

[0133] Please refer to Figure 24 . Figure 24 This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. At least one isolation element 970A, a semiconductor layer 7222, a conductive film 2431, and a gate oxide layer 7224 are formed. The semiconductor layer 7222, conductive film 2431, and gate oxide layer 7224 extend on a plane formed by a second direction D2 and a third direction D3, spanning the array region 101 and the peripheral region 102. The semiconductor layer 7222, conductive film 2431, and gate oxide layer 7224 may be disposed on the semiconductor layer 7221A. The semiconductor layer 7222 may be located between the conductive film 2431 and the semiconductor layer 7221A. The conductive film 2431 may be located between the gate oxide layer 7224 and the semiconductor layer 7222. An etch-back process can be used to remove the fill element 7223A and a portion of the upper surface 72AU of the isolation element 970 above the semiconductor layer 7221A; the portion of the isolation element 970 retained is the isolation element 970A. After forming the isolation element 970A, a semiconductor layer 7222, a conductive film 2431, and a gate oxide layer 7224 can be sequentially formed on the semiconductor layer 7221A by a deposition process. The semiconductor layer 7222, the conductive film 2431, and the gate oxide layer 7224 can be conformally formed on the semiconductor layer 7221A. The conductive film 2431 may contain a conductive material, such as a metal silicide. The metal silicide may be, for example, titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, etc. In one embodiment, the conductive film 2431 contains tungsten silicide.

[0134] Please refer to Figure 25 . Figure 25This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. Semiconductor layer 7221B, semiconductor layer 7222A, conductive film 2431A, and gate oxide layer 7224A are formed. The upper surfaces of semiconductor layer 7221B, semiconductor layer 7222A, conductive film 2431A, gate oxide layer 7224A, and the upper surface of the layer stack 410A are coplanar. The portion of semiconductor layer 7221A above the upper surface of layer stack 410A, the portion of semiconductor layer 7222 above the upper surface of layer stack 410A, the portion of conductive film 2431 above the upper surface of layer stack 410A, and the portion of gate oxide layer 7224 above the upper surface of layer stack 410A can be removed by etching. The portion of semiconductor layer 7221A that is retained is semiconductor layer 7221B, the portion of semiconductor layer 7222 that is retained is semiconductor layer 7222A, the portion of conductive film 2431 that is retained is conductive film 2431A, and the portion of gate oxide layer 7224 that is retained is gate oxide layer 7224A.

[0135] Please refer to Figure 26 . Figure 26 This is a schematic cross-sectional view of a stage of a method for manufacturing a memory device. In the peripheral region 102, an extension 122 comprising semiconductor layers 1221 and 1222, a conductive portion 324, an insulating film 123, a semiconductor film 1332 comprising semiconductor material films 1332A and 1332B, a conductive film 3331, a gate oxide layer 7224B, and a shallow trench isolation 170 are formed. At least one aperture 2601 is formed in the peripheral region 102. A plurality of apertures 2601 may be arranged separately from each other. One of the plurality of apertures 2601 may expose the upper surface of the dielectric film 177, the upper surface of the shallow trench isolation 170, the upper surface of the dielectric film 6771A, the sidewall of the extension 122, the sidewall of the conductive portion 324, the sidewall of the insulating film 123, the sidewall of the semiconductor film 1332, the sidewall of the conductive film 3331, and the sidewall of the gate oxide layer 7224B. One of the plurality of holes 2601 may expose the upper surface of the dielectric film 6771A, the upper surface of the shallow trench isolation 170, the upper surface of the dielectric film 6772A, the sidewall of the semiconductor film 1332, the sidewall of the conductive film 3331, and the sidewall of the gate oxide layer 7224B. The upper surfaces of the shallow trench isolation 170, the dielectric film 177, the dielectric film 6771A, and the dielectric film 6772A may be coplanar. The semiconductor layer 1222 in the deflection portion 122 may be disposed between the semiconductor layer 1221 and the conductive portion 324. The conductive portion 324 may be disposed between the semiconductor layer 1222 and the insulating film 123. The deflection portion 122 may be disposed at the boundary of the peripheral region 102, or the deflection portion 122 may serve as the boundary between the array region 101 and the peripheral region 102.

[0136] A portion of the isolation element 970A, a portion of the semiconductor layer 7221B, a portion of the semiconductor layer 7222A, a portion of the conductive film 2431A, and a portion of the gate oxide layer 7224A can be removed by etching, thereby forming a hole 2601. The portion of the isolation element 970A that is retained is the shallow trench isolation 170. The portion of the semiconductor layer 7221B that is retained can be divided into semiconductor layer 1221 and semiconductor material film 1332B. The portion of the semiconductor layer 7222A that is retained can be divided into semiconductor layer 1222 and semiconductor material film 1332A. The portion of the conductive film 2431A that is retained can be divided into conductive portion 324 and conductive film 3331. The portion of the gate oxide layer 7224A that is retained can be divided into insulating film 123 and gate oxide layer 7224B. The hole 2601 separates the semiconductor layer 1221 and the semiconductor material film 1332B from each other. The hole 2601 also separates the semiconductor layer 1222 and the semiconductor material film 1332A from each other. Hole 2601 allows the conductive portion 324 to be separated from the conductive film 3331. Hole 2601 also allows the insulating film 123 to be separated from the gate oxide layer 7224B.

[0137] Please refer to Figure 27 . Figure 27 This is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a storage device. A plurality of spacer elements 181 and at least one spacer element 182 are formed in the peripheral region 102. The spacer elements 181 and 182 are located in the aperture 2601. Figure 27 Spacer element 181 and spacer element 182 are illustrated as having arc-shaped sidewalls 181S and 182S, respectively, but the present invention is not limited thereto. Spacer element 181 may be adjacent to the sidewalls of semiconductor film 1332, conductive film 3331, and gate oxide layer 7224B. Spacer element 182 may be adjacent to the sidewalls of diffracted portion 122, conductive portion 324, and insulating film 123. An insulating material (i.e., the material of spacer element 181 and spacer element 182) may be formed in the hole 2601 by a deposition process, and the insulating material may fill the hole 2601; then, a portion of the insulating material may be removed by an etching process, and the portion of the insulating material remaining may be divided into spacer element 181 and spacer element 182.

[0138] In one embodiment, after forming spacer element 181 and spacer element 182, the spacer element 181 can be... Figure 27 The surface of the structure shown (e.g.) Figure 27 The surface indicated by the dashed line is used for ion implantation to introduce N-type or P-type dopants into the surface. Figure 27 The surface of the structure shown. Ion implantation can be performed simultaneously on the structure located in array region 101 and the structure located in peripheral region 102.

[0139] Please refer to Figure 28 . Figure 28 This is a structural cross-sectional schematic diagram of one stage of a method for manufacturing a memory device. A capping layer 1483 is formed. The capping layer 1483 may cover the upper surface of the layer stack 410A, the upper surface of the semiconductor layer 1221, the upper surface of the semiconductor layer 1222, the upper surface of the conductive portion 324, the upper surface of the insulating film 123, the sidewall 182S of the spacer element 182, the upper surface of the dielectric film 177, the upper surface of the shallow trench isolation 170, the upper surface of the dielectric film 6771A, the sidewall 181S of the spacer element 181, the upper surface of the gate oxide layer 7224B, and the upper surface of the dielectric film 6772A. A capping layer 1483 can be conformally formed on the layer stack 410A, the diffracted portion 122, the conductive portion 324, the insulating film 123, the spacer element 182, the dielectric film 177, the shallow trench isolation 170, the dielectric film 6771A, the spacer element 181, and the gate oxide layer 7224B by deposition.

[0140] Please refer to Figures 29 to 33 . Figures 29 to 33 This is a schematic cross-sectional view of the structure of a method for manufacturing a storage device, showing multiple stages. Holes 1501 are formed in the array region 101. Figure 29 An insulating layer 1616 is formed in the array region 101; an insulating film 1621 is formed in the peripheral region 102. Figure 30 An insulating film 1621A, a cover layer 1483B, and an insulating layer 116 are formed. Figure 31 In other embodiments, Figure 31 The steps shown are optional. Forming an interlayer insulating layer 1891 and a hole 1801 penetrating the interlayer insulating layer 1891 ( Figure 32 In array region 101, a stacked structure 110 is formed comprising an insulating layer 111, a conductive layer 112, an insulating layer 113, a conductive layer 114, an insulating layer 115, an insulating layer 116, and a barrier layer 117; a conductive pillar 178 penetrating the stacked structure 110; and an isolation element 1781 disposed between the conductive pillar 178 and the barrier layer 117. Figure 33 ).

[0141] In one embodiment, Figures 29 to 33 The structure shown can be used as a reference. Figures 15 to 19 The manufacturing methods and materials used to form it are described, and will not be repeated here.

[0142] Please refer to Figure 34 . Figure 34This is a schematic cross-sectional view of a stage in a method for manufacturing a storage device. An interlayer insulating layer 191 is formed. A portion of the interlayer insulating layer 191 is in the array region 101, and another portion is in the peripheral region 102. A hole 3401 penetrating the interlayer insulating layer 191 is formed in the array region 101. Holes 3402 and 3403 penetrating the interlayer insulating layer 191, the insulating film 121, and the cover layer 183 are formed in the peripheral region 102. A hole 3404 penetrating the interlayer insulating layer 191 and the insulating film 121 is formed in the peripheral region 102. The number and location of the holes 3401 correspond to the number and location of the channel posts 450. The holes 3401 expose the upper surface of the channel posts 450 (i.e., the upper surface of the pads 454) and the sidewalls of the interlayer insulating layer 191. Holes 3402 and 3403 can be located on opposite sides of the hole 3404. The number and location of the holes 3404 correspond to the number and location of the semiconductor film 1332. The holes 3402 and 3403 can extend along the first direction D1 to the upper surface of the substrate 100. The holes 3402 and 3403 can expose the substrate 100. The hole 3404 can expose the conductive film 3331.

[0143] A portion of the interlayer insulating layer 1891 can be removed by etching to form vias 3401. A portion of the interlayer insulating layer 1891, a portion of the insulating film 1621A, a portion of the capping layer 1483B, a portion of the dielectric film 6771A, and a portion of the dielectric film 6772A can be removed by etching to form vias 3402 and 3403. A portion of the interlayer insulating layer 1891 and the gate oxide layer 7224B can be removed by etching to form vias 3404. After etching to form vias 3401 to 3404, the portion of the interlayer insulating layer 1891 retained is the interlayer insulating layer 191, the portion of the insulating film 1621A retained is the insulating film 121, the portion of the capping layer 1483B retained is the capping layer 183, and the portions of the dielectric films 6771A and 6772A retained are the dielectric films 1333. The insulating film 121, the diffracted portion 122, the insulating film 123 and the conductive portion 324 can form a stacked structure 320.

[0144] Please refer to Figure 35 . Figure 35This is a schematic cross-sectional view of a stage of a method for manufacturing a memory device. At least one transistor 330 is formed in the peripheral region 102. Channel pillars 150 are formed in the array region 101. In one embodiment, a metallic material is formed in holes 3401-3403 by deposition, followed by rapid thermal processing to react the metallic material (e.g., titanium, tungsten, cobalt, or nickel) with an underlying semiconductor material (e.g., silicon) to form a pad 154 in hole 3401, a source 131 in hole 3402, and a drain 132 in hole 3403. In this embodiment, a pad 454 reacts with the metallic material to form a pad 154, a portion of the substrate 100 reacts with the metallic material to form a source 131, and a portion of the substrate 100 reacts with the metallic material to form a drain 132. In another embodiment, an ion implantation process can be performed to introduce N-type or P-type dopant into the surfaces exposed by holes 3401-3403 to form a pad 154 in hole 3401, a source 131 in hole 3402, and a drain 132 in hole 3403. A conductive film 3331, a semiconductor film 1332, and a dielectric film 1333 can form a gate 333. The source 131, drain 132, and gate 333 can form a transistor 330. An insulating pillar 151, a channel layer 152, a charge storage layer 153, and a pad 154 can form a channel pillar 150. In one embodiment, after forming the pad 154 and the transistor 330, unreacted metal material can be removed by etching.

[0145] Please refer to Figure 36 . Figure 36This is a schematic cross-sectional view of a stage in a method for manufacturing a memory device. An interlayer insulating layer 192 is formed. A portion of the interlayer insulating layer 192 is in the array region 101, and another portion is in the peripheral region 102. A channel contact structure 176 is formed in the array region 101. A source contact structure 171, an isolation element 1711 on the sidewall of the source contact structure 171, a drain contact structure 172, an isolation element 1721 on the sidewall of the drain contact structure 172, a gate contact structure 173, and an isolation element 1731 on the sidewall of the gate contact structure 173 are formed in the peripheral region 102. Isolation element 1711 is formed in via 3402, isolation element 1721 is formed in via 3403, and isolation element 1731 is formed in via 3404 by a deposition process. Next, an interlayer insulating layer 192 is formed over the interlayer insulating layer 191 by a deposition process. Next, etching and deposition processes can be used to form a channel contact structure 176 that penetrates the interlayer insulating layers 191 and 192, a source contact structure 171 that penetrates the interlayer insulating layer 192 and the isolation element 1711, a drain contact structure 172 that penetrates the interlayer insulating layer 192 and the isolation element 1721, and a gate contact structure 173 that penetrates the interlayer insulating layer 192 and the isolation element 1731.

[0146] Please refer to Figure 37 . Figure 37 This is a structural cross-sectional schematic diagram of a stage in a method for manufacturing a storage device. Conductive contact structures 175 and 174 are formed. A metal winding layer 140 comprising insulating material 142 and multiple conductive wires 141 is formed on the interlayer insulating layer 192. Conductive contact structures 175 and 174 can be formed in the array region 101 by etching and deposition processes. After forming the conductive contact structures 175 and 174, the metal winding layer 140 can be formed in the array region 101 and the peripheral region 102 by etching and deposition processes. In one embodiment, Figure 36 and Figure 37 The steps shown can be performed in the back-end processes of semiconductor manufacturing.

[0147] In one embodiment, by performing an exemplary drawing... Figures 24 to 37 The method can yield results such as Figure 3 The storage device 20 shown.

[0148] Known methods for manufacturing memory devices employing a peripheral circuit adjacent array (CNA) architecture or a CMOS underarray (CUA) architecture involve forming the peripheral circuitry first, followed by the memory array. However, the high-temperature processing steps used to form the memory array can adversely affect the peripheral circuitry, reducing its performance. The present invention's method for manufacturing memory devices alternates between the memory array manufacturing steps and the peripheral circuitry manufacturing steps, avoiding or reducing the adverse effects of high-temperature processing steps on the peripheral circuitry, thereby improving the performance of the memory device and providing a wider process window. Furthermore, the present invention's method performs an ion implantation process (to form the transistor gate) after forming the channel layer and charge storage layer, avoiding or reducing the adverse effects of the high-temperature processing steps used to form the channel layer and charge storage layer on the state of the ion implantation region. Therefore, the present invention avoids the peripheral circuitry limiting the thermal budget during memory array manufacturing, improves the thermal budget during memory array manufacturing, and increases the crystallinity of the channel layer (due to the improved thermal budget), thereby improving the carrier mobility of the memory device. Furthermore, in order to accommodate the high-temperature processing steps used to form the memory array, known methods of manufacturing memory devices require the use of high-temperature resistant materials (typically with high resistance) to form transistors, rather than using materials that are not heat resistant (typically with low resistance). The memory device and its manufacturing method of the present invention can use materials with lower resistance (e.g., titanium silicide, tungsten silicide, cobalt silicide, and nickel silicide) as the source and / or drain and / or gate of the transistors, which can improve contact resistance, improve gate resistance, improve device performance, and improve thermal budget.

[0149] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A storage device comprising: The substrate includes an array region and a peripheral region; A first stacked structure is located in the array region. The first stacked structure includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer. The first conductive layer, the insulating layer, and the second conductive layer are stacked along a first direction. A second stacked structure is located in the peripheral area; At least one transistor is located in the second stacked structure, the at least one transistor having a conductive film, a dielectric film and a semiconductor film stacked along the first direction; as well as A metal winding layer is located above the first stacked structure and the second stacked structure. The metal winding layer is electrically connected to the at least one transistor, the first conductive layer, and the second conductive layer.

2. The storage device of claim 1, further comprising at least one channel post and a plurality of storage cells, the at least one channel post extending along a second direction opposite to the first direction and penetrating the first stacked structure, the first conductive layer being closer to the substrate than the second conductive layer, and the plurality of storage cells being located between the second conductive layer and the at least one channel post.

3. The storage device according to claim 2, further comprising a source contact structure and a drain contact structure, wherein the at least one transistor has a source, a drain, and a gate, the gate being formed by the conductive film, the dielectric film, and the semiconductor film, the source and the drain being located in a substrate, the source contact structure and the drain contact structure extending along the second direction to the surface of the substrate, and the height of the source contact structure from the substrate and the height of the drain contact structure from the substrate being greater than the height of the at least one channel post from the substrate.

4. The storage device of claim 2, further comprising a conductive post that penetrates the first stacked structure and extends along the second direction to the surface of the substrate, the conductive post being electrically connected to the substrate.

5. The storage device according to claim 4, further comprising a source contact structure and a drain contact structure, wherein the at least one transistor has a source, a drain and a gate, the gate being formed by the conductive film, the dielectric film and the semiconductor film, the source and the drain being located in the substrate, and the height of the source contact structure from the substrate and the height of the drain contact structure from the substrate being greater than the height of the conductive post from the substrate.

6. The storage device according to claim 1, further comprising a first conductive contact structure and a second conductive contact structure, the first conductive contact structure being above the first conductive layer and electrically connected to the first conductive layer, the second conductive contact structure being above the second conductive layer and electrically connected to the second conductive layer, and the first conductive contact structure and the second conductive contact structure being electrically connected to the metal winding layer.

7. The storage device of claim 1, wherein the second stacked structure includes a diffraction adjacent to one end of the first conductive layer, the diffraction including a plurality of semiconductor layers stacked along the first direction and in a direction perpendicular to the first direction.

8. The storage device of claim 7, further comprising at least one first spacer element in the second stacked structure, wherein the at least one first spacer element is located on the sidewalls of the conductive film and the semiconductor film of the at least one transistor.

9. The storage device of claim 8, further comprising a second spacer element in the second stacked structure, wherein the second spacer element is located at one end of the diffracted portion away from the first conductive layer.

10. A method for manufacturing a storage device, comprising: Provides a substrate comprising an array region and a peripheral region; A layer stack is formed in the array region, the layer stack comprising a semiconductor material layer, a dielectric layer, and an insulating layer between the semiconductor material layer and the dielectric layer; Forming channel pillars that penetrate the stacked layers; A diffracted portion is formed adjacent to the stacked layers, wherein the diffracted portion comprises a plurality of semiconductor layers stacked and extending along a first direction and a second direction, the first direction being perpendicular to the second direction; as well as At least one transistor is formed in the peripheral region, the at least one transistor comprising stacked conductive films, dielectric films and semiconductor films.

Images