Semiconductor device and data storage system including the same

Abstract

A semiconductor device includes a substrate including a first region, a second region, and a third region; a stack structure including a gate electrode and an interlayer insulating layer, the gate electrode including a lower gate electrode, a memory gate electrode, and an upper gate electrode; first contact structures, in the third region, extending different lengths in a first direction by penetrating an uppermost interlayer insulating layer among the interlayer insulating layer or at least a portion of the upper gate electrode, and electrically connected to the upper gate electrode, respectively, wherein each of the first contact structures includes a through insulating structure extending and penetrating at least a portion of the upper gate electrode and in contact with an upper surface of the assigned upper gate electrode; and a first pillar penetrating the through insulating structure and in electrical contact with the upper surface of the assigned upper gate electrode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0043038, filed on April 2, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments of this disclosure relate to a semiconductor device and a data storage system including the thereof. Background Technology

[0004] There is a need for semiconductor devices capable of storing high-capacity data in data storage systems. Therefore, methods for increasing the data storage capacity of semiconductor devices have been investigated. For example, as a method for increasing the data storage capacity of semiconductor devices, semiconductor devices comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0005] The exemplary embodiments of this disclosure provide a semiconductor device with improved integration density, which can simplify its manufacturing process.

[0006] An exemplary embodiment of this disclosure provides a data storage system that includes a semiconductor device with improved integration density, which can simplify its manufacturing process.

[0007] In an exemplary embodiment of this disclosure, a semiconductor device includes: a substrate including a first region, a second region, and a third region between the first and second regions; a stacked structure including a gate electrode and an interlayer insulating layer, the gate electrode including a lower gate electrode, a memory gate electrode, and an upper gate electrode sequentially stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the substrate, the interlayer insulating layer being alternately disposed with the gate electrode in the first, second, and third regions; a channel structure penetrating the stacked structure and extending along the first direction in the first region; a support structure penetrating the stacked structure and extending along the first direction in the third region; a first contact structure in the third region extending for different lengths along the first direction by penetrating the uppermost interlayer insulating layer or penetrating at least a portion of the upper gate electrode, and being electrically connected to the upper gate electrode respectively; and a second contact structure in the second region extending for different lengths along the first direction from the uppermost interlayer insulating layer by penetrating the upper gate electrode and at least a portion of the memory gate electrode and the lower gate electrode, and being electrically connected to the lower gate electrode and the memory gate electrode respectively. Each of the first contact structures includes: a through-insulation structure extending in a first direction and penetrating the uppermost interlayer insulation layer or penetrating at least a portion of the upper gate electrode and contacting the upper surface of a distributed upper gate electrode in the upper gate electrode; and a first pillar extending in the first direction by penetrating the through-insulation structure and contacting the upper surface of the distributed upper gate electrode, and a portion of the support structure contacting at least a portion of the through-insulation structure.

[0008] In an exemplary embodiment of this disclosure, a semiconductor device includes: a substrate including a first region, a second region, and a third region between the first and second regions; a stacked structure including a gate electrode and an interlayer insulating layer, the gate electrode including a lower gate electrode, a memory gate electrode, and an upper gate electrode sequentially stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the substrate, the interlayer insulating layer being alternately arranged with the gate electrode in the first, second, and third regions; a channel structure penetrating the stacked structure and extending along the first direction in the first region; and a support structure penetrating the stacked structure and extending along the first direction in the third region. And spaced apart by a first distance; a first contact structure, in the third region, extends along the first direction by different lengths through penetrating the uppermost interlayer insulating layer or penetrating at least a portion of the upper gate electrode, and is electrically connected to the upper gate electrode respectively, and has an upper surface having a first width; and a second contact structure, in the second region, extends along the first direction from the uppermost interlayer insulating layer by different lengths through penetrating the upper gate electrode and at least a portion of the gate electrodes of the memory gate electrode and the lower gate electrode, and is electrically connected to the lower gate electrode and the memory gate electrode respectively, wherein the first width of the first contact structure is greater than the first distance.

[0009] In an exemplary embodiment of this disclosure, a data storage system includes: a semiconductor storage device including a first semiconductor structure containing circuitry, a second semiconductor structure disposed on a surface of the first semiconductor structure, and input / output pads electrically connected to the circuitry; and a controller electrically connected to the semiconductor storage device via the input / output pads and controlling the semiconductor storage device. The second semiconductor structure includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a stacked structure including a gate electrode and an interlayer insulating layer, the gate electrode including a lower gate electrode, a memory gate electrode, and an upper gate electrode sequentially stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the substrate, the interlayer insulating layer being alternately arranged with the gate electrode in the first region, the second region, and the third region; a channel structure penetrating the stacked structure and extending in the first region along the first direction; a support structure penetrating the stacked structure in the third region, extending in the first direction, and spaced apart from each other by a first distance; a first contact structure in the third region extending for different lengths in the first direction by penetrating the uppermost interlayer insulating layer or penetrating at least a portion of the upper gate electrode, electrically connected to the upper gate electrode respectively, and having an upper surface having a first width; and a second contact structure in the second region extending for different lengths in the first direction from the uppermost interlayer insulating layer by penetrating the upper gate electrode and at least a portion of the memory gate electrode and the lower gate electrode respectively, and electrically connected to the lower gate electrode and the memory gate electrode respectively, wherein the first width of the first contact structure is greater than the first distance.

[0010] In an exemplary embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a molded structure by alternately stacking a sacrificial insulating layer and an interlayer insulating layer on a substrate along a first direction perpendicular to the upper surface of the substrate, the molded structure including a first region, a second region, and a third region between the first and second regions; forming a first contact hole of a different depth in the third region by removing the uppermost interlayer insulating layer along the first direction or by removing at least a portion of the upper sacrificial insulating layer of the sacrificial insulating layer; forming a through-insulation structure burying the first contact hole; forming a vertical sacrificial structure that cuts at least a portion of the through-insulation structure; removing the vertical sacrificial structure and forming a support structure; forming a gate electrode by removing the sacrificial insulating layer, the gate electrode including a lower gate electrode, a memory gate electrode, and an upper gate electrode that are sequentially stacked and spaced apart from each other along the first direction; and forming a first pillar that penetrates the through-insulation structure and contacts one of the assigned upper gate electrodes.

[0011] The through-insulation structure may include: an upper surface; a lower surface in contact with the assigned upper gate electrode; an inner surface in contact with the first pillar between the upper and lower surfaces; and an outer surface in contact with the interlayer insulation layer and / or the upper gate electrode, wherein the side surface of each first pillar may be physically spaced apart from the interlayer insulation layer and the upper gate electrode.

[0012] Forming the first post may include making the center of the upper surface of the first post and the center of the upper surface of the through-insulation structure coaxial with each other.

[0013] Forming the first contact hole may include performing at least one photolithography process according to the level of the assigned upper gate electrode.

[0014] Forming a support structure may include: forming a channel structure in a first region; and forming a dummy channel structure with the same shape as the channel structure in a third region as a support structure.

[0015] Forming the first contact hole may include etching to expose the upper surface of the sacrificial insulating layer dispensed from the upper surface of the molded structure.

[0016] The method may further include forming an upper insulating layer on the stacked structure.

[0017] The first column can be formed to penetrate the upper insulation layer and run through the insulation structure together.

[0018] The width of the upper surface of the first column can be less than 1 / 3 to 1 / 4 of the width of the through insulation structure.

[0019] Forming a first contact hole may include forming a first contact hole having a first distance, such that a molded structure can be arranged between the first contact holes.

[0020] Forming a support structure may include forming a support structure such that half or less of the circumference of the upper surface can protrude into the through-insulation structure. Attached Figure Description

[0021] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 This is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0023] Figure 2A and Figure 2B This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0024] Figure 3A , Figure 3B and Figure 3C It is shown Figure 2A and Figure 2B Enlarged view of a portion of the image;

[0025] Figure 4 and Figure 5 This is an enlarged cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0026] Figure 6 and Figure 7 This is a diagram showing a semiconductor device according to an exemplary embodiment of the present disclosure, viewed from above;

[0027] Figure 8 It is shown Figure 7 The diagram shows a cross-sectional view of the semiconductor device.

[0028] Figure 9 This is a diagram showing a semiconductor device according to an exemplary embodiment of the present disclosure, viewed from above;

[0029] Figure 10 , Figure 11 and Figure 12 This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0030] Figures 13A to 13I and Figures 14A to 14D This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0031] Figure 15 This is a diagram illustrating a data storage system including a semiconductor device in an example embodiment of the present disclosure; and

[0032] Figure 16 This is a perspective view illustrating a data storage system of a semiconductor device including an example embodiment of the present disclosure. Detailed Implementation

[0033] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0034] In the following text, reference will be made to Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C A semiconductor device according to an example embodiment is described.

[0035] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 2A and Figure 2B This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 2A The diagram shows the section cut along line I-I'. Figure 1A cross-sectional view of the region of the semiconductor device, and Figure 2B It is the section shown in the diagram along line II-II'. Figure 1 A cross-sectional view of the semiconductor device region. Figure 3A It is shown Figure 2A A magnified view of region "A" in the image. Figure 3B It is shown Figure 2A An enlarged view of region "B" in the image, and Figure 3C It is shown Figure 2B An enlarged view of region "C" in the image.

[0036] refer to Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 may include a storage region R1 and an extension region R2 extending along the X direction to one side of the storage region R1.

[0037] Storage region R1 may be a storage cell region in which a string of storage cells is arranged, and the channel structure CH may be arranged in storage region R1. Extended region R2 may correspond to the region where the channel structure CH is electrically connected to the peripheral circuit structure. For this purpose, a plurality of word line contact structures MC2 may be arranged in extended region R2, and the plurality of word line contact structures MC2 are connected to the gate electrode 130 at different levels. However, the example embodiment is not limited to this configuration.

[0038] The upper contact region R3 can be arranged between the storage region R1 and the extension region R2. An upper contact structure MC1 connected to the upper gate electrode 130U can be arranged in the upper contact region R3. The upper contact region R3 can be defined as the area in which the upper contact structure MC1 for connecting the erase gate electrodes 130U7-130U5 to the series select line, i.e., the series select gate electrodes 130U4-130U1, is arranged.

[0039] More specifically, the upper contact region R3 may be adjacent to the storage region R1, and the upper contact structure MC1 connecting the erase gate electrodes 130U7-130U5 and the string select gate electrodes 130U4-130U1 may be arranged in the upper contact region R3. In this region, the upper gate electrode 130U may not form a stepped structure. Instead, the upper gate electrode 130U may extend flatly from the storage region R1 to the extension region R2, passing through the upper contact region R3.

[0040] In the upper contact region R3, only the contact area of ​​the upper gate electrode 130U connected to the upper contact structure MC1 can be exposed in the through insulation structure 165. In the contact area, the upper gate electrode 130U can make direct physical and electrical contact with the first post 180a of the upper contact structure MC1, respectively.

[0041] The semiconductor device 100 may have a structure in which the storage region R1, the upper contact region R3, and the extended region R2 are continuously arranged along the X direction.

[0042] The semiconductor device 100 may include: a semiconductor substrate 101 extending through a storage region R1, an upper contact region R3, and an extension region R2; a stacked structure (GS1-GSk, where k is a positive integer) including gate electrodes 130 and interlayer insulating layers 120 alternately stacked on the upper surface of the substrate 101; a channel structure CH penetrating the stacked structure GS1-GSk in the storage region R1; an isolation region MS extending along the X direction and penetrating the stacked structure GS1-GSk; and insulating regions SS1 and SS2 penetrating at least a portion of the gate electrode 130. Interconnect structures and passivation layers may further be included beneath the substrate 101.

[0043] The support structure SH and the word line contact structure MC2 can be arranged in the extended region R2.

[0044] The virtual channel structure DCH and the upper contact structure MC1 can be arranged in the upper contact region R3, between the storage region R1 and the extension region R2.

[0045] exist Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C In this embodiment, contact structures MC1 and MC2 may have different lengths to establish an electrical connection between the gate electrode 130 and the corresponding contact structures MC1 and MC2, but the example embodiment is not limited to these configurations.

[0046] Storage regions R1 to extension regions R2 can penetrate the upper insulating layer 194, which forms the upper part of the stacked structure GS. The upper insulating layer 194 may include a second post 180b and a third post 180c for electrical connection with the channel structure CH and the word line contact structure MC2, respectively, as well as cell interconnects 185 formed on the upper insulating layer 194.

[0047] Substrate 101 may include at least one of a conductive material such as doped silicon or a conductive material such as a metal (or metal nitride) to serve as a common source line. For example, substrate 101 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. Substrate 101 may be provided as a bulk wafer or an epitaxial layer.

[0048] The semiconductor device 100 may further include a first horizontal conductive layer 102 and a second horizontal conductive layer 104, a horizontal insulating layer 110 and a substrate insulating layer.

[0049] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be sequentially stacked on the upper surface of the substrate 101 in the storage region R1. The first horizontal conductive layer 102 and the second horizontal conductive layer 104, together with the substrate 101, can form a common source structure CS and can be used as a common source line of the semiconductor device 100. Figure 3A As shown, the first horizontal conductive layer 102 can be directly connected to the channel layer 140 in the lower part of the channel structure CH. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can include semiconductor materials, such as polysilicon. In this case, at least the first horizontal conductive layer 102 can be doped with impurities of the same conductivity type as the substrate 101.

[0050] A horizontal insulating layer 110 may be disposed on the substrate 101 in at least a portion of the upper contact region R3 and the extended region R2, at the same level as the first horizontal conductive layer 102. The horizontal insulating layer 110 may include a first horizontal insulating layer and a second horizontal insulating layer alternately stacked on the substrate 101. The horizontal insulating layer 110 may be a layer remaining after a portion of the first horizontal conductive layer 102 has been replaced during the process of manufacturing the semiconductor device 100. The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon nitride. The first horizontal insulating layer and the second horizontal insulating layer may include different insulating materials.

[0051] The substrate insulating layer may be arranged to cover the curved portion of the second horizontal conductive layer 104 located between the storage region R1 and the upper contact region R3. In some example embodiments, the substrate insulating layer may penetrate the substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 as the through electrode extends from the first semiconductor structure S1 to the second semiconductor structure S2. The through electrode may further penetrate the substrate insulating layer.

[0052] The gate electrodes 130 may be perpendicularly spaced from each other on the upper surface of the substrate 101 and may be included together with the interlayer insulating layer 120 in the stacked structure GS (GS1-GS3).

[0053] In the entire stacked structure GS, the gate electrode 130 may include at least one lower gate electrode 130L forming the gate of a ground select transistor; a plurality of memory gate electrodes 130M forming a plurality of memory cells; and a plurality of upper gate electrodes 130U serving as string select lines forming the gates of string select transistors. Here, the lower gate electrode 130L and the upper gate electrode 130U may be referred to as “lower” and “upper” based on the direction during the manufacturing process. The number of memory gate electrodes 130M forming memory cells may be determined depending on the capacity of the semiconductor device 100. In an example embodiment, one or two (or more) upper gate electrodes 130U and lower gate electrodes 130L may be included, having the same or different structures as the memory gate electrodes 130M. In an example embodiment, the upper gate electrode 130U may include seven electrodes: three erase gate electrodes 130U7-130U5 arranged in descending order and four string select gate electrodes 130U4-130U1. A portion of the gate electrode 130, such as the memory gate electrode 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L, may be a dummy gate electrode 130, but its exemplary embodiments are not limited thereto.

[0054] The gate electrode 130 may extend from the extension region R2 to the storage region R1 on one side, and may be stacked such that each gate electrode 130 has a flat upper surface parallel to the upper surface of the substrate 101, without forming a staircase or step structure. Accordingly, the area of ​​each gate electrode 130 may be substantially uniform.

[0055] The stacked structure GS can include multiple layers of stacked structures GS1-GS3 stacked along the Z direction. Figure 2A and Figure 2B The diagram illustrates three stacked structures GS1, GS2, and GS3, but the example embodiment is not limited to this. Other embodiments may include a stacked structure GS with four to eight levels, or in some cases, only two levels. Each level of the stacked structure GS can be classified by the height required to form a channel via with a predetermined depth, corresponding to the channel portions CH1, CH2, and CH3 of the channel structure CH. The lower stacked structure positioned on the upper surface of the substrate 101 may be referred to as the first stacked structure GS1, and the stacked structures GS2-GS3 on the first stacked structure GS1 may be referred to as the second stacked structure GS2 and the third stacked structure GS3, respectively.

[0056] In the stacked structures GS1-GS3, the gate electrode 130 and the interlayer insulating layer 120 can be stacked alternately along the Z direction. The height (i.e., the length in the Z direction) and the number of gate electrodes 130 in each of the stacked structures GS1-GS3 can be substantially the same; however, the example embodiments are not limited thereto.

[0057] refer to Figure 1 , Figure 2A and Figure 2B The gate electrodes 130 can be isolated from each other in the Y direction by isolation regions MS that extend continuously from the storage region R1 to the extension region R2. The gate electrodes 130 located between a pair of isolation regions MS can be included in a single memory block BLK, but the scope of the memory block BLK is not limited thereto. A portion of the gate electrodes 130 (such as memory gate electrode 130M) can be grouped into a layer within the same memory block BLK.

[0058] The gate electrodes 130 can be stacked vertically and spaced apart from each other along the Z direction across the storage region R1, the upper contact region R3, and the extension region R2, and can maintain a continuous plate shape without forming a stepped or stair-like configuration in the upper contact region R3 or the extension region R2. Therefore, a portion of each gate electrode 130 can be defined as a contact region for the first pillar 180a via the upper contact structure MC1 in the upper contact region R3, and a contact region defined as a contact region for the word line contact structure MC2 in the extension region R2.

[0059] The gate electrode 130 may include a conductive material layer. For example, the conductive material layer may be formed of tungsten (W), ruthenium (Ru), molybdenum (Mo), niobium (Nb), nickel (Ni), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), niobium nitride (NbN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium silicide (TiSi), titanium silicide nitride (TiSiN), tantalum silicide (TaSi), tantalum silicide nitride (TaSiN), ruthenium titanium nitride (RuTiN), nickel silicide (NiSi), cobalt silicide (CoSi), or combinations thereof, but exemplary embodiments are not limited thereto. According to an exemplary embodiment, the gate electrode 130 may also include a diffusion barrier 131, which may include, for example, WN, TaN, TiN, or combinations thereof.

[0060] Interlayer insulating layers 120 may be disposed between gate electrodes 130 and may be included in a stacked structure GS. Similar to gate electrodes 130, interlayer insulating layers 120 may be arranged to be spaced apart from each other in the Z direction perpendicular to the upper surface of substrate 101 and extend in the X direction. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide or silicon nitride.

[0061] In the example embodiments, the interlayer insulating layers 120 may have substantially the same thickness, but variations are possible. For example, the uppermost interlayer insulating layer 121 of the interlayer insulating layers 120 may have a thickness greater than the thickness of the other interlayer insulating layers 120, but the example embodiments are not limited thereto. In the above description, the semiconductor device 100 may be described as including a memory region R1, an upper contact region R3, and an extension region R2, but the stacked structure GS may include a memory region R1, an upper contact region R3, and an extension region R2.

[0062] The isolation region MS can penetrate at least a portion of the gate electrode 130 and can extend along the X direction. The isolation region MS can continuously span the memory region R1, the upper contact region R3, and the extension region R2, and can be arranged parallel to each other in the X direction. The isolation region MS can penetrate the entire stacked gate electrode 130 and can be connected to the substrate 101. The isolation region MS can extend along the X direction as an integration region, or can extend intermittently in a portion, or can be arranged only in a portion of the region. The isolation region MS can be linear in the XY plane, or can have a shape in which the side surfaces can have continuous curves and can extend along the X direction.

[0063] An insulating layer may be disposed in the isolation region MS. Due to the high aspect ratio, the insulating layer may have a shape in which the width decreases toward the substrate 101, but exemplary embodiments thereof are not limited thereto. The upper surface of the insulating layer may contact the upper insulating layer 194, and the lower surface may contact the upper surface of the substrate 101.

[0064] Insulating regions SS1 and SS2 can extend along the X direction between adjacent isolation regions MS. Insulating regions SS1 and SS2 can selectively penetrate only the upper gate electrodes 130U1-130U7, i.e., erase gate electrodes 130U7-130U5, and series select lines 130U4-130U1, and can divide the upper gate electrode 130U into multiple sub-regions within the stacked structure GS.

[0065] Reference Figure 1 The first insulating region SS1 can extend along the X direction across both the storage region R1 and the upper contact region R3. The first insulating regions SS1 can be parallel to each other between the isolation regions MS and can be spaced apart from each other along the Y direction. The second insulating region SS2 can be arranged between the upper contact region R3 and the extended region R2 and can extend along the Y direction. The upper gate electrode 130U can be divided into multiple sub-regions by the first insulating region SS1, the isolation regions MS, and the second insulating region SS2, and the channel structure CH of the corresponding sub-region can be selected only according to the voltage level of the upper gate electrode 130U in the corresponding sub-region.

[0066] The first insulating region SS1 and the second insulating region SS2 can be arranged to have the same length in the Z direction from the top, and can be arranged at a level lower than the lower surface of the lowermost upper gate electrode 130U1 in the upper gate electrode 130U, and at a level higher than the lower surface of the interlayer insulating layer 120 below the lowermost upper gate electrode 130U1. Accordingly, the upper gate electrode 130U can be completely penetrated and isolated by the first insulating region SS1 and the second insulating region SS2, and can include a plurality of sub-regions that are physically / electrically completely spaced apart from each other. The upper contact region R3 can have a plate shape in which each of the upper gate electrodes 130U may not have a stepped difference in each sub-region.

[0067] The first insulating region SS1 and the second insulating region SS2 can selectively penetrate only the upper gate electrode 130U and may not extend below the memory gate electrode 130M, so that the memory gate electrode 130M and the lower gate electrode 130L can be isolated from each other without passing through the insulating regions SS1 and SS2. As a result, the memory gate electrode 130M and the lower gate electrode 130L can be stacked separately in the form of an integrated board up to the memory region R1, the upper contact region R3, and the extended region R2.

[0068] The first insulating region SS1 can be arranged to span a portion of the channel structure CH in the storage region R1. The first insulating region SS1 can have a predetermined width and can extend across multiple channel structures CH arranged in a zigzag pattern along the X direction. Therefore, when the multiple channel structures CH are uniformly spaced, the first insulating region SS1 can extend while cutting at least a portion of the channel structure CH. The first insulating region SS1 can be recessed into the upper end of the channel structure CH, for example, the portion of the channel structure CH facing the seven upper gate electrodes 130U, and correspondingly, a portion of the channel structure CH can be removed. In this case, when viewed in the XY plane, the channel structure CH can be recessed to cut 1 / 3 to 1 / 4 of the circumference of the upper surface. The first insulating region SS1 may not pass through the channel central axis of the channel structure CH and can be arranged such that 2 / 3 or more of the channel structure CH can remain on the upper surface, but exemplary embodiments are not limited thereto. The channel structure CH into which the first insulating region SS1 is recessed can be an effective channel structure actually used as a storage cell, rather than a dummy channel structure. The first insulating region SS1 can extend from the storage region R1 in a linear shape to the upper contact region R3, or it can extend from the storage region R1 in a wavy shape.

[0069] Each of the insulating regions SS1 and SS2 may include an upper insulating layer. The upper insulating layer may contain an insulating material, such as silicon oxide, silicon nitride, or silicon nitride.

[0070] The channel structures CH can be arranged in rows and columns and spaced apart from each other on the substrate 101 within the storage region R1. Within the storage region R1, the channel structures CH can be arranged in a zigzag pattern along one direction in the XY plane. The channel structures CH can penetrate the gate electrode 130 and can extend in a direction perpendicular to the upper surface of the substrate 101 (e.g., along the Z direction). The channel structures CH can have a columnar shape and can have sloping side surfaces, the width of which decreases towards the substrate 101 depending on the aspect ratio.

[0071] Each of the channel structures CH can have the form in which k channel portions CH1-CHk of k stacked structures GS1-GSk penetrating the gate electrode 130 are connected to each other, where k is a positive integer such as 1, 2, or 3. In an example embodiment, the first to third channel portions CH1-CH3 penetrating the three stacked structures GS1-GS3 can be connected to each other.

[0072] like Figure 3A As shown in the enlarged view, each of the first channel portions CH1 to the third channel portions CH3 may have an upper end with a width greater than the width of the lower end. Each side surface may have an inclined surface, the width of which decreases toward the substrate 101 due to the width difference between the upper and lower ends. The lower ends of the channel portions CH1-CH3 in the upper portion and the upper ends of the channel portions CH1-CH3 in the lower portion may be connected to each other and may form a curved portion.

[0073] Each of the channel structures CH may include a first portion of the stacked structures GS1-GS3, and a second portion that protrudes below the stacked structures GS1-GS3 and contacts the substrate 101.

[0074] The channel layer 140 may be entirely disposed within the channel structure CH and may have a side surface having an annular shape surrounding the buried insulating layer 147 therein, or in exemplary embodiments may have a columnar shape, such as a cylindrical or prismatic shape, without the buried insulating layer 147. The channel layer 140 may comprise a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type or N-type impurities.

[0075] The channel pad 149 may be disposed in the upper part of the channel layer 140 in the channel structure CH. The channel pad 149 may cover the upper surface of the buried insulating layer 147 and may be electrically connected to the channel layer 140. The channel pad 149 may include, for example, doped polysilicon.

[0076] A channel dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. The channel dielectric layer 145 may include a tunneling layer 141, a charge storage layer 142, and a barrier layer 143 stacked sequentially from the channel layer 140. The tunneling layer 141 can tunnel charge into the charge storage layer 142, which may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer 142 may be a charge trapping layer or a floating gate conductive layer. The barrier layer 143 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. According to an example embodiment, at least a portion of the channel dielectric layer 145 may extend horizontally along the gate electrode 130.

[0077] A portion of the channel dielectric layer 145 can be removed, allowing the first horizontal conductive layer 102 to directly contact the channel layer 140.

[0078] The channel layer 140, the channel dielectric layer 145, and the buried insulating layer 147 can be interconnected between the first channel portion CH1 to the third channel portion CH3.

[0079] The dummy channel structures (DCHs) can be arranged in the upper contact region R3. These structures may be identical or similar in form to the channel structures (CHs), but they are not used as actual memory in the semiconductor device 100. The dummy channel structures (DCHs) can be arranged regularly in columns and rows in the upper contact region R3. The arrangement of the dummy channel structures (DCHs) may differ from that of the channel structures (CHs). For example, the dummy channel structures (DCHs) may be arranged in a checkerboard pattern, and the channel structures (CHs) may be arranged in a zigzag pattern. Furthermore, the spacing Id between the dummy channel structures (DCHs) can be greater than the spacing between the channel structures (CHs).

[0080] exist Figure 1 In the example, the dummy channel structure DCH is shown as being arranged to form two rows in each sub-region, but its example embodiments are not limited to this.

[0081] A portion of the dummy channel structure DCH can surround the upper contact structure MC1. For example... Figure 1 As shown, four dummy channel structures (DCHs) can be arranged around an upper contact structure (MC1), and at least a portion of the dummy channel structures (DCHs) surrounding the upper contact structure (MC1) can overlap with the upper contact structure (MC1). A portion of the dummy channel structures (DCHs) can penetrate the stacked structure (GS) arranged in the gaps between adjacent upper contact structures (MC1).

[0082] The channel structure CH and the dummy channel structure DCH can have a circular or circular shape, but other shapes (such as elliptical) are also possible. The dummy channel structure DCH can penetrate the stacked structure GS, similar to the channel structure CH, and the channel dielectric layer 145 can be disposed in the region contacting the substrate 101 and the horizontal insulating layer 110, so that the channel layer 140 is not exposed and thus remains insulated from the substrate 101. The dummy channel structure DCH can serve as a support structure, preventing deformations such as warping of the stacked structure GS.

[0083] Support structures SH can be arranged in the extended region R2. Support structures SH can be insulating structures, which may include insulating materials such as oxides, nitrides, oxynitrides, or carbon oxides, and may have a structure different from the dummy channel structure DCH. Support structures SH can be arranged regularly in columns and rows in the extended region R2. Support structures SH can have a diameter larger than the maximum diameter of the channel structure CH but smaller than the maximum diameter W4 of the word line contact structure MC2. The shape, number, and / or spacing of support structures SH can vary. Support structures SH can have a circular or similar shape, but exemplary embodiments are not limited thereto; support structures SH can have an elliptical shape. Similar to the channel structure CH, support structures SH can have a vertical portion penetrating the stack structure GS and extending along the Z direction, and a horizontal portion protruding from the vertical portion toward each gate electrode 130, but the shape of support structures SH is not limited thereto. Support structures SH can also have a structure including multiple curved portions corresponding to the curved portions of the first to third channel portions CH1-CH3 of the channel structure CH. Support structures SH can be supports that can prevent deformation such as warping of the stack structure GS.

[0084] The semiconductor device 100 may include contact structures MC1 and MC2, respectively connected to the gate electrode 130, in the upper contact region R3 and the extended region R2. Contact structures MC1 and MC2 may penetrate the uppermost interlayer insulating layer 121, extend downward along the Z direction, and connect to the upper surface of the assigned gate electrode 130. Contact structures MC1 and MC2 may have a circular or elliptical shape in the XY plane, such as... Figure 1 As shown, they can be arranged spaced apart from each other in the X and Y directions. The contact structures MC1 and MC2 can be arranged in a grid pattern or a zigzag pattern, and the arrangement and shape of the upper contact structure MC1 and the zigzag contact structure MC2 can be different from each other.

[0085] The word line contact structure MC2 can be arranged in alternating rows in a zigzag pattern in the extended region R2, and the upper contact structure MC1 can be arranged in rows in the upper contact region R3 in the sub-regions separated by the insulating regions SS1 and SS2.

[0086] The upper contact structure MC1 can be arranged in the upper contact region R3, and can be connected to a predetermined number of upper gate electrodes 130U used as erase gate electrodes 130U7-130U5, and a predetermined number of upper gate electrodes 130U used as series select lines 130U4-130U1, respectively.

[0087] exist Figure 1 , Figure 2A and Figure 2B The diagram shows three erase gate electrodes 130U7-130U5 and four series select lines 130U4-130U1. Therefore, the seven upper contact structures MC1 connected to the upper gate electrodes 130U1-130U7 can be arranged in sub-regions. That is, the seven upper contact structures MC1 connected to the upper gate electrode 130U can be spaced apart from each other by a first distance I1 in rows within the sub-regions of the upper gate electrode 130U, which are divided by a first insulating region SS1 and a second insulating region SS2.

[0088] In an example embodiment, the upper gate electrode 130U may have a flat upper surface in the upper contact region R3 without a stepped structure in the form of a staircase, and may be coplanar with the upper surface of the upper gate electrode 130U in the extended region R2. The upper contact structure MC1 may penetrate from the upper surface of the stacked structure GS to the upper part of the assigned upper gate electrode 130U, and may contact the contact region of the assigned upper gate electrode 130U.

[0089] The contact area in the upper gate electrode 130U may have the same area and shape as the lower surface of the upper contact structure MC1, and may be understood as the exposed surface exposed when forming the upper contact hole for forming the upper contact structure MC1.

[0090] In each sub-region, one upper contact structure MC1 can be connected to one upper gate electrode 130U, or alternatively, multiple upper contact structures MC1 can be connected to one upper gate electrode 130U. Therefore, the number of upper contact structures MC1 assigned to each of the sub-regions can be the same, and the number of upper contact structures MC1 assigned to each of the sub-regions can be an integer multiple of the number of upper gate electrodes 130U.

[0091] like Figure 1As shown, when the number of upper contact structures MC1 is the same as the number of upper gate electrodes 130U in each sub-region, the upper contact structures MC1 arranged at the same position in each sub-region can contact the upper gate electrodes 130U at the same level.

[0092] For example, when the upper contact structure MC1 most adjacent to the channel structure CH is represented as the first upper contact structure MC1, the first upper contact structure MC1 can be connected to the uppermost upper gate electrode 130U7, and the lower end of the upper contact structure MC1 can be horizontally lowered by one gate electrode 130 towards the extended region R2. The contact direction and order are not limited to this and can be varied.

[0093] Each of the upper contact structures MC1 may include a through insulation structure 165 and a first post 180a.

[0094] The through-insulation structure 165 can be a structure that buries the entire upper contact hole from the opening on the upper surface of the stacked structure GS to the upper surface of the assigned upper gate electrode 130U.

[0095] Accordingly, the through-insulation structure 165 may include an upper surface coplanar with the upper surface of the stacked structure GS, a lower surface in contact with the upper surface of the assigned upper gate electrode 130U, and a side surface connecting the upper and lower surfaces. The upper surface of the through-insulation structure 165 may have a circular, elliptical, or polygonal shape, and for example, the maximum diameter of the upper surface may have a first width W1. The first width W1 of the upper surface may be greater than the width of the lower surface, and therefore, the side surface may have a bevel. The first width W1 of the upper surface may be equal to or less than the fourth width W4 of the upper surface of the word line contact structure MC2.

[0096] The through-insulation structure 165 can be a cylindrical structure with a first thickness t1, and its outer surface can contact the upper gate electrode 130U or the interlayer insulating layer 120, while its inner surface can surround the first pillar 180a. The first thickness t1 of the through-insulation structure 165 can be greater than the thickness of the side insulating layer 160 of the second contact structure MC2.

[0097] The through-insulation structure 165 within the sub-region can have different first lengths h1 in the Z direction, wherein each first length h1 corresponds to the distance from the upper surface of the stacked structure GS to the upper surface of the assigned upper gate electrode 130U.

[0098] The through-insulation structure 165 may include an insulating material and may include at least one of oxides, carbon oxides, or oxynitrides. For example, the through-insulation structure may include silicon oxide, may include the same material as the interlayer insulating layer 120, and may be implemented by a material different from the silicon nitride forming the sacrificial insulating layer 118.

[0099] Each of the upper contact structures MC1 may include a first pillar 180a that penetrates through the insulating structure 165 and directly contacts the upper surface of the assigned upper gate electrode 130U.

[0100] The first post 180a may extend from the upper surface of the upper insulating layer 194, penetrate the upper insulating layer 194, and continuously pass through the through insulating structure 165. Therefore, the upper surface Sa of the first post 180a may be coplanar with the upper surface of the contact area of ​​the upper insulating layer 194, and the lower surface Sb may contact the upper surface of the allocated upper gate electrode 130U. A portion of the first post 180a may protrude into the allocated upper gate electrode 130U, and the lower surface Sb of the first post 180a may be positioned below the lower surface of the through insulating structure 165; however, the scope of the exemplary embodiment is not limited thereto. The upper surface Sa of the first post 180a may have a second width W2, and the second width W2 may be smaller than the first width W1. For example, the second width W2 may be less than 1 / 3 to 1 / 4 of the first width W1. The second width W2 of the upper surface Sa of the first post 180a may be greater than the width of the lower surface Sb, and the side surface connecting the upper surface Sa and the lower surface Sb may have a bevel. The second width W2 of the upper surface Sa of the plurality of first pillars 180a may be the same, and the width of the lower surface Sb may be different; however, the scope of the example embodiment is not limited thereto.

[0101] The central axis l1 passing through the center of the second width W2 of the first post 180a can be coaxial with the central axis l1 passing through the center of the first width W1 of the through insulation structure 165. Therefore, the first post 180a can be understood as being arranged at the center of the through insulation structure 165.

[0102] The side surface of the first post 180a may be spaced apart from the outer surface of the through-insulation structure 165, and may be physically and electrically spaced apart from the penetrated upper gate electrode 130U. The through-insulation structure 165 may be arranged between the first post 180a and the upper gate electrode 130U.

[0103] The first post 180a may have a second length h2 in the Z direction, which may be greater than the first length h1. That is, the upper surface Sa of the first post 180a may be positioned above the upper surface of the through insulation structure 165, while the lower surface Sb of the first post 180a may be arranged at or below the lower surface of the through insulation structure 165, so that the first post 180a can completely penetrate the through insulation structure 165.

[0104] The first pillar 180a may include a lower surface Sb and a contact barrier layer 184 on a side surface, and may include a conductive material layer 183 on the contact barrier layer 184. The conductive material layer 183 may include at least one of tungsten (W), copper (Cu), aluminum (Al), or alloys thereof. For example, the conductive material layer 183 may include tungsten (W). The contact barrier layer 184 may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0105] The four dummy channel structures DCH that are in contact with and surrounding the upper contact structure MC1 can be as follows: Figure 1 The arrangement is shown, and at least a portion of the four dummy channel structures DCH can cut through a portion of the through insulation structure 165. Figure 1 As shown, the four dummy channel structures DCH can be arranged with the same spacing as the first post 180a arranged on the central axis l1 of the upper contact structure MC1. Each of the dummy channel structures DCH around the upper contact structure MC1 can be arranged while cutting at least a portion of the upper contact structure MC1.

[0106] In other words, when the dummy channel structures DCH are spaced apart from each other to have a spacing distance Id, the first width W1 of the upper surface of the through insulation structure 165 of the upper contact structure MC1 can be greater than the spacing distance Id. Therefore, at least one dummy channel structure DCH can be arranged to overlap or intersect with a portion of the through insulation structure 165, thereby partially cutting into a portion of the through insulation structure 165.

[0107] refer to Figure 3C The upper surface of the dummy channel structure DCH can be coplanar with the upper surface of the through insulation structure 165, and can extend toward the substrate 101 while cutting the through insulation structure 165, so that 1 / 2 to 1 / 4 of the circumference of the upper surface of the dummy channel structure DCH can protrude into the through insulation structure 165.

[0108] The protruding lengths d1 and d2 of the dummy channel structure DCH protruding into the through insulation structure 165 can be different for each of the dummy channel structures DCH. For example, the protruding length d1 of the dummy channel structure DCH arranged on the left side of the first post 180a can be different from the protruding length d2 of the dummy channel structure DCH arranged on the right side.

[0109] The side surface of the dummy channel structure DCH that cuts at least a portion of the through insulation structure 165 may be spaced apart from the side surface of the first post 180a in the through insulation structure 165.

[0110] The spacing between the first post 180a and the dummy channel structure DCH can be different for each of the dummy channel structures DCH. For example, the distance between the dummy channel structures DCH arranged on the left side of the first post 180a can be different from the distance between the dummy channel structures DCH arranged on the right side.

[0111] As described above, when the upper contact structure MC1 is arranged in a sub-region, structural stability can be ensured by regularly arranging the dummy channel structure DCH while cutting a portion of the upper contact structure MC1.

[0112] Therefore, in the upper contact region R3, the dummy channel structures DCH are spaced apart by a distance Id, which is less than a first distance I1 and less than a first width W1. The first distance I1 is the spacing between the upper contact structures MC1, and the first width W1 represents the maximum diameter of the upper surface of the through-insulation structure. This arrangement helps to ensure the structural stability in the upper contact region R3.

[0113] In this case, the dummy channel structure DCH that cuts into at least a portion of the upper contact structure MC1 can be offset from the central axis l1 of the upper contact structure MC1 to avoid direct contact with the first post 180a.

[0114] The word line contact structures MC2 can be arranged at a second distance I2, and can be arranged in a zigzag pattern in the extended area R2. The second distance I2 can be greater than the first distance I1. It may include a contact plug 170 and a side insulating layer 160 surrounding the contact plug 170.

[0115] Contact plug 170 may include a conductive layer that may bury the central region of the contact hole, and may include a columnar shape extending along the Z direction from an upper surface coplanar with the upper surface of the upper insulating layer 194 to a lower surface contacting the assigned gate electrode 130. Word line contact structure MC2 may include a curved portion depending on its length. The fourth width W4 of the upper surface of word line contact structure MC2 may be greater than the width of the lower surface, thereby creating a sloping side surface connecting the upper and lower surfaces. The upper surface of word line contact structure MC2 may be coplanar with the upper surface of the through-insulation structure 165 of upper contact structure MC1, and may be coplanar with the upper surface of stacked structure GS.

[0116] Contact plug 170 may further include a conductive layer and contact barrier layers on the side and lower surfaces of the conductive layer. The fourth width W4 of the upper surface of the word line contact structure MC2 may be substantially the same as the width of the upper surface of the contact plug 170; however, the scope of the exemplary embodiment is not limited thereto. The fourth width W4 of the word line contact plug MC4 may be greater than or the same as the first width W1 of the upper contact structure MC1.

[0117] A side insulating layer 160 may be disposed between the stacked structure GS penetrated by the contact plug 170 and the contact plug 170. The side insulating layer 160 may be disposed on the side surface of the contact plug 170, and its upper end may be positioned at the same level as the upper surface of the contact plug 170, and its lower end may be positioned at the same level as the lower surface of the contact plug 170 or at a higher level. The lower end of the side insulating layer 160 may be disposed to expose the upper surface of the assigned gate electrode 130, and may be disposed to insulate the upper portion of the assigned gate electrode 130.

[0118] The side insulating layer 160 can be disposed on the side surface of the word line contact structure MC2 to electrically insulate the word line contact structure MC2 from the adjacent gate electrode 130. In addition, the side insulating layer 160 can make physical and electrical contact with the contact area of ​​the assigned gate electrode 130 through the exposed lower surface of the word line contact structure MC2.

[0119] In the extended region R2, when a word line contact structure MC2 is assigned to each of the memory gate electrode 130M and the lower gate electrode 130L, the word line contact structure MC2 can have different lengths so as to connect to the gate electrodes 130M and 130L at different levels.

[0120] exist Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C In the example embodiment, the first to third stacked structures GS1-GS3 are shown as including gate electrodes 130 in each of eight levels, and 17 gate electrodes 130M and 130L can be retained when the eight gate electrodes 130U in the upper part are upper gate electrodes 130U. A word line contact structure MC2 can be arranged in the extended region R2, and the length of the word line contact structure MC2 is adjusted differently to contact the upper surfaces of the 17 gate electrodes 130M and 130L.

[0121] The word line contact structures MC2 can be arranged in various ways, and in example embodiments, such as Figure 1 As shown, the word line contact structures MC2 can be arranged in a column, decreasing in the Z and Y directions and contacting each assigned gate electrode 130; however, the scope of the example embodiment is not limited thereto. For example, the word line contact structures MC2 can be arranged in a row and can be arranged symmetrically such that the length can increase towards the center. The word line contact structures MC2 arranged in the last column may include dummy word line contact structures MC2 and can be used as support structures SH without performing the function of selecting actual word lines.

[0122] exist Figure 2A The example illustrates a word line contact structure MC2 that contacts the ninth and twelfth gate electrodes 130; however, the scope of this example embodiment is not limited thereto. The length of the word line contact structure MC2 in the Z direction may indicate that the upper surface is level and the lower surface is leveled.

[0123] The contact plugs 170 of the upper contact structure MC1 and the word line contact structure MC2 may include the same conductive material layer, such as at least one of tungsten (W), copper (Cu), aluminum (Al), or alloys thereof. For example, the conductive material layer may include tungsten (W). The contact barrier layer 171 may surround the conductive material layer and may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0124] The upper insulating layer 194 can be arranged to cover the stacked structure GS, and can also be arranged to cover the channel structure CH, the dummy channel structure DCH, the through insulating structure 165, and the word line contact structure MC2. The upper insulating layer 194 can be formed of an insulating material, and may include, for example, at least one of silicon oxide, silicon nitride, or silicon nitride.

[0125] The upper insulating layer 194 may be arranged to have a predetermined thickness and may be penetrated by the first to third posts 180a, 180b and 180c. The upper insulating layer 194 may include at least one of SiO, SiN, SiCN, SiOC, SiON or SiOCN.

[0126] The second post 180b and the third post 180c, as well as the cell interconnect 185, can be arranged. The second post 180b can be arranged in the extension region R2, penetrating the upper insulating layer 194, and can contact the upper surface of the word line contact structure MC2. The third post 180c can be arranged in the storage region R1, penetrating the upper insulating layer 194, connected to the channel pad 149 of the channel structure CH, and electrically connected to the channel layer 140.

[0127] The second column 180b and the third column 180c may have the same length and shape, and both may have inclined side surfaces such that their width decreases from the upper surface to the lower surface. The upper surfaces of the first column 180a, the second column 180b, and the third column 180c may be positioned at the same level. The lower surfaces of the second column 180b and the third column 180c may also be positioned at the same level, while the lower surface Sb of the first column 180a may be positioned at a lower level. The width W2 of the upper surface of the first column 180a may be substantially the same as the width W3 of the upper surfaces of the second column 180b and the third column 180c; however, the scope of the exemplary embodiment is not limited thereto.

[0128] As used herein, the expression "substantially the same" can mean that the measurement is identical relative to other values ​​compared to it, as will be understood by those skilled in the art, and allows for approximations, inaccuracies, and limitations of the measurement in the relevant context. In one or more aspects, the terms "substantially," "about," and "approximately" can provide industry-acceptable tolerances for the relativity between their respective terms and / or items, such as tolerances of ±1%, ±5%, or ±10% of the actual value, and other suitable tolerances.

[0129] The first post 180a and the second post 180b can be electrically connected to the respective gate electrode 130 via contact plugs MC1 and MC2 connected to the lower surface, respectively. Posts 180a, 180b, and 180c can have a plug-like shape, and the cell interconnect 185 can have a line-like shape; however, the scope of the exemplary embodiment is not limited thereto. The first to third posts 180a, 180b, and 180c can include the same conductive material layer 183, and can include metal. For example, the conductive material layer 183 can include tungsten (W), copper (Cu), aluminum (Al), etc., and can further include a contact barrier layer 184 similar to that of the first post 180a.

[0130] The cell interconnect 185 may include a metal, such as tungsten (W), copper (Cu), aluminum (Al), etc. An insulating layer may be further disposed covering the cell interconnect 185. The insulating layer may be formed of an insulating material, such as at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

[0131] Figure 4 and Figure 5 This is an enlarged cross-sectional view of a semiconductor device according to an example embodiment.

[0132] Apart from the shapes of the upper contact structure MC1 and the dummy channel structure DCH Figure 4 The semiconductor device 100a in the middle can be with Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 in it is the same.

[0133] At least one of the dummy channel structures DCH arranged around the upper contact structure MC1 can be arranged as a through insulation structure 165 that penetrates the upper contact structure MC1.

[0134] The dummy channel structure DCH arranged on one of the left or right sides of the upper contact structure MC1 can be arranged to penetrate the through insulation structure 165, so that the entire dummy channel structure DCH can be arranged in the through insulation structure 165.

[0135] The dummy channel structure DCH arranged on the other side of the left or right side of the upper contact structure MC1 can be arranged to penetrate only a portion of the through insulation structure 165, such that only a portion of the dummy channel structure DCH can cut through the upper contact structure MC1.

[0136] Therefore, another portion of the dummy channel structure DCH on the other side can penetrate the stacked structure GS. The protruding length d3 of the dummy channel structure DCH on one side of the upper contact structure MC1 and the through insulation structure 165 can be greater than the protruding length d4 of the dummy channel structure DCH on the other side of the upper contact structure MC1 and the through insulation structure 165.

[0137] However, the dummy channel structure DCH on one side can also be physically separated from the first column 180a therein.

[0138] In addition to the configuration of the support structure SH in the upper contact area R3 instead of the dummy channel structure DCH, Figure 5 The semiconductor device 100b in the middle can be with Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 is the same.

[0139] The support structure SH may include a support structure SH that penetrates the stacked structure GS between the support structure SH and the upper contact structure MC1, arranged close to the upper contact structure MC1 in a manner similar to the arrangement of the dummy channel structure DCH. The arrangement of the support structure SH can be the same as the arrangement of the dummy channel structure DCH, such as... Figure 1 As shown.

[0140] The support structure SH can be the same as the support structure SH in the extended region R2, and can have a width smaller than that of the support structure SH in the extended region R2; however, the scope of the example embodiment is not limited thereto.

[0141] The support structure SH, which is arranged by cutting a portion of the upper contact structure MC1, can be arranged such that a portion can penetrate the upper contact structure MC1, while another portion can penetrate the stacked structure GS.

[0142] A portion of the upper contact structure MC1, particularly the portion in contact with the through-insulation structure 165, may extend flatly along the side surface of the support structure SH. The portion of the side surface in contact with the stacked structure GS may have a shape with continuously arranged convex protrusions. The convex protrusions may project toward the gate electrode 130.

[0143] Figures 6 to 7This is a diagram showing a semiconductor device according to an example embodiment, viewed from above. Figure 8 It is along Figure 7 The diagram showing the section intercepted by line III-III' in the middle. Figure 7 The diagram shows a cross-sectional view of a semiconductor device.

[0144] In addition to the arrangement in the upper contact area, Figure 6 The semiconductor device 100c in the middle can be with Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 is the same.

[0145] Figure 6 The upper contact structures MC1 in the sub-region can be arranged in rows, and can be arranged such that they have a third distance I3 with adjacent upper contact structures MC1. In this case, the third distance I3 can represent the pitch, which is the distance between the central axes l1 of the upper contact structures MC1, and the third distance I3 can be less than [a certain value]. Figure 1 The first distance I1 in the middle.

[0146] Therefore, the upper contact structures MC1 can be arranged close to each other, with at least a portion of the stacked structure GS arranged between the upper contact structures MC1. As a result, the side surfaces of the two upper contact structures MC1 can remain spaced apart without directly contacting each other.

[0147] A dummy channel structure DCH can be arranged while cutting a portion of the upper contact structure MC1 around each upper contact structure MC1, and the dummy channel structures DCH can be arranged by cutting a portion of the upper channel structure MC1. That is, as... Figure 1 In that case, the dummy channel structure DCH can be arranged not in the gap between the upper contact structures MC1 and only penetrate the stacked structure GS.

[0148] In addition to the through-insulation structure 165 being arranged as a strip extending along the Y direction for a configuration that interconnects multiple sub-regions, Figure 7 and Figure 8 The semiconductor device 100d in the middle can be with Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 is the same.

[0149] Figure 7 and Figure 8The semiconductor device 100d may include a shared through-insulation structure 167 that penetrates a sub-region between adjacent isolation regions MS in the Y direction in the block and extends in a strip shape in the Y direction in a plan view.

[0150] The shared through-insulation structure 167 can extend along the Y direction to simultaneously surround the first post 180a in a column arranged in each sub-region.

[0151] Therefore, the shared through-insulation structure 167 can penetrate the sub-regions simultaneously.

[0152] The shared through-insulation structure 167 may surround the first post 180a arranged in the same column in multiple sub-regions, and the entire first post 180a arranged in the shared through-insulation structure 167 may contact the same upper gate electrode 130U.

[0153] exist Figure 7 The diagram shows eight sub-regions, with seven first pillars 180a arranged in rows within each sub-region, but the number of elements can vary.

[0154] The shared through-insulation structure 167 may be a structure stacked with insulating material, such that the eight first pillars 180a in the shared through-insulation structure 167 can contact the same upper gate electrode 130U, and the first pillar 180a of each sub-region in the shared through-insulation structure 167 can contact the assigned upper gate electrode 130U.

[0155] In this configuration, the first insulating region SS1 can be arranged to penetrate the shared through-insulation structure 167 and the upper gate electrode 130U between the first pillars 180a.

[0156] Therefore, the lower end of the first insulating region SS1 can be positioned at a level lower than the lower surface of the shared through insulating structure 167.

[0157] Figure 9 This is a diagram illustrating a semiconductor device according to an example embodiment, and Figure 10 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0158] Except for the configuration where the width tb of the second insulating region SS2 is greater than the width ta of the first insulating region SS1, Figure 9 The semiconductor device 100e in the middle can be with Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 is the same.

[0159] Figure 9 The first insulating region SS1 can have a second insulating width tb, the second insulating region SS2 can have a first insulating width ta, and the second insulating width tb can be greater than the first insulating width ta.

[0160] The second insulation width tb may have a size substantially similar to the first width W1, which is the width of the upper surface of the upper contact structure MC1; however, the scope of the example embodiment is not limited thereto.

[0161] The relatively wide second insulating region SS2 can be formed simultaneously with the through insulating structure 165 of the upper contact structure MC1. The two structures can be patterned using the same etching process, such that the upper part of the second insulating region SS2 has a width similar to that of the through insulating structure 165.

[0162] The dummy channel structure DCH that penetrates the second insulation region SS2 can be further arranged in the second insulation region SS2, which has a wider width.

[0163] The dummy channel structure DCH in the second insulation region SS2 can be arranged in the second insulation region SS2, such as Figure 9 As shown, or alternatively, the dummy channel structure DCH can be arranged by cutting a portion of the second insulation region SS2.

[0164] The dummy channel structure DCH is shown arranged in rows in the second insulation region SS2; however, the scope of the example embodiment is not limited thereto, and the dummy channel structure DCH can be arranged in various arrangements.

[0165] Figure 10 The semiconductor device 100f may have a structure in which upper insulating layers are sequentially stacked on a stacked structure GS, a first upper insulating layer 192, and a second upper insulating layer 194.

[0166] The first upper insulating layer 192 and the second upper insulating layer 194 may include the same insulating material; however, the scope of the example embodiment is not limited thereto.

[0167] Reference Figure 10 The through-insulation structure 165 of the upper contact structure MC1 of the semiconductor device 100f can have the same as... Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3CThe same structure is used, and the first post 180a can extend from the second upper insulating layer 194 by penetrating the first upper insulating layer 192 and the through insulating structure 165. Therefore, the length of the first post 180a in the Z direction can be longer, and the third length h3 from the upper surface of the through insulating structure 165 to the upper surface Sa of the first post 180a can be longer.

[0168] In the word line contact structure MC2, the upper surface of the contact plug 170 can be arranged at a level higher than the upper surface of the through insulation structure 165, and can be coplanar with the upper surface of the first upper insulation layer 192.

[0169] The second side insulating layer 175 may be further disposed between the first side insulating layer 160 and the contact plug 170, and between the contact plug 170 and the gate electrode 130. The second side insulating layer 175 may be in direct contact with the side surface of the contact plug 170, and may have an upper end at the same level as the upper surface of the contact plug 170, and a lower end substantially aligned with the lower end of the first side insulating layer 160. Therefore, the upper end of the second side insulating layer 175 may be located at a level higher than the upper end of the first side insulating layer 160, and may extend to penetrate the first upper insulating layer 192. As a result, the upper surface of the contact plug 170 and the upper end of the second side insulating layer 175 may be exposed on the first upper insulating layer 192, while the upper end of the first side insulating layer 160 may remain unexposed. The first upper insulating layer 192, the upper surface of the contact plug 170, and the upper end of the second side insulating layer 175 may be substantially coplanar with each other; however, the scope of the exemplary embodiment is not limited thereto.

[0170] The second side insulating layer 175 may be arranged along its side surface with a substantially uniform thickness, extending from the upper end to the lower end. The thickness of the second side insulating layer 175 may be equal to or greater than the thickness of the first side insulating layer 160, or may be less than the thickness of the interlayer insulating layer 120.

[0171] The first insulating layer 160 may include an insulating material, such as silicon oxide, silicon nitride, or silicon nitride. The second insulating layer 170 may include silicon oxide, undoped polysilicon, or silicon nitride.

[0172] The second post 180b arranged on the word line contact structure MC2 can penetrate the second upper insulating layer 194 and can be arranged such that the upper surface can be coplanar with the first post 180a and the lower surface can contact the upper surface of the contact plug 170.

[0173] refer to Figure 11The semiconductor device 100g may include a first semiconductor structure S1 and a second semiconductor structure S2 below the first semiconductor structure S1. The first semiconductor structure S1 may include a memory cell region, and the second semiconductor structure S2 may include a peripheral circuit region. In some example embodiments, the second semiconductor structure S2 may be disposed on the first semiconductor structure S1.

[0174] For the first semiconductor structure S1, a reference can be applied. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The description.

[0175] The second semiconductor structure S2 may include a substrate 201, a source / drain region 205 and a device isolation layer 210 in the substrate 201, a circuit device 220 disposed on the substrate 201, a peripheral region insulating layer 290, a circuit contact plug 270 and a circuit interconnect 280.

[0176] Substrate 201 may have a lower surface extending along the X and Y directions. Substrate 201 may have an active region defined by device isolation layer 210. Source / drain regions 205, including impurities, may be disposed on a portion of the active region. Substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. Substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0177] Circuit device 220 may include planar transistors. Each of circuit devices 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be disposed on both sides of the circuit gate electrode 225 as source / drain regions in the substrate 201.

[0178] The peripheral region insulating layer 290 can be arranged to cover the circuit devices 220 on the lower surface of the substrate 201. The peripheral region insulating layer 290 may include multiple insulating layers formed in different processes. The peripheral region insulating layer 290 may be formed of an insulating material.

[0179] Circuit contact plug 270 and circuit interconnect 280 may be included in a circuit interconnect structure electrically connected to circuit device 220 and source / drain region 205. Circuit contact plug 270 may have a cylindrical shape, and circuit interconnect 280 may have a linear shape. Electrical signals may be applied to circuit device 220 through circuit contact plug 270 and circuit interconnect 280. In areas not shown, circuit contact plug 270 may also be connected to circuit gate electrode 225. Circuit interconnect 280 may be connected to circuit contact plug 270 and may be arranged in multiple layers. Circuit contact plug 270 and circuit interconnect 280 may include conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), etc., and each element may also include a diffusion barrier. In the example embodiment, the number of layers of circuit contact plug 270 and circuit interconnect 280 may vary.

[0180] Figure 12 The semiconductor device 100h in the middle may include Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 serves as a first semiconductor structure S1, and the second semiconductor structure S2 can be arranged as a peripheral circuit structure below the first semiconductor structure S1. The first semiconductor structure S1 can be stacked in the Z direction perpendicular to the second semiconductor structure S2. Specifically, the first semiconductor structure S1 can be arranged in the upper part of the second semiconductor structure S2 along the Z direction. In an example embodiment, conversely, the second semiconductor structure S2 can be arranged on the upper part of the first semiconductor structure S1.

[0181] The first semiconductor structure S1 may further include a bonding structure. Specifically, a first bonding path 195, a first bonding metal layer 198, and a first bonding insulating layer 199 may be included in the first bonding structure of the first semiconductor structure S1. The first bonding path 195 may be disposed on the cell interconnect 185, and the first bonding metal layer 198 may be connected to the first bonding path 195. The first bonding metal layer 198 may have an upper surface exposed to the upper surface of the first semiconductor structure S1. The first bonding metal layer 198 may be bonded to and connected to the second bonding metal layer 298 of the second semiconductor structure S2. The first bonding path 195 and the first bonding metal layer 198 may include a conductive material, such as copper (Cu). The first bonding insulating layer 199 may form a dielectric-dielectric bond with the second bonding insulating layer 299 of the second semiconductor structure S2.

[0182] The second semiconductor structure S2 can be similar to Figure 11The second semiconductor structure S2 in the middle may include a second bonding passage 295 and a second bonding metal layer 298 on the peripheral region insulating layer 290.

[0183] The peripheral region insulating layer 290 can be arranged to cover the circuit devices 220 on the lower surface of the substrate 201. The peripheral region insulating layer 290 may include multiple insulating layers formed in different processes. The peripheral region insulating layer 290 may be formed of an insulating material. A portion of the peripheral region insulating layer 290 may be used as a second bonding insulating layer 299.

[0184] Circuit contact plug 270 and circuit interconnect 280 may be included in a circuit interconnect structure electrically connected to circuit device 220 and source / drain region 205. Circuit contact plug 270 may have a cylindrical shape, and circuit interconnect 280 may have a linear shape. Electrical signals can be transmitted to circuit device 220 through circuit contact plug 270 and circuit interconnect 280. In areas not shown, circuit contact plug 270 may also be connected to circuit gate electrode 225. Circuit interconnect 280 may be connected to circuit contact plug 270 and may be arranged in multiple layers. Circuit contact plug 270 and circuit interconnect 280 may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), etc., and each of the elements may also include a diffusion barrier. In the example embodiment, the number of layers of circuit contact plug 270 and circuit interconnect 280 may vary.

[0185] The second bonding path 295, the second bonding metal layer 298, and the second bonding insulating layer 299 may be included in the second bonding structure and may be disposed below the lowermost portion of the circuit interconnect 280. The second bonding path 295 may have a cylindrical shape, and the second bonding metal layer 298 may have a pad shape, which may be circular or a relatively short line shape in a plane. The lower surface of the second bonding metal layer 298 may be exposed to the lower surface of the second semiconductor structure S2. The second bonding path 295 and the second bonding metal layer 298 may provide an electrical connection path to the first semiconductor structure S1. In an example embodiment, a portion of the second bonding metal layer 298 may be formed solely for bonding purposes and not connected to the circuit interconnect 280. The second bonding path 295 and the second bonding metal layer 298 may include a conductive material, such as copper (Cu).

[0186] The second bonding insulating layer 299 can be defined from the lower surface of the peripheral region insulating layer 290 with a predetermined thickness, but it can also be implemented as an insulating layer on the lower surface of the peripheral region insulating layer 290. The second bonding insulating layer 299 can be arranged for dielectric-dielectric bonding with the first bonding insulating layer 199 of the first semiconductor structure S1. The second bonding insulating layer 299 can also serve as a diffusion barrier for the second bonding metal layer 298, and can include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

[0187] The first semiconductor structure S1 and the second semiconductor structure S2 can be joined together by a bonding between the first bonding metal layer 198 and the second bonding metal layer 298 and by a bonding between the first bonding insulating layer 199 and the second bonding insulating layer 299. The bonding between the first bonding metal layer 198 and the second bonding metal layer 298 can be, for example, a copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layer 199 and the second bonding insulating layer 299 can be, for example, a dielectric-dielectric bonding, such as a SiCN-SiCN bonding. The first and second semiconductor structures S1 and S2 can be joined together by a hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0188] like Figure 12 As shown, the first semiconductor structure S1 and the second semiconductor structure S2 can be packaged with the first semiconductor structure S1 on top, or alternatively, the first semiconductor structure S1 and the second semiconductor structure S2 can be arranged in reverse order with the second semiconductor structure S2 on top.

[0189] Figures 13A to 13I and Figures 14A to 14D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0190] Figures 13A to 13I and Figures 14A to 14D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device in an example embodiment, showing the corresponding... Figure 2A The cross-sectional surface, and Figures 14A to 14D It shows the corresponding Figure 2B The cross-sectional surface.

[0191] Reference Figure 13A Sacrificial insulating layers 118 and interlayer insulating layers 120 are alternately stacked on substrate 101, and molded structures MS1-MS3 can be formed by forming up to the uppermost interlayer insulating layer 121. A vertical sacrificial structure 116 can be formed that penetrates the molded structures MS1-MS3.

[0192] Substrate 101 may be a semiconductor substrate, such as a silicon (Si) wafer. First, a first molded structure MS1 (MS1-MS3) can be formed, and a high aspect ratio contact (HARC) etching can be performed to penetrate this structure, forming a portion of a vertical sacrificial structure 116. A second molded structure MS2 can then be formed, and HARC etching can be performed to penetrate this structure, forming another portion of the vertical sacrificial structure 116. A third molded structure MS3 can be formed in the same manner.

[0193] The sacrificial insulating layer 118 can be replaced by the gate electrode 130 in a subsequent process (see reference). Figure 2A The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material selectively etched under specific etch conditions relative to the interlayer insulating layer 120. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide or silicon nitride, and the sacrificial insulating layer 118 may be formed of a material other than the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In the example embodiment, the thicknesses of the interlayer insulating layers 120 may be different, and the thickness of the uppermost interlayer insulating layer 121 may be greater than the thicknesses of the other interlayer insulating layers 120. The thicknesses of the interlayer insulating layers 120 and the sacrificial insulating layer 118, as well as the number of films included in the layers, may differ from the illustrated example.

[0194] The vertical sacrificial structure 116 can be formed in relation to Figure 2A The vertical sacrificial structure 116 is located at positions corresponding to the channel structure CH, the dummy channel structure DCH, and the support structure SH. The vertical sacrificial structure 116 may be formed, for example, having the same dimensions as the channel structure CH, the dummy channel structure DCH, and the support structure SH. The vertical sacrificial structure 116 may include, for example, carbon (C); however, the scope of the example embodiment is not limited thereto.

[0195] Reference Figure 13B A mask layer can be formed on the uppermost interlayer insulating layer 121, and correspondingly, an upper contact hole OP1 can be formed to form an upper contact structure MC1 in the upper contact region R3.

[0196] Specifically, the upper contact hole OP1 can be formed by performing multiple etching operations to reach the assigned upper gate electrode 130U (corresponding sacrificial insulating layer 118) of each upper contact structure MC1. When forming the upper contact hole OP1, the number of etching operations and the etching sequence can be applied differently depending on the level of the assigned gate electrode 130.

[0197] For example, when the total number of layers of the upper gate electrode 130U is m, in the case of conversion to binary, the number of contact etching operations can be performed as many times as the number of bits in the binary number. Contact etching can be performed at different depths depending on the number of bits in the converted binary number. For example, contact etching corresponding to the first bit can include etching corresponding to one (2... 0 The gate electrode's sacrificial insulating layer 118 and interlayer insulating layer 120, and the contact etching corresponding to the second position may include simultaneous etching corresponding to two (2) 1 The gate electrode has a sacrificial insulating layer 118 and an interlayer insulating layer 120. The contact etching corresponding to the third position may include etching corresponding to the fourth (2) position. 2 The gate electrode has a sacrificial insulating layer 118 and an interlayer insulating layer 120.

[0198] By converting the number of layers of each assigned upper gate electrode 130U into a binary number and applying contact etching corresponding to the bits with 1 in the converted binary number, upper contact holes OP1 with different depths can be formed.

[0199] Therefore, by applying contact etching to the upper contact hole OP1 that corresponds to a different number of bits of the binary number, the etching can be performed only as many times as the number of bits of the binary number, and upper contact holes OP1 with different depths can be formed, so that upper gate electrodes 130U at different levels can be opened respectively.

[0200] like Figure 13C and Figure 14A As shown in the diagram, a through-insulation structure 165 can be formed in each upper contact hole OP1.

[0201] The through-insulation structure 165 may include a material different from the sacrificial insulation layer 118, and may include an insulating material. Therefore, the through-insulation structure 165 may include silicon oxide, silicon carbide, etc.

[0202] The through-insulation structure 165 can be formed by over-depositing insulating material to cover the upper surfaces of the molded structures MS1-MS3 and planarizing to expose the upper surfaces of the molded structures MS1-MS3; however, the scope of the example embodiment is not limited thereto.

[0203] Therefore, a portion of the vertical sacrificial structure 116 of the dummy channel structure DCH can be arranged below the through insulation structure 165.

[0204] Reference Figure 13D and Figure 14B It can form a vertical sacrificial structure 116 that penetrates the third molding structure MS3, and can form a contact hole OP2 in the extended region R2.

[0205] The vertical sacrificial structure 116 penetrating the third molding structure MS3 can be formed as an extension of the vertical sacrificial structure 116 penetrating the second molding structure MS2, and can be formed by embedding carbon after HARC etching.

[0206] The vertical sacrificial structure 116 can be formed by cutting at least a portion of the through insulation structure 165 in the upper contact region R3, thus maintaining the state in which a portion of the through insulation region R3 is partially removed by the vertical sacrificial structure 116.

[0207] In the extended region R2, a mask layer for the word line contact structure MC2 can be formed, and correspondingly, a contact hole OP2 can be formed to form the upper contact structure MC2 in the extended region R2.

[0208] Specifically, the contact hole OP2 can be formed by performing multiple etching operations to reach the assigned gate electrode (corresponding sacrificial insulating layer 118) of each upper contact structure MC2. When forming the contact hole OP2, the number of etching operations and the etching sequence can be applied differently depending on the level of the assigned gate electrode 130.

[0209] For example, when the total number of layers of the gate electrode 130 is n, when converted to binary, the number of contact etchings can be as many as the number of binary digits. Depending on the number of binary digits converted, contact etching can be performed at different depths. The number of contact etching bits can be configured to be even greater, and the method can be the same as that used to form the upper contact hole OP1.

[0210] By converting the number of layers of each assigned gate electrode 130 into a binary number and applying contact etching to the digits with 1s in the converted binary number, contact holes OP2 with different depths can be formed.

[0211] Therefore, by performing contact etching a number of times corresponding to the number of binary digits and changing that number based on the contact hole OP2, it is possible to perform only as many etchings as the number of binary digits, and to form contact holes OP2 of different depths that can open different levels of the gate electrode 130.

[0212] In this case, when the depth of the contact hole OP2 formed in the extended region R2 is greater than the depth of the upper contact hole OP1 formed in the upper contact region R3, the diameter W4 of the contact hole OP2 can be greater than the diameter W1 of the upper contact hole OP1.

[0213] Reference Figure 13E A preliminary contact insulation layer 160P and a contact sacrificial layer 129 can be formed in the contact hole OP2.

[0214] A preliminary contact insulation layer 160P can be conformally formed to cover the sidewalls and bottom surface of each of the contact holes OP2. For example, the preliminary contact insulation layer 160P can be formed using a chemical vapor deposition (CVD) process.

[0215] The contact sacrificial layer 129 may be formed to fill each of the contact holes OP2 on the initial contact insulation layer 160P. The contact sacrificial layer 129 may include a material different from that of the initial contact insulation layer 160P, such as carbon (C). The upper ends of the contact sacrificial layer 129 and the initial contact insulation layer 160P may be coplanar with the uppermost interlayer insulation layer 121.

[0216] refer to Figure 13F and Figure 14C It can remove a portion of the vertical sacrificial structure 116 and form a channel structure CH and a dummy channel structure DCH.

[0217] A mask layer can be formed to expose only the region corresponding to the channel structure CH in the storage region R1 and the region corresponding to the dummy channel structure DCH in the upper contact region R3. Then, by removing the exposed vertical sacrificial structure 116, a channel via can be formed. At least a portion of the channel dielectric layer 145, channel layer 140, channel buried insulating layer 147, and channel pad 149 can be sequentially deposited inside the channel via to form the channel structure CH and the dummy channel structure DCH.

[0218] The channel dielectric layer 145 can be formed to have a uniform thickness using ALD or CVD processes. In this process, the channel dielectric layer 145 can be formed completely or partially, and a portion extending perpendicularly to the substrate 101 along the channel structure CH can be formed in this process. A channel layer 140 can be formed on the channel dielectric layer 145 within the channel vias. A channel buried insulating layer 147 can be formed to fill the channel vias and can be an insulating material. The channel pads 149 can be formed of a conductive material, such as polysilicon.

[0219] Therefore, it is possible to form such as Figure 14C The virtual channel structure DCH with a through-insulation structure 165 is cut in the middle, and can also be arranged in Figure 1 The virtual channel structure DCH between the through insulation structure 165 in the middle.

[0220] A portion of the vertical sacrificial structure 116 can be removed, and a supporting structure SH can be formed.

[0221] A mask layer can be formed in the region corresponding to the support structure SH in the exposed and extended region R2, and the exposed vertical sacrificial structure 116 can be removed to form a dummy via. The process of extending the dummy via can be performed by partially removing the molding structure MS around the dummy via. The extended dummy via can be filled with insulating material to form the support structure SH.

[0222] Reference Figure 13G The sacrificial insulating layer 118 can be removed and the gate electrode 130 can be formed.

[0223] It can be formed to open the corresponding Figure 1 and Figure 2B An isolation opening is provided in the region of the isolation area MS. The isolation opening can be formed by forming multiple vertical holes in the region where the isolation area MS is formed, expanding the multiple vertical holes through a cleaning process or the like, and connecting them to adjacent vertical holes. When the isolation opening is formed by expanding the multiple vertical holes, the side surfaces of the isolation opening may continuously include outwardly curved surfaces; however, the scope of the example embodiment is not limited thereto.

[0224] The sacrificial insulation layer 118 exposed through the isolation opening can be removed. The sacrificial insulation layer 118 can be selectively removed, for example, using wet etching, relative to the interlayer insulation layer 120, the channel structure CH, the dummy channel structure DCH, the through insulation structure 165, the support structure SH, and the initial contact insulation layer 160P.

[0225] The gate electrode 130 can be formed by depositing a conductive material on a region where the sacrificial insulating layer 118 has been removed. The conductive material may include a metal, polysilicon, or a metal silicide. A diffusion barrier 131 may be formed in the gate electrode 130 (see [link to documentation]). Figure 3A Conductive material can be deposited to form the gate electrode 130. In some example embodiments, a portion of the channel dielectric layer 145 can be formed before forming the gate electrode 130. Therefore, a stacked structure GS comprising the first stacked structure to the third stacked structure GS1-GS3 can be formed. After forming the gate electrode 130, insulating material can be deposited in the isolation opening to form an isolation region MS extending in the X direction, such as... Figure 1 As shown.

[0226] like Figure 14D As shown, a first insulating region SS1 and a second insulating region SS2 can be formed that penetrate the upper gate electrode 130U. For example... Figure 1 and Figure 2B As shown, trenches can be formed for removing the upper gate electrode 130U and the interlayer insulating layer 120 in the regions corresponding to the first insulating region SS1 and the second insulating region SS2.

[0227] Between two adjacent isolation regions MS, trenches corresponding to the first insulating region SS1 can be formed by selectively cutting the upper portion of the third stacked structure GS3. These trenches extend from the uppermost interlayer insulating layer 121 through the first upper gate electrode 130U1 to the seventh upper gate electrode 130U7, and extend along the X direction within the storage region R1 and the upper contact region R3. Similarly, trenches corresponding to the second insulating region SS2 can be formed by selectively cutting the upper portion of the third stacked structure GS3. These trenches also extend from the uppermost interlayer insulating layer 121 through the first upper gate electrode 130U1 to the seventh upper gate electrode 130U7, but extend along the Y direction between the upper contact region R3 and the extended region R2. The trenches can be extended by cutting a portion of the channel structure CH in the storage region R1, and the first insulating region SS1 and the second insulating region SS2 can be formed by stacking insulating material in each trench.

[0228] like Figure 13H As shown, a word line contact structure MC2 can be formed.

[0229] Specifically, the contact sacrificial layer 129 in the extended region R2 can be selectively removed for the initial contact insulation layer 160P, and the side and bottom surfaces of the initial contact insulation layer 160P can be exposed.

[0230] By performing a back etching process, the exposed bottom surface of the initial contact insulation layer 160P can be removed.

[0231] Therefore, the contact areas of the memory gate electrode 130M or the lower gate electrode 130L, which are distributed to the bottom surface, can be exposed. In the etch-back process, the gate electrode 130 can be used as an etch barrier layer, and anisotropic etching can be performed in the vertical direction by dry etching.

[0232] Conductive material can be deposited by filling contact hole OP2 to form contact plug 170. First, a contact barrier layer 171 can be formed along the side and bottom surfaces of contact hole OP2, and conductive material can be embedded in the contact barrier layer 171 to form contact plug 170. Contact plug 170 can be physically connected to the gate electrodes 130 distributed below. When filling the entire contact hole OP2, a planarization process can be performed to etch the conductive material until the upper surface of the uppermost interlayer insulating layer 121 is exposed.

[0233] In this case, a planarization process can be performed by chemical mechanical polishing (CMP), and accordingly, the upper surface of the uppermost interlayer insulating layer 121 and the upper surface of the contact plug 170 can be coplanar with each other.

[0234] Reference Figure 13I Interconnect structures can be formed on the stacked structure GS.

[0235] An upper insulating layer 194 can be formed on the stacked structure GS, and first to third pillars 180a, 180b and 180c and cell interconnects 185 can be formed by penetrating the upper insulating layer 194.

[0236] The second post 180b and the third post 180c can be formed by creating post holes that penetrate the upper insulating layer 194 and expose the contact plug 170, and filling the post holes with a conductive material. The first post 180a can be coaxial with the central axis l1 of the through insulating structure 165 in the upper contact region R3, can penetrate the upper insulating layer 194 and the through insulating structure 165, and can contact the upper gate electrode 130U.

[0237] Therefore, the first column 180a can have a longer length than the second column 180b and the third column 180c.

[0238] The first post 180a can be formed by creating a post hole that penetrates the upper insulating layer 194 and runs through the insulating structure 165, and filling the post hole with a conductive material. Unit interconnects 185 can be formed on posts 180a, 180b, and 180c. An insulating layer can be further formed on the unit interconnects 185, and a layer for connecting with... Figure 9 The bonding structure of the second semiconductor structure in the process.

[0239] Figure 15 This is a diagram illustrating a data storage system including a semiconductor device according to an example embodiment.

[0240] Reference Figure 15 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or as an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0241] Semiconductor device 1100 can be implemented as a non-volatile memory device, such as a reference. Figures 1 to 12The NAND flash memory device described in the foregoing example embodiments. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In the example embodiment, the first structure 1100F may be disposed on the side of the second structure 1100S. The first structure 1100F may be configured as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be configured as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0242] In the second structure 1100S, each of the memory cell strings CSTRs may include a plurality of memory cell transistors MCTs arranged between lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 and UT2 adjacent to the bit line BL, as well as lower transistors LT1 and LT2 and upper transistors UT1 and UT2. In the example embodiment, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0243] In the example embodiment, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be configured as gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be configured as gate electrode 130 of memory cell transistor MCT, and gate upper lines UL1 and UL2 may be configured as gate electrodes of upper transistors UT1 and UT2, respectively.

[0244] In an example embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other. At least one of the lower erase control transistor LT1 or the upper erase control transistor UT2 can be used for an erase operation that erases data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0245] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0246] In the first structure 1100F, the decoder circuit 1110 and page buffer 1120 can perform control operations on at least one of the plurality of memory cell transistors (MCTs) to select a memory cell transistor. The decoder circuit 1110 and page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output interconnects 1135 extending from the first structure 1100F to the second structure 1100S.

[0247] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0248] Processor 1210 can control the operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include controller interface 1221 for processing communication with semiconductor device 1100. Through controller interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be sent. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When receiving control commands from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0249] Figure 16 This is a perspective view illustrating a data storage system including a semiconductor device in an example embodiment.

[0250] Reference Figure 16The data storage system 2000 in the example embodiment may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 formed on the motherboard 2001.

[0251] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host via one of the following interfaces: Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Memory (UFS). In an example embodiment, the data storage system 2000 may operate via power supplied by the external host through the connector 2006. The data storage system 2000 may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0252] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0253] DRAM 2004 can be configured as a buffer memory to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can operate as a high-speed buffer memory and can provide space for temporary data storage during the control operation of the semiconductor package 2003. When the data storage system 2000 includes DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003.

[0254] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, adhesive layers 2300 disposed on the lower surfaces of the semiconductor chips 2200, bonding structures 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the bonding structures 2400 on the package substrate 2100.

[0255] The package substrate 2100 can be configured as a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 15 The input / output pads 1101 are included. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 may include a reference... Figures 1 to 12 The semiconductor device described in the foregoing example embodiments.

[0256] In an example embodiment, the bonding structure 2400 can be configured to electrically connect the input / output pads 2210 to bonding lines on the package-on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 can be electrically connected to each other via bonding lines and can be electrically connected to the package-on-package pads 2130 of the package substrate 2100. In an example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 can be electrically connected to each other via a bonding structure 2400 that includes a through-electrode (TSV) instead of a bonding line method.

[0257] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a different interposer substrate than the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected with each other via interconnects formed on the interposer substrate.

[0258] According to the foregoing example embodiments, when the upper gate electrode includes a string select gate electrode, a stepped structure in the form of a ladder may not be formed in the string select gate electrode, and space for arranging string select contact plugs in the allocated string select gate electrode can be formed by an insulating structure. Furthermore, similar to word line select plugs, an insulating structure can be formed to expose the allocated string select gate electrode through etching performed in multiple steps. Therefore, a stepped structure in the form of a ladder and a dummy step structure for the gate electrode can be avoided, ensuring the area of ​​the memory cell region and thus enabling high integration.

[0259] Therefore, a stepped structure can be formed in the area where the word line contact structure is arranged, and a stepped structure can also be formed in the area where the string selection contact plug is arranged, which simplifies the process.

[0260] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes a first region, a second region, and a third region between the first region and the second region; A stacked structure includes a gate electrode and an interlayer insulating layer. The gate electrode includes a lower gate electrode, a memory gate electrode, and an upper gate electrode that are sequentially stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the substrate. The interlayer insulating layer is arranged alternately with the gate electrode in the first region, the second region, and the third region. A channel structure that penetrates the stacked structure and extends along the first direction in the first region; A support structure that penetrates the stacked structure and extends along the first direction in the third region; The first contact structure, in the third region, extends to different lengths in the first direction by penetrating the uppermost interlayer insulating layer or penetrating at least a portion of the upper gate electrode, and the first contact structure is electrically connected to the upper gate electrode respectively. as well as The second contact structure, in the second region, extends for different lengths in the first direction from the uppermost interlayer insulating layer by penetrating at least a portion of the gate electrodes, including the upper gate electrode, the memory gate electrode, and the lower gate electrode. The second contact structure is electrically connected to the lower gate electrode and the memory gate electrode, respectively. Each of the first contact structures includes: The electrode penetrates the insulating structure, extends along the first direction and penetrates the uppermost interlayer insulating layer or at least a portion of the upper gate electrode, and contacts the upper surface of a portion of the upper gate electrode; and The first pillar extends along the first direction by penetrating the through-insulation structure and contacts the upper surface of the allocated upper gate electrode. Some of the supporting structures are in contact with at least a portion of the through-insulation structure.

2. The semiconductor device according to claim 1, wherein, The first column is physically separated from the supporting structure.

3. The semiconductor device according to claim 1, in, The first contact structures are spaced apart by a first interval distance, and A portion of the stacked structure is arranged in the spaced area between the first contact structures.

4. The semiconductor device according to claim 3, wherein, Some of the support structures are arranged in the interval area.

5. The semiconductor device according to claim 1, wherein, The support structure is a dummy channel structure, and each dummy channel structure has the same shape as the channel structure.

6. The semiconductor device according to claim 1, in, The through-insulation structure includes: upper surface; The lower surface is in contact with the allocated upper gate electrode; The inner surface contacts the first post between the upper and lower surfaces; and The outer surface contacts the interlayer insulating layer and / or the upper gate electrode, and The side surface of the first pillar is physically separated from the interlayer insulating layer and the upper gate electrode.

7. The semiconductor device according to claim 6, wherein, The upper surface of the stacked structure is coplanar with the upper surface of the through-insulation structure.

8. The semiconductor device according to claim 6, wherein, The upper surface of the first column is positioned at a level higher than the level of the upper surface of the through insulation structure.

9. The semiconductor device according to claim 6, wherein, The width of the upper surface of the first column is less than 1 / 3 to 1 / 4 of the width of the upper surface of the through insulation structure.

10. The semiconductor device according to claim 6, wherein, The upper surface of the support structure is coplanar with the upper surface of the through insulation structure.

11. The semiconductor device according to claim 6, wherein, At least one of the support structures is arranged between the inner surface and the outer surface of the through-insulation structure.

12. The semiconductor device according to claim 1, wherein, At least one of the support structures protrudes into the through-insulation structure at a diameter of 1 / 2 or less.

13. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A first insulating region, penetrating the upper gate electrode in the first region and the third region, extending along a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first and second directions; and A second insulating region is connected to the first insulating region, penetrates the upper gate electrode between the third region and the second region, and extends along the third direction.

14. The semiconductor device according to claim 1, wherein, Each of the second contact structures includes: A contact plug penetrates the stacked structure and contacts the upper surface of the assigned gate electrode in the lower gate electrode and the memory gate electrode; and A side insulating layer surrounds the side surface of the contact plug and is disposed between the stack structure and the contact plug.

15. The semiconductor device according to claim 14, wherein, The thickness of the through insulation structure is greater than the thickness of the side insulation layer.

16. A semiconductor device, comprising: The substrate includes a first region, a second region, and a third region between the first region and the second region; A stacked structure includes a gate electrode and an interlayer insulating layer. The gate electrode includes a lower gate electrode, a memory gate electrode, and an upper gate electrode that are sequentially stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the substrate. The interlayer insulating layer is arranged alternately with the gate electrode in the first region, the second region, and the third region. A channel structure that penetrates the stacked structure and extends along the first direction in the first region; A support structure, penetrating the stacked structure, extends along the first direction in the third region and is spaced apart from each other by a first distance; The first contact structure, in the third region, extends to different lengths in the first direction by penetrating the uppermost interlayer insulating layer or penetrating at least a portion of the upper gate electrode, the first contact structure being electrically connected to the upper gate electrode respectively, and having an upper surface having a first width; as well as The second contact structure, in the second region, extends for different lengths in the first direction from the uppermost interlayer insulating layer by penetrating at least a portion of the gate electrodes, including the upper gate electrode, the memory gate electrode, and the lower gate electrode. The second contact structure is electrically connected to the lower gate electrode and the memory gate electrode, respectively. Wherein, the first width of the first contact structure is greater than the first distance.

17. The semiconductor device according to claim 16, in, Each of the first contact structures includes: The electrode penetrates the insulating structure, extends along the first direction and penetrates the uppermost interlayer insulating layer or at least a portion of the upper gate electrode, and contacts the upper surface of a portion of the upper gate electrode; and A first post, extending along the first direction, penetrates the through-insulation structure and contacts the upper surface of the allocated upper gate electrode, and The supporting structure is spaced apart from the first pillar.

18. The semiconductor device according to claim 16, in, The first contact structures are spaced apart by a second distance, and A portion of the support structure is arranged within the second distance.

19. The semiconductor device of claim 16, further comprising: A shared through-insulation structure, with multiple first posts commonly surrounding the first contact structure. The plurality of first pillars that penetrate the shared through-insulation structure are in contact with the same upper gate electrode in the upper gate electrode.

20. A data storage system, comprising: A semiconductor memory device includes a first semiconductor structure containing circuitry, a second semiconductor structure disposed on a surface of the first semiconductor structure, and input / output pads electrically connected to the circuitry. as well as The controller is electrically connected to the semiconductor memory device via the input / output pads and controls the semiconductor memory device. The second semiconductor structure includes: The substrate includes a first region, a second region, and a third region between the first region and the second region; A stacked structure includes a gate electrode and an interlayer insulating layer. The gate electrode includes a lower gate electrode, a memory gate electrode, and an upper gate electrode that are sequentially stacked and spaced apart from each other in a first direction perpendicular to the upper surface of the substrate. The interlayer insulating layer is arranged alternately with the gate electrode in the first region, the second region, and the third region. A channel structure that penetrates the stacked structure and extends along the first direction in the first region; The support structures, in the third region, penetrate the stacked structure, extend along the first direction, and are spaced apart from each other by a first distance; A first contact structure, in the third region, extends to different lengths in the first direction by penetrating either the uppermost interlayer insulating layer or at least a portion of the upper gate electrode, the first contact structure being electrically connected to the upper gate electrode, and having an upper surface having a first width; and The second contact structure, in the second region, extends for different lengths in the first direction from the uppermost interlayer insulating layer by penetrating at least a portion of the gate electrodes, including the upper gate electrode, the memory gate electrode, and the lower gate electrode. The second contact structure is electrically connected to the lower gate electrode and the memory gate electrode, respectively. Wherein, the first width of the first contact structure is greater than the first distance.

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