Semiconductor device

Abstract

A semiconductor device includes a peripheral circuit structure and a cell structure, the cell structure including a cell region and a connection region; wherein the cell structure includes: gate electrodes and mold insulating layers alternately stacked in a vertical direction; a channel structure located in the cell region and extending vertically through the gate electrodes; dummy plugs located in the connection region and extending vertically through the gate electrodes; cell plugs located in the connection region and contacting selected electrodes and passing through unselected electrodes at different vertical levels from the selected electrodes; and insulating spacers located on side surfaces of each cell plug.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more specifically, to a semiconductor device including a cell plug. Background Technology

[0002] In electronic systems that require data storage, semiconductor devices capable of storing large amounts of data are needed. Therefore, methods to increase the data storage capacity of semiconductor devices have been investigated. For example, to increase the data storage capacity of semiconductor devices, semiconductor devices comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0003] This disclosure provides a semiconductor device including multiple cell plugs that improve the structural stability of the molded insulating layer by preventing collapse during word line pull back, and eliminates the need for dummy plug pull back processes to increase space utilization, thereby achieving high integration density and excellent electrical characteristics.

[0004] However, the purpose of this disclosure is not limited to those mentioned above, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0005] According to one aspect of this disclosure, a semiconductor device is provided, the semiconductor device including a peripheral circuit structure; and a cell structure, the cell structure being located on the peripheral circuit structure and including a cell region and a connection region, wherein the cell structure includes: a gate electrode and a molded insulating layer, the gate electrode and the molded insulating layer being located in the cell region and the connection region and being alternately stacked in a vertical direction; a channel structure being located in the cell region and extending through the gate electrode and the molded insulating layer along the vertical direction; a plurality of dummy plugs being located in the connection region and extending through the gate electrode along the vertical direction; and a plurality of cell plugs being located in the connection region and contacting the gate electrode. The selected electrode passes through an unselected electrode among the gate electrodes, the unselected electrode being at a different vertical height from the selected electrode; and an insulating spacer is located on the side surface of each of the plurality of unit plugs, wherein each of the plurality of unit plugs has a first length in a first direction and a second length in a second direction intersecting the first direction, the first length being greater than the second length, each of the plurality of unit plugs having a first long side and a second long side extending in the first direction, and having a first short side and a second short side extending in the second direction, and the plurality of dummy plugs are arranged in the first direction and spaced apart by a specific distance from at least one of the first long side and the second long side in the second direction.

[0006] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a peripheral circuit structure; and a cell structure, the cell structure being located on the peripheral circuit structure and including a cell region and a connection region, wherein the cell structure includes: a gate electrode and a molded insulating layer, the gate electrode and the molded insulating layer being located in the cell region and the connection region and being alternately stacked in a vertical direction; a channel structure being located in the cell region and extending along the vertical direction through the gate electrode and the molded insulating layer; a plurality of dummy plugs being located in the connection region and extending along the vertical direction through the gate electrode and the molded insulating layer; a plurality of cell plugs being located in the connection region, contacting a selected electrode among the gate electrodes and passing through an unselected electrode among the gate electrodes, the unselected electrode being at a different vertical height from the selected electrode; and a plurality of insulating spacers, wherein... The plurality of insulating spacers are located on the side surface of each of the plurality of unit plugs and spaced apart in the vertical direction, and each is located between each of the unselected electrodes and each of the plurality of unit plugs, wherein each of the plurality of insulating spacers includes an outer surface and an inner surface, the outer surface contacting each of the unselected electrodes and the inner surface contacting the outer surface of each of the plurality of unit plugs, wherein the height of each of the plurality of insulating spacers in the vertical direction is substantially the same as the height of the corresponding unselected electrode in the vertical direction, wherein each of the plurality of unit plugs has a first length in a first direction and a second length in a second direction intersecting the first direction, the first length being greater than the second length, and wherein the plurality of dummy plugs are spaced apart in the first direction while maintaining a specific distance from each of the plurality of unit plugs in the second direction.

[0007] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a peripheral circuit structure; and a cell structure located on the peripheral circuit structure and including a cell region and a connection region, wherein the cell structure includes: a gate electrode and a molded insulating layer, the gate electrode and the molded insulating layer being located in the cell region and the connection region and being alternately stacked in a vertical direction; a channel structure located in the cell region and extending along the vertical direction through the gate electrode and the molded insulating layer; a plurality of dummy plugs located in the connection region and extending along the vertical direction through the gate electrode and the molded insulating layer; a plurality of cell plugs located in the connection region, the plurality of cell plugs contacting a selected electrode among the gate electrodes and passing through an unselected electrode among the gate electrodes, the unselected electrode being at a different vertical height from the selected electrode; and an insulating spacer located on the side surface of each of the plurality of cell plugs. On the surface, each of the gate electrodes includes a conductive layer and a coating surrounding the conductive layer, the insulating spacer includes an outer surface and an inner surface, the outer surface contacts the unselected electrode and the molded insulating layer, and the inner surface contacts the outer surface of each of the plurality of unit plugs, each of the plurality of unit plugs contacts the conductive layer of the selected electrode, the coating of the selected electrode contacts a portion of the side surface of each of the plurality of unit plugs, each of the plurality of unit plugs has a first length in a first direction and a second length in a second direction intersecting the first direction, the first length being greater than the second length, wherein each of the plurality of unit plugs has a first long side and a second long side extending in the first direction, and has a first short side and a second short side extending in the second direction, and wherein the plurality of dummy plugs are spaced apart in the first direction and spaced apart by a specific distance from at least one of the first long side and the second long side in the second direction. Attached Figure Description

[0008] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram of a semiconductor device according to an embodiment; Figure 2 This is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an embodiment; Figure 3 This is a perspective view of a representative configuration of semiconductor devices according to an embodiment; Figure 4A and Figure 4B yes Figure 3 A top view of a semiconductor device; Figure 5 It is along Figure 4A The line AA' intercepted Figure 4A A schematic cross-sectional view of a semiconductor device; Figure 6A yes Figure 5 A schematic enlarged view of regions DX1 and CX1; Figure 6B yes Figure 5 A schematic enlarged view of the modification example for region CX1; Figure 7 , Figure 8 , Figure 9 and Figure 10 This is a schematic top view of a semiconductor device according to an embodiment; Figure 11 This is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment; Figure 12 yes Figure 11 A schematic enlarged view of region CX1; Figure 13 This is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment; and Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 and Figure 27 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0009] In the following description, embodiments will be illustrated in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same parts, and redundant descriptions thereof are omitted.

[0010] Figure 1 This is a block diagram of the semiconductor device 10 according to an embodiment.

[0011] refer to Figure 1The semiconductor device 10 may include a memory cell array 20 and peripheral circuitry 30. The memory cell array 20 may include multiple memory cell blocks BLK1, BLK2, ..., and BLKn. Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKn may include multiple memory cells. The memory cell blocks BLK1, BLK2, ..., and BLKn may be connected to the peripheral circuitry 30 via bit lines BL, word lines WL, serial select lines SSL, and ground select lines GSL.

[0012] The peripheral circuitry 30 may include a row decoder 32, a page buffer 34, a data input / output (I / O) circuit 36, and a control logic circuit 38. For example, the peripheral circuitry 30 may also include an I / O interface, column logic circuitry, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, etc.

[0013] The cell array 20 can be connected to the page buffer 34 via bit lines BL and to the row decoder 32 via word lines WL, string select lines SSL, and ground select lines GSL. In the cell array 20, each of the multiple memory cells included in multiple cell blocks BLK1, BLK2, ..., and BLKn can be a flash memory cell. The cell array 20 can include a three-dimensional (3D) cell array. The three-dimensional (3D) cell array can include multiple NAND strings, and each NAND string can include multiple memory cells connected to multiple word lines WL vertically stacked on a substrate.

[0014] The peripheral circuit 30 can receive address ADDR, command CMD and control signal CTRL from the outside of the semiconductor device 10, and can send data DATA to external devices outside the semiconductor device 10 and receive data DATA from external devices outside the semiconductor device 10.

[0015] The row decoder 32 can select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., and BLKn in response to an external address ADDR, and can select the word line WL, serial select line SSL, and ground select line GSL of the selected memory cell block. The row decoder 32 can send a voltage for performing a memory operation to the word line WL of the selected memory cell block.

[0016] Page buffer 34 can be connected to memory cell array 20 via bit line BL. During programming operations, page buffer 34 can operate as an input driver to apply a voltage to bit line BL according to the data DATA to be stored in memory cell array 20. During read operations, page buffer 34 can operate as a sense amplifier to sense the data DATA stored in memory cell array 20. Page buffer 34 can be operated according to the control signal PCTL provided from control logic circuitry 38.

[0017] Data I / O circuit 36 ​​can be connected to page buffer 34 via data line DL. During programming operations, data I / O circuit 36 ​​can receive data DATA from the memory controller and can provide programming data DATA to page buffer 34 based on the column address C_ADDR provided from control logic circuit 38. During read operations, data I / O circuit 36 ​​can provide read data DATA stored in page buffer 34 to the memory controller based on the column address C_ADDR provided from control logic circuit 38.

[0018] Data I / O circuit 36 ​​can send addresses or commands input to it to control logic circuit 38 or line decoder 32. Peripheral circuitry 30 may also include electrostatic discharge (ESD) circuitry and pull-up / pull-down drivers.

[0019] Control logic circuit 38 can receive commands CMD and control signals CTRL from the memory controller. Control logic circuit 38 can provide row address R_ADDR to row decoder 32 and column address C_ADDR to data I / O circuit 36. Control logic circuit 38 can generate various internal control signals used in semiconductor device 10 in response to control signal CTRL. For example, control logic circuit 38 can adjust the voltage levels supplied to word line WL and bit line BL during memory operations such as programming or erasing operations.

[0020] Figure 2 This is an equivalent circuit diagram of the memory cell array MCA of the semiconductor device 10 according to an embodiment.

[0021] refer to Figure 2 A memory cell array (MCA) may include multiple memory cell strings (MS). The MCA may include multiple bit lines (BL) (e.g., BL1, BL2, ..., BLm), multiple word lines (WL) (e.g., WL1, WL2, ..., WLn-1, and WLn), at least one string select line (SSL), at least one ground select line (GSL), and a common source line (CSL). The multiple memory cell strings (MS) may be formed between the multiple bit lines (BL) (e.g., BL1, BL2, ..., BLm) and the common source line (CSL). Figure 2An example is shown in which each of the plurality of memory cell strings (MS) includes two string select lines (SSL), but this disclosure is not limited thereto. In another example, each of the plurality of memory cell strings (MS) may include a single string select line (SSL).

[0022] Each memory cell string (MS) may include a string select transistor (SST), a ground select transistor (GST), and multiple memory cell transistors (MC1, MC2, ..., MCn-1 and MCn). The drain region of the string select transistor (SST) may be connected to bit lines BL (BL1, BL2, ..., or BLm), and the source region of the ground select transistor (GST) may be connected to a common source line (CSL). The common source line (CSL) may be the region where the source regions of multiple ground select transistors (GST) are connected together.

[0023] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to multiple word lines WL (e.g., WL1, WL2, ..., WLn-1 and WLn).

[0024] Figure 3 This is a perspective view of a representative configuration of the semiconductor device 100 according to an embodiment. Figure 4A yes Figure 3 A top view of the semiconductor device 100. Figure 5 It is along Figure 4A The line A-A' intercepts Figure 4A A schematic cross-sectional view of the semiconductor device 100. Figure 6A yes Figure 5 A schematic enlarged view of regions DX1 and CX1.

[0025] refer to Figure 3 , Figure 4A , Figure 4B , Figure 5 and Figure 6A The semiconductor device 100 may include a cell structure CS and a peripheral circuit structure PS that overlap each other in the vertical direction Z. The cell structure CS may include a reference Figure 1 The described memory cell array 20, and the peripheral circuit structure PS may include references Figure 1 The peripheral circuit 30 is described.

[0026] The cell structure CS may include multiple storage cell blocks BLK1, BLK2, ... and BLKn. Each of the multiple storage cell blocks BLK1, BLK2, ... and BLKn may include storage cells arranged in three dimensions.

[0027] The peripheral circuit structure PS may include peripheral circuit transistors 120TR disposed on substrate 110. An active region AC may be defined in substrate 110 by device isolation layer 112, and a plurality of peripheral circuit transistors 120TR may be formed on the active region AC. Each of the plurality of peripheral circuit transistors 120TR may include a peripheral circuit gate 120G and a source / drain region 122, the source / drain regions 122 being disposed on both sides (e.g., opposite sides) of a portion of substrate 110 of the peripheral circuit gate 120G.

[0028] Substrate 110 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, a group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Substrate 110 may be provided as a bulk wafer or an epitaxial layer. In another embodiment, substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0029] Multiple peripheral circuit contacts 132 and multiple peripheral circuit wiring layers 134 may be disposed on the upper surface of the substrate 110. An interlayer insulating layer 130 covering multiple peripheral circuit transistors 120TR, multiple peripheral circuit contacts 132, and multiple peripheral circuit wiring layers 134 may be disposed on the substrate 110. The multiple peripheral circuit wiring layers 134 may include a multilayer structure comprising multiple metal layers disposed at different vertical heights. Connection pads 260 may be disposed on the interlayer insulating layer 130, and peripheral circuit structures PS and cell structures CS may be electrically connected and bonded to each other by / through the connection pads 260.

[0030] The cell structure CS can include the cell region MCR, the connection region CON, and the peripheral circuit connection region PRC.

[0031] The cell region MCR can be a region in which a block of memory cells BLK comprising multiple strings of memory cells extending in the vertical direction Z is arranged. In the cell region MCR, a common source layer 210, a gate electrode 230, and a channel structure 240 extending through the gate electrode 230 in the vertical direction Z and connected to the common source layer 210 can be arranged.

[0032] In the connection region CON, a plurality of gate extensions 230E connected to the gate electrode 230, a plurality of cell plugs CP electrically connected to the plurality of gate extensions 230E respectively, and a plurality of dummy plugs DP may be arranged.

[0033] In the peripheral circuit connection area PRC, peripheral plugs PP that extend in the vertical direction Z and are electrically connected to the peripheral circuit wiring layer 134 can be arranged.

[0034] The unit structure CS may include a first surface CS_1 connected to the peripheral circuit structure PS and a second surface CS_2 opposite to the first surface CS_1. For example... Figure 5 As shown, the first surface CS_1 of the unit structure CS can be arranged on the lower side of the unit structure CS, and the second surface CS_2 of the unit structure CS can be arranged on the upper side of the unit structure CS.

[0035] For ease of description, such as Figure 5 As shown, the arrangement of the first surface CS_1, which is closer to the unit structure CS, is referred to as the arrangement at a lower vertical height, and the arrangement of the second surface CS_2, which is closer to the unit structure CS, is referred to as the arrangement at a higher vertical height.

[0036] Gate electrodes 230 can be arranged in the cell region MCR to be spaced apart from each other in the vertical direction Z, and gate electrodes 230 can be alternated with the molded insulating layer 232. Gate electrodes 230 can extend to the connection region CON, and the portion of gate electrodes 230 arranged in the connection region CON can be referred to as gate extension 230E. Gate extensions 230E can be arranged to be spaced apart from each other in the vertical direction Z, and can have the same width in the first horizontal direction X. For example, the side surfaces of gate electrodes 230 can be aligned with each other in the vertical direction Z.

[0037] In an embodiment, the gate electrode 230 may correspond to the memory cell string MS (see [link to documentation]). Figure 2 The memory cell string (MS) includes a ground select transistor (GSL), word lines WL1 to WLn, and at least one string select line (SSL). For example, the uppermost gate electrode 230 can be used as the ground select line GSL, the two lowermost gate electrodes 230 can be used as the string select lines SSL, and the remaining gate electrodes 230 can be used as word lines WL1 to WLn. Therefore, the memory cell string (MS) may include a ground select transistor (GST), a string select transistor (SST), and memory cell transistors MC1 to MCn. Memory cell transistors MC1 to MCn may be disposed between the ground select transistor (GST) and the string select transistor (SST), and may be connected in series with each other. In some embodiments, at least one of the gate electrodes 230 may be used as a dummy word line, but the embodiments are not limited thereto.

[0038] A stacked isolation insulating layer WLI can be disposed in a stacked isolation opening WLH extending in the vertical direction Z through the gate electrode 230 and the molded insulating layer 232. The stacked isolation insulating layer WLI can have an upper surface disposed at a higher vertical height than the uppermost gate electrode 230 and can protrude upward relative to the uppermost gate electrode 230. In some embodiments, the gate electrode 230 disposed between pairs of stacked isolation openings WLH can form a single body.

[0039] The channel structure 240 can be arranged in a channel hole 240H extending in the vertical direction Z through the gate electrode 230 and the molded insulating layer 232. The channel structure 240 may include a gate insulating layer 242, a channel layer 244, a buried insulating layer 246, and a drain region 248. The gate insulating layer 242, the channel layer 244, and the buried insulating layer 246 can be sequentially arranged on the inner wall of the channel hole 240H.

[0040] The channel structure 240 may include a first end 240x disposed near the peripheral circuit structure PS and a second end 240y opposite to the first end 240x. In an embodiment, the channel structure 240 may have inclined side surfaces such that the width of the first end 240x may be greater than the width of the second end 240y.

[0041] A drain region 248 electrically connected to the channel layer 244 can be disposed at the first end 240x of the channel structure 240. The drain region 248 can be connected to the bit line contact BLC, and the channel layer 244 can be electrically connected to the bit line BL through the drain region 248 and the bit line contact BLC. At the second end 240y of the channel structure 240, the upper surface of the channel layer 244 may not be covered by the gate insulating layer 242, and the common source layer 210 can be connected to the upper surface of the channel layer 244.

[0042] In some embodiments, the gate insulating layer 242 may have a structure comprising, sequentially, a tunneling dielectric layer, a charge storage layer, and a barrier dielectric layer on the outer surface of the channel layer 244. The charge storage layer may be a region that stores electrons passing through the tunneling dielectric layer from the channel layer 244, and may comprise silicon nitride, boron nitride, boron silicon nitride, or doped polysilicon.

[0043] In some embodiments, the charge storage layer may include a ferroelectric dielectric material. For example, the charge storage layer may include a metal oxide having ferroelectric properties. For example, the charge storage layer may include a ferroelectric material capable of storing data through hysteresis behavior in response to a voltage applied to the charge storage layer. In embodiments, the charge storage layer may include at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0044] An etch stop layer 222 may be disposed on the uppermost gate electrode 230, and the etch stop layer 222 may comprise polysilicon. In some embodiments, the etch stop layer 222 may be omitted.

[0045] The common source layer 210 can be conformally formed on the etch stop layer 222, connected to the second end 240y of the channel structure 240, and covering the upper surface of the stacked isolation insulating layer WLI. In a top view, the common source layer 210 can be arranged (or extended) over the entire area of ​​the cell region MCR.

[0046] In some embodiments, the common source layer 210 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The common source layer 210 may include a semiconductor doped with n-type impurities. The common source layer 210 may have a crystal structure including at least one selected from single-crystal structures, amorphous structures, and polycrystalline structures. In some embodiments, the common source layer 210 may include polycrystalline silicon doped with n-type impurities.

[0047] Between the stacked overlay insulating layer 234 and the peripheral circuit structure PS, connection paths 252, connection wiring layers 254, and interlayer insulating layers 256 surrounding the connection paths 252 and connection wiring layers 254 can be arranged in multiple layers at different vertical heights, and bit lines BL, cell plugs CP, and peripheral plugs PP can be electrically connected to the peripheral circuit structure PS via connection pads 260.

[0048] The gate electrode 230 may extend horizontally (e.g., in a first horizontal direction X and / or a second horizontal direction Y) within the cell region MCR and the connection region CON. The gate electrode 230 disposed in the connection region CON is referred to as a gate extension 230E. Within the connection region CON, the gate extensions 230E may overlap each other in the vertical direction Z. For example, gate extensions 230E disposed at different vertical heights within the connection region CON may have the same width in the horizontal direction.

[0049] In some embodiments, each gate electrode in the gate electrode 230 may include a conductive layer 2301 and a coating 2302 surrounding the conductive layer 2301. The coating 2302 may be conformally formed on the surface of the conductive layer 2301 of each gate electrode 230. For example, the coating 2302 may include an upper wall formed on the upper surface of the conductive layer 2301, a lower wall formed on the lower surface of the conductive layer 2301, and a sidewall 2302_SW connecting the upper wall and the lower wall to each other. In another embodiment, a portion of the coating 2302 of each gate electrode 230 may be removed, and a portion of the conductive layer 2301 of each gate electrode 230 may be exposed to the outside through the removed portion of the coating 2302.

[0050] In some embodiments, the conductive layer 2301 of each gate electrode 230 may include a metal (such as tungsten, nickel, cobalt, or tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), doped polycrystalline silicon, or a combination thereof. In some embodiments, the coating 2302 of each gate electrode 230 may include an insulating material, such as aluminum oxide (Al₂O₃). x O y ), silicon dioxide (SiO)x ) or titanium dioxide (TiO) x ).

[0051] In the connection region CON, multiple cell plugs CP can extend in the vertical direction Z through the stacked overlay insulating layer 234, the molded insulating layer 232, and the gate extension 230E. The multiple cell plugs CP can have different heights in the vertical direction Z. For example, each cell plug in the multiple cell plugs CP can have a different height depending on the gate electrode 230 to which each cell plug in the multiple cell plugs CP is connected. For example, each cell plug in the multiple cell plugs CP can pass through a different number of gate electrodes 230.

[0052] Each of the multiple cell plugs CP may include a plurality of first side portions CPS1 and a plurality of second side portions CPS2 arranged alternately with each other. The plurality of first side portions CPS1 may correspond to the first side surfaces 2301_S1 of the plurality of gate electrodes 230, and the plurality of second side portions CPS2 may correspond to the side surfaces of the molded insulating layer 232.

[0053] In an embodiment, each of the plurality of cell plugs CP may include a first end CPx and a second end CPy. The first ends CPx of the plurality of cell plugs CP may all be arranged at the same vertical height, and may be arranged at the same vertical height as the upper surface of the stacked overlay insulating layer 234. The second ends CPy of the plurality of cell plugs CP may be arranged at different vertical heights. For example, the second ends CPy of the plurality of cell plugs CP may be located on gate electrodes 230 with different vertical heights.

[0054] The gate electrode 230 may include a selected electrode 230_S and an unselected electrode 230_N. Each of the plurality of cell plugs CP may contact one of the gate electrodes 230. For example, the selected electrode 230_S may be the gate electrode 230 that contacts a cell plug (e.g., a single cell plug) CP. For example, the gate electrode 230 that contacts a cell plug CP may be referred to as the gate electrode 230 corresponding to the cell plug (e.g., a single cell plug) CP.

[0055] For example, the plug CP can contact the conductive layer 2301 of the selected electrode 230_S to be electrically connected to the selected electrode 230_S. The surface CP_S of the plug CP can contact the conductive layer 2301 of the selected electrode 230_S. The side surface of the plug CP and the coating 2302 of the selected electrode 230_S can be spaced apart from each other by an insulating spacer 236 therebetween.

[0056] The unselected electrode 230_N can be one of the gate electrodes 230 located below the selected electrode 230_S. For example, the unselected electrode 230_N can be one of the gate electrodes 230 located between the stacked overlay insulating layer 234 and the selected electrode 230_S. For example, the cell plug CP can extend in the vertical direction Z from the stacked overlay insulating layer 234 through the unselected electrode 230_N and the molded insulating layer 232 to the selected electrode 230_S.

[0057] In an embodiment, each of the plurality of unit plugs CP may include a metal (such as tungsten, nickel, cobalt or tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide or tantalum silicide), doped polysilicon or a combination thereof.

[0058] The insulating spacer 236 may be located on the side surface of each of the plurality of unit plugs CP. For example, the side surface of each of the plurality of unit plugs CP may be surrounded (e.g., completely surrounded) by the insulating spacer 236. For example, the insulating spacer 236 may be arranged between the side surface of the unit plug CP and the side surface of the unselected electrode 230_N and the molded insulating layer 232. Thus, the insulating spacer 236 can insulate (e.g., electrically isolate) each of the plurality of unit plugs CP from the unselected electrode 230_N.

[0059] In an embodiment, the surface CP_S (e.g., the upper surface) of the unit plug CP may be electrically connected to the selected electrode 230_S. The side surfaces of the unit plug CP may not be electrically connected to the unselected electrode 230_N, which is disposed at a lower vertical height than the selected electrode 230_S. For example, an insulating spacer 236 may be located between the unselected electrode 230_N and the side surface of the unit plug CP, which is disposed at a lower vertical height than the selected electrode 230_S. Therefore, the unselected electrode 230_N and the side surface of the unit plug CP may be insulated from each other.

[0060] In an embodiment, the insulating spacer 236 may have an annular horizontal cross-section. For example, the inner surface of the insulating spacer 236 may contact the cell plug CP, and the outer surface of the insulating spacer 236 may contact the molded insulating layer 232 and the unselected electrode 230_N.

[0061] In some embodiments, the insulating spacer 236 may include silicon oxide. In some embodiments, the insulating spacer 236 may include silicon oxide containing a small amount (e.g., 5 atomic percent (at%) or less) of one of the elements comprising chlorine, fluorine, and bromine.

[0062] Each unselected electrode 230_N may include a first side surface 230_N_S1. The first side surface 230_N_S1 of each unselected electrode 230_N may contact the outer surface of the insulating spacer 236. For example, when the cell plug CP passes through the unselected electrode 230_N, the side surface of the hole defined in each unselected electrode of the unselected electrode 230_N may correspond to the first side surface 230_N_S1 of the unselected electrode 230_N.

[0063] The coating 2302 may be located between the first side surface 230_N_S1 of each unselected electrode 230_N and the insulating spacer 236. For example, the first side surface 2301_S1 of the conductive layer 2301 of each unselected electrode 230_N may be covered (e.g., completely covered) by the sidewall 2302_SW of the coating 2302. For example, the second side surface 2301_S2 of the conductive layer 2301 of each unselected electrode 230_N may be horizontally spaced from the insulating spacer 236, wherein the sidewall 2302_SW of the coating 2302 is located between the second side surface 2301_S2 and the insulating spacer 236.

[0064] The outer surface of the insulating spacer 236 can contact the sidewall 2302_SW of the coating 2302 of each unselected electrode 230_N, and the inner surface of the insulating spacer 236 can contact the side surface of the cell plug CP.

[0065] Refer again Figure 5 Multiple dummy plugs (DPs) can be located within the connection region CON. Each dummy plug in the multiple dummy plugs (DPs) can pass through the gate electrode 230 and the molded insulating layer 232. Each dummy plug in the multiple dummy plugs (DPs) can extend in the vertical direction Z. Each dummy plug in the multiple dummy plugs (DPs) can extend in the vertical direction Z from the stacked overlay insulating layer 234 to the upper insulating layer 272, and can pass through the gate electrode 230 and the molded insulating layer 232.

[0066] In some embodiments, the length of each dummy plug in the plurality of dummy plugs DP in the vertical direction Z can be greater than the length of each unit plug in the plurality of unit plugs CP in the vertical direction Z. For example, the number of gate electrodes 230 penetrated by each dummy plug in the plurality of dummy plugs DP can be greater than the number of gate electrodes 230 penetrated by each unit plug in the plurality of unit plugs CP.

[0067] Multiple dummy plugs (DPs) can be arranged around each of multiple element plugs (CPs). In the process of forming the multiple element plugs (CPs), the multiple dummy plugs (DPs) can suppress the sacrificial layer 310 (see [link to documentation]). Figure 18AThe tilting or bending of the gate electrode 230 and the molded insulating layer 232 ensures structural stability.

[0068] refer to Figure 6A Each gate electrode in the gate electrode 230 may include a second side surface 230_S2 facing the dummy plug (e.g., a single dummy plug) DP. For example, when the dummy plug DP passes through each gate electrode 230, the side surface of each gate electrode 230 defining the hole formed in each gate electrode 230 may be the second side surface 230_S2 of each gate electrode 230.

[0069] The second side surface 2301_S2 of the conductive layer 2301 of each gate electrode 230 can face the outer surface DP_S of the dummy plug DP, and the sidewall 2302_SW of the coating 2302 of each gate electrode 230 can cover the second side surface 2301_S2 of the conductive layer 2301.

[0070] For example, the second side surface 2301_S2 of the conductive layer 2301 of each gate electrode 230 can be covered (e.g., completely covered) by the sidewall 2302_SW of the coating 2302 of each gate electrode 230. For example, the second side surface 2301_S2 of the conductive layer 2301 of each gate electrode 230 can be spaced apart from the dummy plug DP in the horizontal direction, wherein the sidewall 2302_SW of the coating 2302 is located between the second side surface 2301_S2 and the dummy plug DP.

[0071] The second side surface 230_S2 of each gate electrode 230 can be the outer side surface 2302_SWO of the sidewall 2302_SW of the coating 2302 of each gate electrode 230. A dummy plug DP can contact the outer side surface 2302_SWO of the sidewall 2302_SW of the coating 2302 of each gate electrode 230. For example, the inner side surface of the sidewall 2302_SW of the coating 2302 can contact the second side surface 2301_S2 of the conductive layer 2301 of each gate electrode 230.

[0072] The second side surface 2301_S2 of the conductive layer 2301 of each gate electrode 230 can be covered by the sidewall 2302_SW of the coating 2302. For example, the second side surface 2301_S2 of the conductive layer 2301 of each gate electrode 230 can be covered by the coating 2302 (e.g., completely covered) and can be spaced apart from the outer surface DP_S of the dummy plug DP in the horizontal direction.

[0073] For example, the outer surface DP_S of the dummy plug DP can contact the outer surface 2302_SWO of the sidewall 2302_SW of the coating 2302 of each gate electrode 230. The outer surface DP_S of the dummy plug DP can be coplanar with the outer surface 2302_SWO of the sidewall 2302_SW of the coating 2302 of each gate electrode 230.

[0074] For example, after forming a plurality of dummy plugs DP, the gate electrode 230 can be formed such that the coating 2302 of the gate electrode 230 can be located (e.g., directly on) the outer surface DP_S of the plurality of dummy plugs DP.

[0075] For example, each of the multiple dummy plugs DP may include silicon oxide, silicon nitride, silicon oxynitride, insulating materials with a dielectric constant lower than that of silicon oxide, or combinations thereof.

[0076] Refer again Figure 5 The upper insulating layer 272 may be disposed on the common source layer 210. The upper insulating layer 272 may have a flat upper surface throughout the cell region MCR and the connection region CON. The common source contact 274 may pass through the upper insulating layer 272 and be connected to the common source layer 210, and the rear wiring layer 276 may be disposed on the upper insulating layer 272 to be electrically connected to the common source contact 274.

[0077] The passivation layer 278 covering the wiring layer 276 can be disposed on the upper insulating layer 272. The passivation layer 278 may include an opening OP exposing the upper surface of the wiring layer 276.

[0078] According to the above embodiment, the cell plug CP can be formed to extend through the gate extension 230E, and the insulating spacer 236 can be located between each gate extension 230E and the side surface of the cell plug CP. Therefore, the semiconductor device 100 can have a step-less contact structure (or step-free contact structure). Therefore, the area occupied by the connection region CON can be reduced.

[0079] Refer again Figure 4A As described above, in the top view, the semiconductor device 100 may include a cell structure CS, which includes a cell region MCR and a connection region CON. A plurality of cell plugs CP and a plurality of dummy plugs DP may be arranged in the connection region CON. Each of the plurality of cell plugs CP may be configured such that its length l1 in a first direction X may be greater than its length l2 in a second direction Y intersecting the first direction X. For example, each of the plurality of cell plugs CP may have a strip shape. With a strip structure, the cell plug CP may have a shape that is narrower in the second direction Y and wider in the first direction X.

[0080] In an embodiment, such as Figure 4A As shown, multiple rows (e.g., three rows in this embodiment) of dummy plugs DP arranged along a first direction X are arranged between unit plugs CP spaced apart from each other along a second direction Y. Within the space between two adjacent unit plugs CP along the second direction Y, the dummy plugs DP arranged at regular intervals (or regular distances) along the first direction X can be arranged to form at least one row. The dummy plugs DP in each row can have the same size and spacing, and can be uniformly distributed along the first direction X.

[0081] The spacing (or distance) S3 between two adjacent unit plugs CP in the second direction Y and between adjacent dummy plugs DP in the second direction Y can be equal to or less than the spacing (or distance) S4 between dummy plugs DP spaced apart in the second direction Y between the unit plugs CP. When the spacing S3 is less than the spacing S4, the dummy plugs DP can be arranged more densely in areas where there are no unit plugs CP, thereby enhancing the support of the molded insulation layer 232 in that area. For example, when the spacings S3 and S4 are the same, the arrangement of the dummy plugs DP in the second direction Y can remain uniform, thereby ensuring the stability of the overall structure. (Reference) Figure 4B In the semiconductor device 100' according to another embodiment, with Figure 4A Unlike other structures, the dummy plugs DP arranged in the first direction X can be arranged in a row among the element plugs CP arranged in the second direction Y. For example, element plugs CP, a row of dummy plugs DP, element plugs CP, a row of dummy plugs DP, element plugs CP, a row of dummy plugs DP, and element plugs CP can be arranged sequentially in the second direction Y. Figure 4B The illustrated embodiments and as shown Figure 4A The structure shown forms a contrast by arranging multiple rows (e.g., three rows in the embodiment described herein) of dummy plugs DP between unit plugs CP spaced apart from each other along the second direction Y. This arrangement can further increase the integration density between unit plugs CP while maintaining the structural stability of the molded insulating layer 232 through the dummy plugs DP.

[0082] In another embodiment, the arrangement of the dummy plug DP at the end of the gate extension 230E in the first direction X can be modified. For example... Figure 4A and Figure 4B As shown, a plurality of dummy plugs DP can be arranged in the first direction X to be spaced apart from each of the two long sides of the cell plug CP in the first direction X. However, in another embodiment, the dummy plugs DP may not be arranged between the cell plugs CP in the end region of the gate extension 230E in the first direction X.

[0083] For example, the distance from the end of the gate extension 230E in the first direction X to one side of the cell plug CP can be substantially the same as the distance from the other side of the cell plug CP to the dummy plug DP. This is because the end of the gate extension 230E itself can serve as a structural support, thus ensuring the structural stability of the molded insulating layer 232 in the end region of the gate extension 230E without the need for a separate dummy plug DP.

[0084] In the above structure where the dummy plug DP is omitted from the end region of the gate extension 230E, the total number of dummy plug DPs can be reduced while maintaining structural stability in the desired region, thereby further improving the efficiency of the manufacturing process. For example, by keeping the distance between the end of the gate extension 230E and the cell plug CP the same as the distance between the dummy plug DP and the cell plug CP, the uniformity and symmetry of the entire structure can be ensured, and the uniformity of electrical characteristics can be improved.

[0085] Through the various embodiments described above, according to this disclosure, by optimizing the arrangement of cell plugs CP and dummy plugs DP, the number of cell plugs CP per unit area can be increased while ensuring the structural stability of the molded insulating layer 232. Furthermore, the efficiency of the manufacturing process and the electrical characteristics of the semiconductor device can be improved.

[0086] The structural features and technical principles of the strip-shaped unit plug will be described in more detail. Each unit plug in a plurality of unit plugs CP can have a strip structure in which its length l1 in a first direction X is greater than its length l2 in a second direction Y intersecting the first direction X. The strip structure is not merely a geometric feature, but also provides significant technical benefits.

[0087] By increasing the dimension of the unit plug CP in the first direction X and decreasing the dimension of the unit plug CP in the second direction Y, the length of the molded insulating layer 232 below the unit plug CP in the first direction X is reduced. The reduced length of the molded insulating layer 232 can fall within the allowable range where multiple dummy plugs DP can be used as structural supports.

[0088] For example, a plurality of dummy plugs (DPs) are arranged to be spaced apart from each other on both sides of the cell plug CP along a first direction X. This arrangement can provide an effective support structure for the molded insulating layer 232 beneath the cell plug CP. The dummy plugs (DPs) spaced apart from each other in the first direction X can prevent structural instability of the molded insulating layer 232 that may occur during word line etch-back under the cell plug CP. The term "word line etch-back" refers to the process of etching back the word line insulating layer to ensure space. In some embodiments, the plurality of dummy plugs (DPs) provide a support structure by contacting the molded insulating layer 232 in the region between each cell plug CP and each dummy plug (DP), and the molded insulating layer 232 beneath the selected electrode 230_S.

[0089] Although the length of the molded insulating layer 232 becomes relatively large in the second direction Y, the structural stability of the molded insulating layer 232 can be maintained even during word line etchback because the dummy plug DP located in the first direction X effectively supports the molded insulating layer 232. This allows the dummy plug etchback process required in existing structures to be omitted. The term "dummy plug etchback" refers to the process of etching the molded insulating layer back using dummy plugs and filling the molded insulating layer with oxide.

[0090] Multiple dummy plugs DP can be arranged in the first direction X, spaced apart from the first long side CP_L1 of the unit plug CP, and can also be arranged in the first direction X, spaced apart from the second long side CP_L2 of the unit plug CP. For example, by arranging the dummy plugs DP spaced apart from each other along the long sides CP_L1 and CP_L2 of the unit plug CP in the first direction X, an optimal support structure can be provided for the molded insulation layer 232 below the unit plug CP.

[0091] For example, by designing the interval (or distance) S1 between adjacent unit plugs CP in the first direction X to be greater than the interval (or distance) S2 between adjacent dummy plugs DP in the first direction X, the dummy plugs DP can be arranged more densely, thereby enhancing the support effect on the molded insulation layer 232.

[0092] By combining the strip cell plug structure and dummy plug arrangement techniques described above, the structural stability of the molded insulating layer 232 can be ensured during word line etchback without the previously required dummy plug etchback process. Furthermore, since the space occupied by the dummy plug etchback can be utilized, the number of cell plugs CP per unit area can be increased, and current paths can be easily ensured, thereby improving the electrical characteristics of the semiconductor device 100.

[0093] Each of the plurality of dummy plugs DP can have a planar cross-sectional area smaller than that of the unit plug CP. For example, the dummy plugs DP can be arranged to be spaced apart from each other in the first direction X and spaced apart from the unit plug CP. The spacing S1 between adjacent unit plugs CP in the first direction X can be greater than the spacing S2 between adjacent dummy plugs DP in the first direction X. In the above arrangement, by reducing the size of the unit plug CP in the second direction Y and increasing the size of the unit plug CP in the first direction X, the structural stability of the molded insulating layer 232 can be ensured during word line etchback without the need for a dummy plug etchback process.

[0094] Multiple unit plugs (CPs) can be arranged at specific intervals (or specific distances) in a first direction X and a second direction Y. Unit plugs (CPs) arranged in the first direction X can overlap each other in the first direction X, and unit plugs (CPs) arranged in the second direction Y can overlap each other in the second direction Y. This overlapping arrangement increases the number of unit plugs (CPs) per unit area. The statement "overlapping each other in the first direction X" indicates a state where, when viewed from the first direction X, the unit plugs (CPs) arranged in the first direction X can completely overlap each other in the first direction X. Similarly, the statement "overlapping each other in the second direction Y" indicates a state where, when viewed from the second direction Y, the unit plugs (CPs) arranged in the second direction Y can completely overlap each other in the second direction Y. In embodiments, "overlapping" can be understood as "completely overlapping".

[0095] For example, the unit plug CP may have a first long side CP_L1 and a second long side CP_L2 formed along a first direction X, and may have a first short side CP_S1 and a second short side CP_S2 formed along a second direction Y. A plurality of dummy plugs DP may be arranged in the first direction X, spaced apart from the first long side CP_L1 of the unit plug CP, and may be arranged in the first direction X, spaced apart from the second long side CP_L2 of the unit plug CP. For example, by arranging the dummy plugs DP spaced apart from each other along the long sides CP_L1 and CP_L2 of the unit plug CP, a support structure can be provided for the molded insulating layer 232 beneath the unit plug CP.

[0096] With the above structure, since the space occupied by the dummy plug etchback can be utilized, the number of cell plugs CP per unit area can be increased, and the current path can be easily ensured, thereby improving the electrical characteristics of the semiconductor device 100. Furthermore, by applying a strip structure in which the size of the cell plug CP increases in the first direction X and decreases in the second direction Y, the structural stability of the molded insulating layer 232 can be maintained during word line etchback even without the dummy plug etchback process.

[0097] Figure 6B yes Figure 5 A schematic enlarged view illustrating a modification example for region CX1. (See reference) Figure 6B In another embodiment, the surface CP_S (e.g., the upper surface) of the unit plug (e.g., a single unit plug) CP can be electrically connected to the groove G of the selected electrode 230_S. The selected electrode 230_S can have a groove G formed on its surface, the groove G facing the interior of the selected electrode 230_S. The end of the unit plug CP including the surface CP_S of the unit plug CP can be located in the groove G, and the surface CP_S of the unit plug CP can contact the inner surface of the groove G.

[0098] In the above structure, the groove G of the selected electrode 230_S can be formed by removing a portion of the conductive layer 2301. For example, the groove G can be a groove formed in the conductive layer 2301 of the selected electrode 230_S, and the groove G can be surrounded by the coating 2302. The conductive layer 2301 within the groove G can be exposed to the outside without being covered by the coating 2302. The surface of the conductive layer 2301 thus exposed can directly contact the surface CP_S of the cell plug CP to form an electrical connection with the surface CP_S. The above structure of the groove G can increase the contact area between the cell plug CP and the selected electrode 230_S, thereby improving the stability of the electrical connection between them.

[0099] The depth of the groove G can be less than the thickness of the conductive layer 2301. This allows the plug CP to have sufficient contact area with the conductive layer 2301 of the selected electrode 230_S while maintaining the structural integrity of the selected electrode 230_S. The contact interface between the surface CP_S of the plug CP and the groove G can form a low-resistance contact, thereby enhancing the effective transmission of electrical signals.

[0100] For example, the coating 2302 of the unselected electrode 230_N can contact the side surface of the cell plug CP, thereby providing electrical insulation between the cell plug CP and the unselected electrode 230_N. This structural arrangement allows the cell plug CP to be electrically connected only to the conductive layer 2301 of the selected electrode 230_S, thus preventing the formation of unwanted electrical paths with the unselected electrode 230_N.

[0101] Figures 7 to 10 These are schematic top views of semiconductor devices 100a, 100b, 100c and 100d according to embodiments.

[0102] exist Figures 7 to 10 In, with Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 and Figure 6A The same reference numerals in the figures indicate the same parts. Figures 7 to 10 It corresponds to Figure 4A A top view. For ease of description, the following will describe... Figures 7 to 10 and Figure 4A The differences between them.

[0103] refer to Figure 7 Multiple unit plugs CPa1, CPa2, ..., CPaan arranged in the first direction X can be arranged in the connection area CON. The lengths la1, la2, ..., lan of the unit plugs CPa1, CPa2, ..., CPaan arranged in the first direction X can gradually increase, and the unit plugs CPa1, CPa2, ..., CPaan can have the same length in the second direction Y.

[0104] For example, the lengths la1, la2, ..., and lan of the unit plugs CPa1, CPa2, ..., and CPaan in the first direction X are related to the lengths of the unit plugs CPa1, CPa2, ..., and CPaan in the third direction Z (e.g., the vertical direction Z). Figure 5 The za1, za2, ..., zan) are proportional. For example, a unit plug formed deeper in the vertical direction Z can have a longer length in the first direction X. When the unit plug is formed deeper, the above structural features can ensure horizontal stability.

[0105] Because deeper cell plugs are formed in the vertical direction Z, penetrating a greater number of gate electrodes 230, the structural stability of the cell plugs becomes more critical. Potential structural instabilities can be compensated for by increasing the length of the cell plugs in the first direction X.

[0106] Multiple dummy plugs DP can be arranged along the first direction X, spaced apart from the unit plugs CPa1, CPa2, ... and CPan. The dummy plugs DP can be symmetrically arranged on both sides of each of the unit plugs CPa1, CPa2, ... and CPan, thereby maintaining the structural stability of the molded insulation layer 232.

[0107] In the above structure, as the lengths of the unit plugs CPa1, CPa2, ... and CPaan increase proportionally to their lengths in the third direction Z, the electrical characteristics and structural stability of the unit plugs located at the edge of the connection region CON can be improved. For example, by keeping the lengths of the unit plugs the same in the second direction Y, the manufacturing process can be simplified and made more consistent.

[0108] For example, a unit plug structure in which the length of the unit plug in the first direction X increases proportionally to its length in the third direction Z can optimize the electrical signal transmission path in the connection region CON and provide uniform electrical characteristics for each unit plug. For example, the above structure can ensure a stable electrical connection even at the edge of the connection region CON.

[0109] refer to Figure 8 In the connection area CON, multiple unit plugs CPb1, CPb2, CPb3 and CPb4 can be arranged at specific intervals (or specific distances) in the first direction X and the second direction Y.

[0110] The unit plugs CPb1 and CPb2 arranged in the first direction X can overlap each other in the first direction X. For example, when viewed in the first direction X, unit plugs CPb1 and CPb2 can have a structure in which the unit plugs overlap each other. The above-mentioned overlapping structure can improve the electrical connection and signal transmission efficiency between unit plugs arranged along the first direction X.

[0111] For example, unit plugs CPb1 and CPb3 arranged in the second direction Y may partially overlap each other. The statement "partially overlap in the second direction Y" indicates a state where, when viewed in the second direction Y, unit plugs CPb1 and CPb3 may not completely overlap each other in the second direction Y, but only partially overlap. For example, unit plugs CPb1 and CPb3 arranged in the second direction Y may be spaced apart by a distance g1. Distance g1 prevents electrical interference between adjacent unit plugs in the second direction Y and ensures independent operation of each unit plug.

[0112] The above arrangement of the unit plugs CPb1, CPb2, CPb3, and CPb4 can optimize space utilization in the connection area CON while ensuring electrical insulation of each unit plug CPb1, CPb2, CPb3, or CPb4. For example, the overlapping structure in the first direction X and the partially overlapping structure in the second direction Y can allow for a greater number of unit plugs per unit area without requiring a dummy plug re-etching process.

[0113] Multiple dummy plugs DP can be arranged in the first direction X, spaced apart from the unit plugs CPb1, CPb2, CPb3, and CPb4. The dummy plugs DP can be arranged between and around the unit plugs, thereby providing structural stability to the molded insulation layer 232.

[0114] When the above structure is combined with a strip structure that increases the size of the cell plug CP in the first direction X and decreases the size of the cell plug CP in the second direction Y, a semiconductor device can be provided in which the structural stability of the molded insulating layer 232 during word line etch-back can be ensured even without a dummy plug etch-back process, the number of cell plugs per unit area can be increased, and the current path can be easily ensured.

[0115] refer to Figure 9 In the connection area CON, multiple unit plugs CPc1, CPc2, CPc3 and CPc4 can be arranged at specific intervals in the first direction X and the second direction Y.

[0116] The element plugs CPc1 and CPc2 arranged in the first direction X can partially overlap each other. For example, when viewed in the first direction X, element plugs CPc1 and CPc2 can have a structure in which the element plugs overlap each other only in a portion of their area and not completely overlap each other. For example, element plugs CPc1 and CPc2 arranged in the first direction X can be spaced apart from each other by a gap g2. The gap g2 can provide an appropriate arrangement density while preventing electrical interference between adjacent element plugs in the first direction X.

[0117] For example, the unit plugs CPc1 and CPc3 arranged in the second direction Y can overlap each other in the second direction Y. When viewed in the second direction Y, unit plugs CPc1 and CPc3 can overlap each other (e.g., completely overlap). The above-described overlapping structure can improve the electrical connection and signal transmission efficiency between unit plugs arranged in the second direction X.

[0118] The aforementioned unit plug arrangement can have a partially overlapping structure in the first direction X and an overlapping structure in the second direction Y, which is consistent with... Figure 8 The arrangement shown is the opposite. Through these various overlapping methods, the design flexibility of semiconductor devices can be increased, and an optimized structure can be selected according to the application environment.

[0119] Multiple dummy plugs DP can be arranged in the first direction X, spaced apart from the unit plugs CPc1, CPc2, CPc3, and CPc4. The dummy plugs DP can be arranged between and around the unit plugs CPc1, CPc2, CPc3, and CPc4 to provide structural stability of the molded insulation layer 232.

[0120] In the above structure, the arrangement of the unit plugs CPc1, CPc2, CPc3, and CPc4, which partially overlap each other in the first direction X and overlap each other in the second direction Y, can provide optimized characteristics in each direction in terms of ensuring current path and signal transmission. For example, the overlap in the second direction Y can improve the efficiency of signal transmission in the second direction Y, and the partial overlap and spacing g2 in the first direction X can provide a proper balance between electrical isolation and arrangement density in the first direction X.

[0121] refer to Figure 10 In the connection area CON, multiple unit plugs CPd1, CPd2, CPd3 and CPd4 can be arranged at specific intervals (or specific distances) in the first direction X and the second direction Y.

[0122] The element plugs CPd1 and CPd2 arranged in the first direction X may partially overlap each other in the first direction X. For example, when viewed in the first direction X, element plugs CPd1 and CPd2 may have a structure in which element plugs CPd1 and CPd2 overlap each other in a partial area rather than their entire area. For example, element plugs CPd1 and CPd2 arranged in the first direction X may be spaced apart from each other by a gap g2. The gap g2 can ensure an appropriate arrangement density while preventing electrical interference between adjacent element plugs in the first direction X.

[0123] For example, unit plugs CPd1 and CPd3 arranged in the second direction Y may partially overlap each other in the second direction Y. When viewed in the second direction Y, unit plugs CPd1 and CPd3 may overlap each other only in a portion of their area. For example, unit plugs CPd1 and CPd3 arranged in the second direction Y may be spaced apart from each other by a distance g1. The distance g1 can prevent electrical interference between adjacent unit plugs in the second direction Y and can ensure independent operation of each unit plug.

[0124] and Figure 8 and Figure 9 The arrangement shown differs from the others. The aforementioned arrangement can have partial overlap in both the first direction X and the second direction Y, and the interval g2 or interval g1 can remain constant. This arrangement allows for a greater number of unit plugs per unit area while maintaining independent electrical characteristics in the first direction X and the second direction Y.

[0125] Multiple dummy plugs DP can be arranged in the first direction X, spaced apart from the unit plugs CPd1, CPd2, CPd3, and CPd4. The dummy plugs DP can be arranged around the unit plugs CPd1, CPd2, CPd3, and CPd4 to provide structural stability of the molded insulation layer 232.

[0126] Compared to conventional circular cell plug structures, the aforementioned partially overlapping and spaced structures can increase the number of cell plugs per unit area while reducing electrical interference between cell plugs. For example, by implementing partially overlapping and spaced structures in both the first direction X and the second direction Y, an optimal balance between the electrical characteristics and structural stability of the semiconductor device 100 can be achieved.

[0127] For example, by combining the above structure with a strip cell plug structure, a semiconductor device can be provided in which the structural stability of the molded insulating layer 232 is ensured during word line etch-back without a dummy plug etch-back process, and the current path is easily ensured.

[0128] Figure 11 This is a schematic cross-sectional view of a portion of the semiconductor device 100e according to an embodiment, and Figure 12 yes Figure 11 A schematic enlarged view of part of the CX1.

[0129] exist Figure 11 and Figure 12 In, with Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 and Figure 6A The same reference numerals in the figures indicate the same parts. Figure 11 It corresponds to Figure 5 The cross-sectional view, and Figure 12 It corresponds to Figure 6A A cross-sectional view. In the following text, for ease of description, the description will be... Figure 11 and Figure 12 and Figure 5 and Figure 6A The differences between them.

[0130] refer to Figure 11 and Figure 12 Multiple insulating spacers 236a may be located on the side surface of each of the multiple unit plugs CP. For example, the side surface of each of the multiple unit plugs CP may be surrounded by insulating spacers 236a.

[0131] In some embodiments, insulating spacers 236a located on the side surfaces of a cell plug (e.g., a single cell plug) CP may be spaced apart from each other in the vertical direction Z. For example, the insulating spacers 236a may be spaced apart from each other in the vertical direction Z such that a molded insulating layer 232 is interposed therebetween. The insulating spacers 236a may be located between the cell plug CP and each gate electrode 230. For example, the insulating spacers 236a may be arranged between the cell plug CP and each unselected electrode 230_N.

[0132] In an embodiment, the surface CP_S (e.g., the upper surface) of the unit plug CP may be electrically connected to the selected electrode 230_S, and the side surface of the unit plug CP may not be electrically connected to the unselected electrode 230_N arranged at a lower vertical height than the selected electrode 230_S.

[0133] The insulating spacer 236a can be located between the unselected electrode 230_N and the side surface of the cell plug CP at a lower vertical height than the selected electrode 230_S, and thus the unselected electrode 230_N and the side surface of the cell plug CP can be insulated from each other.

[0134] In an embodiment, each insulating spacer 236a may have an annular horizontal cross-section. For example, the second side surface 236a_S2 of each insulating spacer 236a may be the inner side surface that contacts the cell plug CP, and the first side surface 236a_S1 of each insulating spacer 236a may be the outer side surface opposite to the second side surface 236a_S2 of each insulating spacer 236a. The thickness of each insulating spacer 236a in the horizontal direction, such as the distance between the first side surface 236a_S1 and the second side surface 236a_S2 of each insulating spacer 236a, may be in the range of, for example, from about 10 angstroms (Å) to about 100 angstroms (Å).

[0135] like Figure 12 As shown, the upper surface of each insulating spacer 236a can be arranged at the same height as the upper surface of the unselected electrode 230_N facing each insulating spacer 236a, and the bottom surface of each insulating spacer 236a can be arranged at the same height as the bottom surface of the unselected electrode 230_N facing each insulating spacer 236a.

[0136] The height of each insulating spacer 236a in the vertical direction Z can be the same as the height of each unselected electrode 230_N in the vertical direction Z. For example, the height of each insulating spacer 236a in the vertical direction Z can be greater than the height of the conductive layer 2301 of each unselected electrode 230_N in the vertical direction Z.

[0137] In some embodiments, each insulating spacer 236a may include silicon oxide. In some embodiments, each insulating spacer 236a may include silicon oxide containing a small amount (e.g., 5 at% or less) of one of the elements including chlorine, fluorine, and bromine.

[0138] Each unselected electrode 230_N may include a first side surface 230_N_S1. The first side surface 230_N_S1 of each unselected electrode 230_N may face the side surface of the cell plug CP. For example, when the cell plug CP passes through the unselected electrode 230_N, the side surface of each unselected electrode 230_N defining the hole formed in each unselected electrode 230_N may be the first side surface 230_N_S1 of the unselected electrode 230_N.

[0139] The first side surface 230_N_S1 of each unselected electrode 230_N may include the first side surface 2301_S1 of the conductive layer 2301 of each unselected electrode 230_N and the first side surface 2302_S1 of the coating 2302 of each unselected electrode 230_N. For example, the first side surface 2301_S1 of the conductive layer 2301 of each unselected electrode 230_N may face the cell insert CP, and the first side surface 2302_S1 of the coating 2302 of each unselected electrode 230_N may face the cell insert CP. The first side surface 2301_S1 of the conductive layer 2301 of each unselected electrode 230_N and the first side surface 2302_S1 of the coating 2302 of each unselected electrode 230_N may contact the first side surface 236a_S1 of each insulating spacer 236a. For example, the first side surface 236a_S1, which is the outer surface of each insulating spacer 236a, can contact the first side surface 2301_S1 of the conductive layer 2301 of each unselected electrode 230_N, and can contact the first side surface 2302_S1 of the coating 2302 of each unselected electrode 230_N.

[0140] Each of the multiple unit plugs CP may have multiple first side portions CPS1 and multiple second side portions CPS2 arranged alternately with each other. The multiple first side portions CPS1 may contact the second side surface 236a_S2 of the multiple insulating spacers 236a, and the multiple second side portions CPS2 may contact the side surface of the molded insulating layer 232.

[0141] Figure 13 This is a schematic cross-sectional view of a portion of the semiconductor device 100f according to an embodiment. Figure 13 A semiconductor device 100f is shown, wherein a cell structure CS is arranged on a peripheral circuit structure PS, such that the bit line BL of the cell structure CS can face upwards in the vertical direction Z. In the following description, for ease of description, the following will be described... Figure 13 Semiconductor device 100f and Figure 5 The differences between semiconductor devices 100.

[0142] refer to Figure 13The common source layer 210 can be arranged on the peripheral circuit structure PS in the cell region MCR, and the buried insulating layer 212 can be arranged on the peripheral circuit structure PS in the connection region CON. The gate electrode 230 and the molded insulating layer 232 can be arranged on the common source layer 210 and the buried insulating layer 212.

[0143] The channel structure 240 may have sloping sidewalls, such that the width of the first end 240x may be greater than the width of the second end 240y. The second end 240y of the channel structure 240 may be arranged close to the peripheral circuit structure PS, and the first end 240x of the channel structure 240 may be arranged away from the peripheral circuit structure PS.

[0144] In an embodiment, each of the plurality of unit plugs CP may have a first end CPx and a second end CPy, and the first ends CPx of the plurality of unit plugs CP may all be arranged at the same vertical height, or at the same vertical height as the upper surface of the stacked covering insulating layer 234. The second ends CPy of the plurality of unit plugs CP may be arranged at different vertical heights.

[0145] The second end CPy of the multiple unit plugs CP can be arranged close to the peripheral circuit structure PS, and the first end CPx of the multiple unit plugs CP can be arranged far away from the peripheral circuit structure PS.

[0146] The peripheral circuit structure PS may include a landing pad 140, and a peripheral plug PP extending in the vertical direction Z may be electrically connected to the landing pad 140.

[0147] Figures 14 to 27 This is a cross-sectional view of a method for manufacturing a semiconductor device 100 according to an embodiment. Figures 14 to 18B , Figure 19A , Figure 20A , Figure 21A , Figure 22 and Figures 24 to 27 Is along Figure 4A The cross-sectional diagram corresponding to the section intercepted by line A-A'. Figure 19B yes Figure 19A A magnified view of regions DX and CX, and Figure 20B and Figure 21B They are Figure 20A and Figure 21A A magnified view of region CX.

[0148] refer to Figure 14 A buffer insulating layer 220 can be formed on the unit substrate 210P, and an etch stop layer 222 can be formed on the buffer insulating layer 220.

[0149] In an embodiment, the unit substrate 210P may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The buffer insulating layer 220 may be formed of silicon oxide. In an embodiment, the etch stop layer 222 may be formed of polysilicon.

[0150] Subsequently, in the cell region MCR and the connection region CON, the sacrificial layer 310 and the molded insulating layer 232 can be alternately formed on the etch stop layer 222 to form a molded stack MST.

[0151] In some embodiments, the sacrificial layer 310 and the molded insulating layer 232 may be formed of materials that are etch-selective relative to each other. For example, the sacrificial layer 310 may each comprise silicon nitride, and the molded insulating layer 232 may each comprise silicon oxide.

[0152] refer to Figure 15 A channel structure 240 extending in the vertical direction Z through the molded stack MST can be formed in the cell region MCR.

[0153] In an embodiment, during the process of forming the channel structure 240, a channel hole 240H passing through the molded stacked MST can be formed in the cell region MCR. A gate insulating layer 242, a channel layer 244, and a buried insulating layer 246 can be sequentially formed on the inner wall of the channel hole 240H. A drain region 248 can be formed at the entrance (or upper opening) of the channel hole 240H.

[0154] In one embodiment, the channel hole 240H may extend in the vertical direction Z through the molded stack MST, the etch stop layer 222 and the buffer insulating layer 220, and the upper surface of the unit substrate 210P may be exposed at the bottom of the channel hole 240H.

[0155] The channel structure 240 may include a first end 240x and a second end 240y opposite thereto. The first end 240x of the channel structure 240 may be adjacent to or disposed at the same vertical height as the upper surface of the molded stacked MST, and the second end 240y of the channel structure 240 may be disposed in contact with the upper surface of the cell substrate 210P and disposed at a vertical height below the upper surface of the cell substrate 210P. In some embodiments, the width of the first end 240x of the channel structure 240 in the horizontal direction may be greater than the width of the second end 240y of the channel structure 240 in the horizontal direction.

[0156] refer to Figure 16A stacked covering insulating layer 234 can be formed on the upper surface of the molded stacked MST. The stacked covering insulating layer 234 can cover the entire upper surface of the molded stacked MST in the cell region MCR and the connection region CON. The stacked covering insulating layer 234 can have a flat top surface and a flat bottom surface over the entire area of ​​the cell region MCR and the connection region CON, and can have a constant thickness over the entire area of ​​the cell region MCR and the connection region CON.

[0157] Subsequently, a stack isolation opening WLH extending in the vertical direction Z through the molded stack MST and the stack overlay insulating layer 234 can be formed in the cell region MCR and the connection region CON. The stack isolation opening WLH can also extend in the cell region MCR and the connection region CON along the first horizontal direction X (see...). Figure 4A )extend.

[0158] In the connection region CON, a plurality of dummy plug vias DPH extending in the vertical direction Z through the molded stack MST can be formed. In some embodiments, the process of forming the plurality of dummy plug vias DPH can be performed simultaneously with the etching process of forming the stacked isolation opening WLH. In other embodiments, the process of forming the plurality of dummy plug vias DPH can be performed simultaneously with the etching process of forming the channel structure 240.

[0159] refer to Figure 17 Insulating material can be filled in Figure 16 The interior of each of the plurality of dummy plug holes DPH formed in the middle is used to form a dummy plug DP, and a first protective layer 320 may be formed inside the stacked isolation opening WLH.

[0160] In embodiments, the dummy plug DP may include silicon oxide, silicon nitride, silicon oxynitride, an insulating material with a dielectric constant lower than silicon oxide, or a combination thereof. Stacked isolation insulating layer WLI (reference) Figure 19A and Figure 19B The dummy plug (DP) and the dummy plug (DP) may include the same material, but in some embodiments may include different materials.

[0161] In the method of forming a dummy plug DP, an insulating material can be deposited inside the dummy plug orifice DPH, and then a planarization process, such as chemical mechanical planarization (CMP) or etch-back process, can be performed to remove the insulating material, exposing the upper surface of the stacked overlay insulating layer 234. Using the above method, the dummy plug DP can be formed by filling the dummy plug orifice DPH only with insulating material.

[0162] refer to Figure 18AMultiple cell plug holes CPH extending in the vertical direction Z can be formed by removing portions of the stacked overlay insulating layer 234 and the molded stack MST in the connection region CON. The multiple cell plug holes CPH can have varying heights (or varying depths) in the vertical direction Z. The multiple cell plug holes CPH can have different heights (or different depths) to expose the upper surfaces of the corresponding sacrificial layers 310 among the multiple sacrificial layers 310.

[0163] For example, a plurality of unit plug holes CPH may include a first hole H1 that exposes the upper surface of the uppermost sacrificial layer 310, a second hole H2 that exposes the upper surface of the sacrificial layer 310 directly below the uppermost sacrificial layer 310, and a m-th hole Hm that exposes the upper surface of the m-th sacrificial layer 310 from the upper surface of the molded stack MST.

[0164] For example, each of the multiple unit plug holes CPH can expose the upper surface of the sacrificial layer 310 on which a selected electrode 230_S corresponding to the unit plug CP to be formed within the unit plug hole CPH is formed. For example, each of the multiple unit plug holes CPH can expose the upper surface of the sacrificial layer 310 directly below which the lowermost unselected electrode 230_N_L corresponding to the unit plug CP to be formed within the unit plug hole CPH is formed.

[0165] refer to Figure 18B ,exist Figure 18A After an insulating layer 332 is formed on the inner wall of each of the multiple unit plug holes CPH formed in the process, a second protective layer 330 can be formed.

[0166] An insulating layer 332 formed on the inner wall of each of the plurality of unit plug holes CPH may be located between the side surface of the unit plug CP to be formed later and the unselected electrode 230_N, and may serve as an insulating spacer 236. The insulating layer 332 may be conformally formed along the inner wall of the unit plug hole CPH and may comprise silicon oxide. In some embodiments, the insulating layer 332 may comprise silicon oxide containing a small amount (e.g., 5 at% or less) of one of the elements comprising chlorine, fluorine, and bromine.

[0167] The insulating layer 332 can be formed using methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma-enhanced chemical vapor deposition (PECVD). The thickness of the insulating layer 332 can be in the range of, for example, about 10 Å to about 100 Å, and can be determined within a range that ensures electrical insulation between the cell plug CP and the unselected electrode 230_N without excessively reducing the internal space of the cell plug orifice CPH.

[0168] The second protective layer 330 may be formed inside each of the plurality of cell plug holes CPH in which the insulating layer 332 is formed. The second protective layer 330 may protect the cell plug holes CPH during subsequent processes such as removing the sacrificial layer 310 and forming the gate electrode 230. The second protective layer 330 may include a sacrificial material, such as a photoresist, a carbon-containing material, or a polymeric material.

[0169] The second protective layer 330 can be formed by spin coating, CVD, or other suitable deposition methods, and can fill (e.g., completely fill) the interior of the cell plug via CPH. The upper part of the second protective layer 330 can be removed by a CMP process or an etch-back process to expose the upper surface of the stacked overlay insulating layer 234. In this manner, the second protective layer 330 can remain only inside the cell plug via CPH, and therefore, the shape of the cell plug via CPH can be maintained during subsequent processes.

[0170] refer to Figure 19A and Figure 19B It can remove the arrangement in the stacked isolation opening WLH. Figure 18A and Figure 18B The first protective layer 320 is then removed, and the sacrificial layer 310 exposed on the inner wall of the stacked isolation opening WLH can be removed. The gate electrode 230 can then be formed from a metallic material in the space from which the sacrificial layer 310 is removed. A stacked isolation insulating layer WLI can then be formed in the stacked isolation opening WLH.

[0171] For example, in the process of forming the gate electrode 230, a coating 2302 can be formed first, and then a conductive layer 2301 can be formed in the interior space of the coating 2302. For example, the conductive layer 2301 can be surrounded by the coating 2302.

[0172] For example, the conductive layer 2301 of each gate electrode 230 may be spaced apart from the dummy plug DP in such a way that a coating 2302 is located therebetween. The conductive layer 2301 of each gate electrode 230 penetrated by the cell plug hole CPH may be spaced apart from the insulating layer 332 in such a way that a coating 2302 is located therebetween.

[0173] When multiple sacrificial layers 310 are replaced by multiple gate electrodes 230, the multiple gate electrodes 230 can extend horizontally in the cell region MCR and the connection region CON. The gate electrodes 230 arranged in the connection region CON are referred to as gate extensions 230E. The multiple gate extensions 230E in the connection region CON can overlap each other in the vertical direction. For example, multiple gate extensions 230E arranged at different vertical heights in the connection region CON can have the same width in the horizontal direction.

[0174] refer to Figure 20A and Figure 20B It can remove in Figure 19A The second protective layer 330 is formed in the middle, and the bottom surface of the insulating layer 332 can be removed to expose the gate electrode 230 to the outside.

[0175] Figure 20A This is an overall cross-sectional view after the bottom surface of the second protective layer 330 and the insulating layer 332 has been removed. Figure 20A The diagram shows the state where the second protective layer 330, previously filled inside the cell plug orifice CPH, has been completely removed, leaving the cell plug orifice CPH empty. Therefore, the insulating layer 332 can still remain on the sidewall of the cell plug orifice CPH. The insulating layer 332 can serve as an insulating spacer 236, providing electrical insulation between the cell plug CP formed in subsequent processes and the unselected electrode 230_N.

[0176] Figure 20B yes Figure 20A An enlarged view of region CX is shown, and the cell plug hole CPH and its surrounding structure are shown in more detail. The selected electrode 230_S at the bottom of the cell plug hole CPH, the lowest unselected electrode 230_N_L above it, and the unselected electrode 230_N further above it are shown. A molded insulating layer 232 may be arranged between the gate electrodes.

[0177] In the process of removing the bottom surface of the insulating layer 332, the coating 2302 located on the upper surface of the selected electrode 230_S can also be removed. Therefore, the conductive layer 2301 of the selected electrode 230_S can be exposed to the outside at the bottom of the cell plug hole CPH. The exposed conductive layer 2301 can then directly contact the cell plug CP to be formed in subsequent processes to form an electrical connection with the cell plug CP.

[0178] The removal of the bottom surface of the insulating layer 332 and the coating 2302 can be performed using a selective etching process. In this process, the insulating layer 332 on the sidewall of the cell plug hole CPH can be retained, so that the cell plug CP to be formed in subsequent processes can be electrically insulated from the unselected electrodes 230_N and 230_N_L.

[0179] refer to Figure 21A and Figure 21B Multiple unit plugs CP can be formed inside multiple unit plug holes CPH.

[0180] In an embodiment, the unit plug CP may have a first end CPx and a second end CPy. The first end CPx of the unit plug CP may be disposed at the same vertical height as the upper surface of the stacked covering insulating layer 234, and the second end CPy of the unit plug CP may be disposed on the conductive layer 2301 of the selected electrode 230_S corresponding to the unit plug CP. The side surface of the unit plug CP may contact the insulating spacer 236. Therefore, each of the plurality of unit plugs CP may be electrically connected to its corresponding selected electrode 230_S.

[0181] Each of the multiple unit plugs CP can be formed by depositing a conductive material inside the unit plug orifice CPH. In embodiments, the unit plug CP may include a metal (such as tungsten, nickel, cobalt, or tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), doped polycrystalline silicon, or a combination thereof. The deposition of the conductive material may be performed by CVD, ALD, or physical vapor deposition (PVD).

[0182] like Figure 21B As shown more clearly, the bottom surface of the unit plug (e.g., a single unit plug) CP can directly contact and thus be electrically connected to the conductive layer 2301 of the selected electrode 230_S corresponding to the unit plug CP. The side surface of the unit plug CP may not be electrically connected to the unselected electrode 230_N, which is arranged at a higher vertical height than the selected electrode 230_S corresponding to the unit plug CP. This is because the insulating spacer 236 is located between the unit plug CP and the unselected electrode 230_N.

[0183] Insulating spacer 236 can be made from reference Figure 20A and Figure 20B The described insulating layer 332 is transformed and may have a tubular structure surrounding the side surface of the cell plug CP. The insulating spacer 236 may have an inner surface and an outer surface. The inner surface may contact the side surface of the cell plug CP, and the outer surface may contact the coating 2302 of the unselected electrode 230_N and the molded insulating layer 232.

[0184] According to this disclosure, the unit plug CP can have a strip structure in which its length in the first direction X is greater than its length in the second direction Y in a top view. In the strip structure, by increasing the size of the unit plug CP in the first direction X and decreasing the size of the unit plug CP in the second direction Y, the structural stability of the molded insulating layer 232 can be ensured during word line etchback without requiring a dummy plug etchback process.

[0185] After depositing the cell plug CP, a planarization process (such as CMP or etch-back) can be performed to remove the top of the conductive material, thereby exposing the upper surface of the stacked overlay insulating layer 234. Through the planarization process, the first end CPx of the cell plug CP can be positioned at the same vertical height as the upper surface of the stacked overlay insulating layer 234.

[0186] refer to Figure 22 This can form a bit line contact BLC and bit line BL that are electrically connected to the channel structure 240.

[0187] Subsequently, a connection path 252 and a connection wiring layer 254, which electrically connect to the bit line BL and the cell plug CP, and an interlayer insulating layer 256 can be formed. Connection pads 260 can be formed on the upper surface of the interlayer insulating layer 256.

[0188] refer to Figure 23 The peripheral circuit structure PS can be prepared.

[0189] Peripheral circuit transistors 120TR can be formed on a substrate 110 in which the active region AC is defined by a device isolation layer 112. Multiple peripheral circuit transistors 120TR, multiple peripheral circuit contacts 132 electrically connected to the substrate 110, and multiple peripheral circuit wiring layers 134 can be formed on the substrate 110. An interlayer insulating layer 130 covering the multiple peripheral circuit transistors 120TR, the multiple peripheral circuit contacts 132, and the multiple peripheral circuit wiring layers 134 can be formed on the substrate 110. Connecting pads 260 can be formed on the upper surface of the interlayer insulating layer 130.

[0190] refer to Figure 24 The peripheral circuit structure PS can be attached to the unit structure CS. The peripheral circuit structure PS and the unit structure CS can be attached together by a metal-oxide hybrid bonding method using connecting pads 260 and interlayer insulating layers 130 and 256, but the embodiments are not limited to this. The metal-oxide hybrid bonding method is a method that simultaneously bonds metal pads and oxide insulating layers together, ensuring both electrical connectivity and physical bond strength.

[0191] Then, the structure where the peripheral circuit structure PS and the unit structure CS are attached together can be flipped so that the substrate 110 can face upwards.

[0192] refer to Figure 25 The unit substrate 210P can be removed. The unit substrate 210P can be removed by a grinding process and a subsequent etching process, and the buffer insulating layer 220 can be exposed.

[0193] Subsequently, the buffer insulating layer 220 can be removed, exposing the upper surface of the etch stop layer 222. With the removal of the buffer insulating layer 220, the second end 240y of the channel structure 240 can protrude onto the upper surface of the etch stop layer 222.

[0194] With the removal of the cell substrate 210P and the buffer insulating layer 220, the upper side of the stacked isolation insulating layer WLI and the upper side of the dummy plug DP can also be exposed and protrude above the etch stop layer 222.

[0195] Subsequently, a portion of the gate insulating layer 242 exposed at the second end 240y of the channel structure 240 can be removed to expose the upper surface of the channel layer 244. In some embodiments, the upper surface of the gate insulating layer 242 may be disposed on the same plane as the upper surface of the channel layer 244.

[0196] In other embodiments, the process of removing the gate insulating layer 242 may be performed until the upper surface of the etch stop layer 222 is exposed. In some embodiments, the gate insulating layer 242 may be disposed at a height below the upper surface of the channel layer 244, and the upper side of the gate insulating layer 242 may be removed such that the upper surface of the channel layer 244 and a portion of the sidewalls of the channel layer 244 are exposed.

[0197] refer to Figure 26 A common source layer 210 can be formed in the cell region MCR, the connection region CON, and the peripheral circuit connection region PRC. The common source layer 210 can be formed of polysilicon. For example, the common source layer 210 can be formed of polysilicon doped with n-type impurities. In the cell region MCR, the common source layer 210 can be conformally formed on the exposed upper surfaces of the etch stop layer 222 and the channel layer 244. For example, the common source layer 210 can directly contact and thus electrically connect to the upper surface of the channel layer 244 at the second end 240y of the channel structure 240.

[0198] A portion of the common source layer 210 and a portion of the etch stop layer 222 can be removed from the connection region CON and the peripheral circuit connection region PRC.

[0199] refer to Figure 27 In the cell region MCR, the connection region CON and the peripheral circuit connection region PRC, an upper insulating layer 272 can be formed on the common source layer 210 and the uppermost molded insulating layer 232.

[0200] Subsequently, a mask pattern can be formed on the upper insulating layer 272, and this mask pattern can be used as an etching mask to remove a portion of the upper insulating layer 272 to form a rear contact hole. The rear contact hole can expose the upper surface of the common source layer 210. Conductive material can be filled in the rear contact hole to form a common source contact 274, and a rear wiring layer 276 electrically connected to the common source contact 274 can be formed on the upper insulating layer 272.

[0201] Subsequently, a passivation layer 278 covering the back wiring layer 276 can be formed on the upper insulating layer 272, and an opening OP can be formed in the passivation layer 278 to expose the upper surface of the back wiring layer 276.

[0202] By performing the above process, semiconductor device 100 can be completed.

[0203] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Peripheral circuit structure; And a unit structure, which is located on the peripheral circuit structure, the unit structure including a unit area and a connection area. The unit structure includes: A gate electrode and a molded insulating layer are located in the cell region and the connection region and are alternately stacked in the vertical direction; A channel structure located in the cell region and extending along the vertical direction through the gate electrode and the molded insulating layer; Multiple dummy plugs are located in the connection region and extend along the vertical direction through the gate electrode and the molded insulating layer; A plurality of unit plugs are located in the connection region, each of the plurality of unit plugs contacting a selected electrode among the gate electrodes and passing through an unselected electrode among the gate electrodes, the unselected electrode being at a different vertical height from the selected electrode; and Insulating spacers are located on the side surfaces of each of the plurality of unit plugs. Each of the plurality of unit plugs has a first length in a first direction and a second length in a second direction intersecting the first direction, wherein the first length is greater than the second length. Each of the plurality of unit plugs has a first long side and a second long side extending in the first direction, and a first short side and a second short side extending in the second direction. The plurality of dummy plugs are arranged in the first direction and are spaced apart from at least one of the first long side and the second long side by a specific distance in the second direction.

2. The semiconductor device according to claim 1, wherein, The plurality of dummy plugs are located between the plurality of unit plugs adjacent in the second direction, and are spaced apart in the first direction and spaced apart from each of the plurality of unit plugs. The plurality of unit plugs are spaced apart in the second direction.

3. The semiconductor device according to claim 1, wherein, The distance between adjacent unit plugs in the first direction is greater than the distance between adjacent dummy plugs in the first direction.

4. The semiconductor device according to claim 1, wherein, The plurality of unit plugs are arranged at specific distances in the first direction and the second direction, respectively. Wherein, the unit plugs arranged in the first direction overlap in the first direction, and The unit plugs arranged in the second direction overlap in the second direction.

5. The semiconductor device according to claim 1, wherein, The plurality of unit plugs are arranged at specific distances in the first direction and the second direction, respectively. Wherein, the unit plugs arranged in the first direction completely overlap in the first direction, and In this configuration, the unit plugs arranged in the second direction partially overlap in the second direction.

6. The semiconductor device according to claim 1, wherein, The plurality of unit plugs are arranged at specific distances in the first direction and the second direction, respectively. Wherein, the unit plugs arranged in the first direction partially overlap in the first direction, and The unit plugs arranged in the second direction overlap in the second direction.

7. The semiconductor device according to claim 1, wherein, The plurality of unit plugs are arranged at specific distances in the first direction and the second direction, respectively. Wherein, the unit plugs arranged in the first direction partially overlap in the first direction, and In this configuration, the unit plugs arranged in the second direction partially overlap in the second direction.

8. The semiconductor device according to claim 1, wherein, The insulating spacer includes an outer surface and an inner surface. The outer surface contacts the unselected electrode and the molded insulating layer, and The inner surface contacts the outer surface of each of the plurality of unit plugs.

9. The semiconductor device according to claim 1, wherein, Each of the gate electrodes includes a conductive layer and a coating surrounding the conductive layer. Each of the plurality of unit plugs contacts the conductive layer of the selected electrode, and The coating of the selected electrode contacts a portion of the side surface of each of the plurality of unit plugs.

10. The semiconductor device according to claim 9, wherein, Each of the plurality of unit plugs contacts the selected electrode in a groove in the conductive layer, and The groove is recessed in the vertical direction.

11. The semiconductor device according to claim 1, wherein, Regardless of the height of each of the plurality of unit plugs in the vertical direction, each of the plurality of unit plugs has substantially the same planar area.

12. The semiconductor device according to claim 11, wherein, The first length of each of the plurality of unit plugs is proportional to the height of each of the plurality of unit plugs in the vertical direction.

13. A semiconductor device, the semiconductor device comprising: Peripheral circuit structure; And a unit structure, which is located on the peripheral circuit structure, and the unit structure includes a unit region and a connection region. The unit structure includes: A gate electrode and a molded insulating layer are located in the cell region and the connection region and are alternately stacked in the vertical direction; A channel structure located in the cell region and extending along the vertical direction through the gate electrode and the molded insulating layer; Multiple dummy plugs are located in the connection region and extend along the vertical direction through the gate electrode and the molded insulating layer; A plurality of unit plugs are located in the connection region, each of the plurality of unit plugs contacting a selected electrode among the gate electrodes and passing through an unselected electrode among the gate electrodes, the unselected electrode being at a different vertical height from the selected electrode; and Multiple insulating spacers are located on the side surface of each of the multiple unit plugs. The plurality of insulating spacers are spaced apart in the vertical direction and each is located between each of the unselected electrodes and each of the plurality of unit plugs. Each of the plurality of insulating spacers includes an outer surface and an inner surface, the outer surface contacting each of the unselected electrodes, and the inner surface contacting the outer surface of each of the plurality of unit plugs. The height of each of the plurality of insulating spacers in the vertical direction is substantially the same as the height of the corresponding unselected electrode in the vertical direction. Each of the plurality of unit plugs has a first length in a first direction and a second length in a second direction intersecting the first direction, wherein the first length is greater than the second length, and The plurality of dummy plugs are spaced apart in the first direction while maintaining a specific distance from each of the plurality of unit plugs in the second direction.

14. The semiconductor device according to claim 13, wherein, Each of the plurality of unit plugs has a first long side and a second long side extending in the first direction, and a first short side and a second short side extending in the second direction.

15. The semiconductor device according to claim 14, wherein, The plurality of dummy plugs are spaced apart from the first long side in the first direction and from the second long side in the first direction.

16. The semiconductor device according to claim 14, wherein, The plurality of dummy plugs are spaced apart from the first short side or the second short side.

17. The semiconductor device according to claim 13, wherein, Each of the gate electrodes includes a conductive layer and a coating surrounding the conductive layer. Each of the plurality of insulating spacers is located between the side surface of each of the unselected electrodes and each of the plurality of unit plugs. The first side surface of the conductive layer of each of the unselected electrodes faces the side surface of each of the plurality of unit plugs. The first side surface of the coating of each of the unselected electrodes faces the side surface of each of the plurality of unit plugs, and The first side surface of each of the plurality of insulating spacers directly contacts the first side surface of the conductive layer of each of the unselected electrodes and the first side surface of the coating of each of the unselected electrodes.

18. A semiconductor device, the semiconductor device comprising: Peripheral circuit structure; And a unit structure, which is located on the peripheral circuit structure, the unit structure including a unit area and a connection area. The unit structure includes: A gate electrode and a molded insulating layer are located in the cell region and the connection region and are alternately stacked in the vertical direction; A channel structure located in the cell region and extending along the vertical direction through the gate electrode and the molded insulating layer; Multiple dummy plugs are located in the connection region and extend along the vertical direction through the gate electrode and the molded insulating layer; Multiple unit plugs are located in the connection region, the multiple unit plugs contacting a selected electrode among the gate electrodes and passing through an unselected electrode among the gate electrodes, the unselected electrode being at a different vertical height from the selected electrode; and Insulating spacers are located on the side surfaces of each of the plurality of unit plugs. Each of the gate electrodes includes a conductive layer and a coating surrounding the conductive layer. The insulating spacer includes an outer surface and an inner surface, the outer surface contacting the unselected electrode and the molded insulating layer, and the inner surface contacting the outer surface of each of the plurality of unit plugs. Each of the plurality of unit plugs contacts the conductive layer of the selected electrode. The coating of the selected electrode contacts a portion of the side surface of each of the plurality of unit plugs. Each of the plurality of unit plugs has a first length in a first direction and a second length in a second direction intersecting the first direction, wherein the first length is greater than the second length. Each of the plurality of unit plugs has a first long side and a second long side extending in the first direction, and a first short side and a second short side extending in the second direction. The plurality of dummy plugs are spaced apart in the first direction and spaced apart by a specific distance from at least one of the first long side and the second long side in the second direction.

19. The semiconductor device according to claim 18, wherein, The plurality of dummy plugs are symmetrically located on both sides along the first direction relative to each of the plurality of unit plugs.

20. The semiconductor device according to claim 18, wherein, Each of the plurality of dummy plugs provides a support structure by contacting the molded insulating layer in the region between each of the plurality of unit plugs and each of the plurality of dummy plugs, and the molded insulating layer located below the selected electrode.

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