Methods for forming memory structures of 3D NAND flash memory

Abstract

A method for forming a memory structure for 3D NAND flash memory includes forming a layer stack over a substrate, the layer stack including an alternating sequence of gate layers and gate-to-gate spacer layers; forming recessed regions in sidewalls around memory holes in the layer stack; forming an initial charge-trapping layer in each recessed region; depositing a tunnel oxide layer in the memory holes; depositing a channel layer on the tunnel oxide layer; forming contact trenches in the layer stack; forming gate cavities in the layer stack by etching the gate layers laterally from the contact trenches in a direction toward the memory holes; oxidizing a portion of the initial charge-trapping layer in each gate cavity such that the oxidized portion forms a blocking oxide layer and a non-oxidized portion of the initial charge-trapping layer remains to form a final charge-trapping layer between the blocking oxide and the memory holes; and forming gate layers in the gate cavities by depositing gate material in the gate cavities through the contact trenches.

Description

Technical Field

[0001] This invention generally relates to a method for forming a memory structure for 3D NAND flash memory. Background Technology

[0002] Bit density in the 3D NAND flash memory roadmap is increasing every year. Until now, increases in bit density have been achieved by increasing the number of stacked memory cells along the vertical dimension. However, this approach is becoming increasingly difficult and costly. Therefore, there is growing interest in technologies that shrink cells along the vertical dimension. Vertical shrinkage (“z-pitch shrinkage”) is achieved by reducing the thickness of individual layers in the layer stack, such as word line (gate) layers and oxide gate spacer layers.

[0003] Current 3D NAND technology is typically based on so-called charge-trapping cells, which employ a charge-trapping layer (such as silicon nitride) as the storage layer. The charge-trapping layer is separated from the gate layer by a barrier oxide layer. Traditionally, the charge-trapping layer and the barrier oxide layer are deposited as a continuous layer along the sidewalls of the memory vias in a layer stack. z-shrinkage leads to a reduction in inter-cell spacing, which can in turn degrade the retention performance of the continuous charge-trapping layer. Therefore, a scalable technique is needed to allow the formation of discontinuous charge-trapping layers, so that each memory cell can be equipped with a separate charge-trapping layer. Summary of the Invention

[0004] A direct method for forming discontinuous charge trapping layers is as follows: trenching the gate layers of the memory stack from the memory apertures relative to the gate spacer layers using isotropic etching; depositing a continuous barrier oxide layer along the sidewalls of the memory apertures and within the trenches; cutting the continuous barrier oxide layer with isotropic etchback to form discrete barrier oxide layers in each trench; depositing a continuous charge trapping layer along the sidewalls of the memory apertures and within the trenches; and cutting the continuous charge trapping layer with isotropic etchback to form discrete charge trapping layers on the barrier oxide layer in each trench. However, this process requires two isotropic etchback processes with extremely high control precision to uniformly cut the barrier oxide layer and the charge trapping layer. It is conceivable that such process control will be difficult to achieve, or at least extremely challenging, with the reduction in z-pitch considered in future 3D NAND roadmaps.

[0005] In light of the above, the aim is to address this challenge and provide a method that allows for the reliable formation of discontinuous / cut barrier oxide layers and charge trapping layers under aggressive z-pitch reduction. Specifically, the aim is to achieve this while avoiding the need to cut continuous barrier and charge trapping layers through two highly controlled isotropic etch-back processes, or at least reducing the number of such etch processes required.

[0006] Therefore, according to one aspect of the present invention, a method for forming a memory structure for 3D NAND flash memory is provided, the method comprising: A layer stack is formed over a substrate, the layer stack comprising an alternating sequence of gate layers and gate spacer layers; A recessed region is formed in the sidewalls surrounding the memory hole by etching back the gate layer laterally relative to the gate spacer layer from the stacked memory hole. An initial charge trapping layer is formed in each recessed region; Deposit a tunneling oxide layer in the memory hole; Deposit a channel layer on the tunneling oxide layer; Contact trenches are formed in the stacked layers; A gate cavity is formed in the layer stack by etching the gate layer laterally back from the contact trench in the direction toward the memory hole, wherein the gate cavity exposes the initial charge trapping layer; A portion of the initial charge trapping layer in each gate cavity is oxidized, such that the oxidized portion forms a barrier oxide layer, and the non-oxidized portion of the initial charge trapping layer is retained to form a final charge trapping layer between the barrier oxide and the memory via; and After forming the barrier oxide layer and the final charge trapping layer, a gate layer is formed in the gate cavity by depositing gate material in the gate cavity via contact trenches.

[0007] The method according to this aspect enables the formation of a memory structure comprising vertically separated lateral memory stacks, each lateral memory stack including a corresponding discrete barrier oxide layer and a corresponding discrete charge trapping layer for each gate layer (or similarly for each memory cell).

[0008] Instead of depositing a continuous barrier oxide layer in the recessed region and then "cutting" it into multiple discrete portions by etching, this method forms discrete barrier oxide layers by oxidizing a portion of the initial charge trapping layer. The initial charge trapping layer is contacted via radially outward contact trenches and gate cavities, which are formed between gate spacer layers by removing a "sacrificial" gate layer. Therefore, discrete barrier oxide layers can be formed at each gate level without the need for separate deposition and etching of continuous barrier oxide layers.

[0009] This allows for reduced process variability because the thickness of the barrier oxide layer (in the lateral direction) can be precisely controlled by the degree / depth of oxidation of the initial charge-trapping layer. This is much easier to achieve than precise thickness control by depositing and etching back the barrier oxide material in the recessed region from the memory via.

[0010] The reduced process variability facilitates the formation of discrete charge-trapping layers. A common material choice for gate spacer layers is oxide (typically silicon oxide). Therefore, it is conceivable that performing region-selective deposition (ASD) of charge-trapping material on a previously deposited barrier oxide layer in a recessed region, without any apparent simultaneous deposition on the gate spacer layer, would be challenging. However, since the charge-trapping layer according to this method is formed prior to the formation of the barrier oxide layer, the gate layer can still be contacted from the memory via. For example, by being formed from a non-oxide material such as nitrides, such as silicon nitride, amorphous silicon (a-Si), or polycrystalline silicon, the gate layer can provide a material contrast with the gate spacer layer. Therefore, the gate layer facilitates the deposition of charge-trapping material with sufficient region selectivity to allow ASD of the charge-trapping material in the recessed region. An embodiment of ASD of discrete charge-trapping layers in a recessed region will be described below.

[0011] The reduced process variability resulting from forming a barrier oxide layer using an oxidation-based method also facilitates the formation of discrete charge trapping layers in the recessed region using non-ASD methods, which will be further elaborated below.

[0012] In summary, regardless of whether the charge trapping layer is formed using ASD or non-ASD methods, this method can therefore limit the number of deposition and etch-back processes required to form a discrete barrier oxide layer.

[0013] The approach in this regard enables the advantages discussed above to be achieved in a manner with minimal impact on overall process complexity. This is because the contact trenches and gate cavities are subsequently used to provide functional gate material, such as replacement metal gate (RMG) layers or stacks for each gate level.

[0014] In some embodiments, the method further includes: Before forming the initial charge trapping layer, an etch stop layer is formed on the etched-back gate layer in the recessed region; and Subsequently, an initial charge trapping layer is deposited on the etch stop layer in each recessed region; The presence of an etch stop layer further enhances process control, as lateral etchback of the gate layer from the contact trench can reliably stop at the etch stop layer. This contributes to the formation of a more uniform gate cavity, even when the gate layer and the initial charge trapping layer are formed from materials with little or no etch contrast (such as both being formed from silicon nitride). In any case, the etch stop layer can be used to shield the initial charge trapping layer from the etch chemicals used to etch the gate layer.

[0015] The method may further include opening the etch stop layer to expose the initial charge trapping layer before oxidizing the portion of the initial charge trapping layer in each gate cavity. Thus, the initial charge trapping layer can be exposed to the oxidizing environment or chemicals of subsequent oxidation processes.

[0016] In some embodiments, the etch stop layer is deposited in each recessed region by a (first) region-selective deposition process.

[0017] Therefore, an etch stop layer can be deposited in each recessed region by etching the stop material via ASD. During the etch stop material ASD, the gate layer defines a (seed) region that promotes deposition, while the gate spacer layer defines a (non-growth) region that inhibits deposition (e.g., after undergoing surface passivation), thereby helping to prevent the selective deposition of oxide material in the recessed region.

[0018] In some embodiments, the initial charge trapping layer is deposited on the etch stop layer in each recessed region by a (second) region-selective deposition process.

[0019] Therefore, instead of depositing a continuous charge-trapping layer and then "cutting" it into multiple discrete portions by etching, discrete charge-trapping layers can be deposited "directly" in the recessed region via ASD. This is achieved by a (discrete) etch-stop layer defining a seed (deposition-promoting) region ("growth region") within the recessed region, while the gate spacer layer defines a region that inhibits deposition (non-growth) (e.g., after surface passivation). This facilitates selective deposition of the charge-trapping material in the charge-trapping layer. Consequently, depositing charge-trapping material in the vertical regions between gate layers (i.e., the end faces of the gate spacer layer facing the memory holes) can be avoided, thus eliminating the need to cut continuous charge-trapping material layers by etching. By avoiding the need to cut the charge-trapping material by etching, the lateral thickness of the charge-trapping layer (i.e., the thickness dimension viewed in the lateral direction) can be precisely controlled by maintaining selective deposition growth conditions until the target thickness is reached.

[0020] In some embodiments, the portion of the initial charge-trapping layer is oxidized via a thermal oxidation process. Therefore, a simple, reliable, and cost-effective process can be used to form the barrier oxide layer, which is also relatively gentle on non-target layers (e.g., gate spacer layers). The thermal oxidation process also facilitates reliable oxidation in high aspect ratio structures.

[0021] In some embodiments, the portion of the initial charge-trapping layer is oxidized by a plasma oxidation process.

[0022] In some embodiments, contact trenches are formed after the deposition of the tunneling oxide layer and the channel layer. This enables a rational overall process flow, thereby avoiding the need for separate covering and exposure of the charge trapping layer from the memory vias before and after the formation of the barrier oxide layer.

[0023] In some embodiments, the method further includes filling the memory hole with a plugging material before forming the contact trench. Therefore, a charge trapping layer and (if present) a tunneling oxide layer and a channel layer can be applied from the memory hole side before forming the contact trench.

[0024] In some embodiments, the plugging material comprises an oxide. This can be particularly advantageous when the plugging material is deposited after the formation of the tunneling oxide layer and the channel layer. The oxide can thus be retained as an insulating filler in the memory holes of the finished memory structure.

[0025] In some embodiments that include forming an etch stop layer, the etch stop layer comprises a metal oxide or a metal nitride. Such etch stop materials (e.g., alumina, hafnium oxide, titanium oxide, or titanium nitride) facilitate process control because they provide sufficient etch contrast relative to typical sacrificial gate layer materials and charge trapping materials. Furthermore, they can define an efficient deposition-promoting surface for ASD with respect to the charge trapping material, particularly relative to non-metallic oxide or non-metallic nitride (typically silicon oxide) gate spacer layers. Additionally, metal oxides or metal nitrides can be reliably deposited on typical sacrificial gate layer materials via ASD.

[0026] In some embodiments, the etch stop layer is formed to have a (lateral) thickness of 2 nm or less. Since the etch stop layer serves only as an etch stop layer and optionally as a seed layer for the charge-trapping material ASD, it can be formed as a relatively thin layer. Therefore, the etch stop layer does not need to unnecessarily occupy the depth available in the recessed region for the initial charge-trapping layer.

[0027] In some embodiments, the initial charge-trapping layer is a silicon-containing layer, such as a silicon nitride layer. Silicon-containing layers are suitable for charge-trapping layers. Specifically, silicon nitride is an efficient and reasonable implementation of charge-trapping memory cells. Furthermore, silicon nitride is suitable for ASD on conformal metal oxides or metal nitrides without causing any significant co-deposition on silicon oxide. The silicon-containing layer (such as silicon nitride) can also be oxidized (e.g., in a thermal process) to form a high-quality barrier oxide. Attached Figure Description

[0028] The above and additional objects, embodiments, features, and effects of the invention will be better understood through the following illustrative and non-limiting detailed description, with reference to the accompanying drawings. Unless otherwise stated, the same reference numerals will be used for the same elements in the drawings.

[0029] Figure 1a -b schematically illustrates a schematic cross-sectional view and a top view of the initial structure for forming a memory structure according to an embodiment.

[0030] Figure 2 The structure after the formation of the depression region is shown.

[0031] Figure 3 The structure after forming an etch stop layer in the recessed region is shown.

[0032] Figure 4 The structure after the initial charge trapping layer is formed in the recessed region is shown.

[0033] Figure 5 The structure is shown after the formation of the tunnel barrier layer and the channel layer and the plugging of the memory holes.

[0034] Figure 6 The structure after removing the contact trenches in the layer stack is shown.

[0035] Figure 7 The structure after the gate cavity is formed is shown.

[0036] Figure 8 The structure after the etch stop layer in the gate cavity is turned on is shown.

[0037] Figure 9 The structure is shown after partially oxidizing the etch stop layer to form a barrier oxide layer in each gate cavity.

[0038] Figure 10 The structure after filling the gate cavity with gate material is shown. Detailed Implementation

[0039] Embodiments of a method for forming a memory structure for 3D NAND flash memory, such as 3D gate-all-around NAND (3D GAANAND), will now be described with reference to the accompanying drawings. The drawings are schematic only, and the relative dimensions of some structures and layers may be exaggerated and not drawn to scale. Instead, the dimensions may be adjusted to make the illustration clear and easy to understand. When present in the drawings, the indicated axes X, Y, and Z consistently refer to a first horizontal or lateral, a second horizontal or lateral, and a vertical direction, respectively. As used herein, the terms “horizontal” and “lateral” refer to directions parallel to the supporting substrate (main surface) of the memory structure. Lateral / horizontal direction can also be understood as a direction parallel to the in-plane direction of the gate layer and the gate spacer layer. The term “vertical” refers to a direction parallel to the normal direction of the substrate (main surface), i.e., lateral to the substrate. The term “radial” direction is also mentioned herein. This term should be understood relative to a given memory aperture (e.g., Figure 1a The radial direction of the memory hole 4) is parallel to the horizontal XY plane. Therefore, the terms "radially inward" and "radially outward" refer to the radially inward and outward directions relative to a given memory hole, respectively. Related terms (such as "radially inside" and "radially outside") may be used accordingly to indicate the relative radial position or distance of a feature or element relative to a given memory hole.

[0040] Figure 1a -b schematically illustrates a cross-sectional view and a top view of structure 1 in the initial stage of the method, respectively. Structure 1 includes a layer stack 10, which represents a precursor or initial structure for a memory structure, and will undergo the processing steps of the method disclosed below.

[0041] A layer stack 10 is formed over the substrate 2 and includes an alternating sequence of gate layer 14 and gate spacer layer 12. The gate spacer layer 12 and the gate layer 14 are stacked on top of each other in the vertical direction Z.

[0042] Substrate 2 can be a conventional substrate suitable for semiconductor processing and for supporting memory structures of 3D NAND flash memory. Substrate 2 can be, for example, a Si substrate, a Ge substrate, or a SiGe substrate. Other examples include silicon-on-insulator (SOI) substrates, GeOI substrates, or SiGeOI substrates.

[0043] Gate layer 14 can be a silicon-containing layer, such as a SiN layer, an amorphous silicon layer, or a polycrystalline silicon layer. Gate layer 14 is a sacrificial gate layer, intended to be replaced by an RMG stack in subsequent process steps.

[0044] The gate spacer layer 12 may be an oxide-containing layer, typically a silicon oxide (e.g., SiO2) layer or another suitable (e.g., low-k) interlayer dielectric. The gate spacer layer 12 is arranged in the layer stack 10 to provide vertical separation between memory cells / word lines of the memory device to be formed.

[0045] The layer stack 10 can be formed by depositing layers of gate material (e.g., nitride) and gate spacer material (e.g., oxide) interchangeably using deposition processes known in the art (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)).

[0046] The number of gate spacer layers 12 and gate layers 14 can be determined based on the expected number of stacked memory cells in the memory device. Note that the number of layers 12 and 14 in the illustrated layer stack 10 is merely a non-limiting example, and the methods disclosed herein are compatible with virtually any number (e.g., 64, 128, 256 or more) of memory cell stacks currently used or anticipated in the industry.

[0047] As an example, the gate spacer layer 12 and the gate layer 14 can each be formed to have a corresponding layer thickness in the range of 5-25 nm. The z-pitch of the layer stack 10 (i.e., the combined thickness of a gate spacer layer and a gate layer 14) can be in the range of about 45 nm to 15 nm or less.

[0048] Although omitted for illustrative purposes, the layer stack 10 may optionally be capped by a capping layer (e.g., a semiconductor layer (e.g., silicon) deposited on the topmost gate spacer layer 12). The capping layer may be used to protect the topmost gate spacer layer 12 during subsequent processing.

[0049] After layers 12 and 14 (and optional capping layer) of the deposition layer stack 10, memory holes 4 can be patterned in the layer stack 14 by photolithography and etching processes. Although Figure 1a -b shows a portion of the layer stack 10 surrounding a single memory hole 4, but it should be noted that the corresponding memory hole 4 can be patterned at each location of the corresponding vertical string of memory cells. As shown, the memory hole 4 can be formed to extend through each gate spacer layer 12 and gate layer 14 of the layer stack 10. Figure 1b As further shown in the top view, the memory hole 4 can be formed with a circular cross-sectional shape (occupying an area), such that the memory hole 4 can be formed with a generally cylindrical shape. However, the memory hole 4 can also be formed with other cross-sectional shapes, such as elliptical or polygonal shapes.

[0050] Although Figure 1aNot shown, but as is known in the art, layer stack 10 may also include sub-stacks of select layers and source layers below layers 12 and 14, for forming the select plate and source plate of the memory device, respectively. Thus, the select layer and source layer can form the bottom sub-stack of layer stack 10. The select layer and source layer can be formed using conventional techniques and materials (e.g., doped semiconductor layers, such as polysilicon) and are separated by layers of interlayer dielectric.

[0051] exist Figure 2 In this process, a recessed region 18 is formed in the sidewalls of the layer stack 10 surrounding the memory hole 4 by etching back the gate layer 14 relative to the gate spacer layer 12 in the lateral direction (i.e., along the X-axis, in the radially outward direction) from the memory hole 4. Thus, each recessed region / groove 18 is formed between a pair of gate spacer layers 12. Due to its circumferential extension around the sidewalls of the memory hole 4, the recessed region 18 can extend circumferentially around the memory hole 4. In the example of a circular memory hole 4, the recessed region 18 can be annular.

[0052] The gate layer 14 can be etched back using an etching process suitable for selectively etching the gate layer 14 relative to the gate spacer layer 12. That is, the etching process can be adapted to selectively etch (i.e., remove) the material of the gate layer 14 (e.g., silicon nitride, amorphous silicon, or polycrystalline silicon) relative to the material of the gate layer 14 (e.g., an oxide material), such that the gate layer 14 can be etched back laterally without causing any substantial etch back of the gate spacer layer 12. The etching process can be adapted to be applied to the sidewalls of the layer stack 10 through the memory via 4. The etching process can be an isotropic etching process. However, any suitable selective etching process (wet or dry) that provides sufficient lateral etch content for the gate layer 14 can be used.

[0053] The recessed region 18 can be formed with a lateral / radial depth (along the X-axis) that satisfies or exceeds the expected lateral thickness of the lateral memory stack, such as the combined lateral thickness of the barrier oxide and charge trapping layer at each gate level. Figure 9 It can be understood that the lateral depth of the recessed region 18 is determined by the lateral depth (radial extension) of the lateral etching back. For example, the lateral depth of the recessed region 18 can be in the range of 6-20 nm. The depth of the recessed region 18 can be controlled by controlling the time of the lateral etching back.

[0054] exist Figure 3 In this process, an etch stop layer 20 has been deposited on the etched-back gate layer 14 in the recessed region 18. The etch stop layer 20 is a discrete layer, and each discrete layer is formed in a corresponding recessed region 18, for example on a corresponding gate layer 14.

[0055] The purpose of etching the stop layer 20 is to facilitate the subsequent gate cavity formation step. Figure 7 During this period, it acts as an etch stop layer. Another optional purpose of the etch stop layer 20 is to act as a seed layer for the charge trapping material ASD. Figure 4 The etch stop layer 20 will also be removed before the barrier oxide layer is formed. Figure 9 Therefore, the etch stop layer 20 is only a temporary process layer and has no function or may not exist in the final memory structure. Thus, as... Figure 3 As shown, the etch stop layer 20 can typically be formed as a relatively thin layer, and its thickness will in any case not exceed the thickness required to provide the functionality.

[0056] Since the recessed region 18 will also accommodate some of the initial charge trapping layer 21 of minimum target thickness, each etch stop layer 20 is deposited to only partially fill its associated recessed region 18. Therefore, also after the formation of the etch stop layer 20, the sidewalls of the memory via 4 define the recessed / contoured sidewalls. The etch stop layer 20 is formed to have a thickness less than the lateral depth (along the X-axis) of the recessed region 18. Here, the thickness of the etch stop layer 20 refers to its lateral thickness, the thickness along the X-axis, i.e., the in-plane direction parallel to the gate layer 14. For example, the etch stop layer 20 may be formed to have a thickness of about 2 nm or less (such as about 1 nm). This range of thicknesses is compatible with the aforementioned depth range of the recessed region 18 and the thickness range of the initial charge trapping layer 21 discussed below.

[0057] For example, the etch stop layer 20 may comprise or be formed of a metal oxide or metal nitride, such as AlO. x HfO x TiN, TiO2, or some other material (high-k oxide or nitride) suitable for use as an etch-stopping material. These materials can also facilitate the use of charge-trapping materials in ASD as described below.

[0058] The etch stop layer 20 can advantageously be deposited on the etch-back gate layer 14 in each recess region 18 using an ASD process (first ASD process). Therefore, etch stop material for forming the etch stop layer 20 can be selectively deposited in the recess regions 18. This deposition can continue until discrete portions of etch stop material of a target thickness are deposited in each recess region 18, each portion defining a corresponding discrete etch stop layer 20. During ASD, the etch-back end face of the gate layer 14 facing the memory hole 4 can define a (seed) region that promotes the deposition of the etch stop material, while the gate spacer layer 12 defines a (non-growth) region that inhibits deposition. The etch stop material can be deposited using any suitable deposition process (e.g., ALD or CVD process) that facilitates the deposition of the etch stop material in the recess regions 18.

[0059] It is conceivable that typical material choices for gate layer 14 (e.g., silicon nitride, amorphous silicon, or polycrystalline silicon) can provide a sufficiently favorable surface for growth relative to the gate spacer layer (e.g., silicon oxide) to facilitate ASD of the etch-stop material (e.g., metal oxide or nitride). To further facilitate ASD of the etch-stop layer 20, the layer stack 10 may optionally undergo a processing step prior to the deposition of the etch-stop material to define a growth region within the recessed region 18 (e.g., on the end face of the etched-back gate layer 14) and a non-growth region outside the recessed region 18. This processing step can be adapted to functionalize the surface portion / end face of the etched-back gate layer 14 in the ASD recessed region 18 relative to the etch-stop material. Alternatively or complementary, the processing step can be adapted to passivate the exposed surface portion of the ASD gate spacer layer 12 relative to the barrier oxide material. The etch-stop material can then be selectively deposited in the growth region within the recessed region 18. For example, functionalization may include depositing a deposition-facilitating layer on the end face of the etched-back gate layer 14 in the recessed region 18. Alternatively or complementary, the layer stack 10 may undergo a processing adapted to the exposed surface portion of the ASD passivated gate spacer layer 12 relative to the etch-stop material. For example, some deposition processes favor deposition on hydrogen-terminated surfaces (e.g., deposition processes preferentially deposit material on hydrogen-terminated surfaces). Therefore, the processing may be adapted to increase the presence of hydrogen-terminated bonds on the gate layer 14 (thus facilitating deposition thereon) and / or decrease the presence of hydrogen-terminated bonds on the gate spacer layer 12 (thus suppressing deposition thereon). As another example, siloxanes, aminosilanes, trichlorosilanes, small molecule inhibitors (SMIs, such as dimethylaminotrimethylsilane (DMA-TMS), trimethyltrimethoxysilane, trimethoxytrichlorosilane, etc.) or self-assembled monolayers (SAMs, such as alkylsilanes) can be used to selectively passivate the silicon oxide (SiO2) gate spacer layer 12 relative to the silicon nitride / amorphous silicon / polycrystalline silicon gate layer 14 to allow etch-stop material on the ASD at the end face of the gate layer 14.

[0060] While using ASD to form the etch stop layer 20 can be advantageous, non-selective deposition of the etch stop material can also be used to form it. For example, the etch stop material can be deposited using a conformal and non-selective deposition process. Subsequently, portions of the etch stop material deposited outside the recess 18 can be removed by an anisotropic etching process biased in one direction (e.g., substantially from top to bottom in the Z direction), such that the etch stop material deposited within the recess 18 is shielded from etch chemicals, at least on the etch-back end faces of the gate layer 14 (which define the surface portions furthest from the memory via 4), by the overhangs provided by the gate spacer layer 12. Since the etch stop layer 20 can be formed as a relatively thin layer (e.g., about 2 nm or less), any etch stop material portions that may remain on the surface portions of the gate spacer layer 12 within the recess 18 can have a relatively minor impact on the available space of the initial charge trapping layer 21. Furthermore, a relatively short etching step is sufficient to remove the charge trapping material deposited outside the recess 18. Alternatively, the non-selective deposition method described below for charge-trapping materials can be applied in a corresponding manner to achieve non-selective deposition of etch-stop materials. In this case, the etch-stop material can be etched back until the etch-stop material remains essentially only on the etched-back end faces of the gate layer 14 (these end faces define the surface portion furthest from the memory via 4).

[0061] exist Figure 4 In this process, an initial charge trapping layer 21 has been formed in each recessed region 18. The initial charge trapping layer 21 is a discrete layer, and each discrete layer is formed in the corresponding recessed region 18 on the etch stop layer 20.

[0062] The initial charge trapping layer 21 can be formed by an ASD process (second ASD process) using an etch stop layer 20 as a seed layer. Therefore, by using the etch stop layer 20 as a seed (nucleating thereon), charge trapping material can be selectively deposited in the recessed region 18.

[0063] The deposition of charge-trapping material can continue until discrete portions of the charge-trapping material of the target thickness are deposited in the recessed region 18, each portion defining a corresponding discrete charge-trapping layer 21. During ASD, the gate spacer layer 12 defines a (non-growth) region that inhibits the deposition of charge-trapping material, while the etch stop layer 20 defines a (seed) region that promotes the deposition of charge-trapping material.

[0064] Charge-trapping materials can include silicon nitride (SiN, i.e., Si3N4). Silicon nitride is an efficient and reasonable way to implement charge-trapping memory cells. For example, silicon nitride can be deposited onto any of the above-mentioned examples of etch stop layer materials (metal oxides or metal nitrides, such as Al2O3) using ASD. x HfO x The initial charge trapping layer 21 can be a silicon-containing layer, such as TiN or TiO2. More generally, the charge trapping material can be or contains silicon, meaning the initial charge trapping layer 21 can be a silicon-containing layer. For example, the charge trapping material can be silicon, meaning the initial charge trapping layer 21 can contain or contain a silicon layer. Composite layer structures of the initial charge trapping layer 21 are also possible. For example, the initial charge trapping layer 21 can include first and second layers (sublayers) deposited sequentially, wherein the first sublayer is silicon or a silicon-containing layer, and the second sublayer is a metal layer (such as TiN or Ru). The first sublayer will be the portion of the initial charge trapping layer 21 exposed from the gate cavity 22. Figure 7 Therefore, the first layer of each initial charge trapping layer 21 can be a silicon-containing layer or a silicon layer, such that the barrier oxide layer 24 can be formed by its oxidation, as described below. It is conceivable that ASDs can also be used for other options of charge trapping materials, as long as they can be deposited on the etch stop layer 20 in the recessed region 18 in a region-selective manner and can be oxidized to form the barrier oxide layer 24. Any suitable deposition process (conformal or non-conformal) – such as ALD or CVD processes – can be used to deposit the charge trapping material.

[0065] To facilitate ASD of the charge-trapping material, the layer stack 10 may undergo a processing step prior to depositing the charge-trapping material to define a growth region within the recessed region 18 (e.g., on the etch stop layer 20) and a non-growth region outside the recessed region 18. This processing step may be adapted to (further) functionalize the etch stop layer 20 relative to the ASD of the charge-trapping material. As a supplement or alternative, the processing step may be adapted to passivate the exposed surface portion of the gate spacer layer 12 relative to the ASD of the charge-trapping material. Subsequently, the charge-trapping material may be selectively deposited on the growth region within the recessed region 18. The examples of functionalization and passivation discussed above regarding ASD of the reference barrier oxide material are correspondingly applicable to ASD of the charge-trapping material. As a specific, non-limiting example, the SiO2 surface may be selectively passivated by DMA-TMS suppression relative to TiO2 or TiN.

[0066] While using ASD to form the initial charge-trapping layer 21 can be advantageous, non-selective deposition of the charge-trapping material can also be used to form the initial charge-trapping layer 21. For example, the charge-trapping material can be deposited as a continuous layer using a conformal deposition process to completely fill (e.g., by pinching) the recessed region 18. The local lateral thickness (along the X direction) of the charge-trapping material deposited in the recessed region 18 can therefore exceed the local thickness of the charge-trapping material deposited outside the recessed region 18. Subsequently, the charge-trapping material can be etched back (e.g., isotropically) such that portions of the charge-trapping material deposited outside the recessed region 18 are removed, and the portions of the charge-trapping material filling the recessed region 18 are retained to define a discrete initial charge-trapping layer 21 therein.

[0067] At the current stage of the process, the blocking oxide layer 24 ( Figure 9 The initial charge-trapping layer has not yet been formed. Therefore, during the formation of the initial charge-trapping layer, prior deposition and etch-back of the blocking oxide have not yet occurred. Consequently, the variability between the recesses 18 (e.g., in terms of the depth, height, and profile of the interior space of the recesses 18) can be smaller. More uniform recesses, in turn, facilitate control over both the deposition thickness of the continuous charge-trapping layer and the etch-back.

[0068] Regardless of whether the initial charge trapping layer 21 is formed using an ASD or non-ASD process, the initial charge trapping layer 21 can each be formed to have a lateral thickness (along the X-axis) in the range of approximately 6-20 nm (e.g., 6-20 nm minus the thickness of the etch stop layer 20). More generally, the initial charge trapping layer 21 can be formed to completely fill the remaining internal space of the recessed region 18 after the formation of the etch stop layer 20. The end face of the discrete initial charge trapping layer 21 facing the memory hole 4 can therefore become substantially flush with the end face of the gate spacer layer 12 facing the memory hole 4. In other words, the sidewalls of the memory hole 4 can (e.g., again) be restored to a substantially straight profile, or have at least a reduced morphology compared to before the formation of the initial charge trapping layer 21.

[0069] Therefore, in Figure 4 In the process stages shown, each recessed region 18 has been equipped with (e.g., “refilled” and / or “regrown”) an etch stop layer 20 and an initial charge trapping layer 21.

[0070] exist Figure 5In this structure, a tunneling oxide layer 30 and a subsequent channel layer 32 have already been formed along the sidewalls of the memory aperture 4. Therefore, the tunneling oxide layer 30 is formed or contacts the initial charge trapping layer 21 of the lateral memory stack (more specifically, along the corresponding radially inward end face of the initial charge trapping layer 21 facing the memory aperture 4). The tunneling oxide layer 30 and the channel layer 32 can each be conformally deposited, for example, using a corresponding ALD process. After the tunneling oxide layer 30 is deposited, it can be subjected to top-down (opposite to the Z-axis direction) anisotropic etching to remove portions of the tunneling oxide layer 30 deposited on the horizontally oriented surface of structure 1.

[0071] The tunneling oxide layer 30 can be formed of any material conventionally used in the industry for tunneling oxide layers; a non-limiting example is SiON. Similarly, the channel layer 32 can be formed of any suitable channel material conventionally used in the industry for channel layers, typically a semiconductor material (e.g., Si, SiGe, or Ge). Although Figure 4 Although not shown, the channel layer 32 may extend beyond the portion shown in structure 1 to facilitate connection with peripheral semiconductor devices and circuit systems such as selection transistors.

[0072] After forming the tunneling oxide layer 30 and the channel layer 32, the memory via 4 is filled with an embolization or filler material 34 (such as an interlayer dielectric (e.g., SiO2) or other low-k dielectric). The embolization material 34 can be deposited, for example, by CVD or physical vapor deposition (PVD). Subsequently, the structure 1 can be planarized (e.g., by chemical mechanical polishing (CMP)) to remove excess embolization material outside the memory via 4, thereby obtaining... Figure 5 Structure 1 is shown.

[0073] exist Figure 6 In the layer stack 10, contact trenches 19 have already been formed. Contact trenches 19 are formed at locations outside the memory vias 4 in the layer stack 10, i.e., spaced laterally / radially from the memory vias 4. Contact trenches 19 extend through each gate spacer layer 12 and gate layer 14 of the layer stack 10. Therefore, contact trenches 19 expose the radially outward-facing end surface of each gate layer 14 relative to the memory vias 4. In the illustrated example, contact trenches 19 are formed after channel layer 32 and thus extend further through channel layer 32. Contact trenches 19 can be patterned in the layer stack 10 using photolithography and etching processes.

[0074] The contact groove 19 can be formed to at least partially surround the memory hole 4. As shown, the contact groove 19 can be formed on opposite sides of the memory hole 4, for example, as two slit-shaped groove segments or as a continuously extending groove. For example, the contact groove 19 can be formed to circumferentially (i.e., completely circumferentially surround) the memory hole 4. In this case, the contact groove 19 can have a cross-sectional area / shape (viewed from top to bottom) corresponding to the memory hole 4. For example, as a non-limiting example, if the memory hole 4 is circular, the contact groove 19 can be annular and substantially concentric with the memory hole 4.

[0075] Although Figure 6 A contact groove 19 is shown, but it should be noted that a corresponding contact groove can be formed for each other memory hole 4 in structure 1. Adjacent memory holes can also share a contact groove. For example, a pair of slit-shaped contact groove segments can be formed on opposite sides of one or more rows of memory holes.

[0076] exist Figure 7 In the layer stack 10, a gate cavity 22 has been formed between the gate spacer layers 12 by laterally etching back the gate layer 14 from the contact trench 19 in the direction toward the memory hole 4 (i.e., laterally, in the radially inward direction). The discussion regarding the lateral etchback of the gate layer 14 to form the recessed region 18 applies accordingly to the etching of the gate cavity 22. Therefore, the etching process can be an isotropic etching process, or any other suitable selective etching process (wet or dry) can be used, which provides a sufficient lateral etch component toward the gate layer 14. For example, the gate cavity can be etched using the same type of etching process used to form the recessed region 18. Due to the lateral etch component of the etching process used to etch back the gate layer 14, as shown, the gate layer 14 can further extend radially outward from the contact trench 19, for example toward one or more adjacent memory holes.

[0077] The etchback has stopped (in the radially inward direction) on the etch stop layer 20 that separates the initial charge trapping layer 21 from the gate cavity 22. The etch stop layer 20 can be used in particular for etch stop detection, but timed etchback is also possible if the etch stop layer 20 can ensure that over-etching into the initial charge trapping layer 21 is avoided. Furthermore, since the position of the etch stop layer 20 is determined by the etchback depth of the gate layer 14 used to form the recessed region 18, the formation of the gate cavity 22 can be relatively insensitive to slight off-center placement of the contact trench 19 relative to the memory hole 4 (e.g., non-concentric placement, which may occur due to edge placement errors during the photolithographic patterning of the contact trench 19).

[0078] Therefore, in Figure 7In the process stage shown, gate cavities 22 extending radially and circumferentially have been formed at each gate level, wherein each gate cavity 22 is separated from the memory aperture 4 (here filled with plug material 34) by discrete etch stop layers 20 and discrete initial charge trapping layers 21. In the example of a circular memory aperture 4, the gate cavity 22 may be annular.

[0079] exist Figure 8 In this process, the etch stop layer 20 (e.g., through a short isotropic etch step) has been opened to expose the initial charge trapping layer 21 in each gate cavity 22, and more specifically, the radially outward end face of each initial charge trapping layer 21. Therefore, the initial charge trapping layer 21 is ready for subsequent oxidation processes.

[0080] exist Figure 9 In each gate cavity 22, the radially outer portion 21b of the initial charge trapping layer 21 ( Figure 8 As shown, the radially inner unoxidized portion 21a of each initial charge trapping layer 21 (shown in the figure) has been oxidized to form discrete barrier oxide layers 24. Figure 8 (As shown in the diagram) This layer is retained to form the final charge trapping layer 26 between the barrier oxide layer 24 and the memory via 4. The initial charge trapping layer 21 can be exposed to the oxidation environment / oxidant of the oxidation process through the gate cavity 22.

[0081] Thus, discrete barrier oxide layers 24 can be formed without separately depositing and etching continuous barrier oxide layers. Furthermore, the thickness of the barrier oxide layer 24 (i.e., its lateral thickness along the X direction) can be precisely controlled by the oxidation depth of the initial charge-trapping layer 21. Assuming the initial thickness of the initial charge-trapping layer 21 is within the range described above, the oxidation depth (and therefore the thickness of the barrier oxide layer 20) can, for example, be in the range of 4-15 nm, depending on the initial thickness of the initial charge-trapping layer 21 and the target thickness of the final charge-trapping layer 26.

[0082] When the initial charge trapping layer 21 is a silicon-containing layer (such as a silicon nitride layer or a silicon / metal layer), the blocking oxide layer 24 can be formed as a silicon oxide (SiO2) layer.

[0083] The oxidation process can be, for example, a thermal oxidation process. Therefore, the barrier oxide layer 20 can be formed by a thermal oxide. The oxide can be a low-temperature oxide (LTO) or a high-temperature oxide (HTO). An alternative to the thermal oxidation process is a plasma oxidation process.

[0084] exist Figure 10In this process, after forming the barrier oxide layer 24 and the final charge trapping layer 26, a final (functional) gate layer or stack 36 is formed in the gate cavity 22 by depositing gate material in the gate cavity 22 via contact trench 19. This corresponds to gate layer / gate stack deposition in an RMG process. Gate material deposition may include depositing one or more conductive layers, such as metals (such as one or more of TiN and W). The deposition of conductive layers may be performed after the deposition of a (conformal) high-k gate dielectric.

[0085] Therefore, in Figure 10 In the process stage shown, the memory structure 1 has been formed to include discrete barrier oxide layers 24 and discrete charge trapping layers 26 for each gate level. These layers define a lateral memory stack between the respective gate layers / stacks 36 and the (shared) tunnel barrier layer 30 and channel layer 32.

[0086] This process can be further carried out with conventional process steps in 3D NAND manufacturing, as known in the art. For example, structure 1 can be further processed to contact each gate layer 36 with peripheral semiconductor devices and circuit systems, such as select transistors and word line drivers. For example, the gate layer 36 can be patterned into a stepped structure prior to contact formation.

[0087] Although in the foregoing, the contact trench 19 and gate cavity 22 are formed after the tunneling barrier layer 30 and channel layer 32, the reverse order is also possible. For example, after forming the initial charge trapping layer 21, the memory hole 4 can be filled with a temporary plugging material. Subsequently, the contact trench 19 and gate cavity 22 can be formed, a barrier oxide layer 24 can be formed by applying an oxidation process, and the gate cavity can be filled with gate material 36. Subsequently, the temporary plugging material can be removed, and the tunneling barrier layer 30 and channel layer 32 can be formed in the memory hole 4. However, it is conceivable that the illustrated order of forming the contact trench 19 and gate cavity 22 after forming the tunneling barrier layer 30 and channel layer 32 would result in a more efficient overall process.

[0088] Furthermore, the exemplary embodiments discussed above include forming an etch stop layer 20 prior to forming the initial charge trapping layer 21. However, it is conceivable that a corresponding oxidation-based method for forming the barrier oxide layer 24 could also be used in a process flow that omits such an etch stop layer 20. According to this variation, the method can continue forming discrete initial charge trapping layers 21 in the recessed region 18 directly after the formation of the recessed region 18. In this case, the initial charge trapping layer 21 can be formed by ASD of the charge trapping material, using the etched-back end face of the gate layer 14 exposed in the recessed region 18 as a seed (e.g., after functionalizing and / or passivating the gate layer 14 and the gate spacer layer 12, respectively). When the gate cavity 22 is formed ( Figure 7 When the gate layer 14 is etched back, the etching can stop accordingly on the initial charge trapping layer 21. Therefore, this approach is more suitable when the gate layer 14 and the charge trapping layer 21 are formed of materials that provide sufficient contrast relative to the etching process used to form the gate cavity 22. However, in principle, this approach can also be used when the gate material and the charge trapping material provide little or no etch contrast, provided that the contact trench 19 is precisely aligned (e.g., concentrically) with the memory hole 4 and the etching process is precisely timed so that the initial charge trapping layer 21 can be exposed along the entire circumference of the memory hole 4 without over-etching in any radial direction.

[0089] Those skilled in the art will recognize that the present invention is by no means limited to the embodiments described above. Rather, many modifications and variations are possible within the scope of the appended claims.

Claims

1. A method for forming a memory structure (1) of 3D NAND flash memory, the method comprising: A layer stack (10) is formed over a substrate (2), the layer stack (10) comprising an alternating sequence of gate layers (14) and gate spacer layers (12); By etching back the gate layer (14) in the lateral direction relative to the gate spacer layer (12) from the memory hole (4) in the stack of layers (10), a recessed region (18) is formed in the sidewall surrounding the memory hole (4). An initial charge trapping layer (21) is formed in each recessed region (18); A tunneling oxide layer (30) is deposited in the memory hole (4); A channel layer (32) is deposited on the tunneling oxide layer (30); Contact trenches (19) are formed in the stack of layers (10); A gate cavity (22) is formed in the layer stack (10) by etching back the gate layer (14) laterally from the contact trench (19) in the direction toward the memory hole (4), wherein the gate cavity (22) exposes the initial charge trapping layer (21). A portion (21b) of the initial charge trapping layer (21) in each gate cavity (22) is oxidized, such that the oxidized portion (21b) forms a barrier oxide layer (24), and the non-oxidized portion (21a) of the initial charge trapping layer is retained to form a final charge trapping layer (26) between the barrier oxide (24) and the memory hole (4). as well as After the barrier oxide layer (24) and the final charge trapping layer (26) are formed, a gate layer (36) is formed in the gate cavity (22) by depositing gate material in the gate cavity (22) via the contact trench (19).

2. The method according to claim 1, characterized in that, Also includes: Before forming the initial charge trapping layer (21), an etch stop layer (20) is formed on the etched back gate layer (14) in the recessed region (18). as well as Subsequently, the initial charge trapping layer (21) is deposited on the etch stop layer (20) in each recessed region (18). The etchback from the contact trench (19) to the gate layer (14) stops at the etch stop layer (20), and The method further includes opening the etch stop layer (20) to expose the initial charge trapping layer (21) before oxidizing the portion (21b) of the initial charge trapping layer (21) in each gate cavity (22).

3. The method according to claim 2, characterized in that, The etch stop layer (20) is deposited in each recessed region (18) by a first region selective deposition process.

4. The method according to any one of claims 2-3, characterized in that, The initial charge trapping layer (21) is deposited on the etch stop layer (20) in each recessed region (18) by a second region selective deposition process.

5. The method according to any one of the preceding claims, characterized in that, The portion (21b) of the initial charge trapping layer (21) is oxidized by a thermal oxidation process or a plasma oxidation process.

6. The method according to any one of the preceding claims, characterized in that, The contact trench (19) is formed after the deposition of the tunneling oxide layer (30) and the channel layer (32).

7. The method according to any one of the preceding claims, characterized in that, It also includes filling the memory hole (4) with plugging material (34) before forming the contact groove (19).

8. The method according to claim 7, characterized in that, The embolic material (34) contains oxides.

9. The method according to any one of the preceding claims, wherein, when referring to claim 2, it is characterized in that, The etch stop layer (20) comprises a metal oxide or a metal nitride.

10. The method according to any one of the preceding claims, wherein, when referring to claim 2, it is characterized in that, The etch stop layer (20) is formed to have a thickness of 2 nm or less.

11. The method according to any one of the preceding claims, characterized in that, Each initial charge trapping layer (21) is a silicon-containing layer, such as a silicon nitride layer.

12. The method according to any one of the preceding claims, characterized in that, The gate spacer layer (12) and the gate layer (14) are formed to have corresponding layer thicknesses in the range of 5-25 nm.

13. The method according to claim 12, characterized in that, The combined thickness of a gate spacer layer (12) and a gate layer (14) is 45 nm or less.

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