Methods for forming memory structures of 3D NAND flash memory

Abstract

A method for forming a memory structure for 3D NAND flash memory includes forming a layer stack over a substrate, the layer stack including an alternating sequence of gate layers and inter-gate spacer layers; forming recessed regions in sidewalls around memory holes in the layer stack by etching back the gate layers relative to the inter-gate spacer layers in a lateral direction from the memory holes in the layer stack; forming discrete blocking oxide layers in each of the recessed regions; depositing a continuous liner layer conformally on exposed surfaces in the memory holes; depositing a continuous sacrificial layer on the liner layer; etching back the sacrificial layer such that the liner layer is exposed outside the recessed regions and discrete portions of the sacrificial layer remain in the recessed regions; removing the exposed portions of the liner layer such that discrete portions of the liner layer covered by the discrete sacrificial layer portions remain in the recessed regions; removing the discrete portions of the sacrificial layer in the recessed regions; forming discrete charge trapping layers in each of the recessed regions; depositing a tunnel oxide layer in the memory holes; and depositing a channel layer on the tunnel oxide layer.

Description

Technical Field

[0001] This invention generally relates to a method for forming a memory structure for 3D NAND flash memory. Background Technology

[0002] Bit density in the 3D NAND flash memory roadmap is increasing every year. Until now, increases in bit density have been achieved by increasing the number of stacked memory cells along the vertical dimension. However, this approach is becoming increasingly difficult and costly. Therefore, there is growing interest in technologies that shrink cells along the vertical dimension. Vertical shrinkage (“z-pitch shrinkage”) is achieved by reducing the thickness of individual layers in the layer stack, such as word line (gate) layers and oxide gate spacer layers.

[0003] Current 3D NAND technology is typically based on so-called charge-trapping cells, which use charge-trapping layers (such as silicon nitride) as storage layers. Traditionally, the charge-trapping layer is a continuous layer deposited along the sidewalls of the memory vias in a layer stack. Z-scaling leads to a reduction in the inter-cell spacing, which in turn can degrade the retention performance of continuous charge-trapping layers. Therefore, a scalable technique is needed to allow the formation of discontinuous charge-trapping layers, so that each memory cell can be equipped with a separate charge-trapping layer. Summary of the Invention

[0004] The object of this invention is to provide a method for forming a memory structure suitable for 3D NAND flash memory, thereby allowing for the reliable formation of discontinuous / segmented charge trapping layers under radical z-pitch reduction.

[0005] Therefore, according to one aspect of the present invention, a method for forming a memory structure for 3D NAND flash memory is provided, the method comprising: A layer stack is formed over a substrate, the layer stack comprising an alternating sequence of gate layers and gate spacer layers; A recessed region is formed in the sidewalls surrounding the memory hole by etching back the gate layer laterally relative to the gate spacer layer from the memory hole in the layer stack. Discrete barrier oxide layers are formed in each recessed region, wherein the thickness of each barrier oxide layer in the lateral direction is less than the depth of each recessed region in the lateral direction. A continuous liner is conformally deposited on the exposed surface in the memory hole, wherein the liner covers the barrier oxide layer in each recessed area; A continuous sacrificial layer is deposited on the liner; The sacrificial layer is etched back, which exposes the liner outside the depression area, while discrete portions of the sacrificial layer remain in the depression area; While using discrete sacrificial layer portions as etching masks, the exposed portions of the substrate are removed, so that the discrete portions of the substrate covered by the discrete sacrificial layer portions remain in the recessed areas. Remove discrete portions of the sacrificial layer in the depression region; Discrete charge trapping layers are formed in each recessed region, wherein each charge trapping layer is deposited on the discrete liner portion while using the discrete liner portion retained in each recessed region as a seed layer by a (first) region-selective deposition process. After forming the charge trapping layer, a tunneling oxide layer is deposited in the memory aperture; and Deposit channel layers on the tunnel oxide layer.

[0006] Therefore, the method according to this aspect enables the formation of a memory structure comprising vertically separated lateral memory stacks, each lateral memory stack containing a corresponding discrete barrier oxide layer and a corresponding discrete charge trapping layer for each gate layer (or similarly for each memory cell).

[0007] Instead of first depositing a continuous charge-trapping layer and then "cutting" it into multiple discrete portions by etching, this method uses a region-selective deposition (ASD) process to "directly" deposit discrete charge-trapping layers. In this process, the (discrete) substrate portions within the recessed regions are used as seed (deposition-promoting) regions ("growth regions") for the charge-trapping material in the charge-trapping layer. Therefore, depositing charge-trapping material in the vertical regions between gate layers (i.e., the end faces of the gate spacer layers facing the memory holes) can be avoided, thus eliminating the need to cut continuous charge-trapping material layers by etching. By avoiding the need to cut the charge-trapping material by etching, the lateral thickness of the charge-trapping layer (i.e., the thickness dimension viewed in the lateral direction) can be precisely controlled by maintaining selective deposition growth conditions until the target thickness is reached.

[0008] A common material choice for gate spacer layers is oxide (typically silicon oxide). Therefore, it is predictable that performing ASD (Aspect-Oriented Deposition) of the charge-trapping material on the barrier oxide layer in the recessed region without significant simultaneous deposition on the gate spacer layer is challenging. However, by conformally depositing a continuous substrate followed by depositing and etching back a sacrificial layer, discrete substrate portions configured as ASD seed layers for charge-trapping material can be reliably formed within the recessed region. This allows for significantly improved region selectivity in charge-trapping material deposition. In other words, discrete substrate portions can be confined to the recessed region and formed from materials selected to facilitate ASD formation of the charge-trapping material.

[0009] In some embodiments, discrete barrier oxide layers are deposited on the etched-back gate layer in each recessed region by a (second) region-selective deposition process.

[0010] Therefore, the barrier oxide material of the barrier oxide layer can be deposited via ASD, just like a charge-trapping material. During the ASD of the barrier oxide material, the gate layer can define a (seed) region that promotes deposition, which helps the barrier oxide material to be preferentially deposited in the recessed region.

[0011] In some embodiments, discrete barrier oxide layers are formed by oxidizing a portion of the etched-back gate layer in each recess region, such that the oxidized portion forms the discrete barrier oxide layer on the non-oxidized portion of the etched-back gate layer.

[0012] This facilitates the formation of discrete barrier oxide layers within the recessed region in a region-selective manner. Specifically, discrete barrier oxide layers can also be formed where the materials of the gate layer and the gate spacer layer provide limited contrast for ASD. This approach can be used in situations where the gate layer is formed from a material that can be oxidized to a suitable type of oxide for use as a barrier oxide (such as silicon oxide). The gate layer can be formed from silicon-containing materials (e.g., silicon nitride, amorphous silicon (a-Si), or polycrystalline silicon).

[0013] In some embodiments, the portion of the etched-back gate layer is oxidized by a thermal oxidation process.

[0014] Therefore, a simple, reliable, and cost-effective process can be used to form the barrier oxide layer, which is also relatively gentle on non-target layers (such as gate spacer layers). Thermal oxidation processes can also facilitate reliable oxidation in high aspect ratio structures.

[0015] In some embodiments, the portion of the etched-back gate layer is oxidized by a plasma oxidation process.

[0016] In some embodiments, the liner comprises a metal oxide or a metal nitride. Such liner / seed layer materials (e.g., alumina, hafnium oxide, titanium oxide, or titanium nitride) facilitate process control because they can define surfaces that efficiently promote deposition of the charge-trapping material's ASD, particularly relative to non-metallic oxide or non-metallic nitride (typically silicon oxide) gate spacer layers. Furthermore, the metal oxide or metal nitride can be reliably deposited as a continuous and conformal layer, for example, using atomic layer deposition (ALD).

[0017] In some embodiments, the sacrificial layer is deposited to completely fill the remaining space in each recessed region. This can improve process control by providing additional over-etch tolerance during the etch-back of the sacrificial layer. Consequently, this makes it easier to ensure that discrete portions of the sacrificial layer remain to cover the liner in the recessed region after the etch-back is complete.

[0018] In some embodiments, the charge trapping layer is a silicon-containing layer, such as a silicon nitride layer. Silicon-containing layers are suitable for charge trapping layers. Specifically, silicon nitride is an efficient and reasonable implementation of charge-trapping memory cells. Furthermore, silicon nitride is suitable for ASD on conformal metal oxides or metal nitrides without causing any significant co-deposition on silicon oxide.

[0019] In some embodiments, the gate layer is a silicon-containing layer, such as a silicon nitride layer, an amorphous silicon layer, or a polycrystalline silicon layer. Such layers allow the final functional gate to be formed by replacing the metal gate (RMG) process. Polycrystalline silicon gate layers (e.g., when heavily doped) can also be used as functional gates in the final device.

[0020] In some embodiments, the gate layer is a sacrificial gate layer, and the method further includes replacing the sacrificial gate layer with a replacement metal gate layer after forming the charge trapping layer. Therefore, the sacrificial gate layer can be replaced with a functional metal gate layer via an RMG process. The sacrificial gate layer can be removed by etching back the sacrificial gate layer from a second via (e.g., a "contact trench") that is different from the memory via in the layer stack, and subsequently forming an RMG layer replacing the sacrificial gate layer. The RMG layer can be conveniently formed after depositing a tunneling oxide layer and a channel layer. Attached Figure Description

[0021] The above and additional objects, embodiments, features, and effects of the invention will be better understood through the following illustrative and non-limiting detailed description, with reference to the accompanying drawings. Unless otherwise stated, the same reference numerals will be used for the same elements in the drawings.

[0022] Figure 1a -b schematically illustrates a schematic cross-sectional view and a top view of the initial structure for forming a memory structure according to an embodiment.

[0023] Figure 2 The structure after the formation of the depression region is shown.

[0024] Figure 3 The structure after forming a barrier oxide layer in the recessed region is shown.

[0025] Figure 4 The structure after deposition of a continuous conformal liner is shown.

[0026] Figure 5The structure after depositing a sacrificial layer on the liner is shown.

[0027] Figure 6 The structure after the etched-back sacrificial layer is shown.

[0028] Figure 7 The structure after the etched back liner is shown.

[0029] Figure 8 The structure after removing a portion of the sacrificial layer from the recessed region is shown.

[0030] Figure 9 The structure after growing a charge trapping layer in the recessed region is shown.

[0031] Figure 10 The structure after the formation of the tunnel barrier layer and the channel layer is shown.

[0032] Figure 11 The structure after replacing the metal gate process is shown.

[0033] Figure 12-13 An alternative method for forming a barrier oxide layer in the recessed region is shown. Detailed Implementation

[0034] Embodiments of a method for forming a memory structure for 3D NAND flash memory, such as 3D gate-all-around NAND (3D GAANAND), will now be described with reference to the accompanying drawings. The drawings are schematic only, and the relative dimensions of some structures and layers may be exaggerated and not drawn to scale. Instead, the dimensions may be adjusted to make the illustration clear and easy to understand. When present in the drawings, the indicated axes X, Y, and Z consistently refer to a first horizontal or lateral, a second horizontal or lateral, and a vertical direction, respectively. As used herein, the terms “horizontal” and “lateral” refer to directions parallel to the supporting substrate (main surface) of the memory structure. Lateral / horizontal direction can also be understood as a direction parallel to the in-plane direction of the gate layer and the gate spacer layer. The term “vertical” refers to a direction parallel to the normal direction of the substrate (main surface), i.e., lateral to the substrate. The term “radial” direction is also mentioned herein. This term should be understood relative to a given memory aperture (e.g., Figure 1a The radial direction of the memory hole 4) is parallel to the horizontal XY plane. Therefore, the terms "radially inward" and "radially outward" refer to the radially inward and outward directions relative to a given memory hole, respectively. Related terms (such as "radially inside" and "radially outside") may be used accordingly to indicate the relative radial position or distance of a feature or element relative to a given memory hole.

[0035] Figure 1a-b schematically illustrates a cross-sectional view and a top view of structure 1 in the initial stage of the method, respectively. Structure 1 includes a layer stack 10, which represents a precursor or initial structure for a memory structure, and will undergo the processing steps of the method disclosed below.

[0036] A layer stack 10 is formed over the substrate 2 and includes an alternating sequence of gate layer 14 and gate spacer layer 12. The gate spacer layer 12 and the gate layer 14 are stacked on top of each other in the vertical direction Z.

[0037] Substrate 2 can be a conventional substrate suitable for semiconductor processing and for supporting memory structures of 3D NAND flash memory. Substrate 2 can be, for example, a Si substrate, a Ge substrate, or a SiGe substrate. Other examples include silicon-on-insulator (SOI) substrates, GeOI substrates, or SiGeOI substrates.

[0038] Gate layer 14 may be a silicon-containing layer (such as a SiN layer, an amorphous silicon layer, or a polycrystalline silicon layer) to form a sacrificial gate layer 14 intended to be replaced by an RMG stack in subsequent process steps. Gate layer 14 may also be a functional gate layer, such as a highly doped polycrystalline silicon layer.

[0039] The gate spacer layer 12 may be an oxide-containing layer, typically a silicon oxide (e.g., SiO2) layer or another suitable (e.g., low-k) interlayer dielectric. The gate spacer layer 12 is arranged in the layer stack 10 to provide vertical separation between memory cells / word lines of the memory device to be formed.

[0040] The layer stack 10 can be formed by alternately depositing layers of gate material (e.g., nitride) and gate spacer material (e.g., oxide) using deposition processes known in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0041] The number of gate spacer layers 12 and gate layers 14 can be determined based on the expected number of stacked memory cells in the memory device. Note that the number of layers 12 and 14 in the illustrated layer stack 10 is merely a non-limiting example, and the methods disclosed herein are compatible with virtually any number (e.g., 64, 128, 256 or more) of memory cell stacks currently used or anticipated in the industry.

[0042] As an example, the gate spacer layer 12 and the gate layer 14 can each be formed to have a corresponding layer thickness in the range of 5-25 nm. The z-pitch of the layer stack 10 (i.e., the combined thickness of a gate spacer layer and a gate layer 14) can be in the range of about 45 nm to 15 nm or less.

[0043] Although omitted for illustrative purposes, the layer stack 10 may optionally be capped by a capping layer (e.g., a semiconductor layer (e.g., silicon) deposited on the topmost gate spacer layer 12). The capping layer may be used to protect the topmost gate spacer layer 12 during subsequent processing.

[0044] After layers 12 and 14 (and optional capping layer) of the layer stack 10 are deposited, memory holes 4 can be patterned in the layer stack 10 using photolithography and etching processes. Although Figure 1a -b shows a portion of the layer stack 10 surrounding a single memory hole 4, but it should be noted that the corresponding memory hole 4 can be patterned at each location of the corresponding vertical string of memory cells. As shown, the memory hole 4 can be formed to extend through each gate spacer layer 12 and gate layer 14 of the layer stack 10. Figure 1b As further shown in the top view, the memory hole 4 can be formed with a circular cross-sectional shape, such that the memory hole 4 can be formed with a generally cylindrical shape (occupying an area). However, the memory hole 4 can also be formed with other cross-sectional shapes, such as elliptical or polygonal shapes.

[0045] Although Figure 1a Not shown, but as is known in the art, layer stack 10 may also include sub-stacks of select layers and source layers below layers 12 and 14, for forming the select plate and source plate of the memory device, respectively. Thus, the select layer and source layer can form the bottom sub-stack of layer stack 10. The select layer and source layer can be formed using conventional techniques and materials (e.g., doped semiconductor layers, such as polysilicon) and are separated by layers of interlayer dielectric.

[0046] exist Figure 2 In this process, a recessed region 18 is formed in the sidewalls of the layer stack 10 surrounding the memory hole 4 by etching back the gate layer 14 relative to the gate spacer layer 12 in the lateral direction (i.e., along the X-axis, in the radially outward direction) from the memory hole 4. Thus, each recessed region / groove 18 is formed between a pair of gate spacer layers 12. Due to its circumferential extension around the sidewalls of the memory hole 4, the recessed region 18 can extend circumferentially around the memory hole 4. In the example of a circular memory hole 4, the recessed region 18 can be annular.

[0047] The gate layer 14 can be etched back using an etching process suitable for selectively etching the gate layer 14 relative to the gate spacer layer 12. That is, the etching process can be adapted to selectively etch (i.e., remove) the material of the gate layer 14 (e.g., silicon nitride, amorphous silicon, or polycrystalline silicon) relative to the material of the gate layer 14 (e.g., an oxide material), such that the gate layer 14 can be etched back laterally without causing any substantial etch back of the gate spacer layer 12. The etching process can be adapted to be applied to the sidewalls of the layer stack 10 through the memory via 4. The etching process can be an isotropic etching process. However, any suitable selective etching process (wet or dry) that provides sufficient lateral etch content for the gate layer 14 can be used.

[0048] The recessed region 18 can be formed with a lateral / radial depth (along the X-axis) that satisfies or exceeds the expected lateral thickness of the lateral memory stack, such as the combined lateral thickness of the barrier oxide and charge trapping layer at each gate level. Figure 9 It can be understood that the lateral depth of the recessed region 18 is determined by the lateral depth (radial extension) of the lateral etching back. For example, the lateral depth of the recessed region 18 can be in the range of 6-20 nm. The depth of the recessed region 18 can be controlled by controlling the time of the lateral etching back.

[0049] exist Figure 3 In this configuration, discrete barrier oxide layers 20 are formed in each recessed region 18. As shown, the barrier oxide layers 20 are formed to have an X-direction thickness less than the lateral depth of the recessed region 18. Therefore, each (discrete) barrier oxide layer 20 only partially fills the lateral depth of the corresponding recessed region 18. Consequently, after the formation of the barrier oxide layers 20, the sidewalls of the memory aperture 4 define recessed / contoured sidewalls. The discrete barrier oxide layers 20 in each recessed region 18 may, for example, be formed to have a lateral thickness in the range of 4-15 nm. The barrier oxide 24 may comprise silicon oxide (SiO2) or some other oxide material suitable for use as a barrier oxide.

[0050] Discrete barrier oxide layers 20 can be formed using various methods. According to one method, discrete barrier oxide layers 20 can be deposited on etched-back gate layers 14 in each recessed region 18 using an ASD process. Therefore, barrier oxide material for forming the barrier oxide layers 20 can be selectively deposited in the recessed regions 18. This deposition can continue until discrete portions of barrier oxide material of a target thickness are deposited in each recessed region 18, each portion defining a corresponding discrete barrier oxide layer 20. During ASD, the etched-back end face of the gate layer 14 facing the memory via 4 can define a (seed) region that promotes the deposition of the barrier oxide material, while the gate spacer layer 12 defines a (non-growth) region that inhibits deposition.

[0051] The barrier oxide material can be deposited using any suitable deposition process (e.g., ALD or CVD process) that facilitates the deposition of barrier oxide materials (e.g., SiO2) in the recessed region 18 using ASD.

[0052] To facilitate ASD of the barrier oxide layer 20, the layer stack 10 may undergo a processing step prior to depositing the barrier oxide material to define a growth region within the recessed region 18 (e.g., on the end face of the etched-back gate layer 14) and a non-growth region outside the recessed region 18. The processing step may be adapted to functionalize the surface portions / end faces of the etched-back gate layer 14 in the recessed region 18 relative to the ASD of the barrier oxide material. Alternatively, the processing step may be adapted to passivate the exposed surface portions of the gate spacer layer 12 relative to the ASD of the barrier oxide material. Thereafter, the barrier oxide material may be selectively deposited in the growth regions within the recessed region 18. For example, functionalization may include depositing a deposition-facilitating layer on the end face of the etched-back gate layer 14 in the recessed region 18. Alternatively, the layer stack 10 may undergo a processing step adapted to passivate the exposed surface portions of the gate spacer layer 12 relative to the ASD of the barrier oxide material 20. For example, some deposition processes favor deposition on hydrogen-terminated surfaces (e.g., deposition processes preferentially deposit material on hydrogen-terminated surfaces). Therefore, the processing technology can be adapted to increase the presence of hydrogen-terminated bonds on gate layer 14 (thus promoting deposition thereon) and / or decrease the presence of hydrogen-terminated bonds on gate spacer layer 12 (thus inhibiting deposition thereon). As another example, siloxanes, aminosilanes, trichlorosilanes, small molecule inhibitors (SMIs, such as dimethylaminotrimethylsilane (DMA-TMS), trimethyltrimethoxysilane, trimethoxytrichlorosilane, etc.) or self-assembled monolayers (SAMs, such as alkylsilanes) can be used to selectively passivate the silicon oxide (SiO2) gate spacer layer 12 relative to the silicon nitride / amorphous silicon / polycrystalline silicon gate layer 14 to allow blocking of oxide material on the end faces of gate layer 14.

[0053] According to another approach, the discrete barrier oxide layer 20 can instead be formed through a portion of the etched-back gate layer 14 in the oxide recess region 18. This is in Figure 12-13 The diagram schematically illustrates that each barrier oxide layer 20 can be formed by oxidizing a portion 14b of the etched-back gate layer 14 in the corresponding recessed region 18, wherein the oxidized portion 14b forms discrete barrier oxide layers 20 on the remaining unoxidized portion 14a of the gate layer 14. The etched-back gate layer 14 can be exposed to an oxidizing environment / oxidant through the memory via 4. When the gate layer 14 is a silicon-containing layer (such as a silicon nitride layer, amorphous silicon layer, or polycrystalline silicon layer), the barrier oxide layer 20 can be formed as a silicon oxide (SiO2) layer. The oxidation process can be, for example, a thermal oxidation process. The oxide can be a low-temperature oxide (LTO) or a high-temperature oxide (HTO). The oxidation process can also be a plasma oxidation process. The above-described oxidation-based approach is useful for applications involving challenging material combinations that achieve sufficiently selective deposition of barrier oxide materials on the gate layer 14, such as when the gate spacer layer 12 contains SiO2.

[0054] Figure 4 Structure 1 is depicted after the formation of the barrier oxide layer 20 (e.g., according to any of the methods discussed above) and after the further conformal deposition of a continuous liner 21 on the exposed surface in the memory hole 4. Thus, the liner 21 covers (e.g., coats or liners) the exposed surface portion of the layer stack 10 facing the memory hole 4. Due to the conformal nature of the deposition, the liner 21 covers the inner surface of the recessed regions 18, including the barrier oxide layer 20 in each recessed region 18. Figure 4 As shown, the inner surface of the recessed region 18 also includes surface portions of the gate spacer layer 12 above and below each recessed region 18. The liner 21 can be deposited by ALD or some other suitable conformal deposition process.

[0055] Substrate 21 will serve as a seed layer during the subsequent ASD step for forming the charge-trapping layer 24 in the recessed region 18. Therefore, substrate 21 can be formed of any material that can be conformally deposited and serve as a seed layer for the ASD charge-trapping material. For example, substrate 21 can comprise or be formed from metal oxides or metal nitrides, such as AlO. x HfO x TiN, TiO2, or other high-k oxides or nitrides.

[0056] Since the recessed region 18 will also accommodate some of the minimum target thickness of the charge trapping layer 24, the liner 21 is deposited to only partially fill the recessed region 18, as shown. Therefore, the liner 21 is formed to have a thickness less than the remaining lateral depth (along the X-axis) of the recessed region 18, which is partially filled with the barrier oxide layer 10. Furthermore, the thickness of the liner 21 is such that pinch-off of the recessed region 18 is avoided. Here, thickness refers to the local thickness of the liner 21, i.e., the thickness of the liner 21 measured in a direction perpendicular to its underside / support surface at the location where the local thickness is measured. To avoid pinch-off, the thickness of the liner 18 should be less than half the thickness (along the Z-axis) of each gate layer 14, such as at most one-third or one-quarter of the thickness of each gate layer 14, or less. For example, the liner 18 may be formed to have a thickness of about 2 nm or less (such as about 1 nm). This range of thicknesses is compatible with the aforementioned thickness ranges of the gate layer 14 and the barrier oxide layer 20, as well as the depth range of the recessed region 18.

[0057] exist Figure 5 In this process, a continuous sacrificial layer 22 is deposited on the liner 21, including portions of the liner 21 within the remaining interior space of the recessed region 18. It is noteworthy that, as shown, the sacrificial layer 22 can be deposited to completely fill the remaining interior space (within) of each recessed region 18. The benefits of this can be seen from… Figure 6-7 Understanding in Chinese: Figure 6 In this process, the sacrificial layer 22 has been etched back, exposing the liner 21 outside the recessed region 18, while discrete portions 22a of the sacrificial layer 22 remain within the recessed region 18. Figure 7 In this process, while using discrete sacrificial layer portions 22a (i.e., the remaining discrete portions of the etched sacrificial layer 22) as an etching mask, the exposed portions of the substrate 21 (i.e., the portions of the substrate 21 not covered by discrete sacrificial layer portions 22a) are removed, leaving the discrete portions 21a of the substrate 21 covered by discrete sacrificial layer portions 22a within the recessed region 18. Therefore, by ensuring that the sacrificial layer 22 completely fills the remaining internal space of the recessed region 18, it is ensured that when portions of the substrate 21 outside the recessed region 18 are exposed, the discrete sacrificial layer portions 22a remain to cover the substrate 21 within each recessed region 18.

[0058] While completely filling the remaining internal space of the recessed region 18 with the sacrificial layer 22 can contribute to process reliability, it is envisioned that a sufficient criterion is that the sacrificial layer 22 fills the remaining internal space of the recessed region 18 to such an extent that, after etching back the sacrificial layer 22, discrete sacrificial layer portions 22a are retained in the recessed region 18 to a degree sufficient to serve as an etch mask for the substrate 21. Therefore, in any case, by forming discrete sacrificial layer portions 21a in the recessed region 18, discrete substrate portions 21a can be retained after subsequent etching back of the substrate 21.

[0059] exist Figure 7 In the diagram, the etchback of the sacrificial layer 22 is schematically depicted as restoring the sidewalls of the memory via 4 to a substantially straight profile. However, this is not necessary for the functionality of the process. Instead, it is sufficient that a portion of the liner 21 in each recess 18 (particularly the portion extending along the end face of the gate layer 14 associated with the recess 18) is covered by discrete sacrificial layer portions 22a, such that they can be masked and retained during subsequent etchback of the liner 21. Therefore, slightly lateral over-etching of the sacrificial layer portions 22a into the recess 18 does not necessarily reduce process yield.

[0060] Since the sacrificial layer 22 is to be used as an etch mask during the etch-back of the substrate 21, the sacrificial layer 22 can generally be formed of any sacrificial material that can be deposited to reliably fill the remaining internal space of the recessed region 18 and can provide sufficient etch contrast relative to the substrate 21 so that it can be used as an etch mask for the substrate 21 and can eventually be removed from the gate spacer layer 12 without causing collateral damage to the structure 1. Examples of sacrificial materials include semiconductors, metals, polymers, or insulators. For example, to name just a few non-limiting examples, the sacrificial material can be Si, SiN, SiCN, TiN (if not used for the substrate 21), W (if the substrate is TiN), or Mo.

[0061] The sacrificial layer 22 can be deposited using both conformal and non-conformal deposition processes, as long as the deposition process allows for the deposition of sacrificial material to fill the recessed region 18. Non-limiting examples include CVD, ALD, and spin-coating deposition.

[0062] The etching back of the sacrificial layer 22 can be achieved by any suitable isotropic etching process (wet or dry). The substrate 21 can be used for etching stop detection; however, timed etching back is also possible.

[0063] The etchback of the sacrificial layer 21 can be achieved by any suitable isotropic etching process (wet or dry). Here, the gate spacer layer 12 can be used for etch stop detection, however, timed etchback is also possible. Since the substrate 21 is typically deposited to define a relatively thin layer (e.g., 2 nm or less), it is envisioned that a relatively short etch step would be sufficient to remove the exposed portion of the substrate 21.

[0064] exist Figure 8 In this process, discrete sacrificial layer portions 22a have been removed from recessed region 18, thereby exposing discrete substrate portions 21a in recessed region 18. Sacrificial layer portions 22a can be removed using any suitable isotropic etching process (wet or dry), such as with reference. Figure 6 The same etching process is discussed for the etchback of sacrificial layer 22.

[0065] exist Figure 9 In each recessed region 18, discrete charge-trapping layers 24 are formed. Each charge-trapping layer 24 is deposited on a corresponding discrete substrate portion 21a. The charge-trapping layers 24 are formed using an ASD process that uses the discrete substrate portion 21a as a seed layer. Therefore, charge-trapping material can be selectively deposited in the recessed regions 18, with the discrete substrate portion 21a serving as a seed (nucleation site).

[0066] The deposition of charge-trapping material can continue until a discrete portion of charge-trapping material of the target thickness is deposited in each recess region 18, each portion defining a corresponding discrete charge-trapping layer 24. During ASD, the gate spacer layer 12 defines a (non-growth) region that inhibits charge-trapping material deposition, while the liner portion 21a defines a (seed) region that promotes charge-trapping material deposition.

[0067] Charge-trapping materials can include silicon nitride (SiN, i.e., Si3N4). Silicon nitride is an efficient and reasonable way to implement charge-trapping memory cells. For example, silicon nitride can be deposited onto any of the aforementioned examples of substrate materials (metal oxides or metal nitrides, such as Al2O3) using ASD. x HfO x The charge-trapping material can be or contains silicon, meaning that the charge-trapping layer 24 can be a silicon-containing layer. For example, the charge-trapping material can be silicon, meaning that the charge-trapping layer 24 can contain or contain a silicon layer. Composite layer structures of the charge-trapping layer 24 are also possible. For example, the charge-trapping layer 24 can include first and second sequentially deposited layers (sublayers), wherein the first sublayer is silicon or a silicon-containing layer, and the second sublayer is a metal layer (such as TiN or Ru). This method is also contemplated to be compatible with other choices of charge-trapping materials, as long as they can be deposited on the liner portion 21a in the recessed region 18 in a region-selective manner. The charge-trapping material can be deposited using any suitable deposition process (conformal or non-conformal), such as ALD or CVD processes.

[0068] To facilitate ASD of the charge-trapping material, the layer stack 10 can be processed prior to the deposition of the charge-trapping material to define a growth region within the recessed region 18 (e.g., on the liner portion 21a) and a non-growth region outside the recessed region 18. The processing can be adapted to (further) functionalize the liner portion 21a relative to the ASD of the charge-trapping material. Alternatively, the processing can be adapted to passivate the exposed surface portion of the gate spacer layer 12 relative to the ASD of the charge-trapping material. Thereafter, the charge-trapping material can be selectively deposited on the growth region within the recessed region 18. The examples of functionalization and passivation discussed above regarding ASD of barrier oxide materials are correspondingly applicable to ASD of charge-trapping materials. As a specific, non-limiting example, the SiO2 surface can be selectively passivated by DMA-TMS suppression relative to TiO2 or TiN.

[0069] The discrete charge-trapping layers 24 can each be formed to have a lateral thickness (along the X-axis) in the range of 4-8 nm. More generally, the discrete charge-trapping layers 24 can be formed to completely fill the remaining internal space of the recessed region 18. The end face of the discrete charge-trapping layer 24 facing the memory hole 4 can therefore become substantially flush with the end face of the gate spacer layer 12 facing the memory hole 4. In other words, the sidewalls of the memory hole 4 can (e.g., again) be restored to a substantially straight profile, or have at least a reduced morphology compared to before the formation of the charge-trapping layers 24.

[0070] Therefore, in Figure 9 In the process stages shown, each recessed region 18 has been equipped with (e.g., "refilled" and / or "regrown") discrete barrier layers 20, liner portions 21a, and charge trapping layers 24. These layers define lateral memory stacks for the respective gate layers 14.

[0071] exist Figure 10 In this structure, a tunneling oxide layer 30 and a subsequent channel layer 32 have already been formed along the sidewalls of the memory aperture 4. Therefore, the tunneling oxide layer 30 is formed or contacts the discrete charge trapping layer 24 of the lateral memory stack (more specifically, along the corresponding inner end face of the charge trapping layer 24 facing the memory aperture 4). The tunneling oxide layer 30 and the channel layer 32 can each be conformally deposited, for example, using a corresponding ALD process. After the tunneling oxide layer 30 is deposited, it can be subjected to top-down (opposite to the Z-axis direction) anisotropic etching to remove portions of the tunneling oxide layer 30 deposited on the horizontally oriented surface of structure 1.

[0072] The tunneling oxide layer 30 can be formed of any material conventionally used in the industry for tunneling oxide layers; a non-limiting example is SiON. Similarly, the channel layer 32 can be formed of any suitable channel material conventionally used in the industry for channel layers, typically a semiconductor material (e.g., Si, SiGe, or Ge). Although Figure 10 Although not shown, the channel layer 32 may extend beyond the portion shown in structure 1 to facilitate connection with peripheral semiconductor devices and circuit systems such as selection transistors.

[0073] Subsequently, the memory via 4 can be filled with a plug or filler material 34, such as an interlayer dielectric (e.g., SiO2) or other low-k dielectric. If the gate layer 14 is a sacrificial gate layer, the method can further continue as shown, replacing the sacrificial gate layer 14 with a replacement metal gate layer or stack 36. The sacrificial gate layer 14 can be removed by etching back from a second via (e.g., a “contact trench”, not shown) in the layer stack 10 (e.g., if the memory via 4 is represented as a front hole or opening, the second via may be referred to as a back hole or opening). The sacrificial gate layer 14 can then be replaced by filling the laterally / radially extending gate cavity formed at the level of the sacrificial gate layer 14 with an RMG layer or stack. The gate cavity can be etched using an isotropic etching process. For example, the gate cavity can be etched using the same type of etching process as that used to form the recessed region 18.

[0074] The RMG process may include depositing one or more conductive layers, such as metals (such as one or more of TiN and W). The deposition of the conductive layers may be performed after the deposition of a (conformal) high-k gate dielectric.

[0075] Therefore, in Figure 11 As shown in the process stage, memory structure 1 includes discrete barrier layers 20 and discrete charge trapping layers 24 for each gate level. These layers define a lateral memory stack between the respective gate layer / stack 36 and the (shared) tunnel barrier layer 30 and channel layer 32.

[0076] This process can be further carried out with conventional process steps in 3D NAND manufacturing, as known in the art. For example, structure 1 can be further processed to contact each gate layer 14 / 36 with peripheral semiconductor devices and circuit systems, such as select transistors and word line drivers. For example, the gate layers 14 / 36 can be patterned into a stepped structure prior to contact formation.

[0077] Those skilled in the art will recognize that the present invention is by no means limited to the embodiments described above. Rather, many modifications and variations are possible within the scope of the appended claims.

Claims

1. A method for forming a memory structure (1) of 3D NAND flash memory, the method comprising: A layer stack (10) is formed over a substrate (2), the layer stack (10) comprising an alternating sequence of gate layers (14) and gate spacer layers (12); By etching back the gate layer (14) in the lateral direction relative to the gate spacer layer (12) from the memory hole (4) in the stack of layers (10), a recessed region (18) is formed in the sidewall surrounding the memory hole (4). Discrete barrier oxide layers (20) are formed in each recessed region (18), wherein the thickness of each barrier oxide layer (20) in the lateral direction is less than the depth of each recessed region (18) in the lateral direction. A continuous liner (21) is conformally deposited on the exposed surface in the memory hole (4), wherein the liner (21) covers the barrier oxide layer (20) in each recess (18). A continuous sacrificial layer (22) is deposited on the liner (21); The sacrificial layer (22) is etched back, so that the liner (21) outside the recessed area (18) is exposed, and discrete portions (22a) of the sacrificial layer (22) remain in the recessed area (18); While using discrete sacrificial layer portions (22a) as etching masks, the exposed portions of the substrate (21) are removed, such that the discrete portions (21a) of the substrate (21) covered by the discrete sacrificial layer portions (22a) remain in the recessed area (18). Remove discrete sacrificial layer portions (22a) from the recessed region (18); Discrete charge trapping layers (24) are formed in each recessed region (18), wherein each charge trapping layer (24) is deposited on the discrete liner portion (21a) by a first region selective deposition process while using the discrete liner portion (21a) retained in each recessed region (18) as a seed layer. After forming the charge trapping layer (24), a tunneling oxide layer (30) is deposited in the memory hole (4); and A channel layer (32) is deposited on the tunneling oxide layer (30).

2. The method according to claim 1, characterized in that, The discrete barrier oxide layer (20) is deposited on the etched gate layer (14) in each recessed region (18) by a second region selective deposition process.

3. The method according to claim 1, characterized in that, The discrete barrier oxide layer (20) is formed by oxidizing a portion (14b) of the etched-back gate layer (14) in each recessed region (18), such that the oxidized portion (14b) forms the discrete barrier oxide layer (20) on the non-oxidized portion (14a) of the etched-back gate layer (14).

4. The method according to claim 3, characterized in that, The portion (14b) of the etched gate layer (14) is oxidized by a thermal oxidation process or a plasma oxidation process.

5. The method according to any one of the preceding claims, characterized in that, The liner (21) comprises a metal oxide or a metal nitride.

6. The method according to any one of the preceding claims, characterized in that, The sacrificial layer (22) is deposited to completely fill the remaining space in each recessed area (18).

7. The method according to any one of the preceding claims, characterized in that, The charge trapping layer (21) is a silicon-containing layer, such as a silicon nitride layer.

8. The method according to any one of the preceding claims, characterized in that, The discrete barrier oxide layer (20) in each recessed region (18) is formed to have a lateral thickness in the range of 4-12 nm.

9. The method according to any one of the preceding claims, characterized in that, The discrete charge trapping layer (24) is formed with a lateral thickness in the range of 4-8 nm.

10. The method according to any one of the preceding claims, characterized in that, The liner (21) is formed to have a thickness of 2 nm or less.

11. The method according to any one of the preceding claims, characterized in that, The gate spacer layer (12) and the gate layer (14) are formed to have corresponding layer thicknesses in the range of 5-25 nm.

12. The method according to claim 11, characterized in that, The combined thickness of a gate spacer layer (12) and a gate layer (14) is 45 nm or less.

13. The method according to any one of the preceding claims, characterized in that, The gate layer (14) is a sacrificial gate layer, and the method further includes replacing the sacrificial gate layer (14) with a replacement metal gate layer (36) after forming the charge trapping layer (24).

14. The method according to claim 13, characterized in that, The replacement metal gate layer (36) is formed after the deposition of the tunnel oxide layer (30) and the channel layer (32).

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