Method of manufacturing and device for reducing resistance of control gate to word line for nord flash memory cells

Abstract

The application discloses a manufacturing method for reducing resistance between a control gate of a NORD Flash memory cell and a word line, comprising the following steps: 1) applying a bottom anti-reflection layer on the memory cell and a peripheral logic area, and filling the interval pits between the memory cells with the anti-reflection layer to make the surface of the anti-reflection layer on the memory cell flat; 2) performing partial etching on the anti-reflection layer after N-type heavy doping implantation, photolithography and development, so that the memory cell top is exposed, and the anti-reflection layer is reserved at the pit of the memory cell for protection; 3) etching the oxide on the memory cell top by dry etching, and protecting the oxide at the sharp corner of the control gate by using the shadow effect of offset sputtering etching; 4) removing the residual anti-reflection layer by dry etching, and performing an N-type heavy doping implantation process; and 5) completely removing the oxide on the control gate and the word line top to form a complete silicide. The application can completely remove the oxide on the control gate and the word line top, form a complete Salicide, reduce the resistance between the control gate and the word line, and improve the read-write speed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory manufacturing technology, and in particular to a manufacturing method and device for reducing the resistance of the control gate and word line of a NORD Flash memory cell. Background Technology

[0002] NORD Flash memory, as a non-volatile memory device, is widely used in consumer electronics, embedded systems, and automotive electronics due to its high integration, excellent data retention capabilities, and stable read / write performance. The control gate and word lines, as the core conductive structures of a NORD Flash memory cell, directly determine the cell's driving capability, switching speed, and overall read / write performance, making them key parameters affecting device efficiency.

[0003] In traditional NORD Flash manufacturing processes, an FGSP oxide layer is formed at the top of the control gate to meet the structural design and process requirements of the memory cell. The presence of this oxide layer directly blocks the silicide formation path, preventing the formation of a low-resistivity silicide layer at the top of the control gate, resulting in a significantly high control gate resistance. High control gate resistance drastically increases the on-resistance of the memory cell, severely reducing the read / write speed of the Flash device and limiting performance improvements. If a wet etching process is introduced before silicide formation to remove the oxide at the top of the control gate, the etching solution will erode surrounding logic devices, leading to deterioration of their electrical performance. Simultaneously, the inherent lateral etching effect of wet etching will over-etch the control gate's sharp corner structure, damaging its morphology and reducing the breakdown voltage (BV) between the word line and the control gate, thereby deteriorating key reliability indicators such as the memory cell's withstand voltage, fatigue characteristics, and data retention capability.

[0004] On the other hand, in NORD Flash technology, a dedicated oxide layer (word line OX) needs to be placed at the top of the word line to prevent plasma damage to the polysilicon structure of the word line during the control gate CT / poly etching process. According to process requirements, this word line OX layer must be completely removed in subsequent processes. To avoid pitting defects on the polysilicon surface of the word line during etching, a relatively thick word line OX layer is usually required in the process. However, a thick oxide layer is prone to problems such as incomplete etching and excessive residue in subsequent removal processes. Residual word line OX also hinders silicide formation, resulting in persistently high word line resistance, further deteriorating the conductivity of the memory cells, and ultimately causing the overall Flash device's operating speed, power consumption, and stability to fail to meet application requirements.

[0005] In summary, existing NORD Flash processes present inherent contradictions in their approaches to reducing control gate resistance and word line resistance: wet etching damages logic devices and reduces memory cell reliability; retaining oxides prevents the formation of low-resistivity silicides, resulting in high control gate and word line resistances. Current technologies cannot simultaneously achieve effective removal of oxides at the top of the control gate and word line without affecting logic device performance or compromising memory cell reliability, making it difficult to simultaneously solve the technical challenges of excessively high control gate resistance and word line resistance. Summary of the Invention

[0006] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] The technical problem to be solved by the present invention is to provide a manufacturing method and device for reducing the resistance of the control gate and word line of a NORD Flash memory cell, without affecting the performance of the logic device, without compromising the reliability of the control gate tip, and without adding a mask, so as to completely remove the oxide at the top of the control gate and word line to form a complete Salicide, thereby reducing the resistance of the control gate and word line and improving the read and write speed.

[0008] To solve the above-mentioned technical problems, the present invention provides a manufacturing method for reducing the resistance between the control gate and word line of a NORD Flash memory cell, comprising: 1) Spin-coat the bottom anti-reflective layer BARC on the storage cell and the surrounding logic area Peri, and use the fluidity of the anti-reflective layer BARC to fill the gaps between the storage cells, so that the surface of the anti-reflective layer BARC at the top of the storage cell is flat. 2) After N-type heavy doping implantation photolithography PH and development, the anti-reflective layer BARC is partially etched to expose the top of the memory cell CELL, while the anti-reflective layer BARC is retained to protect the pit of the memory cell CELL. 3) Dry etching is used to etch the oxide at the top of the memory cell using Dry ET etching, and the shadowing effect of Offsp etching is used to protect the oxide at the sharp corner of the control gate. 4) Dry etching is used to remove the remaining anti-reflection layer BARC, followed by N-type heavy doping implantation. 5) The oxides at the top of the control gate and word line are completely removed to form a complete silicide (Salicide).

[0009] Optionally, the manufacturing method for reducing the control gate and word line resistance of the NORD Flash memory cell can be further improved, wherein the height of the Peri polysilicon peripheral logic region is lower than that of the memory cell CELL, and the etching of the oxide at the top of the memory cell CELL does not affect the Peri region of the peripheral logic region.

[0010] Optionally, the manufacturing method for reducing the resistance of the control gate and word line of the NORD Flash memory cell can be further improved, wherein the active region AA at the bottom of the memory cell CELL is protected by the anti-reflection layer BARC during etching.

[0011] Optionally, the manufacturing method for reducing the resistance of the NORD Flash memory cell control gate and word line can be further improved by preserving the oxide at the control gate tip during the oxide etching at the top of the memory cell.

[0012] Alternatively, the manufacturing method for reducing the control gate and word line resistance of the NORD Flash memory cell can be further improved by using an existing N-type heavily doped implantation mask without adding a new mask.

[0013] To solve the above technical problems, the present invention provides a NORD Flash memory, including a storage cell (CELL) and a peripheral logic area (Peri). The storage cell (CELL) includes a control gate and a word line. The oxide at the top of the control gate and the word line is completely removed to form a complete silicide (Salicide). An oxide protective layer is retained at the sharp corners of the control gate; The recessed areas between memory cells and the surrounding logic areas (Peri) are protected by an anti-reflective layer (BARC) during the etching process.

[0014] Optionally, the NORD Flash memory can be further improved so that the peripheral logic area Peri is not affected by the etching process at the top of the memory cell.

[0015] Based on the above technical solution, the working principle of the present invention is as follows; This invention fully utilizes the inherent structural height difference between the NORD Flash memory cell (CELL) and the surrounding logic region (Peri), combined with the excellent fluidity, gap-filling ability, and film flatness of the bottom anti-reflective layer (BARC). After spin coating, the anti-reflective layer (BARC) fully fills the pit structure between the memory cells, while maintaining the flatness of the top surface of the memory cell. After N-type heavy doping implantation photolithography and development, the top of the memory cell is exposed by partially etching the anti-reflective layer (BARC), while the memory cell pits, the active region (ACT) at the bottom of the memory cell, and the surrounding logic region remain covered and protected by the anti-reflective layer (BARC). Dry etching is then used to remove the oxide at the top of the memory cell, and the shadowing effect generated by offset sputtering (Offsp) etching prevents the oxide at the control gate sharp corner from being etched, thus completely preserving the control gate sharp corner morphology and protective layer. After completing the removal of the anti-reflective layer (BARC) and N-type heavy doping implantation, the oxide at the top of the control gate and word line is completely removed, allowing for the successful formation of a continuous and complete silicide layer, structurally achieving a significant reduction in the control gate and word line resistance.

[0016] Based on the above technical solution and working principle, the present invention can achieve at least the following technical effects; 1. Significantly reduced resistance and improved read / write speed: The FGSP oxide at the top of the control gate and the word line OX at the top of the word line are completely removed, with no oxide residues hindering the process. A complete and dense Salicide layer can be formed at the top of the control gate and word line, which greatly reduces the resistance of the control gate and word line, effectively improves the charging and discharging rate of the memory cell and the signal transmission speed, and significantly improves the Flash read / write performance.

[0017] 2. Device reliability is unaffected: The shadowing effect of Offsp etching precisely protects the oxide at the control gate tip, preventing the control gate tip from being etched or damaged. This ensures that key reliability indicators such as word line-control gate breakdown voltage, fatigue characteristics, and data retention capability are maintained at the design level, solving the inherent defects of traditional wet etching that damages the control gate tip and degrades reliability.

[0018] 3. No damage to logic device performance: The polysilicon structure height of the peripheral logic area is lower than that of the Flash Cell. During the oxide etching process at the top of the Cell, the Peri region is always covered and protected by the BARC. The etching process will not cause erosion, morphological damage or electrical performance degradation to the logic device, thus achieving process compatibility between the memory area and the logic area.

[0019] 4. Low process cost and easy mass production: This invention relies entirely on existing N-type heavily doped implantation masks to achieve patterning, without the need for additional masks. It only adds BARC spin coating, BARC partial etching, CELL top oxide etching, and BARC removal steps to the standard N-type heavily doped implantation process. The process modification is small, the process compatibility is strong, and the mass production cost is controllable, making it suitable for large-scale industrial applications. Attached Figure Description

[0020] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0021] Figure 1 Schematic diagram of the structure after spin coating BARC according to the present invention; Figure 2 A schematic diagram of the structure of the present invention after N-type heavy doping implantation photolithography and development; Figure 3 A schematic diagram of the BARC portion of this invention after etching; Figure 4 Schematic diagram of the oxide etching structure at the top of the cell in this invention; Figure 5 A schematic diagram of the final control gate and word line forming a complete Salicide structure in this invention; Figure 6 Schematic diagram of the protected position of this invention Figure 1 .

[0022] Figure 7 Schematic diagram of the protected position of this invention Figure 2 . Attached Figure

[0023] 1 and 2 indicate locations where BARC protection is unaffected; 3 indicates the position of the control gate tip when the top oxide ET of the CELL is reached. Detailed Implementation

[0024] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0025] First embodiment; This invention adds BARC spin-coating, BARC partial etching, CELL top oxide etching, and BARC removal steps to the traditional N-type heavy doping implantation process, including: Flash memory cells (CELL) and peripheral logic regions (Peri) are formed on a semiconductor substrate, and a bottom anti-reflective layer (BARC) is spin-coated.

[0026] The fluidity of the BARC is utilized to fully fill the recessed structure between the cells and to keep the BARC surface at the top of the cell flat.

[0027] At this time, the active area ACT at the bottom of the CELL, the CELL intersticed pit area, and the surrounding logic area are all covered and protected by BARC.

[0028] Perform N-type heavy doping implantation lithography (N-type heavy doping implantation PH) and develop to form a lithographic window at the top of the cell; Partial etching of the BARC exposes the top of the cell, while the pitted areas between cells, the active area at the bottom of the cell, and the surrounding logic area retain the BARC protective layer to prevent damage from subsequent etching.

[0029] Dry etching (Dry ET) was used to etch and remove the oxide at the top of the cell.

[0030] The etching process utilizes the shadowing effect of Offsp etching to prevent the oxide in the control gate sharp corner region from being etched, thereby completely preserving the control gate sharp corner structure and protective layer, and ensuring reliability parameters such as word line-control gate breakdown voltage BV.

[0031] Since the polysilicon height of the Peri logic region is lower than that of the CELL, this etching step will not affect the Peri region; The remaining BARC is completely removed by dry etching, exposing the complete pattern structure; N+ source / drain injection (NP S / D Implant); N+ source drain dry strip (NP S / D Dry Strip); N+ Source Leakage Wet Strip (NP S / D Wet Strip); After the above process, the FGSP Oxide at the top of the control gate and the word line OX at the top of the word line are completely removed, and the control gate and the top of the word line can form a complete and continuous silicide, thereby significantly reducing the control gate resistance and word line resistance and improving the Flash read and write speed.

[0032] Second embodiment; This invention provides a NORD Flash memory, including a storage cell (CELL) and a peripheral logic area (Peri). The storage cell (CELL) includes a control gate and word lines, and is implemented based on a first embodiment. The oxide at the top of the control gate and word line is completely removed to form a complete silicide. An oxide protective layer is retained at the sharp corners of the control gate; The recessed areas between the memory cells and the surrounding logic area Peri are protected by the anti-reflective layer BARC during the etching process, while the surrounding logic area Peri is not affected by the etching process at the top of the memory cell.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0034] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A manufacturing method for reducing the resistance between the control gate and word line of a NORD Flash memory cell, characterized in that, include: 1) Spin-coat the bottom anti-reflective layer on the storage cell and the surrounding logic area, and use the fluidity of the anti-reflective layer to fill the gaps between the storage cells, so that the surface of the anti-reflective layer at the top of the storage cell is flat. 2) After N-type heavy doping implantation photolithography and development, the anti-reflection layer is partially etched to expose the top of the memory cell, while the anti-reflection layer is retained to protect the pit of the memory cell. 3) Dry etching is used to etch the oxide at the top of the memory cell, and the shadowing effect of offset sputtering etching is used to protect the oxide at the sharp corner of the control gate. 4) Remove the remaining anti-reflection layer by dry etching, and then perform an N-type heavy doping implantation process; 5) The oxides at the top of the control gate and word line are completely removed to form a complete silicide.

2. The manufacturing method for reducing the resistance of the control gate and word line of a NORD Flash memory cell according to claim 1, characterized in that: The height of the polysilicon in the peripheral logic region is lower than that of the memory cell, so etching the oxide at the top of the memory cell does not affect the peripheral logic region.

3. The manufacturing method for reducing the resistance of the control gate and word line of a NORD Flash memory cell according to claim 1, characterized in that: The active area at the bottom of the memory cell is protected by an anti-reflection layer during etching.

4. The manufacturing method for reducing the resistance of the control gate and word line of a NORD Flash memory cell according to claim 1, characterized in that: The oxide at the control gate sharp corner is retained during the oxide etching at the top of the memory cell.

5. The manufacturing method for reducing the resistance of the control gate and word line of a NORD Flash memory cell according to claim 1, characterized in that: The existing N-type heavily doped implantation mask is used, and no new mask is added.

6. A NORD Flash memory, comprising memory cells and peripheral logic areas, wherein the memory cells include control gates and word lines, characterized in that: The oxide at the top of the control gate and word line is completely removed to form a complete silicide. An oxide protective layer is retained at the sharp corners of the control gate; The pitted areas between memory cells and the surrounding logic areas are protected by an anti-reflective layer during the etching process.

7. The NORD Flash memory according to claim 6, characterized in that: The surrounding logic area was not affected by the etching process at the top of the storage cell.

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