Memory chip and preparation method thereof, memory, and electronic device

Abstract

The application provides a storage chip and a preparation method thereof, a memory and an electronic device, relates to the field of storage, and improves the anti-interference performance while maintaining a low overall operating voltage. The storage chip comprises a substrate, a first stacked structure and a storage unit arranged on the substrate, and the storage unit comprises a capacitor and a selector. The first stacked structure comprises first and second spacing layers arranged in layers, and a hollow part is arranged in the first stacked structure. The capacitor comprises a first electrode, a ferroelectric layer and a second electrode; the first electrode is located between the first and second spacing layers and forms a first groove with an opening facing the hollow part; the second electrode is filled in the hollow part and the first groove; the ferroelectric layer is located between the first and second electrodes, and the first electrode and the ferroelectric layer surround the second electrode once. The selector comprises a third electrode and a dielectric layer; on one side of the hollow part, the dielectric layer is in contact with the first electrode, and the third electrode is arranged on the side of the dielectric layer away from the hollow part.

Description

Technical Field

[0001] This application relates to the field of storage, and more particularly to a storage chip and its fabrication method, a memory, and an electronic device. Background Technology

[0002] Memory is a device for storing data, and based on its data retention characteristics, it can be divided into volatile and non-volatile. Volatile dynamic random access memory (DRAM) occupies the vast majority of the memory market due to its high speed and reliability. Currently, DRAM development is approaching its miniaturization limit. Ferroelectric memory based on hafnium-based materials, as an emerging type of memory, rivals DRAM in speed. Furthermore, the complementary metal-oxide-semiconductor (CMOS) technology in ferroelectric memory can be stacked through back-end processes, and its non-volatility gives it a wider range of potential applications compared to DRAM.

[0003] like Figure 1a As shown, ferroelectric memory typically uses a 1T1C (one transistor and one capacitor) architecture, where each capacitor needs to be connected in series with a transistor. This architecture limits the ability to increase the density of memory arrays. Figure 1b The diagram illustrates a 1TnC architecture (where n is an integer greater than 1), employing a structure similar to 3D flash memory. Plate lines (PLs) and shared local bit lines (BLs) intersect to select transistors and a specific capacitor (selected memory cell). While this architecture effectively increases the density of the memory array, crosstalk issues exist in the partially selected memory cells. Specifically, in a partially selected memory cell, the voltage across the capacitor is affected by the voltage on the local BL, leading to crosstalk problems.

[0004] Selectors, as two-terminal switching devices, have a relatively simple structure and are widely used in phase-change random access memory (PCRAM) and resistive random-access memory (RRAM). For example... Figure 2a As shown, a 1S1C memory cell consisting of a selector and a capacitor can effectively suppress crosstalk problems in half-selected memory cells.

[0005] Figure 2bA schematic diagram of a 1S1C memory cell is shown, which is an overall three-dimensional (3D) trench structure. In this structure, the area of ​​the selector is close to the area of ​​the capacitor and cannot be adjusted. The 1S1C memory cell needs to adjust the area ratio of the selector to the capacitor to achieve the optimal area ratio, so as to improve the anti-disturbance performance while maintaining a low overall operating voltage. Summary of the Invention

[0006] To address the aforementioned technical problems, this application provides a memory chip and its fabrication method, a memory, and an electronic device. By adjusting the relative positions of the selector and the capacitor, the area ratio of the selector and the capacitor is adjusted, thereby achieving an optimal capacitance ratio between the selector and the capacitor. This improves anti-disturbance performance while maintaining a low overall operating voltage.

[0007] In a first aspect, this application provides a memory chip, which includes a substrate, a first stacked structure disposed on the substrate, and memory cells. The memory cells include a capacitor and a selector. Along the column direction from the substrate to the first stacked structure, the first stacked structure includes a first spacer layer and a second spacer layer stacked together. A cutout portion is formed in the first stacked structure, penetrating through the first stacked structure. The capacitor includes a first electrode, a ferroelectric layer, and a second electrode. The first electrode is located between the first spacer layer and the second spacer layer, and forms a first groove opening towards the cutout portion. The second electrode fills the cutout portion and the first groove. The ferroelectric layer is located between the first electrode and the second electrode, and the first electrode and the ferroelectric layer surround the second electrode. The selector includes a third electrode and a dielectric layer. On one side of the cutout portion, the dielectric layer is in contact with the first electrode, and the third electrode is disposed on the side of the dielectric layer opposite to the cutout portion.

[0008] In the structure provided in the embodiments of this application, the area of ​​the selector is the contact area between the dielectric layer and the first electrode. The smaller the contact area between the dielectric layer and the first electrode, the smaller the area ratio of the selector; conversely, the larger the contact area, the larger the area ratio of the selector. The area of ​​the capacitor is the area of ​​the overlapping portion of the first electrode and the second electrode.

[0009] This application can adjust the area of ​​the selector and the area of ​​the capacitor by adjusting the relative position of the selector and the capacitor, thereby adjusting the area ratio of the selector and the capacitor to achieve the optimal area ratio, and thus achieve the optimal capacitance ratio of the selector and the capacitor, so as to improve the anti-disturbance performance while maintaining a low overall operating voltage.

[0010] The relative positions of the selector and capacitor can be achieved during the fabrication of the memory chip. A sacrificial layer can be disposed between the first and second spacer layers. The selector fabrication process involves: removing a portion of the sacrificial layer (this portion is called the first sacrificial layer, which forms a first notch region after removal), and then forming the selector at the first notch region. The capacitor fabrication process involves: forming a cutout in a first stacked structure containing the first spacer layer, sacrificial layer, and second spacer layer; then partially removing the sacrificial layer along the direction pointing towards the sidewall of the sacrificial layer (this portion is called the second sacrificial layer, which forms a second notch region after removal), and forming the capacitor in the second notch region and the cutout.

[0011] In the first scenario, a selector is first formed between the first and second spacer layers, and then a capacitor is formed between the first and second spacer layers. The area of ​​the selector and the area of ​​the capacitor can be adjusted by changing the positions of the resistor and the capacitor. The larger the contact area between the capacitor and the selector, the larger the area of ​​the selector, the larger the area of ​​the removed second sacrificial layer, and the larger the overall area of ​​the capacitor.

[0012] In this case, if the dielectric layer is exactly tangent to the first electrode, the capacitor is symmetrical about the cutout portion. That is, the first electrode is symmetrical about the cutout portion, the ferroelectric layer is symmetrical about the cutout portion, and the portion of the second electrode located in the first groove is also symmetrical about the cutout portion.

[0013] Alternatively, if the contact point between the dielectric layer and the first electrode is a cross-section, the portion of the capacitor located between the first spacer layer and the second spacer layer includes a first portion and a second portion. The first portion contacts the selector, and the second portion is opposite to the first portion. Along the direction from the capacitor to the selector, the total size of the first portion is smaller than the total size of the second portion.

[0014] Based on this, along the direction from the capacitor to the selector, the size of the portion of the removed second sacrificial layer that contacts the selector is smaller than the size of the portion of the removed second sacrificial layer located in other areas. First electrodes are formed at each location using the same semiconductor process, and then ferroelectric layers are formed at each location using the same semiconductor process. Along the direction from the capacitor to the selector, the thickness of the ferroelectric layer in the first part is equal to the thickness of the ferroelectric layer in the second part, and the thickness of the first electrode in the first part is equal to the thickness of the first electrode in the second part. However, after filling the cutout and the first groove with the second electrode, along the direction from the capacitor to the selector, the width of the second electrode in the first part is smaller than the width of the second electrode in the second part.

[0015] In the second scenario, a capacitor is first formed between the first and second spacer layers, and then a selector is formed between the first and second spacer layers. This allows the area of ​​the selector and the capacitor to be adjusted by changing the positions of the resistor and capacitor without affecting the capacitor's function. The larger the contact area between the capacitor and the selector, the larger the area of ​​the selector. Since the capacitor's position is fixed, even a larger contact area between the capacitor and the selector does not affect the capacitor's area.

[0016] In this case, if the dielectric layer is exactly tangent to the first electrode, the capacitor is symmetrical about the cutout portion. That is, the first electrode is symmetrical about the cutout portion, the ferroelectric layer is symmetrical about the cutout portion, and the portion of the second electrode located in the first groove is also symmetrical about the cutout portion.

[0017] Alternatively, if the contact point between the dielectric layer and the first electrode is a cross-section, the portion of the capacitor located between the first spacer layer and the second spacer layer includes a first portion and a second portion. The first portion contacts the selector, and the second portion is opposite to the first portion. Along the direction from the capacitor to the selector, the total size of the first portion is smaller than the total size of the second portion.

[0018] Based on this, if the contact point between the dielectric layer and the first electrode is to be a truncated surface, then the portion of the first electrode in contact with the dielectric layer is partially removed. Therefore, along the direction from the capacitor to the selector, the thickness of the first electrode in the first part is less than the thickness of the first electrode in the second part. However, the ferroelectric layer and the second electrode in the capacitor are not affected by the contact surface between the dielectric layer and the first electrode. Therefore, along the direction from the capacitor to the selector, the thickness of the ferroelectric layer in the first part is equal to the thickness of the ferroelectric layer in the second part, and the width of the second electrode in the first part is equal to the width of the second electrode in the second part.

[0019] In some possible implementations, the dielectric layer is an opening facing away from the second groove of the cutout, and the third electrode is filled in the second groove. That is, the dielectric layer is located not only between the third electrode and the capacitor, but also between the third electrode and the first spacer layer, and between the third electrode and the second spacer layer. Alternatively, the dielectric layer is located between the third electrode and the capacitor, and is not disposed in any other position.

[0020] The dielectric layer located between the third electrode and the capacitor is typically deposited using chemical vapor deposition (CVD), while the dielectric layer forming the second groove is typically deposited using atomic layer deposition (ALD). Compared to the dielectric layer between the third electrode and the capacitor, the dielectric layer forming the second groove has a smaller deposition thickness, allowing a larger current to flow with a smaller voltage applied to the memory cell. This improves the switching characteristics of the selector and saves power consumption.

[0021] In some possible implementations, in the first stacked structure, first and second spacer layers are alternately arranged, and the number of memory cells is multiple. The memory chip also includes bit lines, with the second electrode of a row of memory cells electrically connected to the same bit line.

[0022] In the 1S1C structure shown in related technologies, which is an overall 3D trench structure, only a single layer of memory cells can be fabricated in the column direction due to structural limitations. However, the solution of this application can fabricate multiple layers of memory cells in the column direction. Therefore, compared to related technologies, the embodiments of this application can improve the storage density of the memory chip.

[0023] In some possible implementations, there are multiple memory cells along the row direction. The memory chip also includes board lines, with the third electrode of a row of memory cells electrically connected to the same board line.

[0024] In some possible implementations, the second electrode of a column of memory cells is multiplexed as a bit line, and the third electrode of a row of memory cells is multiplexed as a board line.

[0025] In some possible implementations, the material of the dielectric layer includes tunneling dielectric materials or threshold switching materials.

[0026] Secondly, this application provides a memory, which includes a controller and the memory chip described in the first aspect, wherein the controller is used to control the reading and writing of data in the memory cells of the memory chip.

[0027] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0028] Thirdly, this application provides an electronic device, including a circuit board and the memory described in the second aspect, wherein the memory is electrically connected to the circuit board.

[0029] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0030] Fourthly, this application provides a method for fabricating a memory chip, comprising: forming a second stacked structure on a substrate, the second stacked structure including a first spacer layer, a sacrificial layer, and a second spacer layer stacked thereon; removing the sacrificial layer to form a cutout portion penetrating the second stacked structure, and forming a capacitor and a selector between the first spacer layer and the second spacer layer; the capacitor includes a first electrode, a ferroelectric layer, and a second electrode; the first electrode is located between the first spacer layer and the second spacer layer and has an opening facing the cutout portion in a first groove; the second electrode fills the cutout portion and the first groove; the ferroelectric layer is located between the first electrode and the second electrode, and the first electrode and the ferroelectric layer surround the second electrode; the selector includes a third electrode and a dielectric layer; on one side of the cutout portion, the dielectric layer is in contact with the first electrode, and the third electrode is disposed on the side of the dielectric layer away from the cutout portion.

[0031] In the structure provided in this application, the area of ​​the selector is the contact area between the dielectric layer and the first electrode. The smaller the contact area between the dielectric layer and the first electrode, the smaller the area ratio of the selector; conversely, the larger the contact area, the larger the area ratio of the selector. The area of ​​the capacitor is the area of ​​the overlapping portion of the first electrode and the second electrode.

[0032] This application can adjust the area of ​​the selector and the area of ​​the capacitor by adjusting the relative position of the selector and the capacitor, thereby adjusting the area ratio of the selector and the capacitor to achieve the optimal area ratio, and thus achieve the optimal capacitance ratio of the selector and the capacitor, so as to improve the anti-disturbance performance while maintaining a low overall operating voltage.

[0033] In some possible implementations, removing the sacrificial layer and forming a capacitor and a selector between the first and second spacer layers includes: partially removing the sacrificial layer along a direction pointing towards the sidewalls of the sacrificial layer to form a first gap region between the first and second spacer layers; filling the first gap region with a selector; partially removing the second stacked structure along a direction pointing towards the substrate to form a cutout; further removing the sacrificial layer along a direction pointing towards the selector to form a second gap region between the first and second spacer layers to expose the selector; and forming a capacitor in the second gap region and the cutout.

[0034] In the memory chip fabricated through this step, the area of ​​the selector and the area of ​​the capacitor can be adjusted by changing the positions of the resistors and capacitors. The larger the contact area between the capacitor and the selector, the larger the area of ​​the selector, the larger the area of ​​the removed second sacrificial layer, and the larger the overall area of ​​the capacitor.

[0035] In this case, if the dielectric layer is exactly tangent to the first electrode, the capacitor is symmetrical about the cutout portion. That is, the first electrode is symmetrical about the cutout portion, the ferroelectric layer is symmetrical about the cutout portion, and the portion of the second electrode located in the first groove is also symmetrical about the cutout portion.

[0036] Alternatively, if the contact point between the dielectric layer and the first electrode is a cross-section, the portion of the capacitor located between the first spacer layer and the second spacer layer includes a first portion and a second portion. The first portion contacts the selector, and the second portion is opposite to the first portion. Along the direction from the capacitor to the selector, the total size of the first portion is smaller than the total size of the second portion.

[0037] Based on this, along the direction from the capacitor to the selector, the size of the portion of the removed second sacrificial layer that contacts the selector is smaller than the size of the portion of the removed second sacrificial layer located in other areas. First electrodes are formed at each location using the same semiconductor process, and then ferroelectric layers are formed at each location using the same semiconductor process. Along the direction from the capacitor to the selector, the thickness of the ferroelectric layer in the first part is equal to the thickness of the ferroelectric layer in the second part, and the thickness of the first electrode in the first part is equal to the thickness of the first electrode in the second part. However, after filling the cutout and the first groove with the second electrode, along the direction from the capacitor to the selector, the width of the second electrode in the first part is smaller than the width of the second electrode in the second part.

[0038] In some possible implementations, removing the sacrificial layer and forming a capacitor and a selector between the first and second spacer layers includes: partially removing the second stacked structure in a direction pointing towards the substrate to form a cutout; partially removing the sacrificial layer in a direction pointing towards the sidewall of the cutout to form a second gap region between the first and second spacer layers; forming a capacitor in the second gap region and the cutout; further removing the sacrificial layer in a direction pointing towards the capacitor to form a first gap region between the first and second spacer layers to expose the capacitor; and filling the first gap region with a selector.

[0039] In the memory chip fabricated through this step, the area of ​​the selector and the area of ​​the capacitor can be adjusted by changing the positions of the resistor and the capacitor without affecting the function of the capacitor. The larger the contact area between the capacitor and the selector, the larger the area of ​​the selector. Since the position of the capacitor is fixed, even if the contact area between the capacitor and the selector is larger, it does not affect the area of ​​the capacitor.

[0040] In this case, if the dielectric layer is exactly tangent to the first electrode, the capacitor is symmetrical about the cutout portion. That is, the first electrode is symmetrical about the cutout portion, the ferroelectric layer is symmetrical about the cutout portion, and the portion of the second electrode located in the first groove is also symmetrical about the cutout portion.

[0041] Alternatively, if the contact point between the dielectric layer and the first electrode is a cross-section, the portion of the capacitor located between the first spacer layer and the second spacer layer includes a first portion and a second portion. The first portion contacts the selector, and the second portion is opposite to the first portion. Along the direction from the capacitor to the selector, the total size of the first portion is smaller than the total size of the second portion.

[0042] Based on this, if the contact point between the dielectric layer and the first electrode is to be a truncated surface, then the portion of the first electrode in contact with the dielectric layer is partially removed. Therefore, along the direction from the capacitor to the selector, the thickness of the first electrode in the first part is less than the thickness of the first electrode in the second part. However, the ferroelectric layer and the second electrode in the capacitor are not affected by the contact surface between the dielectric layer and the first electrode. Therefore, along the direction from the capacitor to the selector, the thickness of the ferroelectric layer in the first part is equal to the thickness of the ferroelectric layer in the second part, and the width of the second electrode in the first part is equal to the width of the second electrode in the second part. Attached Figure Description

[0043] Figure 1a Circuit diagram of a 1T1C memory cell provided for related technologies;

[0044] Figure 1b Circuit diagram of a 1TnC memory cell provided for related technologies;

[0045] Figure 2a A circuit diagram of the 1S1C memory cell provided in an embodiment of this application;

[0046] Figure 2b A structural diagram of the 1S1C memory cell provided for related technologies;

[0047] Figure 3a This is a diagram showing the relationship between the modules in the electronic device provided in the embodiments of this application;

[0048] Figure 3b An interaction diagram of the various modules in the memory provided in the embodiments of this application;

[0049] Figure 4a A circuit diagram of the 1S1C memory cell provided in an embodiment of this application;

[0050] Figure 4b for Figure 4a Structure diagram of storage unit A in the middle;

[0051] Figure 4c A perspective view of a memory chip provided in an embodiment of this application;

[0052] Figure 4d for Figure 4b A cross-sectional view of the storage cell B1-B2;

[0053] Figure 5a A top view of the selector and capacitor provided in an embodiment of this application;

[0054] Figure 5b A top view of the selector and capacitor provided in an embodiment of this application;

[0055] Figure 6a This is a structural diagram of a memory chip provided in an embodiment of this application;

[0056] Figure 6b This is a structural diagram of a memory chip provided in an embodiment of this application;

[0057] Figure 7 This is a structural diagram of a memory chip provided in an embodiment of this application;

[0058] Figure 8a A perspective view of a memory chip provided in an embodiment of this application;

[0059] Figure 8b A perspective view of a memory chip provided in an embodiment of this application;

[0060] Figure 8c This is a structural diagram of a memory chip provided in an embodiment of this application;

[0061] Figure 9 A flowchart illustrating the fabrication process of a memory chip provided in an embodiment of this application;

[0062] Figures 10a-10g A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0063] Figure 11 A flowchart illustrating the fabrication process of a memory chip provided in an embodiment of this application;

[0064] Figures 12a-12f This is a process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application. Detailed Implementation

[0065] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0066] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0067] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0068] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0069] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0070] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, a communication electronics product, or any other device that includes a memory.

[0071] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, memory devices, radar, base stations, and other devices containing memory.

[0072] Figure 3aThis application provides a schematic diagram of the structure of a memory in an electronic device. The memory may be, for example, DRAM, resistive random-access memory (RRAM), magnetic random-access memory (MRAM), ferroelectric random-access memory (FeRAM), etc. The electronic device may also include a circuit board, and the memory is electrically connected to the circuit board.

[0073] like Figure 3b As shown, the memory includes a memory array, a controller, row decoders, column decoders, etc. The memory array includes memory cells, and each memory cell includes transistors and capacitors. The processor can send the address of the selected memory cell to the row decoders and column decoders through the controller. After decoding the received address, the row decoders and column decoders determine at least one memory cell in the memory array as the selected memory cell, and then perform read and write operations on the selected memory cell.

[0074] Currently, volatile DRAM dominates the memory market due to its high speed and reliability, but DRAM development is nearing its miniaturization limits. For example... Figure 1a As shown, memory typically employs a 1T1C (one transistor and one capacitor) architecture, where each capacitor requires a transistor connected in series. This architecture limits the ability to increase memory array density. Ferroelectric memory, based on hafnium-based materials, is an emerging type of memory that rivals DRAM in speed. Furthermore, the CMOS in ferroelectric memory can be stacked through back-end processes, and its non-volatility gives it broader potential applications compared to DRAM.

[0075] Figure 1b A 1TnC ferroelectric memory architecture (n is an integer greater than 1) is shown, which adopts a structure similar to 3D flash memory. The board line PL and the shared bit line local BL cross-select the transistor and a capacitor (selected memory cell). Although this architecture effectively improves the density of the memory array, crosstalk problems exist in the partially selected memory cells. That is, in the partially selected memory cells, the voltage across the capacitor is affected by the voltage on the local BL, causing crosstalk problems in the partially selected memory cells.

[0076] Selectors, as two-terminal switching devices, have a relatively simple structure and are widely used in PCRAM and RRAM. For example... Figure 2a As shown, a 1S1C memory cell consisting of a selector and a capacitor can effectively suppress crosstalk problems encountered by half-selected memory cells. Furthermore, the 1S1C memory cell does not contain complex transistors, which helps to increase the memory's storage density.

[0077] Figure 2b A schematic diagram of a 1S1C memory cell is shown, which is an overall 3D trench structure. In this structure, the area of ​​the selector is close to the area of ​​the capacitor and cannot be adjusted. The 1S1C memory cell needs to adjust the area ratio of the selector to the capacitor to achieve the optimal area ratio, so as to improve the anti-disturbance performance while maintaining a low overall operating voltage.

[0078] Based on this, embodiments of this application provide a memory chip, such as... Figures 4a-4d As shown, the memory chip includes a substrate 10, a first stacked structure and a memory cell disposed on the substrate 10, and the memory cell includes a capacitor and a selector.

[0079] like Figure 4d As shown, along the column direction of the substrate 10 pointing to the first stacked structure, the first stacked structure includes a first spacer layer 31 and a second spacer layer 32 stacked together. A cutout portion is provided in the first stacked structure, and the cutout portion penetrates the first stacked structure.

[0080] like Figure 4c and Figure 4d As shown, the capacitor includes a first electrode 11, a ferroelectric layer 12, and a second electrode 13. The first electrode 11 is located between a first spacer layer 31 and a second spacer layer 32, and forms a first groove with an opening facing the hollow portion. The second electrode 13 fills the hollow portion and the first groove. The ferroelectric layer 12 is located between the first electrode 11 and the second electrode 13, and the first electrode 11 and the ferroelectric layer 12 surround the second electrode 13. (For ease of illustration,) Figure 4c The first spacer layer 31 and the second spacer layer 32 are not shown.

[0081] like Figure 4c and Figure 4d As shown, the selector includes a third electrode 21 and a dielectric layer 22. On one side of the cutout portion, the dielectric layer 22 is in contact with the first electrode 11, and the third electrode 21 is disposed on the side of the dielectric layer 22 away from the cutout portion.

[0082] In the structure provided in this application embodiment, the area of ​​the selector is the contact area between the dielectric layer 22 and the first electrode 11, such as... Figure 5a and Figure 5b As shown, the smaller the contact area between the dielectric layer 22 and the first electrode 11, the smaller the area ratio of the selector; conversely, the larger the contact area, the larger the area ratio of the selector. The area of ​​the capacitor is the area of ​​the overlapping portion of the first electrode 11 and the second electrode 13.

[0083] This application can adjust the area of ​​the selector and the area of ​​the capacitor by adjusting the relative position of the selector and the capacitor, thereby adjusting the area ratio of the selector and the capacitor to achieve the optimal area ratio, and thus achieve the optimal capacitance ratio of the selector and the capacitor, so as to improve the anti-disturbance performance while maintaining a low overall operating voltage.

[0084] The relative positions of the selector and capacitor can be determined during the fabrication of the memory chip. A sacrificial layer 33 can be disposed between the first spacer layer 31 and the second spacer layer 32. The selector fabrication process involves removing a portion of the sacrificial layer 33 (this portion is called the first sacrificial layer, and the removal of the first sacrificial layer forms a first notch region), and then forming the selector at the first notch region. The capacitor fabrication process involves forming a cutout in a first stacked structure containing the first spacer layer 31, the sacrificial layer 33, and the second spacer layer 33, and then partially removing the sacrificial layer 33 along the direction pointing towards the sidewall of the sacrificial layer 33 (this portion is called the second sacrificial layer, and the removal of the first sacrificial layer forms a second notch region), and forming the capacitor in the second notch region and the cutout. Specifically:

[0085] In the first scenario, a selector is first formed between the first spacer layer 31 and the second spacer layer 32, and then a capacitor is formed between the first spacer layer 31 and the second spacer layer 32. The area of ​​the selector and the area of ​​the capacitor can be adjusted by adjusting the positions of the resistor and the capacitor. The larger the contact area between the capacitor and the selector, the larger the area of ​​the selector, the larger the area of ​​the removed second sacrificial layer, and the larger the overall area of ​​the capacitor.

[0086] In this case, such as Figure 4d and Figure 5a As shown, if the dielectric layer 22 is exactly tangent to the first electrode 11, then the capacitor is symmetrical about the hollow part, that is, the first electrode 11 is symmetrical about the hollow part, the ferroelectric layer 12 is symmetrical about the hollow part, and the part of the second electrode 13 located in the first groove is also symmetrical about the hollow part.

[0087] Or, such as Figure 5b and Figure 6a As shown, if the contact point between the dielectric layer 22 and the first electrode 11 is a cross-section, the portion of the capacitor located between the first spacer layer 31 and the second spacer layer 32 includes a first portion and a second portion. The first portion is in contact with the selector, and the second portion is opposite to the first portion. Along the direction from the capacitor to the selector, the total size of the first portion is smaller than the total size of the second portion.

[0088] Based on this, such as Figure 6aAs shown, along the direction from the capacitor to the selector, the size of the portion of the removed second sacrificial layer that contacts the selector is smaller than the size of the portion of the removed second sacrificial layer located in other areas. After forming the first electrode 11 at each location using the same semiconductor process, and then forming the ferroelectric layer 12 at each location using the same semiconductor process, along the direction from the capacitor to the selector, the thickness of the ferroelectric layer 12 in the first part is equal to the thickness of the ferroelectric layer 12 in the second part, and the thickness of the first electrode 11 in the first part is equal to the thickness of the first electrode 11 in the second part. However, after filling the hollow portion and the first groove with the second electrode 13, along the direction from the capacitor to the selector, the width d1 of the second electrode 13 in the first part is smaller than the width d2 of the second electrode 13 in the second part.

[0089] In the second scenario, a capacitor is first formed between the first spacer layer 31 and the second spacer layer 32, and then a selector is formed between the first spacer layer 31 and the second spacer layer 32. This allows the area of ​​the selector and the area of ​​the capacitor to be adjusted by changing the positions of the resistor and the capacitor without affecting the function of the capacitor. The larger the contact area between the capacitor and the selector, the larger the area of ​​the selector. Since the position of the capacitor is fixed, even if the contact area between the capacitor and the selector is larger, it does not affect the area of ​​the capacitor.

[0090] In this case, such as Figure 4d and Figure 5a As shown, if the dielectric layer 22 is exactly tangent to the first electrode 11, then the capacitor is symmetrical about the hollow part, that is, the first electrode 11 is symmetrical about the hollow part, the ferroelectric layer 12 is symmetrical about the hollow part, and the part of the second electrode 13 located in the first groove is also symmetrical about the hollow part.

[0091] Or, such as Figure 5b and Figure 6b As shown, if the contact point between the dielectric layer 22 and the first electrode 11 is a cross-section, the portion of the capacitor located between the first spacer layer 31 and the second spacer layer 32 includes a first portion and a second portion. The first portion is in contact with the selector, and the second portion is opposite to the first portion. Along the direction from the capacitor to the selector, the total size of the first portion is smaller than the total size of the second portion.

[0092] Based on this, such as Figure 6bAs shown, if the contact point between the dielectric layer 22 and the first electrode 11 is to be a truncated surface, then the portion of the first electrode 11 in contact with the dielectric layer 22 is partially removed. Therefore, along the direction from the capacitor to the selector, the thickness d3 of the first electrode 11 in the first part is less than the thickness d4 of the first electrode 11 in the second part. The ferroelectric layer 12 and the second electrode 13 in the capacitor are not affected by the contact surface between the dielectric layer 22 and the first electrode 11. Therefore, along the direction from the capacitor to the selector, the thickness of the ferroelectric layer 12 in the first part is equal to the thickness of the ferroelectric layer 12 in the second part, and the width of the second electrode 13 in the first part is equal to the width of the second electrode 13 in the second part.

[0093] In some possible implementations, the selector within the memory cell can function as a bidirectional threshold switch to control whether the memory cell is selected. Optionally, the material of the dielectric layer 22 in the selector can include tunneling dielectric materials, threshold switch materials, etc. Threshold switch materials can include ovonic threshold switching (OTS) materials, field-assisted superlinear threshold (FAST) materials, insulator-metal transition (IMT) materials, mixed ionic-electron conduction (MIEC) materials, etc.

[0094] In some possible implementations, the capacitor in the embodiments of this application can also be replaced with other devices, which are also suitable for the storage field. For example, the ferroelectric layer 12 can be replaced with a magnetic material, and the storage cell is 1S1M (a selector and a magnetic device); or, the ferroelectric layer 12 can also be replaced with a resistive switching material, and the storage cell is 1S1R (a selector and a resistive switching device).

[0095] In some possible ways of implementation, such as Figure 6a and Figure 6b As shown, the dielectric layer 22 has an opening facing away from the second groove of the hollow portion, and the third electrode 21 is filled in the second groove. That is, the dielectric layer 22 is located not only between the third electrode 21 and the capacitor, but also between the third electrode 21 and the first spacer layer 31, and between the third electrode 21 and the second spacer layer 32. Or, as Figure 7 As shown, the dielectric layer 22 is located between the third electrode 21 and the capacitor, and is not located in any other position.

[0096] Figure 7The dielectric layer 22 shown is typically deposited using a chemical vapor deposition (CVD) process, while the dielectric layer 22 forming the second groove is typically deposited using an atomic layer deposition (ALD) process. Compared to Figure 7 The dielectric layer 22 shown has a smaller thickness, forming a second groove. Applying a smaller voltage to the memory cell allows a larger current to flow, which can improve the switching characteristics of the selector and save power consumption.

[0097] In some embodiments, the preceding text used a single-layer memory cell as an example to describe the structure of a memory chip. The memory cells provided in this application embodiment can also be multiple, arranged along both row and column directions.

[0098] Figure 4a An exemplary circuit connection diagram of 18 memory cells is shown, which includes two memory arrays. Each memory array includes 9 memory cells, with 3 memory cells in both the column and row directions. Figure 8b As shown, a dielectric material 34 is also provided between adjacent memory arrays to electrically isolate the adjacent memory arrays.

[0099] There are multiple storage cells in the column direction. In the first stacking structure, the first spacing layer 31 and the second spacing layer 32 are alternately arranged. For example... Figures 8a-8c As shown, the selector and first electrode 11 of each memory cell are located between adjacent first spacer layers 31 and second spacer layers 32. In addition, the ferroelectric layer 12 extends from the sidewall of the cutout to the space between adjacent first spacer layers 31 and second spacer layers 32, and the second electrode 13 penetrates the entire cutout and extends to the space between adjacent first spacer layers 31 and second spacer layers 32.

[0100] Figure 2b In the 1S1C structure shown in related technologies, due to structural limitations, only a single layer of memory cells can be fabricated in the column direction. However, the solution of this application embodiment can fabricate multiple layers of memory cells in the column direction. Therefore, compared to related technologies, this application embodiment can improve the storage density of the memory chip.

[0101] In some possible implementations, the memory chip also includes a bit line BL, with the second electrode 13 of a row of memory cells electrically connected to the same bit line BL. For ease of illustration, Figure 8a The first spacer layer 31 and the second spacer layer are not shown. Figure 8b for Figure 8aThe longitudinal cross-sectional view shows that there are multiple memory cells in the row direction. The memory chip also includes a board line PL, and the third electrode 21 of a row of memory cells is electrically connected to the same board line PL.

[0102] Optionally, the second electrode 13 of a column of memory cells is multiplexed as a bit line BL, and the third electrode 21 of a row of memory cells is multiplexed as a board line PL.

[0103] In another embodiment, this application also provides a method for fabricating a memory chip. Figure 9 The fabrication process of first forming a selector and then forming a capacitor is shown. Specifically, it can be achieved through the following steps:

[0104] S110, such as Figure 10a As shown, a second stacked structure is formed on the substrate 10. The second stacked structure includes a first spacer layer 31, a sacrificial layer 33, and a second spacer layer 32 stacked together.

[0105] In some possible implementations, the materials of the first spacer layer 31, the sacrificial layer 33, and the second spacer layer 32 are not limited, as long as the sacrificial layer 33, the first spacer layer 31, and the second spacer layer 32 all have a high etching selectivity. In this way, the first spacer layer 31 and the second spacer layer 32 will not be damaged during the partial removal of the sacrificial layer 33 in subsequent processes.

[0106] Optionally, the materials of the first spacer layer 31 and the second spacer layer 32 may include insulating oxides, and the material of the sacrificial layer 33 may include silicon nitride, etc.

[0107] S120, such as Figure 10b As shown, the sacrificial layer 33 is partially removed along the direction pointing towards the sidewall of the sacrificial layer 33, forming a first gap region between the first spacer layer 31 and the second spacer layer 32.

[0108] S130, such as Figure 10c and Figure 10d As shown, a selector is filled in the first notch region, and the selector includes a third electrode 21 and a dielectric layer 22.

[0109] like Figure 10c As shown, a dielectric layer 22 can be deposited using an ALD process. The resulting dielectric layer 22 has an opening facing away from the sacrificial layer 33, and the third electrode 21 fills the second groove. That is, the dielectric layer 22 is located not only between the third electrode 21 and the sacrificial layer 33, but also between the third electrode 21 and the first spacer layer 31, and between the third electrode 21 and the second spacer layer 32.

[0110] Or, such as Figure 10dAs shown, a dielectric layer 22 can be deposited using a CVD process. The resulting dielectric layer 22 is located between the third electrode 21 and the sacrificial layer 33 and is not placed in any other location.

[0111] Compared to Figure 10d The dielectric layer 22 shown, Figure 10c The dielectric layer 22 shown in the second groove is thinner, allowing a larger current to flow through with a smaller voltage applied to the memory cell, which can improve the switching characteristics of the selector and save power consumption.

[0112] S140, such as Figure 10e As shown, along the direction from the second stacked structure to the substrate, the second stacked structure is partially removed to form a hollow portion that penetrates the second stacked structure.

[0113] S150, such as Figure 10f As shown, along the direction from the cutout to the selector, the sacrificial layer 33 is removed again, forming a second gap region between the first spacer layer 31 and the second spacer layer 32. Alternatively, the remaining sacrificial layer 33 can be retained in the portion where the selector is not located, so that the remaining sacrificial layer can serve a supporting function.

[0114] S160, such as Figure 10g and Figure 8c As shown, a first electrode 11 of the capacitor is filled in the second notch region, and a ferroelectric layer 12 and a second electrode 13 of the capacitor are formed in the second notch region and the hollow portion. The first electrode 11 is located between the first spacer layer 31 and the second spacer layer 32, and has an opening facing the first groove of the hollow portion. The second electrode 13 is filled in the hollow portion and the first groove, and the ferroelectric layer 12 is located between the first electrode 11 and the second electrode 13, with the first electrode 11 and the ferroelectric layer 12 surrounding the second electrode 13. On one side of the hollow portion, the dielectric layer 12 is in contact with the first electrode 11, and the third electrode 21 is disposed on the side of the dielectric layer 22 facing away from the hollow portion.

[0115] In the structure provided in this application embodiment, the area of ​​the selector is the contact area between the dielectric layer 22 and the first electrode 11, such as... Figure 5a and Figure 5b As shown, the smaller the contact area between the dielectric layer 22 and the first electrode 11, the smaller the area ratio of the selector; conversely, the larger the contact area, the larger the area ratio of the selector. The area of ​​the capacitor is the area of ​​the overlapping portion of the first electrode 11 and the second electrode 13.

[0116] This application can adjust the area of ​​the selector and the area of ​​the capacitor by adjusting the relative position of the selector and the capacitor, thereby adjusting the area ratio of the selector and the capacitor to achieve the optimal area ratio, and thus achieve the optimal capacitance ratio of the selector and the capacitor, so as to improve the anti-disturbance performance while maintaining a low overall operating voltage.

[0117] Furthermore, in the memory chip prepared through steps S110-S160, the area of ​​the selector and the area of ​​the capacitor can be adjusted by adjusting the positions of the resistors and capacitors. The larger the contact area between the capacitor and the selector, the larger the area of ​​the selector, the larger the area of ​​the removed second sacrificial layer, and the larger the overall area of ​​the capacitor.

[0118] In this case, such as Figure 4d and Figure 5a As shown, if the dielectric layer 22 is exactly tangent to the first electrode 11, then the capacitor is symmetrical about the hollow part, that is, the first electrode 11 is symmetrical about the hollow part, the ferroelectric layer 12 is symmetrical about the hollow part, and the part of the second electrode 13 located in the first groove is also symmetrical about the hollow part.

[0119] Or, such as Figure 5b and Figure 6a As shown, if the contact point between the dielectric layer 22 and the first electrode 11 is a cross-section, the portion of the capacitor located between the first spacer layer 31 and the second spacer layer 32 includes a first portion and a second portion. The first portion is in contact with the selector, and the second portion is opposite to the first portion. Along the direction from the capacitor to the selector, the total size of the first portion is smaller than the total size of the second portion.

[0120] Based on this, such as Figure 6a As shown, along the direction from the capacitor to the selector, the size of the portion of the removed second sacrificial layer that contacts the selector is smaller than the size of the portion of the removed second sacrificial layer located in other areas. After forming the first electrode 11 at each location using the same semiconductor process, and then forming the ferroelectric layer 12 at each location using the same semiconductor process, along the direction from the capacitor to the selector, the thickness of the ferroelectric layer 12 in the first part is equal to the thickness of the ferroelectric layer 12 in the second part, and the thickness of the first electrode 11 in the first part is equal to the thickness of the first electrode 11 in the second part. However, after filling the hollow portion and the first groove with the second electrode 13, along the direction from the capacitor to the selector, the width d1 of the second electrode 13 in the first part is smaller than the width d2 of the second electrode 13 in the second part.

[0121] Other explanations and beneficial effects of the embodiments in this application are the same as those of the embodiment "Memory Chip", and will not be repeated here. Furthermore, Figures 10a-10gThe fabrication process of a memory chip is schematically illustrated by arranging multiple memory cells along a column direction. The structure provided in this application not only enables the stacking of multiple memory cells in the column direction to improve the storage density of the memory chip, but also allows multiple selectors within multiple memory cells to be fabricated using the same semiconductor process, and multiple memory cells within multiple memory cells to be fabricated using the same semiconductor process. Furthermore, the fabrication process diagram of a single memory cell in the column direction can be found in the textual descriptions of S110-S160. Figures 10a-10g .

[0122] In another embodiment, this application also provides a method for fabricating a memory chip. Figure 11 The fabrication process of first forming a capacitor and then forming a selector is shown. Specifically, it can be achieved through the following steps:

[0123] S210, such as Figure 10a As shown, a second stacked structure is formed on the substrate 10. The second stacked structure includes a first spacer layer 31, a sacrificial layer 33, and a second spacer layer 32 stacked together.

[0124] In some possible implementations, the materials of the first spacer layer 31, the sacrificial layer 33, and the second spacer layer 32 are not limited, as long as the sacrificial layer 33, the first spacer layer 31, and the second spacer layer 32 all have a high etching selectivity. In this way, the first spacer layer 31 and the second spacer layer 32 will not be damaged during the partial removal of the sacrificial layer 33 in subsequent processes.

[0125] Optionally, the materials of the first spacer layer 31 and the second spacer layer 32 may include insulating oxides, and the material of the sacrificial layer 33 may include silicon nitride, etc.

[0126] S220, such as Figure 12a As shown, along the direction from the second stacked structure to the substrate 10, the second stacked structure is partially removed to form a hollow portion that penetrates the second stacked structure.

[0127] S230, such as Figure 12b As shown, the sacrificial layer 33 is partially removed along the direction pointing to the side wall of the hollow part, forming a second gap region between the first spacer layer 31 and the second spacer layer 32.

[0128] S240, such as Figure 12cAs shown, a first electrode 11 of a capacitor is formed in the second notch region, and a ferroelectric layer 12 and a second electrode 13 are formed in the second notch region and the hollow portion. The first electrode 11 is located between the first spacer layer 31 and the second spacer layer 32, and has an opening facing the first groove of the hollow portion; the second electrode 13 fills the hollow portion and the first groove, and the ferroelectric layer 12 is located between the first electrode 11 and the second electrode 13, with the first electrode 11 and the ferroelectric layer 12 surrounding the second electrode 13.

[0129] S250, such as Figure 12d As shown, along the direction of the sacrificial layer 33 pointing towards the capacitor, the sacrificial layer 33 is removed again, forming a first gap region between the first spacer layer 31 and the second spacer layer 32 to expose the capacitor. Alternatively, the remaining sacrificial layer 33 may be retained in the portion where the selector is not provided, so that the remaining sacrificial layer can serve as a support.

[0130] S260, such as Figure 12e and Figure 12f As shown, a selector is filled in the first notch area. The selector includes a third electrode 21 and a dielectric layer 22. On one side of the cutout, the dielectric layer 22 is in contact with the first electrode 11, and the third electrode 21 is disposed on the side of the dielectric layer 22 away from the cutout.

[0131] like Figure 12e As shown, a dielectric layer 22 can be deposited using an ALD process. The resulting dielectric layer 22 has an opening facing away from the sacrificial layer 33, and the third electrode 21 fills the second groove. That is, the dielectric layer 22 is located not only between the third electrode 21 and the sacrificial layer 33, but also between the third electrode 21 and the first spacer layer 31, and between the third electrode 21 and the second spacer layer 32.

[0132] Or, such as Figure 12f As shown, a dielectric layer 22 can be deposited using a CVD process. The resulting dielectric layer 22 is located between the third electrode 21 and the sacrificial layer 33 and is not placed in any other location.

[0133] Compared to Figure 12f The dielectric layer 22 shown, Figure 12e The dielectric layer 22 shown in the second groove is thinner, allowing a larger current to flow through with a smaller voltage applied to the memory cell, which can improve the switching characteristics of the selector and save power consumption.

[0134] In the structure provided in this application embodiment, the area of ​​the selector is the contact area between the dielectric layer 22 and the first electrode 11, such as... Figure 5a and Figure 5bAs shown, the smaller the contact area between the dielectric layer 22 and the first electrode 11, the smaller the area ratio of the selector; conversely, the larger the contact area, the larger the area ratio of the selector. The area of ​​the capacitor is the area of ​​the overlapping portion of the first electrode 11 and the second electrode 13.

[0135] This application can adjust the area of ​​the selector and the area of ​​the capacitor by adjusting the relative position of the selector and the capacitor, thereby adjusting the area ratio of the selector and the capacitor to achieve the optimal area ratio, and thus achieve the optimal capacitance ratio of the selector and the capacitor, so as to improve the anti-disturbance performance while maintaining a low overall operating voltage.

[0136] Furthermore, in the memory chip prepared through steps S210-S260, the area of ​​the selector and the area of ​​the capacitor can be adjusted by changing the positions of the resistor and the capacitor without affecting the function of the capacitor. The larger the contact area between the capacitor and the selector, the larger the area of ​​the selector. Since the position of the capacitor is fixed, even if the contact area between the capacitor and the selector is larger, it does not affect the area of ​​the capacitor.

[0137] In this case, such as Figure 4d and Figure 5a As shown, if the dielectric layer 22 is exactly tangent to the first electrode 11, then the capacitor is symmetrical about the hollow part, that is, the first electrode 11 is symmetrical about the hollow part, the ferroelectric layer 12 is symmetrical about the hollow part, and the part of the second electrode 13 located in the first groove is also symmetrical about the hollow part.

[0138] Or, such as Figure 5b and Figure 6b As shown, if the contact point between the dielectric layer 22 and the first electrode 11 is a cross-section, the portion of the capacitor located between the first spacer layer 31 and the second spacer layer 32 includes a first portion and a second portion. The first portion is in contact with the selector, and the second portion is opposite to the first portion. Along the direction from the capacitor to the selector, the total size of the first portion is smaller than the total size of the second portion.

[0139] Based on this, such as Figure 6b As shown, if the contact point between the dielectric layer 22 and the first electrode 11 is to be a truncated surface, then the portion of the first electrode 11 in contact with the dielectric layer 22 is partially removed. Therefore, along the direction from the capacitor to the selector, the thickness d3 of the first electrode 11 in the first part is less than the thickness d4 of the first electrode 11 in the second part. The ferroelectric layer 12 and the second electrode 13 in the capacitor are not affected by the contact surface between the dielectric layer 22 and the first electrode 11. Therefore, along the direction from the capacitor to the selector, the thickness of the ferroelectric layer 12 in the first part is equal to the thickness of the ferroelectric layer 12 in the second part, and the width of the second electrode 13 in the first part is equal to the width of the second electrode 13 in the second part.

[0140] Other explanations and beneficial effects of the embodiments in this application are the same as those of the embodiment "Memory Chip", and will not be repeated here. Furthermore, Figures 12a-12f The fabrication process of a memory chip is schematically illustrated by arranging multiple memory cells along a column direction. The structure provided in this application not only enables the stacking of multiple memory cells in the column direction to improve the storage density of the memory chip, but also allows multiple selectors within multiple memory cells to be fabricated using the same semiconductor process, and multiple memory cells within multiple memory cells to be fabricated using the same semiconductor process. Furthermore, the fabrication process diagram of a single memory cell in the column direction can be found in the textual descriptions of S210-S260. Figures 12a-12f .

[0141] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory chip, characterized in that, The device includes a substrate, a first stacked structure disposed on the substrate, and a memory cell, wherein the memory cell includes a capacitor and a selector; Along the column direction of the substrate pointing to the first stacked structure, the first stacked structure includes a first spacer layer and a second spacer layer stacked together, and a cutout portion is formed in the first stacked structure, the cutout portion penetrating the first stacked structure; The capacitor includes a first electrode, a ferroelectric layer, and a second electrode; the first electrode is located between the first spacer layer and the second spacer layer, and has an opening facing the hollow portion in a first groove; the second electrode fills the hollow portion and the first groove; The ferroelectric layer is located between the first electrode and the second electrode, and the first electrode and the ferroelectric layer surround the second electrode. The selector includes a third electrode and a dielectric layer; on one side of the cutout portion, the dielectric layer is in contact with the first electrode, and the third electrode is disposed on the side of the dielectric layer opposite to the cutout portion.

2. The memory chip according to claim 1, characterized in that, The dielectric layer has an opening in a second groove that faces away from the hollow portion, and the third electrode is filled in the second groove.

3. The memory chip according to claim 1 or 2, characterized in that, The capacitor is symmetrical about the hollowed-out portion.

4. The memory chip according to claim 1 or 2, characterized in that, The portion of the capacitor located between the first spacer layer and the second spacer layer includes a first portion and a second portion, wherein the first portion is in contact with the selector and the second portion is opposite to the first portion; Along the direction from the capacitor to the selector, the total size of the first portion is smaller than the total size of the second portion; Along the direction from the capacitor to the selector, the thickness of the ferroelectric layer in the first part is equal to the thickness of the ferroelectric layer in the second part, the thickness of the first electrode in the first part is equal to the thickness of the first electrode in the second part, and the width of the second electrode in the first part is less than the width of the second electrode in the second part. or, Along the direction from the capacitor to the selector, the thickness of the ferroelectric layer in the first part is equal to the thickness of the ferroelectric layer in the second part, the width of the second electrode in the first part is equal to the width of the second electrode in the second part, and the thickness of the first electrode in the first part is less than the thickness of the first electrode in the second part.

5. The memory chip according to any one of claims 1-4, characterized in that, In the first stacking structure, the first spacer layer and the second spacer layer are alternately arranged, and the number of storage cells is multiple; The memory chip also includes bit lines, and the second electrodes of a row of memory cells are electrically connected to the same bit lines.

6. The memory chip according to claim 5, characterized in that, Along the row direction, the number of the storage units is multiple; The memory chip also includes a board line, and the third electrode of a row of memory cells is electrically connected to the same board line.

7. The memory chip according to claim 6, characterized in that, The second electrode of a column of the memory cells is multiplexed as the bit line, and the third electrode of a row of the memory cells is multiplexed as the board line.

8. The memory chip according to any one of claims 1-7, characterized in that, The material of the dielectric layer includes tunneling dielectric material or threshold switching material.

9. A memory, characterized in that, The memory includes a controller and a memory chip according to any one of claims 1-8, wherein the controller is used to control the reading and writing of data in the memory cells of the memory chip.

10. An electronic device, characterized in that, It includes a circuit board and the memory of claim 9, wherein the memory is electrically connected to the circuit board.

11. A method for fabricating a memory chip, characterized in that, include: A second stacked structure is formed on a substrate, the second stacked structure including a first spacer layer, a sacrificial layer and a second spacer layer stacked together; The sacrificial layer is removed to form a cutout that penetrates the second stacked structure, and a capacitor and a selector are formed between the first spacer layer and the second spacer layer; the capacitor includes a first electrode, a ferroelectric layer, and a second electrode; the first electrode is located between the first spacer layer and the second spacer layer and has an opening facing the cutout; the second electrode fills the cutout and the first groove. The ferroelectric layer is located between the first electrode and the second electrode, and the first electrode and the ferroelectric layer surround the second electrode; the selector includes a third electrode and a dielectric layer; on one side of the cutout portion, the dielectric layer is in contact with the first electrode, and the third electrode is disposed on the side of the dielectric layer opposite to the cutout portion.

12. The method for fabricating a memory chip according to claim 11, characterized in that, The process of removing the sacrificial layer and forming a capacitor and a selector between the first spacer layer and the second spacer layer includes: The sacrificial layer is partially removed along the direction pointing towards the sidewall of the sacrificial layer, forming a first gap region between the first spacer layer and the second spacer layer; Fill the selector in the first gap region; Along the direction from the second stacked structure to the substrate, the second stacked structure is partially removed to form the cutout portion; Along the direction of the cutout portion pointing to the selector, the sacrificial layer is removed again, forming a second gap area between the first spacer layer and the second spacer layer to expose the selector; The capacitor is formed in the second notch area and the hollowed-out portion.

13. The method for fabricating a memory chip according to claim 11, characterized in that, The process of removing the sacrificial layer and forming a capacitor and a selector between the first spacer layer and the second spacer layer includes: Along the direction from the second stacked structure to the substrate, the second stacked structure is partially removed to form the cutout portion; Along the direction pointing to the sidewall of the hollowed-out portion, the sacrificial layer is partially removed to form a second gap region between the first spacer layer and the second spacer layer; The capacitor is formed in the second notch region and the hollowed-out portion; The sacrificial layer is removed again along the direction from the sacrificial layer to the capacitor, forming a first gap region between the first spacer layer and the second spacer layer to expose the capacitor; Fill the selector in the first gap area.

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