Three-dimensional ferroelectric memory, semiconductor package structure and electronic device

Abstract

The application discloses a three-dimensional ferroelectric memory, a semiconductor packaging structure and an electronic device, and belongs to the technical field of ferroelectric memory technology.The application improves the storage capacity and the storage density by stacking a plurality of ferroelectric memory units in a first direction.The application forms a ladder architecture by setting a reset transistor and connecting a bit line and a plate line through the reset transistor.The application performs read-write operation by combining the potential switching of the bit line and the plate line when the reset transistor is off and a gating transistor is on.The first electrode and the second electrode of the ferroelectric capacitor are short-circuited when the reset transistor is on and the gating transistor is on, so that the charge flowing into the first electrode of the ferroelectric capacitor due to the interference caused by the potential switching of the bit line and the plate line can be released, thereby reducing the adverse effect on the polarization state of the ferroelectric material and improving the stability of the stored data in the ferroelectric capacitor.

Description

Technical Field

[0001] This application relates to the field of ferroelectric memory technology, and in particular to a three-dimensional ferroelectric memory, a semiconductor packaging structure, and an electronic device. Background Technology

[0002] As the feature size of ferroelectric memory cells approaches the lower limit of process technology, planar processes and manufacturing techniques become challenging and costly, resulting in the storage density of planar ferroelectric random access memory (FeRAM) approaching its upper limit. To overcome the limitations of planar FeRAM, three-dimensional (3D) FeRAM has been developed. During read and write operations in 3D FeRAM, a subset of ferroelectric memory cells is selected using word lines (WL), and then read and write operations are performed on this subset by toggle switching on bit lines (BL) and plate lines (PL). Unselected ferroelectric memory cells are affected by disturbances caused by the BL and PL potential switching, impacting the polarization state of the ferroelectric material in the ferroelectric capacitors within these unselected cells, and consequently affecting the stability of the data stored in the ferroelectric capacitors. Summary of the Invention

[0003] This application provides a three-dimensional ferroelectric memory, a semiconductor packaging structure, and an electronic device to improve the stability of data stored in ferroelectric capacitors by increasing storage density and mitigating interference caused by the switching of BL and PL potentials.

[0004] In a first aspect, this application provides a three-dimensional FeRAM, comprising: a first substrate, a memory array, and a reset transistor. The memory array is located on the first substrate, and the reset transistor is located on the side of the memory array facing away from the first substrate. The memory array includes multiple memory structures, each including: multiple ferroelectric memory cells, BL, PL, and multiple WLs. The multiple ferroelectric memory cells are stacked in a first direction, each including a gate transistor and a ferroelectric capacitor. The first electrode of the gate transistor and the first electrode of the ferroelectric capacitor are connected. BL and PL extend along the first direction, BL connecting to the second electrode of the gate transistor in the multiple ferroelectric memory cells, and PL connecting to the second electrode of the ferroelectric capacitor in the multiple ferroelectric memory cells. The multiple WLs extend along a second direction, and the gate of the gate transistor in any ferroelectric memory cell is connected to one WL. Furthermore, BL and PL in any memory structure are connected via a reset transistor. The first direction is perpendicular to the first substrate, and the second direction is perpendicular to the first direction. Therefore, the three-dimensional FeRAM provided in this application, by stacking ferroelectric memory cells, can improve storage capacity and storage density. Furthermore, by setting a reset transistor and connecting BL and PL through it, the connection and disconnection between BL and PL can be achieved by controlling the on and off states of the reset transistor. This allows ferroelectric memory cells and the reset transistor in any memory structure to form a ladder architecture. When the reset transistor is off, the signal transmitted through WL controls the conduction of the selection transistor. Combined with the potential switching on BL and PL, read and write operations on the ferroelectric memory cell can be performed. When the reset transistor is on, BL and PL are connected, and the selection transistor is controlled to conduct through WL, shorting the first and second electrodes of the ferroelectric capacitor. This releases the charge flowing into the first electrode of the ferroelectric capacitor due to interference from the potential switching of BL and PL, effectively reducing the duration of the bias voltage, minimizing the adverse effects on the polarization state of the ferroelectric material, and improving the stability of the data stored in the ferroelectric capacitor.

[0005] In one possible implementation, the plurality of memory structures includes at least two memory structures arranged along a second direction, which can further improve memory capacity and density. Furthermore, in these at least two memory structures, the gate transistors in the ferroelectric memory cells arranged along the second direction are connected to the same wiring loop (WL), and the black-white (BL) and white-white (PL) transistors in any adjacent memory structures are independent of each other. This configuration further improves memory capacity and density. Moreover, by allowing multiple ferroelectric memory cells to share a single wiring loop, larger-scale integration of ferroelectric memory cells can be achieved without significantly increasing wiring complexity. Furthermore, it can reduce crosstalk and improve the flexibility of read / write operations, enhancing the performance and reliability of 3D FeRAM, and supporting high-density storage and high-frequency operation of 3D FeRAM.

[0006] In one possible implementation, the plurality of memory structures includes at least two memory structures arranged along a third direction, which is perpendicular to the first and second directions, respectively. This arrangement can further increase memory capacity and density. Furthermore, in the memory structures arranged along the third direction, the BL and PL of any two memory structures are independent of each other, and each memory structure corresponds to a reset transistor. This allows the equivalent circuit of any memory structure to function as an independent ladder architecture, enabling each memory structure to operate independently in non-read / write states, improving control flexibility and reliability.

[0007] In one possible implementation, in a memory structure arranged along a third direction, the PL (Power Transfer Capacitor) in two adjacent memory structures is located between the ferroelectric capacitors in the two adjacent memory structures. This allows for more efficient use of the memory array space and increases the integration density of the memory array.

[0008] In one possible implementation, the PLs (polarization lines) are symmetrically arranged between the ferroelectric capacitors of two adjacent memory structures. This simplifies the layout design rules and reduces design complexity. Furthermore, during the fabrication process, the original single PL can be etched into two independent PLs, further reducing fabrication complexity and increasing memory cell density.

[0009] In one possible implementation, in a memory structure arranged along a third direction, the gate transistors (BLs) in two adjacent memory structures are located between the gate transistors of the two adjacent memory structures. This allows for more efficient use of the memory array space and increases the integration density of the memory array.

[0010] In one possible implementation, the band gaps (BLs) are symmetrically arranged between the gate transistors of two adjacent memory structures. This simplifies the layout design rules and reduces design complexity. Furthermore, during the fabrication process, the original single BL can be etched into two independent BLs, further reducing fabrication complexity and increasing memory cell density.

[0011] In one possible implementation, the plurality of storage structures includes at least two storage structures arranged along a third direction, which is perpendicular to the first and second directions, respectively. Furthermore, in at least a portion of the storage structures arranged along the third direction, BL and PL are interconnected. Thus, this at least portion of the storage structure can be equivalent to a ladder-like architecture, allowing for more efficient use of the storage array space and increasing the integration density of the storage array.

[0012] In one possible implementation, each memory structure is provided with a corresponding reset transistor, and the gates of the reset transistors corresponding to at least some memory structures are interconnected. Therefore, the multiple reset transistors corresponding to at least some memory structures can be considered as a single unit, so that when some of the reset transistors fail, the other reset transistors can still be controlled to operate, thereby enabling non-read / write and read / write operation processes.

[0013] In one possible implementation, at least part of the memory structure shares a single reset transistor. This configuration reduces the number of reset transistors and lowers design complexity.

[0014] In one possible implementation, the memory structures arranged along a third direction include adjacent first, second, and third memory structures. The PL in the first and second memory structures is located between the ferroelectric capacitors in the first and second memory structures, and the BL in the second and third memory structures is located between the gate transistors in the second and third memory structures. This allows for more efficient use of the memory array space and increases the integration density of the memory array.

[0015] In one possible implementation, the PL in the first storage structure and the PL in the second storage structure are shared. This not only makes the PL in the first storage structure and the PL in the second storage structure equivalent to being interconnected, but also optimizes the storage array layout, increases integration density, reduces wiring complexity, and lowers design difficulty. Furthermore, the BL in the first storage structure and the BL in the second storage structure are interconnected, while the BL in the second storage structure and the BL and PL in the third storage structure are independent of each other. This configuration allows the first and second storage structures to be equivalent to a ladder architecture, and the third storage structure to be equivalent to another ladder architecture with other storage structures, enabling more efficient use of storage array space and increasing the integration density of the storage array.

[0016] In one possible implementation, the BL in the second storage structure and the BL in the third storage structure are shared, the PL in the second storage structure and the PL in the third storage structure are interconnected, and the PL in the first storage structure and the PL and BL in the second storage structure are independent of each other. This configuration allows the second and third storage structures to be equivalent to a ladder architecture, and the first storage structure to be equivalent to other storage structures, enabling more efficient use of the storage array space and increasing the integration density of the storage array.

[0017] In one possible implementation, a control circuit board is also included, comprising a second substrate and a controller located on the second substrate. The controller is connected to the gates of BL, PL, WL, and a reset transistor via pads. This allows the reset transistor to be formed on the memory array, and the control circuit board to the first substrate on which the memory array is formed can be connected via a bonding process, avoiding the incompatibility issues between the complementary metal-oxide-semiconductor (CMOS) process for forming the controller and the process for forming the memory array.

[0018] In one possible implementation, a control circuit board is also included, comprising a second substrate and a controller located on the second substrate. The controller is connected to the gate of a reset transistor, and the controller and reset transistor are connected to BL and PL respectively via pads. The controller is also connected to WL via pads. Thus, the reset transistor can be formed on the control circuit board, and the control circuit board can be connected to the first substrate on which the memory array is formed via a bonding process, avoiding the incompatibility problem between the CMOS process for forming the controller and the process for forming the memory array.

[0019] In one possible implementation, in any storage structure, BL and PL are arranged along a third direction, and the third direction is perpendicular to the first and second directions, respectively. This arrangement reduces wiring complexity, utilizes space more efficiently, facilitates three-dimensional stacking design, and further improves the integration density of the storage array 20.

[0020] In one possible implementation, the gating transistor and ferroelectric capacitor are arranged along a third direction and positioned between BL and PL, with the third direction perpendicular to both the first and second directions. This arrangement optimizes the space utilization of the memory array and reduces design complexity.

[0021] In one possible implementation, a first region of the channel of the gate transistor is connected to BL, a second region of the channel is connected to a first electrode, and WL and a third region of the channel have an overlapping region in a first direction. WL in the overlapping region serves as the gate, and the third region is located between the first and second regions. This allows the first and second regions of the channel to be positioned on opposite sides of the channel, preventing them from contacting each other and fully utilizing each region of the channel. Furthermore, the gate transistor and ferroelectric capacitor can be closely arranged in the third direction, further compressing the size of the ferroelectric memory cell in the third direction and further increasing the storage density. Additionally, by using a portion of WL as the gate of the gate transistor, manufacturing processes and material usage can be reduced, lowering complexity and cost.

[0022] In one possible implementation, WL includes a first sub-signal line and a second sub-signal line, which are respectively located on opposite sides of the channel in a first direction. The first sub-signal line and a third region of the channel have a first overlap region in the first direction, and the second sub-signal line and the third region of the channel have a second overlap region in the first direction. The first sub-signal line in the first overlap region and the second sub-signal line in the second overlap region serve as gates. This configuration, with the first and second sub-signal lines located on opposite sides of the channel in the first direction, not only forms a dual-gate structure, enhancing channel control and improving device performance, but also optimizes the layout and increases the storage density of the memory array.

[0023] In one possible implementation, within the same storage space (WL), the first sub-signal line and the second sub-signal line have an overlapping area in a first direction. For example, within the same WL, the first sub-signal line and the second sub-signal line coincide in the first direction. This arrangement optimizes the layout and increases the storage density of the storage array.

[0024] For example, for a plurality of first sub-signal lines and a plurality of second sub-signal lines arranged along a first direction, the plurality of first sub-signal lines and the plurality of second sub-signal lines overlap in the first direction, which can further optimize the layout and further improve the storage density of the storage array.

[0025] In one possible implementation, in order to increase the capacitance of the ferroelectric capacitor, the first electrode may have a groove extending along the third direction, the opening of the groove facing PL, the second electrode may be filled in the groove, and a ferroelectric dielectric layer is present between the first electrode and the second electrode.

[0026] In one possible implementation, the PL and the second electrode are integrated into a single structure, allowing for direct electrical connection between the PL and the second electrode, shortening the signal transmission path and reducing latency. Furthermore, during the fabrication process, the PL can be inserted into a groove, with the portion of the PL inserted into the groove serving as the second electrode of the ferroelectric capacitor, simplifying the manufacturing process and reducing costs.

[0027] Secondly, this application provides a semiconductor packaging structure, comprising: a packaging substrate and a three-dimensional FeRAM, wherein the three-dimensional FeRAM is packaged on the packaging substrate. The three-dimensional FeRAM is the three-dimensional FeRAM of the first aspect or its embodiments. Because the three-dimensional FeRAM in the embodiments of this application has better performance, the semiconductor packaging structure including the three-dimensional FeRAM also has better performance.

[0028] Thirdly, this application provides an electronic device comprising: a circuit board and a semiconductor package structure, wherein the semiconductor package structure is electrically connected to the circuit board. The semiconductor package structure is the same as the one described in the second aspect. Because the semiconductor package structure in the embodiments of this application has good performance, the electronic device incorporating this semiconductor package structure also has good performance.

[0029] Furthermore, the technical effects of the corresponding solutions in the second and third aspects can be referred to the technical effects that can be obtained from the first aspect and the various implementation methods in the first aspect, and the repeated parts will not be described in detail. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of an electronic device in an embodiment of this application;

[0031] Figure 2A This is a schematic diagram of a semiconductor packaging structure in an embodiment of this application;

[0032] Figure 2B This is a schematic diagram of the charge in a ferroelectric capacitor.

[0033] Figure 3 This is a cross-sectional view of a three-dimensional FeRAM in an embodiment of this application;

[0034] Figure 4A for Figure 3 The diagram shows a top view of the storage array in a three-dimensional FeRAM.

[0035] Figure 4B for Figure 3 The diagram shows a top view of the BL and PL structures in the three-dimensional FeRAM.

[0036] Figure 4C This is a partial three-dimensional structural diagram of the storage array in the three-dimensional FeRAM in the embodiments of this application;

[0037] Figure 5A for Figure 3 The equivalent circuit diagrams of the three storage structures arranged along the third direction in the three-dimensional FeRAM are shown.

[0038] Figure 5B for Figure 3 The equivalent circuit diagram of BL, PL and reset transistor in a storage structure of a three-dimensional FeRAM is shown.

[0039] Figure 6 This is a schematic diagram showing the equivalent circuit of the ferroelectric memory cell and the reset transistor in a memory structure in one embodiment of this application when they are in read / write state and non-read / write state;

[0040] Figure 7A This is a schematic diagram of a three-dimensional FeRAM structure in an embodiment of this application;

[0041] Figure 7B This is another schematic diagram of a three-dimensional FeRAM structure in the embodiments of this application;

[0042] Figure 8 This is another cross-sectional view of the three-dimensional FeRAM in the embodiments of this application;

[0043] Figure 9A for Figure 8 The diagram shows a top view of the storage array in a three-dimensional FeRAM.

[0044] Figure 9B for Figure 8 The diagram shows a top view of the BL and PL structures in the three-dimensional FeRAM.

[0045] Figure 10A for Figure 8 The equivalent circuit diagrams of the first and second storage structures in the three-dimensional FeRAM are shown below.

[0046] Figure 10B for Figure 8 The equivalent circuit diagram of BL, PL and reset transistor in the first and second storage structures of the three-dimensional FeRAM is shown.

[0047] Figure 11A This is yet another equivalent circuit diagram corresponding to the first and second storage structures in the three-dimensional FeRAM of this application embodiment;

[0048] Figure 11B This is another equivalent circuit diagram of BL, PL and reset transistor in the first and second storage structures of the three-dimensional FeRAM in the embodiments of this application;

[0049] Figure 12 This is another cross-sectional view of the three-dimensional FeRAM in the embodiments of this application;

[0050] Figure 13A for Figure 12 The diagram shows a top view of the storage array in a three-dimensional FeRAM.

[0051] Figure 13B for Figure 12 The diagram shows a top view of the BL and PL structures in the three-dimensional FeRAM.

[0052] Figure 14A for Figure 12 The equivalent circuit diagrams corresponding to the second and third memory structures in the three-dimensional FeRAM are shown below.

[0053] Figure 14B for Figure 12 The equivalent circuit diagrams of BL, PL and reset transistors in the second and third memory structures of the three-dimensional FeRAM are shown.

[0054] Figure label:

[0055] 1-Electronic device; 2-Semiconductor packaging structure; 3-Circuit board; 4-Housing; 10-First substrate; 11-First electrode; 12-Second electrode; 13-Ferroelectric dielectric layer; 14-Channel; 14a-First region; 14b-Second region; 14c-Third region; 15-Gate dielectric layer; 16-Groove; 17a-First sub-signal line; 17b-Second sub-signal line; 20-Memory array; 21 / 21_1 / 21_2 / 21_3 / 21_4-Memory structure; 211-Ferroelectric memory cell; 212-Overlapping region; 212a-First overlapping region; 212b-Second overlapping region; 30-Interlayer dielectric layer; 40-Control circuit board; 41-Second substrate; 42-Controller; 50-Pad; Tr-Reset transistor; Ts-Gantling transistor; F1-First direction; F2-Second direction; F3-Third direction. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0057] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0058] To facilitate understanding of the three-dimensional FeRAM, semiconductor packaging structure, and electronic device provided in the embodiments of this application, their application scenarios will be introduced first below.

[0059] The three-dimensional FeRAM provided in this application embodiment can be applied to electronic devices with storage functions. These electronic devices include, but are not limited to, terminal devices, communication devices, and electronic components. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless networks, fixed networks, servers, and smart broadband. Electronic components include, but are not limited to, memory, processing chips (e.g., central processing unit (CPU), graphics processing unit (GPU), artificial intelligence (AI) processors, digital signal processors (DSPs), and neural network processors), system-on-chips (SoCs), etc., which are not listed here.

[0060] The three-dimensional ferroelectric memory, semiconductor packaging structure, and electronic device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0061] Figure 1 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. (Refer to...) Figure 1 The electronic device 1 may include a semiconductor package structure 2 and a circuit board 3, which are electrically connected. For example, the semiconductor package structure 2 may be fixed to the circuit board 3 using bonding or other connection methods to achieve an electrical connection between them, thereby transmitting signals.

[0062] For example, the electronic device 1 may also include a housing 4 having an accommodating space, in which the circuit board 3 is disposed and fixed to the housing 4. Furthermore, the circuit board 3 includes, but is not limited to, a printed circuit board (PCB).

[0063] Figure 2A This is a schematic diagram of a semiconductor packaging structure according to an embodiment of this application. (Refer to...) Figure 2A The semiconductor packaging structure 2 may include a packaging substrate ( Figure 2A(Not shown) and memory, the memory being packaged on a package substrate. Exemplarily, the memory may include a controller and a memory array, the controller being electrically connected to the memory array so that the controller can access the memory array. The memory may include one or more memory arrays. Furthermore, the electronic device may also include a processor, a cache, etc., wherein the memory may be integrated into the processor or independently disposed on a circuit board. Exemplarily, the processor may be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor, or a neural network processor, etc. The circuit board includes, but is not limited to, a printed circuit board (PCB).

[0064] FeRAM is a non-volatile memory. Due to its advantages such as high-speed read / write, high-density storage, low power consumption, and radiation resistance, the aforementioned memory can be configured as FeRAM. Typically, FeRAM contains ferroelectric memory cells, and these ferroelectric memory cells contain ferroelectric capacitors, as shown in the reference... Figure 2B , Figure 2B (a) in the example shows a schematic diagram of the charge in a ferroelectric capacitor. Figure 2B (b) illustrates another schematic diagram of the charge in a ferroelectric capacitor, which may include a first electrode 11, a second electrode 12, and a ferroelectric dielectric layer 13 disposed between the first electrode 11 and the second electrode 12. The ferroelectric material in the ferroelectric dielectric layer 13 can be polarized according to the direction and magnitude of an applied electric field. After the electric field is removed, some polarization can still be maintained; this partial polarization is called residual polarization. Because residual polarization has residual polarization charge, it has a potential difference. To balance this potential difference, the first electrode 11 and the second electrode 12 can induce opposite induced charges. Since the residual polarization is not lost after the electric field is removed, the induced charges can also remain on the first electrode 11 and the second electrode 12. The ferroelectric memory can achieve non-volatile information storage by reading the induced charges.

[0065] Three-dimensional FeRAM can overcome the storage density limitations of traditional planar FeRAM, meeting the ever-increasing data storage demands. During read / write operations in 3D FeRAM, a subset of ferroelectric memory cells is selected via the WL (Wide Link) and then read / write operations are performed on these cells by switching the potentials on BL and PL. Unselected ferroelectric memory cells are subject to disturbance caused by the potential switching on BL and PL. Although the selection transistors in the unselected ferroelectric memory cells are in the off-state, off-state leakage still exists. This causes continuous leakage to the first electrode of the ferroelectric capacitor during repeated disturbances, resulting in a low-amplitude but long-lasting bias voltage on the ferroelectric capacitor. This bias voltage affects the polarization state of the ferroelectric material in the capacitor, leading to errors or corruption in the stored data and impacting the stability of the stored data.

[0066] To address the aforementioned issues, this application provides a three-dimensional FeRAM that, when applied to the memory, can improve storage density, mitigate interference caused by the switching of BL and PL potentials, and enhance the stability of data stored in the ferroelectric capacitor Cs.

[0067] Figure 3 This is a cross-sectional view of a three-dimensional FeRAM in an embodiment of this application. Figure 4A for Figure 3 The diagram shows a top view of the storage array in a three-dimensional FeRAM. Figure 4B for Figure 3 The diagram shows a top view of the BL and PL structures in a three-dimensional FeRAM. Figure 4C This is a partial three-dimensional structural diagram of the storage array in the three-dimensional FeRAM according to an embodiment of this application. Figure 5A for Figure 3 The equivalent circuit diagrams corresponding to the three storage structures arranged along the third direction in the three-dimensional FeRAM are shown below. Figure 5B for Figure 3 The diagram shows the equivalent circuit diagram of BL, PL, and the reset transistor in a storage structure of a three-dimensional FeRAM. (Refer to...) Figures 3 to 5BThe three-dimensional FeRAM in this embodiment may include: a first substrate 10, a memory array 20, and a reset transistor Tr. The memory array 20 is located on the first substrate 10, and the reset transistor Tr is located on the side of the memory array 20 facing away from the first substrate 10. The memory array 20 may include multiple memory structures 21. Each memory structure 21 includes multiple ferroelectric memory cells 211, BL, PL, and multiple WL. The multiple ferroelectric memory cells 211 are stacked on a first direction F1, and the first direction F1 is perpendicular to the first substrate 10, so that the multiple ferroelectric memory cells 211 can be stacked on the first substrate 10, thereby increasing the storage capacity and storage density.

[0068] Furthermore, each ferroelectric memory cell 211 may include a selection transistor Ts and a ferroelectric capacitor Cs, with the first electrode of the selection transistor Ts and the first electrode 11 of the ferroelectric capacitor Cs connected. Additionally, BL and PL extend along a first direction F1, with BL connecting to the second electrode of the selection transistor Ts in the plurality of ferroelectric memory cells 211, and PL connecting to the second electrode 12 of the ferroelectric capacitor Cs in the plurality of ferroelectric memory cells 211. Moreover, the plurality of WLs extend along a second direction F2, with the gate of the selection transistor Ts in any ferroelectric memory cell 211 connected to one WL. This configuration allows the gates of the selection transistors Ts in the same memory structure 21 to be connected to different WLs, enabling independent control of the on / off state of the selection transistors Ts in the same memory structure 21.

[0069] Furthermore, the reset transistor Tr is connected between BL and PL in the storage structure 21. This configuration allows for the connection and disconnection of BL and PL by controlling the on and off states of the reset transistor Tr. This enables a ladder-like architecture between the ferroelectric storage cell and the reset transistor in any storage structure 21. When the reset transistor Tr is off, the signal transmitted through WL controls the conduction of the selection transistor Ts. Combined with the potential switching on BL and PL, read and write operations can be performed on the ferroelectric storage cell 211. When the reset transistor Tr is on, BL and PL are connected, and the selection transistor Ts is turned on by WL, causing the first electrode 11 and the second electrode 12 of the ferroelectric capacitor Cs to be short-circuited. This releases the charge flowing into the first electrode 11 of the ferroelectric capacitor Cs due to interference from the potential switching of BL and PL, effectively reducing the duration of the bias voltage, minimizing the adverse effects on the polarization state of the ferroelectric material, and improving the stability of the data stored in the ferroelectric capacitor Cs.

[0070] The following is combined Figure 6 The working process of the three-dimensional FeRAM in the embodiments of this application is described in detail. Taking the equivalent circuit of a ferroelectric memory cell and a reset transistor in a memory structure as an example, refer to... Figure 6 (a) in the middle, Figure 6 (a) illustrates an equivalent circuit diagram of a ferroelectric memory cell and a reset transistor in a memory structure during read / write operations. In the read / write state (also known as the Active state), the reset transistor Tr is off, the potential on the selected WL is high, and the gate transistor Ts connected to the WL is on. For example, to write a "0" to the ferroelectric capacitor Cs, the potential on PL is high (e.g., 1V) and the potential on BL is low (e.g., 0V), so a "0" can be written to the ferroelectric capacitor Cs. Similarly, to write a "1" to the ferroelectric capacitor Cs, the potential on PL is high (e.g., 1V) and the potential on BL is low (e.g., 0V), so a "0" can be written to the ferroelectric capacitor Cs first. Then, the potential on PL is low and the potential on BL is high, so a "1" can be written to the ferroelectric capacitor Cs.

[0071] Reference Figure 6 (b) in the middle Figure 6 (b) illustrates a schematic diagram of the equivalent circuit of a ferroelectric memory cell and a reset transistor in a memory structure when in a non-read / write state. In the non-read / write state (also known as the Idle state), the reset transistor Tr is turned on, and the selection transistor Ts of each WL control connection is turned on, so that the first electrode 11 and the second electrode 12 of each ferroelectric capacitor Cs are short-circuited. Based on this, the three-dimensional FeRAM in this embodiment can alternate between read / write and non-read / write states. In the read / write state, the unselected ferroelectric memory cell 211 is subjected to interference caused by the switching of BL and PL potentials. Then, in the non-read / write state, since the first electrode 11 and the second electrode 12 of the ferroelectric capacitor Cs are short-circuited, the charge flowing into the first electrode 11 of the ferroelectric capacitor Cs caused by the switching of BL and PL potentials can be released, which can effectively reduce the duration of the bias voltage, thereby reducing the adverse effects on the polarization state of the ferroelectric material and improving the stability of the data stored in the ferroelectric capacitor Cs.

[0072] Understandably, Figure 6 The "√" shown indicates that the gating transistor Ts and the reset transistor Tr are in the on state, and the "×" indicates that the gating transistor Ts and the reset transistor Tr are in the off state.

[0073] For example, refer to Figures 3 to 4C The first direction F1 is perpendicular to the first substrate 10, the second direction F2 is perpendicular to the first direction F1, and the third direction F3 is perpendicular to the first direction F1 and the second direction F2, respectively.

[0074] In one embodiment of this application, reference is made to... Figures 3 to 4CIn any storage structure 21, BL and PL are arranged along the third direction F3, which can reduce wiring complexity, make more efficient use of space, facilitate three-dimensional stacking design, and further improve the integration density of storage array 20.

[0075] In one embodiment of this application, reference is made to... Figures 3 to 4C In any memory structure 21, the selection transistor Ts and the ferroelectric capacitor Cs are arranged along the third direction F3 and placed between BL and PL, which can optimize the space utilization of the memory array 20 and reduce the design complexity.

[0076] For example, refer to Figure 3 An interlayer dielectric layer 30 is provided between the stacked gate transistors Ts and the first electrode 11 of the ferroelectric capacitor Cs along the first direction F1, so as to independently set the stacked gate transistors Ts and the first electrode 11 of the ferroelectric capacitor Cs.

[0077] For example, refer to Figures 3 to 4C In any memory structure 21, on the third direction F3, a selection transistor Ts is disposed between BL and the ferroelectric capacitor Cs. For example, the channel 14 of the selection transistor Ts may include a first region 14a, a second region 14b, and a third region 14c, with the third region 14c located between the first region 14a and the second region 14b. The first region 14a of the channel 14 of the selection transistor Ts is connected to BL and can serve as the first electrode of the selection transistor Ts, thus achieving electrical connection between the selection transistor Ts and BL. Furthermore, the second region 14b is connected to the first electrode 11 and can serve as the second electrode of the selection transistor Ts, thus achieving electrical connection between the selection transistor Ts and the first electrode 11 of the ferroelectric capacitor Cs. Therefore, the first region 14a and the second region 14b of the channel 14 can be disposed on opposite sides of the channel 14, ensuring that the first region 14a and the second region 14b do not contact each other, and fully utilizing each region of the channel 14. Furthermore, the gating transistor Ts and the ferroelectric capacitor Cs can be arranged closely on the third direction F3, which can compress the size of the ferroelectric memory cell 211 on the third direction F3 and further improve the storage density.

[0078] For example, the first region 14a, the third region 14c, and the second region 14b can be arranged along the third direction F3, so that the channel 14 of the gate transistor Ts extends along the third direction F3, which can further reduce the design complexity of the gate transistor Ts. Thus, the first region 14a and the second region 14b of the channel 14 can be respectively located on both sides of the channel 14 in the third direction F3.

[0079] It is understood that the gate transistor Ts can be one or more of various types of switching devices, such as a metal oxide semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and a silicon carbide (SiC) MOSFET. These will not be listed individually in this embodiment. Furthermore, each switching device can include a first terminal, a second terminal, and a gate, wherein the gate is used to control the closing or opening of the switching device. When the switching device is closed, current can be transferred between the first and second terminals. When the switching device is open, no current can be transferred between the first and second terminals. Taking a MOSFET as an example, the first terminal of the switching device can be the source, and the second terminal can be the drain, or vice versa.

[0080] For example, refer to Figures 3 to 4C The WL and the third region 14c of the channel 14 have an overlapping region 212 in the first direction F1, and the WL in the overlapping region 212 serves as the gate of the gate transistor Ts. Therefore, using a portion of the WL as the gate of the gate transistor Ts reduces manufacturing steps and material usage, lowering complexity and cost. Furthermore, to achieve insulation between the gate of the gate transistor Ts and its channel 14, a gate dielectric layer 15 is also provided between the WL and the channel 14 of the gate transistor Ts.

[0081] In one embodiment of this application, the gate of the gate transistor Ts can be configured as a dual-gate structure, which can enhance channel control and improve device performance. For example, refer to... Figures 3 to 4CThe memory array (WL) can include a first sub-signal line 17a and a second sub-signal line 17b, which are electrically connected to form a whole. The first sub-signal line 17a and the second sub-signal line 17b are located on opposite sides of the channel 14 in the first direction F1. The first sub-signal line 17a and the third region 14c of the channel 14 have a first overlapping region 212a in the first direction F1, and the second sub-signal line 17b and the third region 14c of the channel 14 have a second overlapping region 212b in the first direction F1. The first sub-signal line 17a in the first overlapping region 212a and the second sub-signal line 17b in the second overlapping region 212b serve as the gate of the selection transistor Ts. This configuration, with the first sub-signal line 17a and the second sub-signal line 17b located on opposite sides of the channel in the first direction F1, not only forms a dual-gate structure, enhancing channel control and improving device performance, but also optimizes the layout and increases the storage density of the memory array 20. In other embodiments of this application, the gate of the gate transistor Ts can also be a single-gate structure (i.e., one of the first sub-signal line 17a and the second sub-signal line 17b can be used as WL), a three-gate structure (i.e., WL is partially arranged around the channel), or a gate all around (GAA) structure (i.e., WL is arranged around the channel). This application does not limit this.

[0082] For example, refer to Figures 3 to 4C Within the same storage space (WL), the first sub-signal line 17a and the second sub-signal line 17b have overlapping areas in the first direction F1. For example, in the same WL, the first sub-signal line 17a and the second sub-signal line 17b coincide in the first direction F1, which can optimize the layout and improve the storage density of the storage array 20. For example, for multiple first sub-signal lines 17a and multiple second sub-signal lines 17b arranged along the first direction F1, the multiple first sub-signal lines 17a and multiple second sub-signal lines 17b coincide in the first direction F1, which can further optimize the layout and further improve the storage density of the storage array 20.

[0083] In one embodiment of this application, reference is made to... Figure 3 , Figure 4A and Figure 4CTo increase the capacitance of the ferroelectric capacitor Cs, on the third direction F3, the first electrode 11 may have a groove 16 extending along the third direction F3, the opening of which faces PL. The second electrode 12 may be filled in the groove 16, and a ferroelectric dielectric layer 13 is provided between the first electrode 11 and the second electrode 12. Exemplarily, the ferroelectric material of the ferroelectric dielectric layer 13 is a hafnium-based ferroelectric material, which can further compress the size of the ferroelectric memory cell 211 and increase the storage density of the memory array 20. In other embodiments of this application, the ferroelectric material of the ferroelectric dielectric layer 13 may also be other ferroelectric materials, and this application does not limit this to any particular material.

[0084] For example, refer to Figure 3 , Figure 4A and Figure 4C The PL and the second electrode 12 are integrated into one structure, which allows for direct electrical connection between the PL and the second electrode 12, shortening the signal transmission path and reducing latency. Furthermore, during the fabrication process, the PL can be inserted into the groove 16, with the portion of the PL inserted into the groove 16 serving as the second electrode 12 of the ferroelectric capacitor Cs, simplifying the manufacturing process and reducing costs.

[0085] In one embodiment of this application, reference is made to... Figure 4A and Figure 4C The storage array 20 may include at least two storage structures 21 arranged along the second direction F2, which can further improve storage capacity and storage density. Furthermore, in the at least two storage structures 21 arranged along the second direction F2, the gate transistors Ts in the ferroelectric storage cells 211 arranged along the second direction F2 are connected to the same WL, allowing multiple ferroelectric storage cells 211 to share a single WL, enabling larger-scale integration of ferroelectric storage cells 211 without significantly increasing wiring complexity.

[0086] For example, refer to Figure 4A and Figure 4C In at least two storage structures 21 arranged along the second direction F2, the BL and PL in any adjacent storage structures 21 are independent of each other. That is, the BL in the storage structures 21 arranged along the second direction F2 are not electrically connected and do not share a common interface, and the PL in the storage structures 21 arranged along the second direction F2 are also not electrically connected and do not share a common interface. This configuration can reduce crosstalk and improve the flexibility of read and write operations, enhance the performance and reliability of 3D FeRAM, and support high-density storage and high-frequency operation of 3D FeRAM.

[0087] For example, refer to Figure 4A and Figure 4CIn the memory structure 21 arranged along the second direction F2, an interlayer dielectric layer 30 is also provided between BL in any adjacent memory structure 21, an interlayer dielectric layer 30 is also provided between PL in any adjacent memory structure 21, an interlayer dielectric layer 30 is also provided between the channels 14 of the gate transistors Ts in any adjacent memory structure 21, and an interlayer dielectric layer 30 is also provided between the first electrodes 11 of the ferroelectric capacitors Cs in any adjacent memory structure 21.

[0088] For example, refer to Figure 4A and Figure 4C In the storage structure 21 arranged along the second direction F2, BL is arranged sequentially along the second direction F2, and PL is also arranged sequentially along the second direction F2, which can effectively utilize the space of the storage array 20 and reduce wiring complexity.

[0089] Understandably, in order to clearly illustrate the storage structure 21 arranged along the second direction F2 in the embodiments of this application, Figure 4A and Figure 4C The illustration takes three storage structures 21 arranged along the second direction F2 as an example. In other embodiments of this application, the storage structures 21 arranged along the second direction F2 can also be two, four, five, or more, and this application does not limit this. Figure 3 The location of the reset transistor Tr is only shown, but its structure is not shown in detail.

[0090] In one embodiment of this application, reference is made to... Figure 3 and Figure 4A The storage array 20 may include at least two storage structures 21 arranged along the third direction F3, which can further improve storage capacity and storage density. Furthermore, in the storage structures 21 arranged along the third direction F3, the BL and PL in any two storage structures 21 are independent of each other; that is, the BL and PL in the storage structures 21 arranged along the third direction F3 are not shared. This configuration can further reduce crosstalk and improve the flexibility of read and write operations, further enhance the performance and reliability of the 3D FeRAM, and further support the high-density storage and high-frequency operation of the 3D FeRAM.

[0091] Furthermore, referring to Figure 3 , Figure 4A and Figure 5B In the memory structures 21 arranged along the third direction F3, each memory structure 21 is provided with a reset transistor Tr. Therefore, the equivalent circuit of any memory structure 21 can be considered as an independent ladder architecture, allowing each memory structure 21 to independently perform non-read / write operations, improving control flexibility and reliability.

[0092] For example, the first terminal of the reset transistor Tr is connected to BL, the second terminal is connected to PL, and the gate is connected to the reset line (RL) so that the signal transmitted through RL controls the turn-on and turn-off of the reset transistor Tr. Furthermore, the first terminal of the reset transistor Tr can be its source and the second terminal its drain, or vice versa; this application does not limit this.

[0093] It is understood that any memory structure 21 may also be provided with two, three or more reset transistors Tr, and the gates of the multiple reset transistors Tr can be connected to each other to be equivalent to a single reset transistor Tr structure. This application does not limit this.

[0094] In one embodiment of this application, reference is made to... Figure 3 and Figure 4A In the memory structures 21 arranged along the third direction F3, the PL in two adjacent memory structures 21 is located between the ferroelectric capacitors Cs in the two adjacent memory structures 21. This allows for more efficient use of the space in the memory array 20, increasing its integration density. For example, taking adjacent memory structures 21_1, 21_2, and 21_3 arranged along the third direction F3, the PL in memory structures 21_1 and 21_2 is located between the ferroelectric capacitors Cs in memory structures 21_1 and 21_2.

[0095] For example, refer to Figure 3 and Figure 4A The PLs located between the ferroelectric capacitors Cs of two adjacent memory structures 21 are symmetrically arranged. For example, the PLs in memory structures 21_1 and 21_2 are symmetrically arranged. This simplifies the layout design rules and reduces design complexity. Furthermore, during the fabrication process, the original single PL can be etched into two independent PLs, further reducing the fabrication process complexity and increasing the memory cell density.

[0096] In one embodiment of this application, reference is made to... Figure 3 and Figure 4A In the memory structures 21 arranged along the third direction F3, the BL in two adjacent memory structures 21 is located between the gate transistors Ts of the two adjacent memory structures 21. This allows for more efficient use of the space in the memory array 20, increasing its integration density. For example, taking adjacent memory structures 21_1, 21_2, and 21_3 arranged along the third direction F3, the BL in memory structures 21_2 and 21_3 is located between the gate transistors Ts in memory structures 21_2 and 21_3.

[0097] For example, refer to Figure 3 and Figure 4A The BLs are symmetrically arranged between the gate transistors Ts of two adjacent memory structures 21. For example, the BLs in memory structures 21_2 and 21_3 are symmetrically arranged. This simplifies the layout design rules and reduces design complexity. Furthermore, during the fabrication process, the original single BL can be etched into two independent BLs, further reducing fabrication complexity and increasing memory cell density.

[0098] For example, refer to Figure 3 and Figure 4A An interlayer dielectric layer 30 is also provided between the PL between the ferroelectric capacitors Cs of two adjacent memory structures 21, and an interlayer dielectric layer 30 is also provided between the BL between the gate transistors Ts of two adjacent memory structures 21.

[0099] Understandably, in order to clearly illustrate the storage structure 21 arranged along the second direction F2 in the embodiments of this application, Figure 3 and Figure 4A The illustration takes three storage structures 21 arranged along the third direction F3 as an example. In other embodiments of this application, the storage structures 21 arranged along the third direction F3 can also be two, four, five or more, and this application does not limit this.

[0100] In some embodiments, during the fabrication process, the gate transistors Ts and ferroelectric capacitors Cs in the multiple ferroelectric memory cells 211 stacked along the first direction F1 can share process steps such as photolithography, etching, and deposition to achieve a stacked structure. This makes the process of fabricating the memory array in this embodiment highly compatible with the process of fabricating existing three-dimensional dynamic random access memory (DRAM). As a result, existing equipment and processes for fabricating three-dimensional DRAM can be directly utilized, reducing the investment in new equipment and the time and cost of process development.

[0101] Furthermore, during the fabrication process, the memory array 20 can be formed using a SiGe / Si stacked structure (in the SiGe / Si stacked structure, SiGe is the sacrificial layer, and Si is the channel for the gate transistors). Alternatively, the memory array 20 can also employ other stacked structures with etching selectivity, such as using SiN as the sacrificial layer. The channel material is introduced during the process, and the channel material can be an oxide semiconductor material (e.g., IGZO) or polysilicon. However, regardless of the stacked structure used to fabricate the memory array 20, the actual process involves high-temperature steps, which are incompatible with the preceding processes. Therefore, in one embodiment of this application, referring to... Figure 7A , Figure 7AThis is a schematic diagram of a three-dimensional FeRAM structure in an embodiment of this application. A reset transistor Tr is formed on the memory array 20. Exemplarily, the reset transistor can be fabricated on the memory array using back-end processes, including but not limited to processes for forming oxide semiconductor transistors (e.g., IGZO transistors). Based on this, the three-dimensional FeRAM also includes a control circuit board 40, which may include a second substrate 41 and a controller 42 located on the second substrate 41. The controller 42 is connected to the gates of BL, PL, WL and the reset transistor Tr via pads 50, so that the controller 42 can control the memory array to be in a read / write state and a non-read / write state through BL, PL, WL and the reset transistor Tr.

[0102] In yet another embodiment of this application, reference is made to... Figure 7B , Figure 7B This is another schematic diagram of the three-dimensional FeRAM structure in this application embodiment. The reset transistor Tr can be formed on the control circuit board 40 using a front-end process. Based on this, the controller 42 is directly connected to the reset transistor Tr, that is, the controller 42 is also directly connected to the gate, first terminal, and second terminal of the reset transistor Tr, respectively. Furthermore, the controller 42 and the reset transistor Tr are connected to BL and PL respectively via pads 50, and the controller is also connected to WL via pads 50.

[0103] For example, the control circuit board 40 can be connected to the first substrate on which the memory array is formed using a bonding process such as hybrid bonding (HB). Furthermore, the first and second substrates include, but are not limited to, silicon substrates (e.g., substrates made from silicon wafers).

[0104] For example, the controller 42 can be formed on the second substrate using CMOS technology, and the control circuit board can be connected to the first substrate on which the memory array is formed by bonding technology, which can avoid the problem of incompatibility between CMOS technology and the process of forming memory array.

[0105] Figure 8 This is another cross-sectional view of the three-dimensional FeRAM in the embodiments of this application. Figure 9A for Figure 8 The diagram shows a top view of the storage array in a three-dimensional FeRAM. Figure 9B for Figure 8 The diagram shows a top view of the BL and PL structures in a three-dimensional FeRAM. Figure 10A for Figure 8 The equivalent circuit diagrams corresponding to the first and second storage structures in the three-dimensional FeRAM are shown below. Figure 10B for Figure 8The equivalent circuit diagrams of BL, PL, and the reset transistor in the first and second storage structures of the three-dimensional FeRAM are shown below, with reference to... Figures 8 to 10B This embodiment is for Figure 3 The embodiments shown have been modified. The following description only illustrates this embodiment and... Figure 3 The differences between the embodiments shown are not detailed here, but their similarities are not repeated.

[0106] In one embodiment of this application, in at least a portion of the storage structure 21 arranged along the third direction F3, BLs can be interconnected, and PLs are also interconnected. Therefore, this at least a portion of the storage structure 21 can be equivalent to a ladder architecture, which can more efficiently utilize the space of the storage array 20 and increase the integration density of the storage array 20. For example, referring to… Figure 8 , Figure 10A and Figure 10B Taking storage structures 21_1, 21_2, 21_3, and 21_4 arranged along the third direction F3, and each of storage structures 21_1 to 21_4 including N ferroelectric storage cells 211 as an example, if BL and PL in storage structures 21_1 and 21_2 are interconnected, then storage structures 21_1 and 21_2 can be equivalent to a ladder architecture with 2N ferroelectric storage cells 211. Similarly, if BL and PL in storage structures 21_3 and 21_4 are interconnected, then storage structures 21_3 and 21_4 can be equivalent to a ladder architecture with 2N ferroelectric storage cells 211.

[0107] For example, each memory structure 21 may be provided with a corresponding reset transistor Tr, and the gates of the reset transistors Tr provided with at least some of the memory structures 21 are interconnected. Thus, the plurality of reset transistors Tr provided with at least some of the memory structures 21 can be considered as a whole, so that when some of the reset transistors Tr fail, the other reset transistors Tr can still be controlled to operate, thereby realizing the operation process in non-read / write and read / write states. For example, referring to... Figure 8 , Figure 10A and Figure 10BEach of the memory structures 21_1, 21_2, 21_3, and 21_4 is equipped with a corresponding reset transistor Tr. The gates of the reset transistors Tr in memory structures 21_1 and 21_2 are interconnected, allowing them to be simultaneously turned on and off, thus making them equivalent to a single unit. Similarly, the gates of the reset transistors Tr in memory structures 21_3 and 21_4 are interconnected, allowing them to be simultaneously turned on and off, again making them equivalent to a single unit.

[0108] For example, the gates of the reset transistors Tr corresponding to at least a portion of the aforementioned storage structure 21 can be connected to the same RL, so that the gates of these reset transistors Tr can be connected via a single RL. For example, refer to... Figure 8 , Figure 10A and Figure 10B The gates of the reset transistors Tr set in storage structures 21_1 and 21_2 are connected to one RL, and the gates of the reset transistors Tr set in storage structures 21_3 and 21_4 are connected to another RL.

[0109] It is understood that any memory structure 21 may also be provided with two, three or more reset transistors Tr, and the gates of the multiple reset transistors Tr can be connected to each other to be equivalent to a single reset transistor Tr structure. This application does not limit this.

[0110] In other embodiments of this application, at least some of the storage structures 21 described above may also share a single reset transistor Tr, which can reduce the number of reset transistors Tr and reduce design complexity. For example, refer to... Figure 11A and Figure 11B , Figure 11A This is yet another equivalent circuit diagram corresponding to the first and second storage structures in the three-dimensional FeRAM of this application. Figure 11B This is another equivalent circuit diagram of BL, PL and reset transistor in the first and second storage structures of the three-dimensional FeRAM in the embodiments of this application. Storage structures 21_1 and 21_2 share a reset transistor Tr, and storage structures 21_3 and 21_4 share another reset transistor Tr.

[0111] In one embodiment of this application, reference is made to... Figures 8 to 9BThe memory structure 21 arranged along the third direction F3 may include adjacent first, second, and third memory structures. PL in the first memory structure and PL in the second memory structure are located between the ferroelectric capacitors Cs in the first and second memory structures. BL in the second and third memory structures are located between the gate transistors Ts in the second and third memory structures. Therefore, the space of the memory array 20 can be utilized more efficiently, increasing the integration density of the memory array 20.

[0112] For example, the PL in the first storage structure and the PL in the second storage structure are shared. This not only makes the PL in the first storage structure and the PL in the second storage structure equivalent to being interconnected, but also optimizes the layout of the storage array 20, increases integration density, reduces wiring complexity, and lowers design difficulty. Furthermore, the BL in the first storage structure and the BL in the second storage structure are interconnected, while the BL in the second storage structure and the BL and PL in the third storage structure are independent of each other. This configuration allows the first and second storage structures to be equivalent to a ladder architecture, and the third storage structure to be equivalent to a ladder architecture with other storage structures 21. This allows for more efficient use of the space in the storage array 20 and increases the integration density of the storage array 20.

[0113] For example, refer to Figures 8 to 10B Storage structure 21_1 serves as the first storage structure, and storage structure 21_2 serves as the second storage structure. The PL in storage structure 21_1 and storage structure 21_2 is located between the ferroelectric capacitors Cs in storage structure 21_1 and storage structure 21_2, and storage structure 21_1 and storage structure 21_2 share the PL. The BL of storage structure 21_1 and storage structure 21_2 can be connected through the wiring layer at the top of storage array 20 (i.e., the wiring layer between the layer where the reset transistor Tr is located and the layer where the storage array 20 is located), so that storage structure 21_1 and storage structure 21_2 are equivalent to a ladder architecture. Similarly, storage structure 21_3 can also be used as the first storage structure, and storage structure 21_4 can also be used as the second storage structure. The PL in storage structure 21_3 and storage structure 21_4 is located between the ferroelectric capacitors Cs in storage structure 21_3 and storage structure 21_4, and storage structure 21_3 and storage structure 21_4 share the PL. The BL of storage structure 21_3 and storage structure 21_4 can be connected through the wiring layer at the top of storage array 20 (i.e., the wiring layer between the layer where the reset transistor Tr is located and the layer where the storage array 20 is located), so that storage structure 21_3 and storage structure 21_4 can also be equivalent to a ladder architecture.

[0114] For example, refer to Figures 8 to 9BStorage structure 21_2 serves as the second storage structure, and storage structure 21_3 serves as the third storage structure. The BL in storage structure 21_2 and storage structure 21_3 is located between the gate transistors Ts in storage structure 21_2 and storage structure 21_3. Furthermore, the BL in storage structure 21_2 and storage structure 21_3 are independent of each other, and the PL in storage structure 21_2 and storage structure 21_3 are also independent of each other.

[0115] It is understood that the storage structure 21 arranged along the third direction F3 can be repeatedly arranged based on the structure of storage structures 21_1 to 21_3, and its specific structure will not be described in detail here. Furthermore, to clearly illustrate the storage structure 21 arranged along the third direction F3 in this embodiment, Figures 8 to 10B Taking two adjacent storage structures 21 arranged along the third direction F3 as an example of equivalent ladder architecture, in other embodiments of this application, three, four or more adjacent storage structures 21 arranged along the third direction F3 can also be taken as an example of equivalent ladder architecture, and no specific limitation is made here.

[0116] Furthermore, the implementation methods of the reset transistor Tr and the control circuit board in this embodiment can be referred to... Figure 7A and Figure 7B The implementation methods shown are not described in detail here.

[0117] Figure 12 This is another cross-sectional view of the three-dimensional FeRAM in the embodiments of this application. Figure 13A for Figure 12 The diagram shows a top view of the storage array in a three-dimensional FeRAM. Figure 13B for Figure 12 The diagram shows a top view of the BL and PL structures in a three-dimensional FeRAM. Figure 14A for Figure 12 The equivalent circuit diagrams corresponding to the second and third storage structures in the three-dimensional FeRAM are shown below. Figure 14B for Figure 12 The equivalent circuit diagrams of BL, PL, and the reset transistor in the second and third memory structures of the 3D FeRAM are shown below, with reference to... Figures 12 to 14B This embodiment is for Figure 8 The embodiments shown have been modified. The following description only illustrates this embodiment and... Figure 8 The differences between the embodiments shown are not detailed here, but their similarities are not repeated.

[0118] In another embodiment of this application, the BL in the second storage structure and the BL in the third storage structure can be shared. This not only makes the PL in the second storage structure and the PL in the third storage structure equivalent to being interconnected, but also optimizes the layout of the storage array 20, increases integration density, reduces wiring complexity, and lowers design difficulty. Furthermore, the PL in the second storage structure and the PL in the third storage structure are interconnected, while the PL in the first storage structure and the PL in the second storage structure are independent of each other. This configuration allows the second and third storage structures to be equivalent to a ladder architecture, and the first storage structure and other storage structures 21 to be equivalent to a ladder architecture, enabling more efficient use of the space in the storage array 20 and increasing the integration density of the storage array 20.

[0119] For example, refer to Figures 12 to 14B Storage structure 21_2 serves as the second storage structure, and storage structure 21_3 serves as the third storage structure. The BL in storage structure 21_2 and storage structure 21_3 is located between the gate transistors Ts in storage structure 21_2 and storage structure 21_3, and storage structure 21_2 and storage structure 21_3 share the BL. The PL of storage structure 21_2 and storage structure 21_3 can be connected through the wiring layer at the top of storage array 20 (i.e., the wiring layer between the layer where the reset transistor Tr is located and the layer where storage array 20 is located), so that storage structure 21_2 and storage structure 21_3 are equivalent to a ladder architecture.

[0120] For example, refer to Figures 12 to 14B Storage structure 21_1 serves as the first storage structure, and storage structure 21_2 serves as the second storage structure. The PL in storage structure 21_1 and storage structure 21_2 is located between the ferroelectric capacitors Cs in storage structure 21_1 and storage structure 21_2, and the PL in storage structure 21_1 and storage structure 21_2 are independent of each other, as are the BL in storage structure 21_1 and storage structure 21_2.

[0121] It is understood that the storage structure 21 arranged along the third direction F3 can be repeatedly arranged based on the structure of storage structures 21_1 to 21_3, and its specific structure will not be described in detail here. Furthermore, to clearly illustrate the storage structure 21 arranged along the third direction F3 in this embodiment, Figures 12 to 14B Taking two adjacent storage structures 21 arranged along the third direction F3 as an example of equivalent ladder architecture, in other embodiments of this application, three, four or more adjacent storage structures 21 arranged along the third direction F3 can also be taken as an example of equivalent ladder architecture, and no specific limitation is made here.

[0122] Furthermore, the implementation methods of the reset transistor Tr and the control circuit board in this embodiment can be referred to... Figure 7A and Figure 7B The implementation methods shown are not described in detail here.

[0123] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A three-dimensional ferroelectric memory, characterized in that, include: First substrate; A memory array, located on a first substrate, includes multiple memory structures. Each memory structure includes multiple ferroelectric memory cells, bit lines, plate lines, and multiple word lines. The multiple ferroelectric memory cells are stacked in a first direction. Each ferroelectric memory cell includes a gate transistor and a ferroelectric capacitor. The first electrode of the gate transistor and the first electrode of the ferroelectric capacitor are connected. The bit lines and the plate lines extend along the first direction. The bit lines are connected to the second electrodes of the gate transistors in the multiple ferroelectric memory cells, and the plate lines are connected to the second electrodes of the ferroelectric capacitors in the multiple ferroelectric memory cells. The multiple word lines extend along a second direction, and the gate of the gate transistor in any ferroelectric memory cell is connected to one word line. A reset transistor is located on the side of the memory array facing away from the first substrate, and the reset transistor is connected between the bit line and the plate line in the memory structure; The first direction is perpendicular to the first substrate, and the second direction is perpendicular to the first direction.

2. The three-dimensional ferroelectric memory according to claim 1, characterized in that, The plurality of storage structures includes at least two storage structures arranged along the second direction; In the at least two memory structures, the gate transistors in the ferroelectric memory cells arranged along the second direction are connected to the same word line, and the bit lines and board lines in any adjacent memory structures are independent of each other.

3. The three-dimensional ferroelectric memory according to claim 1 or 2, characterized in that, The plurality of storage structures includes at least two storage structures arranged along a third direction, the third direction being perpendicular to the first direction and the second direction, respectively; In the memory structures arranged along the third direction, the bit lines and board lines in any two memory structures are independent of each other, and each memory structure is provided with a reset transistor.

4. The three-dimensional ferroelectric memory according to claim 3, characterized in that, In the storage structure arranged along the third direction, the plate lines in two adjacent storage structures are located between the ferroelectric capacitors in the two adjacent storage structures.

5. The three-dimensional ferroelectric memory according to claim 4, characterized in that, The plate lines located between the ferroelectric capacitors of the two adjacent storage structures are symmetrically arranged.

6. The three-dimensional ferroelectric memory according to any one of claims 3-5, characterized in that, In the memory structures arranged along the third direction, the bit lines in two adjacent memory structures are located between the gate transistors of the two adjacent memory structures.

7. The three-dimensional ferroelectric memory according to claim 6, characterized in that, The bit lines located between the gating transistors of the two adjacent memory structures are symmetrically arranged.

8. The three-dimensional ferroelectric memory according to claim 1 or 2, characterized in that, The plurality of storage structures includes at least two storage structures arranged along a third direction, the third direction being perpendicular to the first direction and the second direction, respectively; In at least a portion of the storage structure arranged along the third direction, the bit lines and the board lines are interconnected.

9. The three-dimensional ferroelectric memory according to claim 8, characterized in that, Each of the aforementioned memory structures is provided with a corresponding reset transistor, and the gates of the reset transistors provided with corresponding to at least some of the memory structures are interconnected. Alternatively, at least some of the memory structures may share a single reset transistor.

10. The three-dimensional ferroelectric memory according to claim 8 or 9, characterized in that, The memory structure arranged along the third direction includes an adjacent first memory structure, a second memory structure, and a third memory structure. The board lines in the first memory structure and the board lines in the second memory structure are located between the ferroelectric capacitors in the first memory structure and the ferroelectric capacitors in the second memory structure. The bit lines in the second memory structure and the bit lines in the third memory structure are located between the gate transistors in the second memory structure and the gate transistors in the third memory structure.

11. The three-dimensional ferroelectric memory according to claim 10, characterized in that, The board lines in the first storage structure and the board lines in the second storage structure are shared. The bit lines in the first storage structure and the bit lines in the second storage structure are interconnected. The bit lines in the second storage structure and the bit lines and board lines in the third storage structure are independent of each other.

12. The three-dimensional ferroelectric memory according to claim 10, characterized in that, The bit lines in the second storage structure are shared with the bit lines in the third storage structure. The board lines in the second storage structure and the board lines in the third storage structure are interconnected. The board lines in the first storage structure and the board lines and bit lines in the second storage structure are independent of each other.

13. The three-dimensional ferroelectric memory according to any one of claims 1-12, characterized in that, It also includes a control circuit board, which includes a second substrate and a controller located on the second substrate; The controller is connected to the bit lines, board lines, word lines, and the gate of the reset transistor via pads; or, The controller is connected to the gate of the reset transistor. The controller and the reset transistor are connected to the bit line and the board line respectively via pads. The controller is also connected to the word line via pads.

14. The three-dimensional ferroelectric memory according to any one of claims 1-13, characterized in that, In any of the aforementioned memory structures, the bit lines and the board lines are arranged along a third direction, and / or the gating transistor and the ferroelectric capacitor are arranged along a third direction and disposed between the bit lines and the board lines; The third direction is perpendicular to both the first direction and the second direction.

15. The three-dimensional ferroelectric memory according to any one of claims 1-14, characterized in that, The first region of the channel of the gate transistor is connected to the bit line, the second region of the channel is connected to the first electrode, the word line and the third region of the channel have an overlapping region in the first direction, and the word line in the overlapping region serves as the gate. The third region is located between the first region and the second region.

16. The three-dimensional ferroelectric memory according to claim 15, characterized in that, The word line includes a first sub-signal line and a second sub-signal line, which are respectively located on both sides of the channel in the first direction. The first sub-signal line and the third region of the channel have a first overlapping region in the first direction, and the second sub-signal line and the third region of the channel have a second overlapping region in the first direction. The first sub-signal line in the first overlapping region and the second sub-signal line in the second overlapping region serve as the gate.

17. A semiconductor packaging structure, characterized in that, It includes a packaging substrate and a three-dimensional ferroelectric memory as described in any one of claims 1-16, wherein the three-dimensional ferroelectric memory is packaged on the packaging substrate.

18. An electronic device, characterized in that, include: The circuit board and the semiconductor package structure as described in claim 17, wherein the semiconductor package structure is electrically connected to the circuit board.

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