Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. The manufacturing method comprises: forming a storage tube well and a selection tube well in a substrate with a deep well; forming a gate on each well region and making a side wall; and performing a light doped drain and a heavy doped region injection after the side wall is formed. The light doped drain injection comprises a first angle and a second angle injection. The application performs a light doped drain injection after the side wall is formed, realizes independent adjustment of the storage unit and the logic region device performance, uses the size angle superposition injection, overcomes the physical obstruction caused by the large angle injection due to the narrow spacing between the storage tube and the selection tube, enables the light doped drain outside the device to effectively extend to the gate, and optimizes the electrical performance and the reliability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] In the field of semiconductor memory technology, non-volatile memories (NSCs) can retain stored data without loss even when power is off, and are therefore widely used in various electronic devices. Among them, the dual-transistor (2T) silicon-silicon oxide-silicon nitride-silicon oxide-silicon (SONOS) NSC is particularly suitable for small-capacity, low-power chip designs due to its significant advantages such as simpler manufacturing process and design structure, and lower erase / write current. Furthermore, its strong data erasure and write capabilities make it ideal for high-reliability applications with stringent data security requirements.

[0003] In a conventional 2T SONOS memory, the cell region is typically composed of a SONOS memory transistor and a select transistor. To form a complete transistor device structure and effectively suppress short-channel effects, source-drain structures are usually fabricated in the semiconductor substrate. This typically involves performing ion implantation at specific doses on both sides of the gate structure to form a lightly doped drain (LDD) region, followed by sidewall formation on the gate sidewalls and high-concentration ion implantation to form a heavily doped region.

[0004] With the continuous improvement of semiconductor integration and the diversification of application scenarios, how to rationally arrange the manufacturing process and doping technology of semiconductor devices, and continuously ensure and optimize the electrical performance of memory cells, has always been a direction of continuous attention and research in the semiconductor manufacturing field. Summary of the Invention

[0005] The present invention aims to solve the technical problem in the existing non-volatile memory semiconductor device manufacturing process, where, in order to achieve independent adjustment of the performance of the memory cell region and the logic region, the lightly doped drain implantation is adjusted to be performed after the sidewall is formed. Due to the extremely narrow spacing between the memory tube and the select tube, the large-angle ion implantation is physically blocked, which prevents the lightly doped drain impurities from effectively penetrating under the polysilicon gate, thereby causing device structural defects and a serious deterioration in electrical performance.

[0006] To address the aforementioned technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] Step 1: Provide a substrate having a first conductivity type, and selectively implant impurities of a second conductivity type onto the substrate to form a deep well;

[0008] Step 2: Selectively inject the first type of conductivity impurity into the deep well to form a storage well and a selection well, respectively;

[0009] Step 3: Form a memory gate dielectric layer on the memory tube well, form a select gate dielectric layer on the select tube well, and form gates on the memory gate dielectric layer and the select gate dielectric layer respectively. Then, form sidewalls on the sidewalls of the gates.

[0010] Step 4: After forming the sidewalls, ion implantation is performed to form lightly doped drains and heavily doped regions. The implantation of the lightly doped drains includes a first angle implantation and a second angle implantation, and the implantation angle of the second angle implantation is greater than the implantation angle of the first angle implantation.

[0011] Preferably, the first conductivity type is P-type and the second conductivity type is N-type.

[0012] Preferably, in step three, the storage gate dielectric layer includes a charge trapping multilayer dielectric layer.

[0013] Preferably, the charge-trapping multilayer dielectric layer comprises a silicon oxide-silicon nitride-silicon oxide composite dielectric layer.

[0014] Preferably, in step three, the selected gate dielectric layer includes a silicon oxide layer.

[0015] Preferably, in step three, the material of the gate comprises polycrystalline silicon.

[0016] Preferably, in step four, the implantation of the lightly doped drain and the implantation of the heavily doped region are completed using the same photomask.

[0017] Preferably, in step four, the first angle injection symmetrically injects impurities into the lower regions on both sides of the gate.

[0018] Preferably, in step four, due to the obstruction effect of the distance between the storage tube and the selection tube, the second angle injection can only be effectively injected outside the storage tube and the selection tube.

[0019] Preferably, in step four, the superposition of the first angle injection and the second angle injection results in a lightly doped drain injection amount in the outer region of the memory tube and the select tube that penetrates below the gate, which is greater than the lightly doped drain injection amount in the region between the memory tube and the select tube that penetrates below the gate.

[0020] To address the aforementioned technical problems, the present invention also provides a semiconductor device manufactured using the described method, the semiconductor device comprising:

[0021] The substrate has a first type of conductivity;

[0022] A deep well, located within the substrate, has a second conductivity type;

[0023] Storage traps and selection traps, located within the deep traps, have the first conductivity type;

[0024] The memory gate structure and the select gate structure are located on the memory tube well and the select tube well, respectively. The memory gate structure and the select gate structure each include a gate dielectric layer, a gate located on the gate dielectric layer, and a sidewall located on the gate sidewall.

[0025] The lightly doped drain and heavily doped regions are located in the memory well and the select well on both sides of the gate;

[0026] The lightly doped drain below the gate has an asymmetric structure, and the size of the lightly doped drain below the gate in the region outside the memory tube and the select tube is larger than the size of the lightly doped drain below the gate in the region between the memory tube and the select tube.

[0027] Preferably, the gate dielectric layer of the memory transistor includes a silicon oxide-silicon nitride-silicon oxide composite layer, and the gate structure of the select transistor includes a silicon oxide layer.

[0028] As described above, the semiconductor device manufacturing method and the semiconductor device of the present invention have the following beneficial effects:

[0029] This invention delays the implantation of lightly doped drains in the memory cell region until after sidewall formation, and allows the lightly doped drains and heavily doped regions to share the same photomask. This not only reduces photolithography steps and mask costs but also successfully enables independent adjustment of the heavy doping processes in the memory cell region and the surrounding logic region. More importantly, this invention introduces a hybrid ion implantation method combining a first angle and a second large angle, overcoming the physical shielding challenges faced in the presence of sidewall obstructions and narrow device spacing. The first angle, with a small tilt, maintains the basic short-channel control characteristics, while the second large angle tilt implantation effectively extends impurities to the bottom of the gate in the outer regions of the memory and select transistors, compensating for junction depth loss. This unique process forms an asymmetric lightly doped drain structure with a small inner implantation amount and a large outer implantation amount on the final device. This prevents punch-through effects inside the transistor and reduces parasitic resistance in the outer source and drain regions, optimizing electrical performance and reliability. Attached Figure Description

[0030] Figure 1 The diagram shows a process flow diagram of the semiconductor device manufacturing method of the present invention;

[0031] Figure 2 The diagram shows a cross-sectional view of the semiconductor device after the formation of the deep well according to the present invention.

[0032] Figure 3 The diagram shows a cross-sectional view of the semiconductor device after the formation of the memory trap and the selection trap according to the present invention.

[0033] Figure 4 The diagram shows a cross-sectional view of the semiconductor device after the formation of the gate structure and sidewalls according to the present invention.

[0034] Figure 5 The diagram shows a cross-sectional view of the semiconductor device after the implantation of the lightly doped drain and heavily doped regions according to the present invention. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] A method for manufacturing a semiconductor device, comprising:

[0037] Please refer to Figure 1 , Figure 1 The present disclosure illustrates a process flow for a semiconductor device manufacturing method according to some embodiments thereof, which can be executed in a manufacturing system comprising a variety of semiconductor processing equipment to construct non-volatile memory and peripheral circuitry.

[0038] Step 1: Provide a substrate 101 having a first conductivity type, and selectively implant impurities of a second conductivity type onto the substrate 101 to form a deep well 102;

[0039] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments, the first conductivity type may also be N-type and the second conductivity type may be P-type.

[0040] Please refer to Figure 2 , Figure 2 The cross-sectional structure of the semiconductor device after the deep well 102 is formed in the initial manufacturing stage is shown. In the initial stage of the semiconductor manufacturing process, the manufacturing system provides a substrate 101 as a physical support base for building the entire memory and peripheral logic circuits. The first conductivity type is usually set to P-type or N-type according to the polarity requirements of the overall circuit, and the corresponding second conductivity type is configured with the opposite conductivity polarity.

[0041] Substrate 101 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The semiconductor in the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0042] In the process of forming the deep well 102, a thin sacrificial oxide layer is first grown on the surface of the substrate 101 by thermal oxidation to protect the lattice surface and reduce the channeling effect in the subsequent ion implantation process. Then, a photoresist layer is spin-coated on the sacrificial oxide layer. An opening region corresponding to the size of the deep well 102 is defined in the photoresist layer by exposure and development processes. Then, an ion beam containing impurities of the second conductivity type is implanted into the substrate 101 to a predetermined depth through the opening region using an ion implantation device.

[0043] After ion implantation, residual photoresist on the surface is removed using plasma ashing or wet stripping processes, and the substrate 101 is then subjected to high-temperature thermal annealing. High-temperature annealing can be achieved through rapid thermal annealing or laser-triggered annealing. This process causes the implanted impurity atoms to occupy substitutional positions in the silicon lattice, thereby achieving electrical activation. Simultaneously, it repairs crystal structure damage caused by ion bombardment. The resulting deep well 102 provides a good reverse bias junction isolation environment in the vertical direction for the memory cells to be formed above, reducing noise interference and the probability of parasitic leakage current in the substrate 101.

[0044] Step 2: Selectively inject impurities of the first conductivity type into the deep well 102 to form the storage well 103 and the selection well 104, respectively.

[0045] Please refer to Figure 3 , Figure 3The cross-sectional structure of the semiconductor device after the memory tube well 103 and the select tube well 104 are formed inside the deep well 102 is shown. In step two, in order to construct a device region with relatively independent electrical properties inside the deep well 102, a new mask pattern needs to be prepared again by photolithography. After spin-coating an anti-reflective coating and photoresist, the mask pattern defining the positions of the memory tube and the select tube is transferred onto the photoresist using a photolithography machine. After development, a portion of the area inside the deep well 102 is exposed. Subsequently, an ion implantation process for impurities of the first conductivity type is performed. During this implantation process, multiple implantations at different depths can be performed by adjusting the implantation energy and dose.

[0046] The aforementioned implantation can include anti-penetration implantation to prevent deep penetration, shallow implantation to adjust the channel threshold voltage, and deep implantation to form the well body. The superposition of multiple implantations can form a storage well 103 and a select well 104 with a specific concentration gradient inside the deep well 102. The storage well 103 and the select well 104 can be spatially spaced apart from each other, or they can be directly connected regions with different doping concentration distributions.

[0047] By constructing independent well structures for the memory transistor and the select transistor respectively, different back-gate bias voltages can be applied to the memory transistor well 103 and the select transistor well 104 during circuit operation. This allows for independent optimization and control of the programming and erasing efficiency of the non-volatile memory transistor and the switching capability of the select transistor, thereby improving the overall read performance of the semiconductor device. After well implantation, a corresponding annealing step is performed to activate impurities, preparing the device for the subsequent fabrication of the gate 106 structure.

[0048] Step 3: A memory gate dielectric layer 105a is formed on the memory trap 103, a select gate dielectric layer 105b is formed on the select trap 104, and gate 106 is formed on the memory gate dielectric layer 105a and the select gate dielectric layer 105b respectively. Then, a sidewall 108 is formed on the sidewall of the gate 106.

[0049] In some embodiments, in step three, the storage gate dielectric layer 105a includes a charge trapping multilayer dielectric layer.

[0050] In some embodiments, the charge trapping multilayer dielectric layer includes a silicon oxide-silicon nitride-silicon oxide composite dielectric layer.

[0051] In some embodiments, in step three, the selected gate dielectric layer 105b includes a silicon oxide layer.

[0052] In some embodiments, in step three, the material of the gate 106 includes polycrystalline silicon.

[0053] Please refer to Figure 4 , Figure 4The cross-sectional structure of the semiconductor device after forming the gate 106 structure and sidewall 108 is shown. The process of forming the memory gate dielectric layer 105a and the select gate dielectric layer 105b involves a combination of various thin film deposition and growth processes. For the silicon oxide-silicon nitride-silicon oxide composite dielectric layer, which serves as a charge trapping multilayer dielectric layer, the bottom silicon oxide layer acts as a charge tunneling layer and is typically grown on the surface of the memory well 103 using an in-situ vapor generation process or a high-temperature thermal oxidation process to ensure a low defect state density at the silicon-silicon oxide interface. The middle silicon nitride layer serves as a charge storage layer and is formed using a low-pressure chemical vapor deposition or atomic layer deposition process. The top silicon oxide layer serves as a barrier layer and is formed using chemical vapor deposition or high-density plasma deposition technology to prevent the charge stored in the middle layer from leaking to the upper gate 106. Depending on the requirements of different technology nodes, the charge trapping layer can also be replaced with hafnium oxide, aluminum oxide, or other high-dielectric-constant materials.

[0054] For the selected gate dielectric layer 105b, which primarily serves as a switch insulator, a thermally oxidized pure silicon oxide layer or a nitrogen-doped silicon oxide layer can be used to improve breakdown resistance. After forming the dielectric layer, full-area deposition of the gate 106 material is performed. Polycrystalline silicon, a common gate 106 material, is formed using a furnace tube low-pressure chemical vapor deposition process, and appropriate conductive impurities are incorporated during or after deposition to reduce resistivity. Alternatively, the gate 106 can be made of amorphous silicon or a metal gate structure. The metal gate can include low-resistivity materials such as titanium nitride, tantalum nitride, tantalum carbide, tungsten, aluminum, copper, or metal silicides, and their stack-up combinations.

[0055] After depositing the gate 106 material, the gate 106 line pattern is defined by photolithography, and excess gate 106 material is removed using an anisotropic dry etching process based on fluorine- or chlorine-based gases, stopping at the surfaces of the underlying memory gate dielectric layer 105a and select gate dielectric layer 105b to avoid damaging the channel. After etching the gate 106, one or more layers of insulating material are conformally deposited across the entire semiconductor device surface as a preparatory layer for the sidewalls 108. The material can be selected from silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon nitride. Finally, the conformal insulating material is vertically etched back using a maskless reactive ion etching process, and the portion remaining on the sidewalls of the gate 106 forms the sidewalls 108. The sidewalls 108 protect the sidewalls of the gate 106 from contamination by subsequent processes and also provide self-aligned geometric boundaries for the upcoming source / drain implantation.

[0056] Step 4: After forming the sidewall 108, ion implantation is performed to form a lightly doped drain 107 and a heavily doped region 109. The implantation of the lightly doped drain 107 includes a first angle implantation and a second angle implantation, and the implantation angle of the second angle implantation is greater than the implantation angle of the first angle implantation.

[0057] In some embodiments, in step four, the implantation of the lightly doped drain 107 and the implantation of the heavily doped region 109 are performed using the same photomask.

[0058] In some embodiments, in step four, the first angle injection symmetrically injects impurities into the lower regions on both sides of the gate 106.

[0059] In some embodiments, in step four, due to the obstruction effect of the distance between the storage tube and the selection tube, the second angle injection can only be effectively injected outside the storage tube and the selection tube.

[0060] In some embodiments, in step four, after the superposition of the first angle injection and the second angle injection, the amount of lightly doped drain 107 injected into the region outside the memory tube and the select tube below the gate 106 is greater than the amount of lightly doped drain 107 injected into the region between the memory tube and the select tube below the gate 106.

[0061] Please refer to Figure 5 , Figure 5 The cross-sectional structure of the semiconductor device after implantation of the lightly doped drain 107 and the heavily doped region 109 is shown. In conventional process flows, the implantation of the lightly doped drain 107 in the memory cell region is usually scheduled before the formation of the sidewalls 108, but this limits the optimization of the memory cell region to the process steps of the surrounding logic region. In this embodiment, the implantation timing of the lightly doped drain 107 is postponed to after the formation of the sidewalls 108. At this time, the corresponding region is exposed using the same photomask, and the ion implantation of the lightly doped drain 107 and the heavily doped region 109 is performed consecutively. This process reorganization reduces the number of photolithography steps and the use of photomasks, reduces manufacturing costs, and eliminates the overlay alignment errors that may be caused by multiple photolithography steps.

[0062] To overcome the physical obstruction caused by the sidewall 108 to the lightly doped drain 107 impurities entering the region below the gate 106, a hybrid implantation mode combining a first-angle implantation and a second-angle implantation is introduced in this step. The first-angle implantation uses a low tilt angle or an incident angle close to perpendicular to the wafer surface, and the wafer is rotated during implantation to avoid channel effects. This low-angle implantation allows some impurities to penetrate through the bottom edge of the sidewall 108, forming a symmetrical and shallow basic doping distribution below both sides of the gate 106, maintaining the basic short-channel control characteristics of the device. However, due to the obstruction of the sidewall 108, the inward penetration of the first-angle implantation is limited.

[0063] To increase the lateral diffusion size of impurities below gate 106, a second angle implantation with a high tilt angle is then employed. When the high-energy ion beam is incident on the wafer surface at a large angle, the geometry's shielding effect comes into play. Due to the very narrow spacing between the memory gate 106 and the select gate 106, two adjacent towering gates 106 and the attached sidewalls 108 form a trench with a large depth-to-width ratio. The ion beam incident at a large angle is blocked by the in front gate 106 structure, preventing a significant amount of impurities from reaching the substrate 101 region between the memory and select gates.

[0064] In the outer regions of the memory and select transistors, where there is no obstruction from adjacent devices, ions implanted at the second angle can penetrate the surface along an inclined trajectory, reaching deeper locations below the gate 106. By superimposing the doses at the first and second angles, the implantation amount of lightly doped drain 107 in the outer region is increased without significantly increasing the implantation energy, while maintaining a lower implantation amount in the inner region of the device. This asymmetric doping state allows the memory and select transistors, even with the sidewall 108 providing obstruction, to still recover sufficient lightly doped drain 107 concentration and size on the outer side, bringing the overall on-current and other electrical parameters back to the normal range of the design target, thus improving the signal margin during the memory cell readout process.

[0065] In some embodiments, the implantation process of the lightly doped drain 107 is not limited to two implantation steps consisting of a single first-angle implantation and a single second-angle implantation. Instead, it can be extended to a multi-step tilt implantation scheme that includes three or more implantation parameters, depending on the need for fine control of the device junction depth profile. For example, the implantation process may include implantation sequences with different tilt angles, such as a first angle, a second angle, a third angle, or even more, or doping may be performed by continuously gradient scanning of the ion beam incident angle.

[0066] When implementing the multi-step implantation scheme described above, in addition to adjusting the incident tilt angle to address the geometric shielding effect of the sidewall 108, the implantation energy and impurity dosage can be independently configured for each implantation step. Simultaneously, multi-step tilt implantation can be combined with wafer azimuth rotation control, allowing the ion beam to enter the substrate 101 from different side azimuth angles, thereby further improving the spatial uniformity of the doping distribution. Furthermore, the types of impurities used in different implantation steps can be different or combined. For example, when constructing an N-type lightly doped drain, multiple implantation steps at different angles can use impurity elements with different atomic masses and diffusion coefficients, such as phosphorus, arsenic, or antimony; when constructing a P-type lightly doped drain, impurity ions such as boron, boron difluoride, or indium can be flexibly combined.

[0067] This multi-step, multi-angle, and multi-doped composite implantation strategy can construct a smoother, lightly doped drain 107 profile with a specific concentration gradient in the three-dimensional space below the gate 106, further modulating the electric field distribution at the edge of the device channel. The introduction of multiple implantation steps helps to more flexibly compensate for the junction depth loss caused by the inward extension of the outer regions of the memory and select transistors, and alleviates the problem of excessive concentration of lattice damage that may be caused by a single high-dose, large-angle implantation. Thus, under the process constraint of implantation after the formation of the sidewall 108, the thermal carrier degradation resistance and overall reliability of the semiconductor device can be optimized.

[0068] A semiconductor device, manufactured using the aforementioned method, comprises:

[0069] Substrate 101 has a first conductivity type;

[0070] The deep well 102, located in the substrate 101, has a second conductivity type;

[0071] Storage trap 103 and selection trap 104, located in deep trap 102, have a first conductivity type;

[0072] The gate structure of the memory transistor and the gate structure of the select transistor are located on the memory transistor well 103 and the select transistor well 104, respectively. Both the gate structure of the memory transistor and the gate structure of the select transistor include a gate dielectric layer (e.g., the gate dielectric layer 105a of the memory transistor and the gate dielectric layer 105b of the select transistor), a gate 106 located on the gate dielectric layer, and a sidewall 108 located on the sidewall of the gate 106.

[0073] The lightly doped drain 107 and the heavily doped region 109 are located in the memory well 103 and the select well 104 on both sides of the gate 106;

[0074] Among them, the lightly doped drain 107 driven into the gate 106 has an asymmetric structure. The size of the lightly doped drain 107 driven into the gate 106 in the outer region of the memory tube and the select tube is larger than the size of the lightly doped drain 107 driven into the gate 106 in the region between the memory tube and the select tube.

[0075] In some embodiments, the storage gate dielectric layer 105a includes a silicon oxide-silicon nitride-silicon oxide composite layer, and the select gate dielectric layer 105b includes a silicon oxide layer.

[0076] Please refer to the reference again. Figure 5Due to the large-angle mixing implantation under the presence of sidewall 108, the lightly doped drain 107 below the gate 106 exhibits an asymmetrical distribution in physical morphology. When cross-sectional analysis of this semiconductor device is performed, it is observed that in the substrate 101 region outside the memory transistor and the select transistor, the lateral junction depth of the impurities in the lightly doped drain 107 extending towards the center of the gate 106 is relatively large, and the peak impurity concentration is also high. However, the lightly doped drain 107 located below the adjacent gap between the memory transistor and the select transistor has a shorter lateral distance extending towards the center of the gate 106, and the impurity distribution is sparser.

[0077] This asymmetric, lightly doped drain 107 size distribution results in lower parasitic series resistance and larger gate 106 overlap capacitance on the outer side of the device, improving carrier injection efficiency and device switching speed. The relatively small doping size on the inner side of the device helps prevent premature circuit-through of the depletion regions beneath adjacent gates 106, maintaining good breakdown resistance.

[0078] After forming the aforementioned front-end device structure, including the gate 106, lightly doped drain 107, and heavily doped region 109, the manufacturing process moves to the back-end interconnect module construction stage. First, a self-aligned silicide process can be performed on the exposed surfaces of the heavily doped region 109 and the polysilicon gate 106 to form a metal silicide layer. This process typically involves covering the entire wafer surface with a barrier metal layer via physical vapor deposition; the material can be selected from nickel, cobalt, titanium, tungsten, platinum, or alloys of these metals. A first rapid thermal annealing process is then performed, causing a solid-state reaction between the covering metal and the underlying silicon to form a metal-rich silicide phase, while the metal deposited on insulating materials such as the sidewalls 108 or isolation structures remains unreacted. After selectively stripping the unreacted metal using a specific wet etching solution, a second, higher-temperature thermal annealing can be performed as needed to transform the metal silicide into a stable phase with lower resistivity, thereby reducing the parasitic contact resistance between the transistor source / drain and gate.

[0079] After the metal silicide layer is fabricated, a contact hole etch stop layer is typically deposited conformally on the device surface. This stop layer can be made of silicon nitride, silicon oxynitride, or carbon-doped silicon nitride. Besides controlling the depth of subsequent etching, this stop layer can also improve the carrier mobility of the underlying channel by adjusting its internal tensile or compressive stress. Next, an interlayer dielectric layer is formed over the entire surface area above the etch stop layer. Materials for the interlayer dielectric layer include traditional dielectric materials such as tetraethyl orthosilicate oxide, phosphosilicate glass, borosilicate glass, and fluorine-doped silicate glass. In more advanced manufacturing processes, to reduce parasitic capacitance and RC delay caused by interconnect structures, materials with lower dielectric constants than silicon dioxide can be used, such as carbon-doped silicon oxide, porous silicon oxide, spin-coated glass, or organic polymer dielectric layers. This interlayer dielectric layer is mainly deposited using techniques such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or flow-through chemical vapor deposition. Subsequently, chemical mechanical polishing (CMP) is used to planarize the wafer surface, providing a flat reference surface for subsequent photolithographic pattern transfer.

[0080] Photoresist is coated and patterned on top of the planarized interlayer dielectric layer. Anisotropic dry etching is then used to penetrate the interlayer dielectric layer and the bottom etch stop layer, exposing the underlying metal silicide layer and forming a through-hole contact. Before filling the contact hole with the main conductive metal, a barrier layer and an adhesion layer are deposited along the inner wall and bottom of the contact hole to prevent metal atoms from diffusing into the surrounding dielectric material and to improve interfacial adhesion. Common barrier layer materials include titanium, titanium nitride, tantalum, tantalum nitride, or a combination of these materials. Deposition methods include physical vapor deposition or atomic layer deposition with high step coverage. Subsequently, conductive metal is filled into the contact hole using chemical vapor deposition or electroplating. The filler material can be selected from materials such as tungsten, cobalt, ruthenium, copper, or aluminum, depending on the requirements of different process nodes. After metal filling, chemical mechanical polishing is used to remove excess metal and the barrier layer that have overflowed onto the surface of the interlayer dielectric layer. The metal solid remaining inside the contact hole forms the conductive contact plug.

[0081] After completing the bottom contact plug, a multi-layered metal interconnect network is built on top of the semiconductor device. This multi-layered interconnect structure is typically fabricated using a double damascene process, where interconnect vias and routing trenches are sequentially etched into the inter-metal dielectric layer. Similar to the bottom contact plug, a metal barrier layer is conformally deposited on the inner surface of the trenches and vias, followed by a thin copper seed layer sputtered via physical vapor deposition. Then, copper is electrochemically plated to fill the entire trench and via network, followed by thermal annealing to recrystallize the copper grains and reduce film resistance. Finally, excess copper is removed by chemical mechanical polishing. This double damascene routing process is repeated multiple times according to the integrated circuit design routing requirements, forming a copper interconnect layer structure containing multiple horizontal conductors and vertical vias. Through this three-dimensional interwoven metal interconnect network, memory transistors and select transistors are electrically connected to the read / write driver circuits, address decoders, sense amplifiers, and power management modules surrounding the semiconductor chip. After all interconnect layers are fabricated, a passivation protective layer composed of materials such as high-density plasma silicon nitride, undoped silicate glass, or polyimide will be placed on the top layer of the chip, and lead pads will be created to enable electrical signal interaction and power supply connection between the internal memory module and the external package pins.

[0082] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, At least including: Step 1: Provide a substrate having a first conductivity type, and selectively implant impurities of a second conductivity type onto the substrate to form a deep well; Step 2: Selectively inject the first type of conductivity impurity into the deep well to form a storage well and a selection well, respectively; Step 3: Form a memory gate dielectric layer on the memory tube well, form a select gate dielectric layer on the select tube well, and form gates on the memory gate dielectric layer and the select gate dielectric layer respectively. Then, form sidewalls on the sidewalls of the gates. Step 4: After forming the sidewalls, ion implantation is performed to form lightly doped drains and heavily doped regions. The implantation of the lightly doped drains includes a first angle implantation and a second angle implantation, and the implantation angle of the second angle implantation is greater than the implantation angle of the first angle implantation.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The first conductivity type is P-type, and the second conductivity type is N-type.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step three, the storage gate dielectric layer includes a charge trapping multilayer dielectric layer.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that: The charge-trapping multilayer dielectric layer includes a silicon oxide-silicon nitride-silicon oxide composite dielectric layer.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step three, the selected gate dielectric layer includes a silicon oxide layer.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step three, the material of the gate includes polycrystalline silicon.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step four, the implantation of the lightly doped drain and the implantation of the heavily doped region are completed using the same photomask.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step four, the first angle injection symmetrically injects impurities into the lower regions on both sides of the gate.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step four, due to the obstruction effect of the distance between the storage tube and the selection tube, the second angle injection can only be effectively injected outside the storage tube and the selection tube.

10. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step four, the superposition of the first angle injection and the second angle injection results in a lightly doped drain injection amount in the outer region of the memory tube and the select tube that is injected below the gate, which is greater than the lightly doped drain injection amount in the region between the memory tube and the select tube that is injected below the gate.

11. A semiconductor device, characterized in that, The semiconductor device, manufactured using the method of any one of claims 1 to 10, comprises: The substrate has a first type of conductivity; A deep well, located within the substrate, has a second conductivity type; Storage traps and selection traps, located within the deep traps, have the first conductivity type; The memory gate structure and the select gate structure are located on the memory tube well and the select tube well, respectively. The memory gate structure and the select gate structure each include a gate dielectric layer, a gate located on the gate dielectric layer, and a sidewall located on the gate sidewall. The lightly doped drain and heavily doped regions are located in the memory well and the select well on both sides of the gate; The lightly doped drain below the gate has an asymmetric structure, and the size of the lightly doped drain below the gate in the region outside the memory tube and the select tube is larger than the size of the lightly doped drain below the gate in the region between the memory tube and the select tube.

12. The semiconductor device according to claim 11, characterized in that: The storage transistor gate dielectric layer includes a silicon oxide-silicon nitride-silicon oxide composite layer, and the select transistor gate structure includes a silicon oxide layer.

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