Semiconductor device, in-memory computing system, and electronic device

Abstract

A semiconductor device, a compute-in-memory system and an electronic device are disclosed. The semiconductor device comprises: a first die comprising a first substrate and a first circuit layer, the first circuit layer being formed in a first direction of the first substrate, the first circuit layer comprising an interface circuit configured to communicate with an external device; an inductor connected to the interface circuit; a second die stacked on the first die in the first direction, the second die comprising a second circuit layer; and a first interconnection structure configured to connect the first circuit layer and the second circuit layer. The semiconductor device can reduce the influence of parasitic capacitance when the interface circuit communicates with the external device, and can improve the rate of communication with the external device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory computing system, and an electronic device. Background Technology

[0002] During chip manufacturing, circuits can be formed on a substrate. These circuits may include logic circuits and interface circuits. The logic circuits are used to implement the chip's main functions, while the interface circuits are used for external communication. For example, they can perform one or more operations such as buffering, assembling, or converting data or signaling to be transmitted. For instance, data processed by the logic circuits or signaling generated can be transmitted externally through the interface circuits, or the logic circuits can obtain data or signaling from external sources through the interface circuits.

[0003] Chips may face diverse working environments during use. As a bridge for external communication, the interface circuit needs to maintain stable and reliable operation under different working environments. Summary of the Invention

[0004] This application provides a semiconductor device, in-memory computing system, and electronic device that comprehensively considers the design of chip packaging and protection circuits to meet the chip's internal communication needs while improving the stability or reliability of the chip interface circuit.

[0005] In a first aspect, a semiconductor device is provided, comprising: a first die including a first substrate and a first circuit layer, the first circuit layer being formed in a first direction of the first substrate and including an interface circuit for external communication; an inductor connected to the interface circuit; a second die stacked on the first die along the first direction, and the second die including a second circuit layer; and a first interconnect structure for connecting the first circuit layer and the second circuit layer.

[0006] In this way, faster data transmission between the first and second dies can be achieved with shorter traces, resulting in faster transmission speeds, lower transmission losses, and lower power consumption within the semiconductor device. The inductor can reduce the impact of parasitic capacitance during interface circuit communication with external systems, helping to improve the speed of external communication. This, in turn, improves the stability or reliability of the chip's interface circuit while meeting the chip's high internal communication requirements. In some implementations of the first aspect, the inductor includes: an inductor layer formed on the side of the first substrate facing away from the first circuit layer.

[0007] Thus, since there is a large space on the side of the first substrate away from the first circuit layer, the design of the inductor layer can be more flexible; at the same time, it can also avoid mutual interference caused by the mutual coupling between the inductor layer and the circuit layer of the second die, which helps to improve the maximum speed of high-speed I / O of the first die and reduce the circuit noise of the second die.

[0008] In some implementations of the first aspect, the inductor layer includes: a first conductive structure connected to the interface circuit; and a second conductive structure connected to the first conductive structure.

[0009] In this way, by forming an inductor layer through a multilayer conductive structure, the inductors formed on the multilayer conductive structure can be spatially intersected, which helps to improve the Q value of the inductor, thereby stabilizing and increasing the maximum speed of high-speed I / O.

[0010] In some implementations of the first aspect, at least one of the first conductive structure and the second conductive structure forms a winding structure.

[0011] In some implementations of the first aspect, the semiconductor device further includes a wiring layer formed on the side of the inductor layer opposite to the first substrate.

[0012] In some implementations of the first aspect, the semiconductor device further includes: a wiring layer formed on the side of the first substrate opposite to the first circuit layer, wherein a winding structure is formed in the wiring layer.

[0013] In some implementations of the first aspect, the semiconductor device further includes: a first shielding structure for shielding the traces of the interface circuit.

[0014] Thus, by providing a shielding structure for the traces used to shield the interface circuit in the semiconductor device, it helps to reduce the mutual interference between the interface circuit and the circuit layer of the second die, and helps to improve the flexibility of the circuit layer design.

[0015] In some implementations of the first aspect, the inductor includes an active inductor formed within the first circuit layer.

[0016] In some implementations of the first aspect, the inductor includes: an inductor structure formed on the side of the first substrate facing the first circuit layer; and a second shielding structure for shielding the inductor structure.

[0017] In some implementations of the first aspect, a wiring layer is formed on the surface of the first substrate facing away from the second die for connecting external terminals of the semiconductor device.

[0018] In some implementations of the first aspect, the semiconductor device further includes: a third die stacked on the second die along a first direction, and the third die including a third circuit layer; and a second interconnect structure for connecting the third circuit layer and the second circuit layer.

[0019] In some implementations of the first aspect, the semiconductor device further includes a third interconnect structure for connecting the first circuit layer and the third circuit layer.

[0020] In some implementations of the first aspect, the third die includes a third substrate on which a third circuit layer is formed on the surface of the third substrate facing the second die.

[0021] In some implementations of the first aspect, the second die includes a second substrate; a second circuit layer is formed on the surface of the second substrate facing the first die; or, a second circuit layer is formed on the surface of the second substrate away from the first die.

[0022] Secondly, this application provides a memory computing system, which includes a semiconductor device in any possible implementation of the first aspect; a substrate including in-board wiring for connecting the semiconductor device to pins of the memory computing system or for connecting the semiconductor device to other semiconductor devices.

[0023] Thirdly, this application provides an electronic device, including a semiconductor device in any possible implementation of the first aspect, or including a memory computing system in the second aspect. Attached Figure Description

[0024] Figure 1 A schematic structural diagram of a semiconductor device according to an exemplary embodiment of this application is shown.

[0025] Figure 2 Another schematic structural diagram of a semiconductor device according to an exemplary embodiment of this application is shown.

[0026] Figure 3 Another schematic structural diagram of a semiconductor device according to an exemplary embodiment of this application is shown.

[0027] Figure 4 Another schematic structural diagram of a semiconductor device according to an exemplary embodiment of this application is shown.

[0028] Figure 5 Another schematic structural diagram of a semiconductor device according to an exemplary embodiment of this application is shown.

[0029] Figure 6 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0030] Figure 7 Another schematic structural diagram of a semiconductor device according to an exemplary embodiment of this application is shown.

[0031] Figure 8 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Detailed Implementation

[0032] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0033] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0034] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0035] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0036] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0037] During chip manufacturing, circuits, including logic circuits and interface circuits, can be grown on a substrate. Wiring structures are grown on these circuits to facilitate the routing of terminals for external connections as traces and electrodes. A wiring layer is then grown, and the chip is packaged facing the substrate. This substrate-facing packaging method facilitates the connection between the interface circuits and the substrate. With the development of artificial intelligence and big data, the demands on chip processing power and efficiency are increasing, while power consumption is also decreasing. Therefore, embodiments of this application package multiple dies internally within the chip. These dies can be stacked in a first direction (e.g., perpendicular to the substrate direction). Dies with circuitry are positioned facing the stacking direction (or the direction away from the substrate) and bonded to other dies in a face-up configuration. This achieves higher efficiency, lower power consumption, and higher stability for data or signaling transmission between the dies within the chip. External communication interface circuits can be connected to the substrate through interconnect structures that pass through the substrate.

[0038] The above integration methods can be used in in-memory computing architectures to improve their computing performance. In an in-memory computing architecture, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and at least one processing circuit; the storage circuit is used to store data; for example, the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling data writing, reading, computation, or sensing computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computations based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0039] Semiconductor devices manufactured using the above integration methods can improve chip performance. However, the chip's interface circuits may be subject to interference due to the inclusion of protection circuits, leading to a decrease in interface performance. For example, to reduce the impact of static electricity on the interface circuits, electrostatic discharge (ESD) circuits can be implemented. When these ESD circuits face other dies within the chip, they may generate significant parasitic capacitances between the metal structures of the circuitry, thereby affecting the speed of the interface circuitry.

[0040] In view of this, this application proposes a semiconductor device, in-memory computing system, and electronic device that comprehensively considers the design of chip packaging and protection circuits to meet the chip's large internal communication needs while improving the stability or reliability of the chip interface circuit.

[0041] Figure 1 A schematic structural diagram of a semiconductor device 100 provided in an embodiment of this application is shown. The semiconductor device 100 may include: a first die 111, including a first substrate 1111 and a first circuit layer 1112, the first circuit layer 1112 being formed in a first direction of the first substrate 1111, the first circuit layer 1112 including an interface circuit 11121 for external communication; an inductor 112 connected to the interface circuit 11121; a second die 113 stacked on the first die 111 along the first direction, and the second die 113 including a second circuit layer 1131; and a first interconnect structure 114 for connecting the first circuit layer 1112 and the second circuit layer 1131.

[0042] In this way, face-up bonding enables faster data transmission between the first and second dies with shorter traces, resulting in faster transmission speeds, lower transmission losses, and lower power consumption within the semiconductor device. The inductor setting can reduce the impact of parasitic capacitance when the interface circuit communicates with the outside, which helps to improve the speed of external communication. Thus, while meeting the chip's large internal communication needs, it also improves the stability or reliability of the chip's interface circuit.

[0043] The circuit layers in this application embodiment (e.g., including a first circuit layer, a second circuit layer, or a third circuit layer, etc.) may include logic circuit portions and wiring portions, with the wiring portions used to lead out external connections of the logic circuits. The logic circuit portions may include semiconductor devices such as transistors. The logic circuit portions may include portions formed in a substrate. The logic circuit portions and wiring portions may be formed in different dielectric layers. The interconnect structure may include bonding structures between dies and vertical interconnect structures formed in the circuit layers, such as via structures filled with conductive material.

[0044] Reference Figure 1 The first interconnect structure 114 includes a portion disposed between the first die 111 and the second die 113. Optionally, the first interconnect structure 114 may also include a portion disposed within the first die 111. For example, the first interconnect structure 114 may further include a connection structure, such as a through-silicon via (TSV), disposed in the substrate of the first die 111. For example, the first interconnect structure 114 may further include a connection structure, such as a wiring structure, disposed in the first circuit layer of the first die 111.

[0045] Optionally, the first interconnect structure 114 may further include portions disposed within the second die 113. For example, the first interconnect structure 114 may further include connection structures, such as TSVs, disposed in the substrate of the second die 113. For example, the first interconnect structure 114 may further include connection structures, such as wiring structures, disposed in the second circuit layer of the second die 113.

[0046] Optionally, the inductor 112 includes an inductor layer formed on the side of the first substrate 1111 opposite to the first circuit layer 1112.

[0047] Thus, since there is a large space on the side of the first substrate away from the first circuit layer, the design of the inductor layer can be more flexible. At the same time, it can also prevent mutual interference caused by the coupling between the inductor layer and the circuit layer of the second die, which helps to increase the maximum speed of the interface circuit used as high-speed IO on the first die and reduce the circuit noise of the second die.

[0048] For ease of representation, Figure 1 The substrate of the second die 113 is not shown in the figure. The second circuit layer 1131 may be formed along the first direction on one side of the substrate of the second die 113, for example, it may be formed on the side facing the first die 111, or on the side away from the first die 111.

[0049] For example, Figure 2 Another schematic structural diagram of the semiconductor device 100 provided in an embodiment of this application is shown. The inductor layer 1121 may be formed on the side of the first substrate 1111 opposite to the first circuit layer 1112. The interface circuit 11121 may be connected to the inductor layer 1121 via metal traces and through-silicon vias (TSVs) in the first substrate 1111.

[0050] Optionally, the inductor layer 1121 includes: a first conductive structure 11211 connected to the interface circuit 11121; and a second conductive structure 11212 connected to the first conductive structure 11211. The inductor layer 1121 may include a multilayer conductive structure. The first conductive structure 11211 may include the conductive structure closest to the first substrate 1111 in the multilayer conductive structure. The first conductive structure 11211 may also include another conductive structure in the multilayer conductive structure. Compared with forming an inductor layer through a single-layer conductive structure, forming an inductor layer through a multilayer conductive structure has the advantages of increasing the portion that can be used to form the inductor, thereby increasing the inductance value; and increasing the non-extending dimension of the inductor structure, reducing the unit resistance value along the extending direction, reducing losses, and improving the Q value.

[0051] Optionally, at least one of the first conductive structure 11211 and the second conductive structure 11212 can form a winding structure. The winding structure includes a multi-turn structure. The winding structure can increase the inductance value of the inductor. Optionally, the first conductive structure 11211 and the second conductive structure 11212 can form a cross-winding structure. A cross-winding structure means that one turn of the multi-turn winding of the first conductive structure 11211 is located between two adjacent turns of the multi-turn winding of the second conductive structure 11212, and / or, one turn of the multi-turn winding of the second conductive structure 11212 is located between two adjacent turns of the multi-turn winding of the first conductive structure 11211. The cross-winding structure can reduce the capacitance between the two conductive layers, which can improve the Q value of the inductor, and the improvement in Q value is more significant at higher frequencies.

[0052] Optionally, the semiconductor device 100 further includes a wiring layer 115 formed on the side of the inductor layer 1121 facing away from the first substrate 1111, for connecting terminals of the semiconductor device to the outside.

[0053] Optionally, a winding structure is formed in the wiring layer 115. Thus, the inductance value of the inductor can be increased through the first conductive structure 11211, the second conductive structure 11212, and the winding structure formed in the wiring layer. The winding structures of the first conductive structure 11211, the second conductive structure 11212, and adjacent layers in the wiring layer 115 may include a cross-winding structure, which can improve the Q value of the inductor, and the improvement in Q value is more significant at higher frequencies.

[0054] Figure 2 The inductor layer 1121 and the wiring layer 115 are both located in the wiring layer formed on the side of the first substrate 1111 away from the first circuit layer 1112. By utilizing the inductor layer 1121, or by utilizing the conductive structure of the inductor layer 1121 and the conductive structure of the wiring layer 115 (e.g., the winding structure), an inductor with a higher Q value can be achieved. Figure 2 For clarity, the dielectric layer containing inductor layer 1121 has been omitted.

[0055] For example, Figure 3 Another schematic structural diagram of the semiconductor device 100 provided in an embodiment of this application is shown. The interface circuit in the first die is connected to metal layer BM1 via metal traces (e.g., traces in the first circuit layer 1112) and TSV. Metal layer BM2 is connected to metal layer BM1. Metal layer BM2 is connected to a wiring layer. A winding structure can be formed in metal layer BM1, and a winding structure can be formed in metal layer BM2. Optionally, a winding structure can also be formed in the wiring layer.

[0056] Optionally, the semiconductor device further includes a first shielding structure 116 for shielding the traces of the interface circuit, such as the traces in the first circuit layer 1112. Thus, by providing a shielding structure in the semiconductor device for shielding the traces of the interface circuit, mutual interference between the interface circuit and the circuit layer of the second die can be reduced. This reduces the spatial distance requirements on the second die and the first die, and also reduces the spatial distance requirements between the circuit layer of the second die and the traces of the interface circuit. It also reduces the impact on the trace design of the second die; for example, in the circuit layer of the second die, traces that are less sensitive to interference can be placed closer to the traces of the interface circuit than traces that are more sensitive to interference to reduce the interference effect, thereby improving the flexibility of the circuit layer design.

[0057] Optionally, the first shielding structure 116 may include a structure formed in the first circuit layer 1112, such as a structure formed by a wiring layer in the first circuit layer 1112. The first shielding structure 116 may be connected to an external terminal of the semiconductor device for coupling a first signal. The first signal may include an anti-interference signal, such as a ground signal. For example, the first shielding structure 116 may be connected to an external terminal of the semiconductor device via the first circuit layer 1112, an interconnect structure (e.g., TSV) in the first substrate, metal layers BM1 and BM2, and a wiring layer.

[0058] Optionally, the inductor layer may include metal layers BM1 and BM2. The structure in metal layer BM1 connected to the interface circuit 11121 may include a first conductive structure 11211 of the inductor layer, and the structure in metal layer BM2 connected to the first conductive structure 11211 may include a second conductive structure 11212 of the inductor layer.

[0059] Optionally, the second die 113 can be connected to an external terminal of the semiconductor device. For example, the second die 113 can be connected via the first interconnect structure 114 (see...). Figure 1 The first circuit layer 1112, the connection structure (e.g., TSV) in the first substrate, the metal layers BM1 and BM2, and the wiring layer are connected to the external terminals of the semiconductor device.

[0060] Optionally, the metal layer BM1 may include a structure connected to the second die 113, a structure connected to the first shielding structure 116, and a structure connected to the interface circuit 11121. The structure in the metal layer BM1 connected to the interface circuit 11121 may include a first conductive structure 11211.

[0061] Optionally, the metal layer BM2 may include a structure connected to the second die 113, a structure connected to the first shielding structure 116, and a structure connected to the first conductive structure 11211. The structure in the metal layer BM2 connected to the first conductive structure 11211 may include a second conductive structure 11212.

[0062] above Figure 3 The circuit structures in the first die 111 and the second die 113 are merely illustrative and are not specifically limited in the embodiments of this application.

[0063] Optionally, the inductor 112 includes an active inductor formed within the first circuit layer 1112.

[0064] For example, Figure 4 Another schematic structural diagram of the semiconductor device 100 provided in an embodiment of this application is shown. The first circuit layer 1112 may include interface circuitry 11121 and an active inductor 1122. The active inductor 1122 helps prevent interference to the second die and helps reduce circuit noise on the second die.

[0065] This application does not limit the structure of the active inductor. For example, the active inductor can be a circuit that uses active devices to simulate the characteristics of physical inductance. The active devices include, for example, transistors and operational amplifiers. Optionally, the active inductor may also include passive RC circuits.

[0066] When a physical inductor (e.g., a wire-wound inductor) faces a second die, the wire-wound inductor couples with the metal layer of the second die, causing mutual interference and affecting the performance of the interface circuitry. This can result in limitations in achieving its maximum speed or increased circuit noise on the second die. Replacing the wire-wound inductor with an active inductor reduces coupling, improves interface circuitry performance, and reduces circuit noise on the second die.

[0067] Optionally, a shielding structure can be used to shield the inductor structure from the influence of the second die. For example, Figure 5 Another schematic structural diagram of a semiconductor device 100 provided in an embodiment of this application is shown. The inductor 112 includes: an inductor structure 1123 formed on the side of a first substrate 1111 facing the first circuit layer 1112; and a second shielding structure 1124 for shielding the inductor structure 1123.

[0068] Optionally, a wiring layer is formed on the surface of the first substrate 1111 that is opposite to the second die 113 for connecting external terminals of the semiconductor device.

[0069] Optionally, the first circuit layer 1112 includes a first control circuit, and the second circuit layer 1131 includes a storage circuit. The first control circuit is used to input data to the storage circuit and read the calculation results output by the storage circuit based on the input data and the stored weight data. In this embodiment, the first control circuit and the storage circuit can perform in-memory calculation.

[0070] Optionally, the die may include the first control circuit described above, and the second die may include a storage circuit. For example, when the second die includes a storage circuit, it may include an SRAM die, a DRAM die, or a flash die, etc., and the flash die may include, for example, a NAND flash die or a NOR flash die.

[0071] Optionally, the second die may include a stack, such as a high-bandwidth memory (HBM) stack, a flash stack, etc.

[0072] For example, the first circuit layer 1112 includes a portion formed within the first substrate 1111 and a portion formed outside the first substrate 1111.

[0073] Optionally, the second die 113 includes a second substrate 1132, on which a second circuit layer 1131 is formed. Thus, by forming the second circuit layer 1131 on the surface facing the first die 111, a higher data transmission rate between the second die 113 and the first die 111 can be achieved.

[0074] For example, a storage circuit can be used to store weight data (also known as weights); a control circuit can be used to control the operating state of the storage circuit. The operating states of the storage circuit include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit. In the calculation state, the storage circuit receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit includes a storage cell array, which includes multiple storage cells arranged in an array.

[0075] Storage cells can utilize the conduction capabilities of semiconductor devices, such as electrical conductance or transconductance, to store weight data. For example, a storage cell can include a resistive storage device or a transistor storage device. For instance, weight data can be stored by controlling the conductance of a resistive storage device, or by controlling the transconductance of a transistor storage device. Alternatively, a storage cell can also utilize a capacitor to store weight data.

[0076] For example, the storage circuit can perform calculations in groups. For instance, a storage cell array includes at least one storage cell group, which in turn includes multiple storage cells that can store multiple weight data, which can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or first data matrix) into the storage cell group within the storage cell array. In calculation mode, the storage circuit receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array includes one-dimensional arrays, two-dimensional arrays, or three-dimensional arrays, etc., and the storage cell group includes multiple storage cells located in the same row or column, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can output their output signals collinearly.

[0077] In some possible embodiments, the storage circuit may also receive signals from the input circuit. The input circuit may convert input data D1 into at least one input signal Sin and provide it to the storage circuit; the storage circuit may convert the received input signal Sin into an output signal Sout based on weight data; the output circuit may convert the output signal Sout into output data D2 and output it. The at least one input signal may be equivalent to a second data vector (or a second data matrix), and the output data D2 may be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0078] As an example, Figure 6 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0079] like Figure 6 As shown, the storage cell array 610 includes multiple storage cells S ij , where i [1,m],j [1, n], where m is the number of rows in the storage cell array and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data w ij When the memory cell array 610 is in the programming state, memory cell S ijThe conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 610 is in the computing state, it can be controlled through storage cell S ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula: .

[0080] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 610. i The input signal may include an analog signal. The input circuit 630 may, for example, include a digital-to-analog converter (DAC) to convert the digital signal into an analog signal for supplying to the memory cell array 610. In some possible embodiments, the input signal to the memory cell array 610 may include a digital signal, represented by waveform characteristics such as pulse width, amplitude, or area. The input circuit 630 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 610.

[0081] In some possible embodiments, the output circuit 640 may include at least one conversion circuit for converting the output signal of the memory cell array 610 and outputting it to a subsequent circuit. This conversion may include one or more of the following: signal type conversion, signal magnitude conversion, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 640 may include a first conversion circuit 641 for performing a first conversion on the output signal of the memory cell array 610. For instance, if the output signal of the memory cell array 610 includes a current signal, the first conversion circuit 641 can convert the current signal into a voltage signal. Alternatively, the output circuit 640 may include a second conversion circuit 642 for performing a second conversion on the output signal of the memory cell array 610. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 641 may be further provided to the second conversion circuit 642 for a second conversion. For example, the first conversion circuit 641 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 642 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense, amplify, or process the signal obtained from the memory cell array 610 or the first conversion circuit 641. Furthermore, in Figure 6 In the example, the in-memory computing system 600 may further include a control circuit 620, which can be used to control the memory cells S in the memory cell array 610. ij The running state, such as the programming state and computation state mentioned above.

[0082] Optionally, the TIA and ADC can be fully or partially housed in the first control circuit of the first circuit layer 1112. Alternatively, the TIA and ADC can be fully or partially integrated with the storage circuit on the same circuit layer.

[0083] Figure 6 This is merely an example illustrating a connection method of memory cells in a memory cell array 610, except... Figure 6Besides the connection method shown, other connection methods can also be used. For example, the input terminals of the memory cells are connected in columns and in rows. Furthermore, the input terminal of the memory cell may include the gate of a transistor memory device, or it may include the source or drain of a transistor memory device; this application does not limit this. This application also does not limit the type of memory cell; the memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, such as metal oxide semiconductor field-effect transistors (MOSFETs), floating gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors. Furthermore, a memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, where the gate of one transistor is connected to the source or drain of the other transistor, and the charge stored at the gate can be used to characterize weight data. Optionally, the gate can also be connected to a capacitor to increase the stability and duration of the stored charge.

[0084] Optionally, the first circuit layer 1112 includes a first control circuit, and the second circuit layer 1131 includes a storage circuit. The first control circuit is used to read data from the storage circuit and perform calculations on the data. The first control circuit and the storage circuit in this embodiment can be used for near-memory computation.

[0085] For example, the first storage circuit is a three-dimensional storage circuit that includes a multi-layer storage cell array in a first direction.

[0086] For example, Figure 7 Another schematic structural diagram of the semiconductor device 100 provided in this application is shown.

[0087] The semiconductor device 100 further includes: a third die 117 stacked on the second die 113 along a first direction, and the third die 117 includes a third circuit layer 1171; and a second interconnect structure 118 for connecting the third circuit layer 1171 and the second circuit layer 1131.

[0088] In the above structure, the semiconductor device includes more dies. The die positions are flexibly designed according to the transmission content between the dies, so that the connection method and transmission content between the dies are more compatible, improving transmission efficiency while reducing the complexity of the wiring. For example, the first die and the second die can be connected face to face, or the second die and the third die can be connected face to face. The face-to-face connection between the dies can meet the requirements of high-speed data transmission or high-speed control.

[0089] Optionally, the semiconductor device 100 further includes a third interconnect structure 119 for connecting the first circuit layer 1112 and the third circuit layer 1171.

[0090] Reference Figure 8 The second interconnect structure 118 includes a portion disposed between the second die 113 and the third die 117. Optionally, the second interconnect structure 118 may also include a portion disposed within the second die 113. For example, the second interconnect structure 118 may further include a connection structure, such as a TSV, disposed in the substrate of the second die 113. For example, the second interconnect structure 118 may further include a connection structure, such as a wiring structure, disposed in the second circuit layer of the second die 113.

[0091] Optionally, the second interconnect structure 118 may further include portions disposed within the third die 117. For example, the second interconnect structure 118 may further include connection structures, such as TSVs, disposed in the substrate of the third die 117. For example, the second interconnect structure 118 may further include connection structures, such as wiring structures, disposed in the third circuit layer of the third die 117.

[0092] For example, if the second die 113 is a storage die, then the third die 117 can be a control die. The second circuit layer 1131 of the second die 113 may include a first storage circuit. The third circuit layer 1171 of the third die 117 may include a second control circuit. The first circuit layer 1112 of the first die 111 may include a first control circuit. The first control circuit can communicate with the first storage circuit via data; the first control circuit can communicate with the second control circuit via signaling; the second control circuit can control the first storage circuit based on the signaling of the first control circuit.

[0093] For example, the first control circuit can send a read signal to the second control circuit, and the second control circuit can activate some storage cells in the first storage circuit based on the read signal, so that the first control circuit can read the data in these storage cells.

[0094] By placing the first storage circuit between the two control circuits, high-speed or high-bandwidth data transmission can be achieved between the first control circuit and the first storage circuit, providing a tighter / more reliable coupling method. Furthermore, signaling control can be implemented between the first and second control circuits. Since the bandwidth of signaling control is less than the data bandwidth, the requirements for interconnect structures are lower, thus reducing the complexity of the interconnect structures within the bonding layer and circuit layer. Moreover, by using the second control circuit to parse the signaling from the first control circuit and convert it into operational control of the storage circuit, the complexity requirements for the storage circuit can be reduced. Furthermore, implementing the signaling parsing and the specific operation control of the storage circuit in the vertical direction allows for more efficient use of the horizontal area of ​​the storage circuit, maximizing its use for dense storage or computation.

[0095] For example, if the second die 113 is a control die, then the third die 117 can be a storage die. For example, if the second die 113 is a control die, then the third die 117 can be multiple storage dies stacked along a first direction. The second circuit layer of the second die 113 includes a second control circuit, and the third circuit layer of the third die includes a first storage circuit. Using this structure, multiple third dies (storage dies) can be stacked along the first direction within the die group, which is beneficial for expanding the computing power or storage capacity of the first die group.

[0096] Optionally, the first circuit layer 1112 includes a first control circuit, and the second circuit layer 1131 or the third circuit layer 1171 includes a first storage circuit. The first control circuit is used to input data into the first storage circuit and read the calculation result output by the first storage circuit based on the input data and the stored weight data. In the embodiments of this application, the first control circuit and the first storage circuit can realize in-memory calculation.

[0097] Optionally, the third die 117 includes a third substrate 1172, on the surface of the third substrate 1172 facing the second die 113, a third circuit layer 1171 is formed.

[0098] Figure 7 The bonding methods between the dies are for illustrative purposes only. Optionally, the first and second dies can be bonded face-to-face, i.e., the first and second circuit layers are stacked opposite each other. Optionally, the second and third dies can be bonded face-to-back / back-to-face, i.e., the second circuit layer and the third substrate or the second substrate and the third circuit layer are stacked opposite each other.

[0099] Face-to-face bonding can be used for data transmission; face-to-back / back-to-face or back-to-back bonding can be used for signaling transmission, thus improving data transmission speed. Signaling control bandwidth is less than data bandwidth, requiring less interconnect structure, thereby reducing the complexity of interconnect structures within the bonding layer and circuit layer, and improving data transmission speed in semiconductor devices by shortening the data transmission distance between dies.

[0100] This application embodiment also provides a memory computing system, which includes the above-mentioned semiconductor device 100 and a substrate, including in-board wiring, which is used to connect the semiconductor device and the pins of the memory computing system or to connect the semiconductor device and other semiconductor devices.

[0101] This application also provides an electronic device, including the semiconductor device 100 described above, or including the in-memory computing system described above.

[0102] This application also provides an electronic device, which can be found in [reference 1]. Figure 8 . Figure 8 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Figure 8 As shown, the electronic device 800 may include any of the above-mentioned in-memory computing systems 810 for processing data of the electronic device. The electronic device may also include an input / output device 820 for receiving user input or outputting processing results. This application does not limit the input type and output type; for example, input may include voice input, text input, image input, or video input. Output may include text output, voice output, image output, or video output. The electronic device may also include a processor 830, which can process data provided to the in-memory computing system 810 or process the output data of the in-memory computing system 810. The output of the input / output device 820 may include output based on the processor 830 or output based on the in-memory computing system 810.

[0103] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic devices. According to some embodiments, the electronic device may also include devices such as servers.

[0104] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A semiconductor device, characterized in that, include: The first die includes a first substrate and a first circuit layer, the first circuit layer being formed in a first direction of the first substrate, and the first circuit layer including an interface circuit for external communication. An inductor is connected to the interface circuit. The second die is stacked on the first die along the first direction, and the second die includes a second circuit layer; A first interconnect structure is used to connect the first circuit layer and the second circuit layer.

2. The semiconductor device according to claim 1, characterized in that, The inductor includes: An inductor layer is formed on the side of the first substrate opposite to the first circuit layer.

3. The semiconductor device according to claim 2, characterized in that, The inductor layer includes: The first conductive structure is connected to the interface circuit; The second conductive structure is connected to the first conductive structure.

4. The semiconductor device according to claim 2 or 3, characterized in that, The semiconductor device further includes: A wiring layer, formed on the side of the inductor layer opposite to the first substrate, is used to connect the external terminals of the semiconductor device.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that, The semiconductor device further includes: The first shielding structure is used to shield the traces of the interface circuit.

6. The semiconductor device according to claim 1, characterized in that, The inductor includes: An active inductor is formed within the first circuit layer.

7. The semiconductor device according to claim 1, characterized in that, The inductor includes: An inductor structure is formed on the side of the first substrate facing the first circuit layer; The second shielding structure is used to shield the inductor structure.

8. The semiconductor device according to claim 6 or 7, characterized in that, A wiring layer is formed on the surface of the first substrate opposite to the second die for connecting the external terminals of the semiconductor device.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The semiconductor device further includes: A third die is stacked on top of the second die along the first direction, and the third die includes a third circuit layer; The second interconnect structure is used to connect the third circuit layer and the second circuit layer.

10. The semiconductor device according to claim 9, characterized in that, The third die includes a third substrate, on the surface of the third substrate facing the second die, the third circuit layer is formed.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The second die includes a second substrate; The second circuit layer is formed on the surface of the second substrate facing the first die; or, the second circuit layer is formed on the surface of the second substrate away from the first die.

12. An in-memory computing system, characterized in that, include: The semiconductor device as claimed in any one of claims 1 to 11; A substrate, including in-board traces, the in-board traces being used to connect the semiconductor device to the pins of the in-memory computing system or to connect the semiconductor device to other semiconductor devices.

13. An electronic device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 11, or the in-memory computing system as described in claim 12.

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