Semiconductor device

Abstract

A semiconductor device having different types of memory devices in the same chip is provided. A data transfer speed between two memory devices is improved. The semiconductor device includes a first layer, a second layer, and a third layer. The first layer includes a first memory device in which a plurality of nonvolatile first memory elements are stacked in a thickness direction of the first layer. The second layer includes a second memory device including a plurality of second memory elements including a transistor including an oxide semiconductor. The third layer includes a first driver circuit which controls an operation of the first memory device and a second driver circuit which controls an operation of the second memory device. The first layer, the second layer, and the third layer have a portion which overlaps with each other.

Description

[0001] This application is a divisional application of the invention patent application with application number 202480012610.5, application date March 11, 2024, international application number PCT / IB2024 / 052308, national phase entry date August 14, 2025, and invention title "Semiconductor Device". Technical Field

[0002] One aspect of the present invention relates to a storage device. Another aspect of the present invention relates to a semiconductor device including a storage device.

[0003] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, or manufacturing methods thereof. A semiconductor device refers to any device capable of operating using the characteristics of a semiconductor. Background Technology

[0004] Non-volatile storage devices are integrated into various mobile devices, such as smartphones and tablets, smartwatches, and wearable devices for AR (Augmented Reality) or VR (Virtual Reality). While hard disk drives have been the primary non-volatile storage devices until now, flash memory is increasingly used in these mobile devices due to its shock resistance, miniaturization, lightweight design, and lack of physical operation.

[0005] On the other hand, transistors containing oxide semiconductors (also known as oxide semiconductor transistors, OS (Oxide Semiconductor) transistors) are known. OS transistors have the characteristic of having extremely small drain current (also known as off-state current) when the transistor is in the off state. Patent Document 1 discloses a NAND-type memory device using OS transistors.

[0006] [Preliminary Technology Documents]

[0007] [Patent Literature]

[0008] [Patent Document 1] International Patent Application Publication No. 2022 / 0068967 Summary of the Invention

[0009] The technical problem that the invention aims to solve

[0010] Data stored in non-volatile memory devices used for storage is often temporarily read out to higher-level storage devices such as DRAM and sent to the processor. Therefore, the faster the data transfer speed between the non-volatile memory device and DRAM, the better.

[0011] One objective of this invention is to provide a semiconductor device that includes different types of memory devices within the same chip. Another objective of this invention is to improve the data transfer speed between two memory devices. Finally, another objective of this invention is to provide a semiconductor device that includes two types of memory devices and peripheral circuitry within the same chip.

[0012] One objective of this invention is to provide a highly reliable storage device or semiconductor device. Another objective of this invention is to provide a storage device or semiconductor device with a novel structure. Finally, one objective of this invention is to improve at least one of the problems of the prior art.

[0013] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not necessarily require achieving all of the above objectives. Note that objectives other than those described above can be extracted from the description in the specification, drawings, claims, etc.

[0014] means of solving technical problems

[0015] One aspect of the present invention is a semiconductor device comprising a first layer, a second layer, and a third layer. The first layer comprises a first storage device comprising a plurality of non-volatile first storage elements stacked in the thickness direction of the first layer. The second layer comprises a second storage device having a plurality of second storage elements. The second storage elements include transistors having oxide semiconductors. The third layer comprises a first driving circuit for controlling the operation of the first storage device and a second driving circuit for controlling the operation of the second storage device. The first layer and the second layer, the second layer and the third layer, and the first layer and the third layer each have overlapping portions.

[0016] Furthermore, in the aforementioned semiconductor device, the first layer is preferably located on the third layer. In this case, the second layer is preferably located on the third layer.

[0017] Furthermore, in the aforementioned semiconductor device, the third layer is preferably located between the first layer and the second layer.

[0018] Furthermore, in the aforementioned semiconductor device, the first storage element preferably includes a first conductive layer, a first semiconductor layer, and a functional layer located therebetween. In this case, the functional layer preferably includes a thin film exhibiting ferroelectric properties.

[0019] Furthermore, in the aforementioned semiconductor device, the first storage element preferably includes a first conductive layer, a first semiconductor layer, and a functional layer located therebetween. In this case, the functional layer preferably contains at least one of hafnium and zirconium. Additionally, the functional layer preferably also contains scandium, yttrium, and one or more elements belonging to the lanthanides.

[0020] Furthermore, in the aforementioned semiconductor device, the transistor preferably includes a gate insulating layer. In this case, the gate insulating layer preferably comprises a thin film exhibiting ferroelectric properties.

[0021] Furthermore, in the aforementioned semiconductor device, the second layer preferably includes an insulating layer. Moreover, the transistor preferably includes a source electrode, a drain electrode, and a second semiconductor layer. In this case, the source electrode and the drain electrode are preferably in contact with the second semiconductor layer. Additionally, one of the source electrode and the drain electrode is preferably located above the insulating layer, and the other of the source electrode and the drain electrode is preferably located below the insulating layer.

[0022] Invention Effects

[0023] According to one aspect of the present invention, a semiconductor device comprising different types of memory devices within the same chip can be provided. Furthermore, the data transfer speed between the two memory devices can be improved. Additionally, a semiconductor device comprising two types of memory devices within the same chip and peripheral circuitry can be provided.

[0024] Furthermore, according to one aspect of the present invention, a highly reliable storage device or semiconductor device can be provided. Additionally, a storage device or semiconductor device with a novel structure can be provided. According to one aspect of the present invention, at least one of the problems in the prior art can be improved.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the invention does not necessarily require all of the above-described effects. Note that effects other than those described above can be extracted from the description in the specification, drawings, claims, etc. Brief description of the attached figures

[0026] Figure 1A and Figure 1B This is an example of the structure of a semiconductor device.

[0027] Figures 2A to 2C This is an example of the structure of a semiconductor device.

[0028] Figures 3A to 3E This is an example of the structure of a storage device.

[0029] Figure 4 This is an example of the structure of a semiconductor device.

[0030] Figure 5 This is an example of the structure of a semiconductor device.

[0031] Figure 6 This is an example of the structure of a storage device.

[0032] Figures 7A to 7C This is an example of the structure of a storage device.

[0033] Figure 8 This is an example of the structure of a semiconductor device.

[0034] Figure 9A and Figure 9B This is an example of the structure of a storage device.

[0035] Figure 10 This is a graph illustrating the hysteresis characteristic.

[0036] Figure 11A and Figure 11B This is an example of the structure of a storage device.

[0037] Figure 12 This is an example of the structure of a semiconductor device.

[0038] Figure 13 This is an example of the structure of a semiconductor device.

[0039] Figure 14 This is an example of the structure of a semiconductor device.

[0040] Figure 15 This is an example of the structure of a semiconductor device.

[0041] Figure 16 This is an example of the structure of a semiconductor device.

[0042] Figure 17 This is an example of the structure of a semiconductor device.

[0043] Figure 18 This is an example of the structure of a semiconductor device.

[0044] Figure 19 This is an example of the structure of a semiconductor device.

[0045] Figure 20 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0046] Figures 21A to 21H This is a diagram illustrating an example of the circuit structure of a memory cell.

[0047] Figure 22A and Figure 22B This is a three-dimensional diagram illustrating an example of a semiconductor device structure.

[0048] Figure 23 This is a block diagram illustrating the CPU.

[0049] Figure 24A and Figure 24B It is a 3D diagram of a semiconductor device.

[0050] Figure 25A and Figure 25B It is a 3D diagram of a semiconductor device.

[0051] Figure 26A and Figure 26B It is a diagram that shows various storage devices in a hierarchical manner;

[0052] Figures 27A to 27J This is a diagram illustrating an example of an electronic device.

[0053] Figures 28A to 28E This is a diagram illustrating an example of an electronic device.

[0054] Figures 29A to 29C This is a diagram illustrating an example of an electronic device.

[0055] Figure 30 This is a schematic diagram of an example of a space device.

[0056] Methods of implementing the invention

[0057] The embodiments will now be described with reference to the accompanying drawings. Note that the embodiments can be implemented in many different ways, and those skilled in the art will readily understand that the methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the following embodiments.

[0058] Note that in the structure of the invention described below, the same reference numerals are used across different figures to denote the same parts or parts having the same function, without omitting repeated descriptions. Furthermore, when denoteing parts with the same function, the same shading lines are sometimes used without additional reference numerals.

[0059] Note that in the accompanying drawings described in this specification, the size of structural elements, the thickness of layers, or areas are sometimes exaggerated for ease of understanding. Therefore, the invention is not limited to the dimensions shown in the drawings.

[0060] The ordinal numbers such as "first" and "second" used in this specification are appended to avoid confusion of structural elements, not to limit the number. (Implementation Method 1)

[0061] In this embodiment, a semiconductor device and a memory device according to one aspect of the present invention are described.

[0062] One aspect of the present invention is a semiconductor device comprising two storage devices. The semiconductor device has a stacked structure comprising a first layer including storage cells (also called storage elements) of a first storage device, a second layer including storage cells of a second storage device, and a third layer including a first driving circuit for controlling the operation of the first storage device and a second driving circuit for controlling the operation of the second storage device. This allows for a reduction in the wiring length between the first and second storage devices, thereby increasing the amount of data exchanged between them per unit time.

[0063] The first storage device preferably includes non-volatile storage elements used for storage. Furthermore, it preferably has a larger data capacity than the second storage device. For example, a high-capacity storage device having a so-called three-dimensional structure in which storage elements are arranged not only in the in-plane direction of the first layer but also stacked in the thickness direction is preferred. More specifically, a 3D-NAND type storage device comprising a memory string extending in the normal direction of the formed surface is preferred.

[0064] As the first storage device, a non-volatile storage device utilizing ferroelectric materials is preferred. This allows for a storage device with higher reliability and lower power consumption compared to so-called charge-trapping storage elements.

[0065] The second storage device is preferably a storage device with a faster access speed than the first storage device. The second storage device can also be a volatile storage device whose information is lost when power is cut off. More specifically, DRAM (Dynamic Random Access Memory) can be used.

[0066] Furthermore, as a second storage device, a storage device is more preferably adopted in which the storage cell uses a transistor (OS transistor) in which oxide semiconductor is used for the channel formation region. Due to the extremely low leakage current of the OS transistor in the off state, the storage device using OS transistors can retain data for a longer period compared to DRAM, thereby reducing power consumption. Moreover, oxide semiconductors can be formed as thin films, so OS transistors can be fabricated on any surface to which they are formed. For example, there is an advantage that circuits composed of OS transistors can be directly stacked on semiconductor circuits such as those made of single-crystal silicon.

[0067] The following are more specific examples, with reference to the accompanying drawings.

[0068] Figure 1A A semiconductor device 10 according to one aspect of the present invention is shown. The semiconductor device 10 has a structure in which layers 11, 12 and 13 are stacked sequentially. Layer 12 is sandwiched between layers 11 and 13.

[0069] Figure 1BThis diagram shows the layers of the semiconductor device 10 separately. Layer 13 includes a storage device 31 having multiple storage elements (storage cells) and a connection portion 32. Layer 12 includes a storage device 21 having multiple storage elements and a terminal portion 22. Layer 11 includes a drive circuit 43 for controlling the operation of the storage device 31 and a drive circuit 42 for controlling the operation of the storage device 21.

[0070] Layer 12 can use storage devices with larger data capacity than Layer 13 and that include non-volatile storage elements. On the other hand, Layer 13 can use storage devices with faster access speeds than Layer 12.

[0071] The drive circuit 43 is connected to the drive circuit 42 via wiring 45, enabling data communication between them. For example, data can also be transferred from storage device 31 to storage device 21 via drive circuit 43, wiring 45, and drive circuit 42. Conversely, data can also be transferred from storage device 21 to storage device 31.

[0072] The semiconductor device 10 is provided with a plurality of plugs 23 that connect the circuit (here, the drive circuit 42) disposed in layer 11 to the terminal portion 22 of layer 12. Additionally, the semiconductor device 10 is provided with a plurality of plugs 33 that connect the circuit (here, the drive circuit 43) disposed in layer 11 to the connection portion 32 of layer 13. A portion of the plugs 33 penetrates layer 12.

[0073] By adopting the above structure, the footprint can be significantly reduced compared to arranging two storage devices and two drive circuits in a single configuration. Furthermore, compared to arranging the storage devices and drive circuits in a single configuration, the wiring length between them can be shortened, thus reducing wiring overhead. Therefore, the speed of data writing and reading can be improved in each storage device.

[0074] In addition, Figure 1B The area overlapping with the terminal portion 22 in layer 13 can also be used as part of the storage device 31. That is, the storage device 31 can have a structure that includes the portion overlapping with the terminal portion 22 in layer 12. By effectively utilizing space, the data capacity of the storage device 31 can be increased, which is therefore preferred.

[0075] Figure 2A This is an example of a case where the positions of layer 12 and layer 13 are swapped, with layer 13 located between layers 11 and 12. In this case, a portion of plug 23 penetrates layer 13.

[0076] In addition, such as Figure 2B As shown, layer 11 can also be positioned between layers 12 and 13. Figure 2B In the middle, layer 11 is located above layer 12, and layer 13 is located above layer 11.

[0077] also, Figure 2C It is an exchange Figure 2B Examples of the positions of layers 12 and 13: layer 11 is located on layer 13, and layer 12 is located on layer 11.

[0078] exist Figure 2B and Figure 2C In the structure shown, plugs 23 and 33 can also be designed so that neither side penetrates other layers. Therefore, the physical length of plugs 23 and 33 can be shortened, thus increasing operating speed. Furthermore, the areas in layer 12 that overlap with plug 33 and the areas in layer 13 that overlap with plug 23 can be used as storage devices 21 and 31, respectively, thereby increasing the data capacity of both storage devices.

[0079] Next, an example of a structure that can be used for the storage device 21 disposed in layer 12 will be described. Figure 3A This is a three-dimensional schematic diagram of storage device 21.

[0080] The storage device 21 is disposed on the insulating layer 50 and includes a plurality of memory strings 60. The memory strings 60 include a plurality of unit transistors stacked in a direction perpendicular to the top surface of the insulating layer 50. Furthermore, the storage device 21 includes a plurality of conductive layers 51, 52, 53, 54, and 55 for various wiring, as well as a plurality of connectors 56.

[0081] exist Figure 3A In the diagram, arrows indicate the mutually orthogonal X, Y, and Z directions. The memory strings 60 are arranged at equal intervals in the X and Y directions. Figure 3A The diagram illustrates, as an example, a block comprising 5×5 memory strings 60. Storage device 21 includes multiple such blocks. Note that, in practice, a block preferably includes more memory strings 60.

[0082] A memory string 60 is configured to connect conductive layers 53 and 54. For example, conductive layer 53 is used as a source line, and conductive layer 54 is used as a bit line. Additionally, multiple conductive layers 51 are stacked between conductive layers 53 and 54. Conductive layers 51 are used as control gate lines. Furthermore, a conductive layer 52 serving as a select line is disposed between the uppermost conductive layer 51 and conductive layer 54. The multiple conductive layers 51 are each connected to one of multiple conductive layers 55 via connectors 56.

[0083] Conductive layers 54 and 52 extend in directions that intersect each other, forming a 5×5 matrix. Additionally, conductive layers 51 and 53 are connected to all memory strings 60 (here, 5×5 strings) within their respective blocks.

[0084] Note that although Figure 3(A) shows an example of a structure with five conductive layers 51, the number of layers is not limited to this. A higher number of layers results in a greater number of unit transistors constituting a memory string 60, thereby increasing the data capacity of the storage device 21. The more unit transistors constituting a memory string 60, the better; for example, it can be 64 or more, 128 or more, 160 or more, 192 or more, 224 or more, or 256 or more.

[0085] Figure 3B Selectively shown is a memory string 60 and its surrounding structure. The portion of the memory string 60 that intersects with the conductive layer 51 is provided with memory cells 65 serving as unit transistors. The lowermost conductive layer 51 of the plurality of conductive layers 51 can also be used as a select line.

[0086] Figure 3C yes Figure 3B The circuit diagram of the structure shown is as follows. Conductive layer 53 corresponds to wiring CL, conductive layer 54 corresponds to wiring BL, the bottom conductive layer 51 corresponds to wiring SSL, and all other conductive layers 51 correspond to wiring WL (wiring WL1 to wiring WLm (m is an integer greater than 2)). Conductive layer 52 corresponds to wiring BSL.

[0087] like Figure 3C As shown, a transistor STr, multiple transistors CTr, and a transistor BTr are disposed between wiring BL and wiring CL. Transistors STr and BTr are used as select transistors, and transistor CTr is used as a unit transistor. Transistor CTr is used as a storage element.

[0088] Furthermore, the transistor CTr can be, for example, a charge-trapping flash memory or a floating-gate flash memory. Alternatively, a memory element utilizing ferroelectric materials can be used, having a structure in which a ferroelectric capacitor is connected to the gate, a structure in which the ferroelectric material is used as the gate insulating layer, or a structure in which a ferroelectric capacitor is connected to one of the source and drain electrodes.

[0089] Figure 3D and Figure 3E Showing the use in Figure 3B and Figure 3C This is an example where a pair of memory strings constitute a memory string 60. In this case, conductive layer 53 is used as the gate line of the channel, and conductive layer 57 is used as the source line. The transistor PTr, located at the bottom of the U-shaped memory string, is used as a select transistor (also called a channel transistor) to connect the pair of memory strings. The gate of transistor PTr is connected to wiring PL.

[0090] Next, an example of a structure that can be used for storage device 21, storage device 31, drive circuit 42, and drive circuit 43 will be described.

[0091] Figure 4 This is a block diagram illustrating an example structure of the OSC circuit and the MCL memory cell section. The OSC circuit is the circuit included in the drive circuits 42 and 43, while the MCL memory cell section is the circuit including the memory cells included in the storage device 21. Furthermore, in Figure 4 The memory cell section OMCL is shown in the diagram. The memory cell section OMCL is a circuit that includes the memory cells included in the memory device 31.

[0092] The memory cell section (MCL) includes a memory cell array (MCA). The memory cell array (MCA) includes multiple memory strings (SRGs). The memory strings (SRGs) are electrically connected to wiring (BL). The memory strings (SRGs) include multiple transistors (CTr), selection transistors (BTr), and transistors (STr) connected in series. Note that a semiconductor CTR is used as a cell transistor and is included in the memory cell (MC) included in the string (SRG).

[0093] A single-cell transistor is a transistor that operates with normally-on characteristics and includes a control gate and a charge storage layer. The charge storage layer is disposed in a region overlapping the channel formation region with a tunnel insulating film. The control gate is disposed in a region overlapping the charge storage layer with a barrier film. In the single-cell transistor, a tunneling current is generated by applying a write potential to the control gate and supplying a predetermined potential to the first or second terminal of the single-cell transistor, injecting electrons from the channel formation region of the single-cell transistor into the charge storage layer. As a result, the threshold voltage increases in the single-cell transistor in which electrons are injected into the charge storage layer. Alternatively, a floating gate can be used instead of the charge storage layer.

[0094] Alternatively, a structure in which a ferroelectric capacitor is connected to the gate or a structure in which a ferroelectric material is used as the gate insulating layer can be used as a unit transistor. By adopting the above structures, reliability can be further improved and power consumption can be reduced.

[0095] The channel forming regions of transistors BTr, CTr, and STr preferably include any one of silicon, germanium, gallium arsenide, silicon carbide (SiC), metal oxide, or multiple materials selected from the above materials.

[0096] In particular, in the channel formation region, an oxide of one or more metals selected from indium, element M (e.g., selected from aluminum, gallium, yttrium, tin), and zinc is preferably used. This metal oxide can be used as a wide-bandgap semiconductor, enabling transistors BTr, CTr, and STr containing this metal oxide in the channel formation region to have very low off-state currents. That is, since the leakage current of transistors BTr, CTr, and STr in the off-state can be reduced, the power consumption of the memory device can sometimes be reduced.

[0097] Note that, although Figure 4 An example is shown where transistors BTr and STr are formed in the memory cell section MCL, but transistors BTr and STr can also be formed in the circuit OSC.

[0098] Furthermore, the storage cell array MCA comprises multiple storage cells MC within the string SRG. These multiple storage cells MC are configured in a row-column structure (also known as a matrix). Note that the storage cell array MCA comprises m cells in one column and n cells in one row, i.e., a total of m×n storage cells MC (where m and n are integers greater than or equal to 2). Additionally, the storage cell MC located in row i and column j (where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n) is denoted as MC[i, j].

[0099] Routing lines WL consist of multiple word lines, each row of which is electrically connected to the memory cell MC. Routing lines BL consist of multiple bit lines, each column of which is electrically connected to the memory cell MC. Additionally, routing lines CL are power lines.

[0100] Next, the connection structure of the SRG series is explained. Transistor BTr, multiple transistors CTr, and transistor STr are connected in series. Transistor BTr is electrically connected to wiring BL, and transistor STr is electrically connected to wiring BL.

[0101] The BSL and SSL wires are used to select the string during write, read, and delete operations. The BSL wire is electrically connected to the gate of the BTR transistor, and the SSL wire is electrically connected to the gate of the STr transistor.

[0102] Note that although a structure is used where a series SRG is electrically connected to a wiring BL, this invention is not limited to this. For example, as Figure 5 As shown, the memory cell section MCL can also employ a structure where multiple serial SRGs are electrically connected to a single wiring BL. Note that... Figure 5 The block diagram shows a portion of the memory cell section MCL and the circuit OSC.

[0103] The OSC circuit includes the control circuit CTR, the PRPH circuit, the ORPH circuit, and the output circuit OUTP. The control circuit CTR receives control signals CS (clock signal, chip enable signal, write enable signal, address signal, etc.) and data signals WDATA from outside the semiconductor device 10.

[0104] Circuit PRPH is equivalent to the aforementioned drive circuit 42, and circuit ORPH is equivalent to the aforementioned drive circuit 43. Here, although an example is shown where circuits PRPH and ORPH jointly use control circuit CTR and output circuit OUTP, they may each have one or both of control circuit CTR and output circuit OUTP.

[0105] The control circuit CTR has the function of writing data to the memory cell section MCL and reading data from the memory cell section MCL via the access circuit PRPH. Additionally, the control circuit CTR has the function of accessing the memory cell section ORPH and writing data to the memory cell section OMCL and reading data from the memory cell section OMCL.

[0106] For example, when a write command based on the control signal CS and a data signal WDATA are input from outside the semiconductor device 10, the control circuit CTR first writes the data signal WDATA to the memory cell section OMCL. Then, it reads the data written from the memory cell section OMCL and writes the read data to the memory cell section MCL. That is, the memory cell section OMCL can be considered as a cache memory for the memory cell section MCL. Note that when the amount of data in the data signal WDATA is small, the control circuit CTR can have the function of directly writing to the memory cell section MCL without going through the memory cell section OMCL.

[0107] When a read command based on the control signal CS is input from outside the semiconductor device 10, the control circuit CTR reads data from the memory cell section MCL (if the data exists in the memory cell section OMCL, it can also be read from the memory cell section OMCL) and outputs it to the output circuit OUTP. The output circuit OUTP outputs the data signal RDATA to the outside of the semiconductor device 10. Note that write commands and read commands include address signals.

[0108] Additionally, the control circuit CTR can also perform error detection and correction (also known as ECC: Error Check and Correct) when reading data from the memory cell section MCL. The memory cell section OMCL can also be used as a cache memory for error detection and correction by the control circuit CTR. Note that the signals processed by the control circuit CTR and the functions of the control circuit CTR are not limited to these; other signals can be input (or output) as needed, and the control circuit CTR can also have other functions.

[0109] In other words, the control circuit CTR can write the data signal WDATA input from the outside of the semiconductor device 10 to the memory cell OMCL, read the written data from the memory cell OMCL, and write the read data back to the memory cell OMCL. Because the data signal WDATA input from the outside of the semiconductor device 10 moves through the connector in the semiconductor device 10, the data travel distance is short.

[0110] The semiconductor device 10 includes a memory cell section OMCL. Because the data movement distance between the memory cell section OMCL and the memory cell section MCL is short, it has the characteristics of low signal transmission delay, high-speed operation, and suppression of power consumption increases due to parasitic capacitance. The memory cell section OMCL can be used as a high-speed cache memory in the semiconductor device 10. That is, it can be used as a storage device to temporarily store data sent from or received from the semiconductor device 10, for example, from the processor.

[0111] The PRPH circuit includes, for example, a WLD circuit, a BLD circuit, and a CVC circuit. The WLD circuit is used as a word line driver circuit and is electrically connected to the WL wiring. The BLD circuit is used as a bit line driver circuit and is electrically connected to the BL wiring. The CVC circuit is used to generate a constant potential and output this constant potential power supply and is electrically connected to the CL wiring. Note that the PRPH circuit may also exclude the CVC circuit; for example, the CVC circuit may be located outside the semiconductor device 10. In this case, the semiconductor device 10 has a structure that supplies a constant potential to the memory cell section MCL from the outside.

[0112] The ORPH circuit includes, for example, the OWLD and OBLD circuits. The OWLD circuit is used as a word line driver circuit and is electrically connected to wiring wwl and rwl. The OBLD circuit is used as a bit line driver circuit and is electrically connected to wiring wbl and rbl.

[0113] Next, an example of the structure of the storage cell section OMCL will be described. Figure 6 This is a block diagram illustrating an example of the structure of the OMCL (Memory Cell Unit).

[0114] Note that the storage unit OMCL consists of s units in one column and t units in one row, totaling s × t storage units OMC (where s and t are integers greater than or equal to 2). The storage units OMC are arranged in a matrix. Figure 4 In this context, the storage cell OMC located in row p and column r (where p is an integer greater than 1 and less than s, and r is an integer greater than 1 and less than t) is recorded as OMC[p, r]. Furthermore, similar to the storage cell section MCL, the storage cell section OMCL can also have a structure in which the storage cells are arranged in three dimensions.

[0115] Wiring wwl and wiring rwl are electrically connected to multiple memory cells OMC arranged in the row direction. Additionally, wiring wbl and wiring rbl are electrically connected to multiple memory cells OMC arranged in the column direction.

[0116] Figure 7A This is a circuit diagram illustrating an example of the structure of a memory cell OMC. The memory cell OMC includes transistor M11, transistor M12, and capacitor C11.

[0117] In transistor M11, one of the source and drain terminals is electrically connected to the gate of transistor M12 and one terminal of capacitor C11, while the other terminal is electrically connected to wiring wbl. The gate is electrically connected to wiring wwl. In transistor M12, one of the source and drain terminals is electrically connected to wiring rbl, while the other terminal is electrically connected to wiring rwl. The other terminal of capacitor C11 is electrically connected to wiring CAL. Wiring CAL is subjected to a specified potential. The connection point to transistor M12 is called node N11.

[0118] Note that in this manual, etc., the term "terminal" is used to describe the input and output of signals, potentials, etc. between the constituent elements. In actual circuits, there are sometimes no physical connections such as "terminals" but only electrical connections such as wiring or electrodes.

[0119] In the memory cell OMC, wiring wbl is used as the write bit line, wiring rbl is used as the read bit line, wiring wwl is used as the write word line, and wiring rwl is used as the read word line. Transistor M11 is used as a switch to turn node N11 on or off with wiring wbl.

[0120] Data is written by applying a high-level potential to wiring wwl, which turns on transistor M11 and electrically connects node N11 to wiring wbl. Specifically, when transistor M11 is on, a potential corresponding to the data to be written is applied to wiring wbl to write that potential to node N11. Then, a low-level potential is applied to wiring wwl, which turns off transistor M11, thereby maintaining the potential of node N11.

[0121] Data is read out by applying a specified potential to the wiring rbl, causing it to float (or be in a floating state), and then applying a low-level potential to the wiring rwl. This process of applying a specified potential to the wiring and then causing it to float is called pre-charging.

[0122] For example, by pre-charging the wiring rbl with potential Vdd, a potential difference is supplied between the source and drain of transistor M12. Since the current flowing between the source and drain of transistor M12 is determined by the potential held by node N11, the potential held by node N11 can be read by reading the potential change of wiring rbl when it is in a floating state.

[0123] The row of memory cells (OMCs) configured to write data is selected by applying a high-level potential to the wiring wwl, and the row of memory cells (OMCs) configured to read data is selected by applying a low-level potential to the wiring rwl. Conversely, applying a low-level potential to the wiring wwl deselects the behavior of memory cells (OMCs) configured not to write data, and applying the same potential to the wiring rwl as the pre-charge potential to the wiring rbl deselects the behavior of memory cells (OMCs) configured not to read data.

[0124] Transistors M11 and M12 can use OS transistors. OS transistors have very small off-state currents, so by using an OS transistor as transistor M11, the potential written to node N11 can be maintained for a long time. That is, data written to the memory cell OMC can be maintained for a long time. Alternatively, by using an OS transistor as transistor M11, the capacitance of capacitor C11 in the memory cell OMC can also be reduced. Alternatively, by using an OS transistor as transistor M11, such as... Figure 7B As shown, the memory cell OMC may also not include capacitor C11. In the case where the memory cell OMC does not include capacitor C11, the potential written to node N11 is maintained by the gate capacitance of transistor M12, etc.

[0125] Transistors M11 and M12 may also have a back gate (also called a second gate or bottom gate). For example, by applying a predetermined potential to the back gate of transistor M11, the threshold voltage of transistor M11 can be increased or decreased. Alternatively, by electrically connecting the back gate of transistor M11 to the gate of transistor M11 (also called the first gate, top gate, or front gate), the on-state current of transistor M11 can be increased.

[0126] Specifically, by shifting the threshold voltage to a negative value, the on-state current of the transistor can be increased, and the OMC (Operational Storage Cell) can operate at high speed. On the other hand, by shifting the threshold voltage of transistor M11 to a positive value, the off-state current of the transistor can be reduced, and the OMC can retain data for a longer period. Alternatively, different potentials can be applied to the back gates of transistors M11 and M12. For example, the potential applied to the back gate of transistor M11 can be decreased, while the potential applied to the back gate of transistor M12 can be increased.

[0127] Alternatively, transistors other than OS transistors can be used for transistors M11 and M12. Transistor M11 is preferably a transistor with low off-state current; for example, a transistor containing a semiconductor with a large bandgap in the channel formation region can be used. A large bandgap semiconductor sometimes refers to a semiconductor with a bandgap of 2.2 eV or higher, and materials other than oxide semiconductors can be included, such as silicon carbide, gallium nitride, and diamond. On the other hand, transistor M12 is preferably a transistor with high on-state current; semiconductor materials such as silicon and germanium can also be used.

[0128] The OMC (Optical Characteristic Cell) is a gain-type memory cell consisting of either 2 transistors and 1 capacitor or 2 transistors and 0 capacitor. Even with a small accumulated charge capacity, the gain-type memory cell can use the nearest transistor to amplify the accumulated charge to function as a memory. The gain-type memory cell can be read out without destroying the stored data (non-destructive readout).

[0129] Alternatively, the memory cell OMC can consist of a transistor and a capacitor. Figure 7C The memory cell OMC shown includes transistor M13 and capacitor C12.

[0130] In transistor M13, one of the source and drain terminals is electrically connected to one terminal of capacitor C12, and the other terminal is electrically connected to wiring abl. The gate terminal is electrically connected to wiring awl. The other terminal of capacitor C12 is electrically connected to wiring CAL. The connection point that connects to one of the source and drain terminals of transistor M13 is called node N12.

[0131] Transistor M13 can use the same OS transistor as transistors M11 and M12. Additionally, Figure 7C In the memory cell OMC shown, the wiring abl is used as a bit line, and the wiring awl is used as a word line.

[0132] The storage unit OMC adopts Figure 7C The configuration shown, while increasing the density of the storage cell OMC, results in destructive reads during data retrieval. Furthermore, even if the storage cell OMC included in the storage cell section OMCL is... Figure 7A , Figure 7B and Figure 7C Any of the storage cells OMC shown can also be randomly accessed by the storage cell OMCL.

[0133] Next, the circuits BLD and OBLD included in the circuit OSC will be explained in more detail. Figure 8 This is a block diagram showing a structural example of a part of the OSC circuit. Figure 8 from Figure 4 The output circuit OUTP and circuit CVC are omitted in the OSC circuit shown. More specific examples of the structure of circuit BLD, circuit OBLD, and signal flow in circuit OSC are shown.

[0134] The circuit BLD may, for example, have a structure including a column decoder CD, a write circuit WC, a read amplifier SA, and an output circuit OPC.

[0135] The column decoder (CD) has the function of selecting the wiring BL electrically connected to the memory cell MC that is to be written to or read from, based on the address signal AD obtained from the control circuit (CTR). Here, the address signal AD is an internal signal of the OSC circuit, corresponding to the address signal in the control signal (CS). Additionally, the address signal AD is also sent to the circuit WLD. The circuit WLD has the function of driving the wiring BSL, wiring WL, and wiring SSL, and also has the function of selecting the wiring WL electrically connected to the memory cell MC that is to be written to or read from, based on the address signal AD.

[0136] The write circuit WC has the function of supplying a potential to the wiring BL selected by the column decoder CD, corresponding to the data signal WD supplied from the control circuit CTR. Here, the data signal WD is an internal signal of the circuit OSC, and is the signal corresponding to the data signal ORD or the data signal WDATA.

[0137] Additionally, the sense amplifier SA amplifies the data signal read from the wiring BL. Note that the amplified data signal, as the data signal RD, is output to the control circuit CTR via the output circuit OPC. The control circuit CTR then outputs a signal corresponding to the data signal RD to the circuit OUTP.

[0138] The circuit OBLD may, for example, have a structure including a column decoder OCD, a write circuit OWC, a precharge circuit OPR, a sense amplifier OSA, and an output circuit OOPC.

[0139] The column decoder OCD has the function of selecting the wiring wbl and wiring rbl that are electrically connected to the memory cell OMC that is to be written to or read from, based on the address signal OAD obtained from the control circuit CTR. Here, the address signal OAD is an internal signal of the circuit OSC. In addition, the address signal OAD is also sent to the circuit OWLD. The circuit OWLD has the function of driving the wiring wwl and wiring rwl, and also has the function of selecting the wiring wwl and wiring rwl that are electrically connected to the memory cell OMC that is to be written to or read from, based on the address signal OAD.

[0140] The write circuit OWC has the function of supplying a potential to the wiring wbl selected by the column decoder OCD, corresponding to the data signal OWD supplied from the control circuit CTR. Here, the data signal OWD is an internal signal of the circuit OSC, and is the signal corresponding to the data signal WDATA.

[0141] Additionally, the precharge circuit OPR functions as a precharge wiring rbl, and the readout amplifier OSA amplifies the data signal read from the wiring rbl. Note that the amplified data signal, as the data signal ORD, is output to the control circuit CTR via the output circuit OOPC. The control circuit CTR outputs the signal corresponding to the data signal ORD to either the write circuit WC or the output circuit OUTP.

[0142] Note that the structural elements of circuits BLD and OBLD are not limited to these; other components can be added as needed, and unnecessary components can be removed. Furthermore, the functions of circuits BLD and OBLD are not limited to these; they can have other functions, and unnecessary functions can be removed.

[0143] The above is a description of a semiconductor device 10 according to one aspect of the present invention. According to one aspect of the present invention, since different types of memory devices are included in the same chip, a highly versatile semiconductor device can be provided. Furthermore, the data transfer speed between two memory devices can be improved. Moreover, since two types of memory devices and peripheral circuitry are included in the same chip, a semiconductor device with a small footprint can be realized.

[0144] At least a portion of the structural examples shown in this embodiment and the corresponding drawings can be appropriately combined with other structural examples or drawings.

[0145] (Implementation Method 2)

[0146] In this embodiment, an example of the structure of a memory string according to one aspect of the present invention and a semiconductor device using the memory string are described.

[0147] [Memory string]

[0148] One embodiment of the memory string 100 of the present invention can be used in a 3D-NAND type memory device. Note that in the following figures, arrows are sometimes used to indicate the orthogonal X, Y, and Z directions, respectively.

[0149] Figure 9A This is a cross-sectional view of memory string 100 viewed from the Y direction. Note that... Figure 9A The document describes the central axis 120 of the memory string 100 extending in the Z direction. Additionally, Figure 9B This is the equivalent circuit of memory string 100. Memory string 100 has a structure in which multiple transistors Tr are connected in series. Each transistor is connected to wiring CG.

[0150] The transistor Tr constituting the memory string 100 is used as a ferroelectric transistor (FeFET). A ferroelectric transistor is a transistor that uses a ferroelectric material as an insulator, serving as the gate insulator. A ferroelectric transistor can change its threshold voltage by applying a voltage above the gate. By using this transistor Tr, NAND-type ferroelectric memory can be implemented.

[0151] The memory string 100 includes a conductive layer 101, an m-layer (m is an integer greater than 2) insulating layer 102, and an n-layer (n is an integer greater than 2) conductive layer 103 disposed above a substrate (not shown). The insulating layer 102 and the conductive layer 103 are alternately stacked above the substrate. Figure 9A In the above embodiments, the first insulating layer 102 is referred to as insulating layer 102_1, and the m-th insulating layer 102 is referred to as insulating layer 102_m. Similarly, the first conductive layer 103 is referred to as conductive layer 103_1, and the n-th conductive layer 103 is referred to as conductive layer 103_n. In this embodiment, any insulating layer 102 is simply referred to as "insulating layer 102". Similarly, any conductive layer 103 is simply referred to as "conductive layer 103".

[0152] Additionally, the memory string 100 includes a conductive layer 104, an insulating layer 105, a structure 110, and an insulating layer 121. The structure 110 extends along the Z direction. Furthermore, the structure 110 is disposed between the conductive layers 101 and 104, passing through the insulating layers 102_1 to 102_m and the conductive layers 103_1 to 103_n.

[0153] The structure 110 has a pillar-like structure including a semiconductor layer 112 and a functional layer 118. Specifically, the functional layer 118 is disposed such that the semiconductor layer 112 extends along a central axis 120 and surrounds it. The semiconductor layer 112 has a cylindrical shape along the central axis 120, and the functional layer 118 is arranged concentrically on the outside of the semiconductor layer 112.

[0154] Note that the cross-sectional shape of structure 110 is not limited to a circle; it can also be a triangle, rectangle, or a polygon with more than one pentagon. Furthermore, the profile of the cross-section of structure 110 perpendicular to the Z-direction can be composed solely of curves, or it can be a combination of straight lines and curves.

[0155] An insulating layer 121 is disposed covering the sides of insulating layers 102_1 to 102_m and conductive layers 103_1 to 103_n. A conductive layer 104 is disposed on the insulating layer 102_m. The conductive layers 101 and 104 are electrically connected to the semiconductor layer 112. Furthermore, an insulating layer 105 is disposed on the insulating layers 102_m, 121, and 104.

[0156] The intersection of structure 110 and conductive layer 103 is used as transistor Tr. This transistor Tr is used as a memory cell (also called a memory element).

[0157] The conductive layer 103 is used as the gate of the transistor Tr. The memory string 100 includes n intersections between the structure 110 and the conductive layer 103. Therefore, the memory string 100 includes n transistors Tr, i.e., n memory cells.

[0158] exist Figure 9A , Figure 9B In this embodiment, the first transistor Tr is denoted as transistor Tr_1, and the nth transistor Tr is denoted as transistor Tr_n. In this embodiment, any transistor Tr is simply denoted as "transistor Tr". Similarly, the wiring CG connected to the nth transistor Tr_n is denoted as wiring CG_n.

[0159] In many cases, polycrystalline silicon is used for the main body of a 3D-NAND memory string. In a memory string 100 according to one embodiment of the present invention, a semiconductor layer 112 corresponds to the main body. The semiconductor layer 112 can be made of single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either alone or in combination. For example, silicon and germanium can be used as semiconductor materials. Furthermore, compound semiconductors such as silicon-germanium, silicon carbide (SiC), gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0160] Furthermore, the semiconductor layer 112 can also be a semiconductor whose crystallinity is improved by using a catalyst element. As a catalyst element, an element selected from metallic elements such as nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (Au), and germanium (Ge) can be used.

[0161] For example, crystallinity can be improved by forming amorphous silicon as semiconductor layer 112 and adding nickel as a catalyst element through heat treatment. The catalyst element bonds to silicon to form silicides. Furthermore, the catalyst element readily bonds to areas with many defects, such as amorphous states. Thus, the catalyst element contained in the silicide reacts with the amorphous silicon to form new silicides. In this way, crystallization progresses while the silicide moves. In addition, by bringing the catalyst element to semiconductors containing impurity elements, such as group 15 and group 13 elements, the re-diffusion of the catalyst element can be suppressed.

[0162] Furthermore, when nickel is added as a catalyst element to the semiconductor layer 112, a nickel concentration gradient sometimes occurs within the semiconductor layer 112. For example, the nickel concentration in the region of the transistor used as the channel is lower than the nickel concentration in other regions (e.g., the source region and the drain region). In other words, the nickel concentration in the source region and the drain region is higher than the nickel concentration in the region used as the channel.

[0163] Semiconductor layer 112 is used as the semiconductor layer for forming the channel of transistor Tr. The semiconductor layer used for the transistor can be a multilayer semiconductor. When the semiconductor layer has a multilayer structure, semiconductor materials with different crystal states can be used, or different semiconductor materials can be used.

[0164] In particular, the transistor Tr is preferably an oxide semiconductor transistor in which one of the metal oxides is used in the semiconductor layer 112 where the channel is formed. The band gap of the oxide semiconductor is 2 eV or more, resulting in extremely small off-state current. Therefore, the power consumption of the memory string 100 can be reduced. Therefore, the power consumption of the semiconductor device including the memory string 100 can be reduced.

[0165] Furthermore, the memory cell including the OS transistor can be referred to as "OS memory". Additionally, the memory string 100 including this memory cell can also be referred to as "OS memory".

[0166] Furthermore, compared to transistors that use polysilicon in the semiconductor layer forming the channel, OS transistors can further reduce on-state resistance. In other words, the conductivity of the main body can be improved. By using OS transistors as transistor Tr, the operating speed of the memory string 100 can be increased. Moreover, while transistors using polysilicon experience threshold voltage inhomogeneity due to grain boundaries, OS transistors are less affected by grain boundaries, resulting in less threshold voltage inhomogeneity. Therefore, by using OS transistors as transistor Tr, the memory string 100 can suppress erroneous operation caused by threshold voltage inhomogeneity.

[0167] Furthermore, OS transistors operate stably even at high temperatures with minimal characteristic variation. For example, the off-state current hardly increases even at high temperatures. Specifically, the off-state current hardly increases even at ambient temperatures above room temperature and below 200°C. Additionally, the on-state current does not easily decrease even at high temperatures. Therefore, the memory string 100, including OS memory, operates stably and reliably even at high temperatures. Furthermore, the source-drain insulation breakdown voltage is very high in OS transistors. By using OS transistors as the transistors constituting the memory string 100, a memory string 100 that operates stably and reliably even at high temperatures can be realized. This improves the reliability of semiconductor devices including the memory string 100.

[0168] NAND-type storage devices that include OS memory are also referred to as "OS NAND type" or "OS NAND type storage device". Furthermore, 3D-NAND-type storage devices that include OS memory are also referred to as "3D OS NAND type" or "3D OS NAND type storage device". Therefore, the memory string 100 according to one embodiment of the present invention can be considered a 3D OS NAND type storage device.

[0169] Dielectrics can be used as functional layer 118.

[0170] When an electric field is applied to a dielectric, positively charged and negatively charged portions are generated within the dielectric. This phenomenon is called "polarization." A dielectric that loses its polarization when no electric field is present is called a "paraelectric material," while a dielectric that retains its polarization when no electric field is present is called a "ferroelectric material." Furthermore, the property of retaining polarization when no electric field is present is called "ferroelectricity."

[0171] Functional layer 118 uses a material exhibiting ferroelectric properties. Examples of ferroelectric materials include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, materials containing Group IIIa elements are preferred. For example, materials containing scandium, yttrium, and one or more lanthanide elements are preferred. In particular, yttrium, lanthanum, or scandium are easier to process and have high affinity for semiconductor manufacturing processes, making them preferred. Adding such elements not only ensures stable ferroelectricity but also suppresses characteristic degradation during repeated write operations, thereby improving reliability. Other additive elements include silicon, aluminum, gadolinium, and scandium.

[0172] Oxides containing one or both of hafnium and zirconium readily exhibit ferroelectricity even when fabricated using thin-film deposition methods such as sputtering and ALD. This results in high compatibility with semiconductor manufacturing processes, thereby reducing manufacturing costs.

[0173] In addition, piezoelectric ceramics with perovskite structures, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), and bismuth ferrite (BFO), can also be used as functional layer 118.

[0174] Alternatively, the functional layer 118 can also be an organic ferroelectric material such as polyvinylidene fluoride (PVDF) or a copolymer of polyvinylidene fluoride (VDF) and trifluoroethylene (TrFE).

[0175] Furthermore, as a material exhibiting ferroelectricity, a mixture or compound formed from a plurality of materials selected from the above-mentioned materials can be used, for example. Additionally, the functional layer 118 may have a laminated structure formed from a plurality of materials selected from the above-mentioned materials.

[0176] In particular, hafnium oxide or materials containing hafnium oxide and zirconium oxide (HZO) exhibit ferroelectricity even when processed into thin films of a few nm, and are therefore preferred. By using hafnium oxide or hafnium zirconium oxide, the thickness of the functional layer 118 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0177] Furthermore, when hafnium zirconium oxide (HfZrO) is used as a material exhibiting ferroelectric properties... X When X is a real number greater than 0, atomic layer deposition (ALD) is preferred, and thermal ALD is particularly preferred. Furthermore, plasma-enhanced ALD (including thermal ALD) is preferred.

[0178] Furthermore, when using the thermal ALD method, it is preferable to use a material that does not contain hydrocarbons (also known as HC) as a precursor. Either or both of the hydrogen and carbon contained in the film can sometimes hinder crystallization. Therefore, it is preferable to reduce the concentration of either or both of the hydrogen and carbon in the film by using a precursor that does not contain hydrocarbons. For example, chlorine-based materials can be cited as precursors that do not contain hydrocarbons. Note that when using hafnium zirconium oxide, chlorine-based precursors such as HfCl4 and ZrCl4 can be used as precursors.

[0179] In addition, when using hafnium zirconium oxide in the functional layer 118, it is preferable to alternately deposit hafnium oxide and zirconium oxide with a 1:1 composition using thermal ALD or plasma ALD.

[0180] Furthermore, H2O or O3 can be used as the oxidant in the thermal ALD process or the ALD process utilizing plasma. However, the oxidant is not limited to these and may also include any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0181] The impurity concentration in the membrane used for functional layer 118 is preferably low. In particular, the lower the concentrations of hydrogen (H) and carbon (C), the better. Specifically, the hydrogen concentration in the membrane is preferably 5 × 10⁻⁶. 20 atoms / cm 3 Hereinafter, 1×10 is more preferred. 20 atoms / cm 3 The following. Furthermore, the carbon concentration in the membrane is preferably 5 × 10⁻⁶. 19 atoms / cm 3 The following, or more preferably, is 1×10 19 atoms / cm 3 the following.

[0182] Furthermore, there are no particular restrictions on the crystalline structure of the film used for functional layer 118, as long as it is a crystalline structure without centrosymmetry and possessing polarity. For example, a crystal system other than cubic can be used. In addition, the film used for functional layer 118 can have a single-crystal structure or a polycrystalline structure, or it can have a composite structure including amorphous and crystalline structures.

[0183] The ferroelectric layer used for functional layer 118 is also called a "ferroelectric layer". Ferroelectric layers have hysteresis characteristics. Figure 10 This is a graph illustrating an example of hysteresis characteristics. In Figure 10 In the diagram, the horizontal axis represents the voltage (electric field) applied to the ferroelectric layer, and the vertical axis represents the polarization of the ferroelectric layer. Note that the electric field strength can be calculated by dividing the voltage by the thickness of the ferroelectric layer.

[0184] The hysteresis characteristics of the ferroelectric layer can be represented by curves 71 and 72. The voltage at the intersection of curves 71 and 72 is called the saturation polarization voltage VSP and the saturation polarization voltage -VSP.

[0185] When a voltage below -VSP is applied to the ferroelectric layer and then the applied voltage is gradually increased, the polarization of the ferroelectric layer increases according to curve 71. On the other hand, when a voltage above VSP is applied to the ferroelectric layer and then the applied voltage is gradually decreased, the polarization of the ferroelectric layer decreases according to curve 72. Note that VSP is sometimes referred to as the "positive saturation polarization voltage" or "first saturation polarization voltage," and -VSP is referred to as the "negative saturation polarization voltage" or "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage can be the same or different.

[0186] Here, the voltage at which the polarization of the ferroelectric layer changes according to curve 71 and reaches zero is called the coercive voltage Vc. Furthermore, the voltage at which the polarization of the ferroelectric layer changes according to curve 72 and reaches zero is called the coercive voltage -Vc. The values ​​of Vc and -Vc are values ​​between -VSP and VSP. Note that Vc is sometimes referred to as the "positive coercive voltage" or "first coercive voltage," and -Vc is sometimes referred to as the "negative coercive voltage" or "second coercive voltage." The absolute values ​​of the first and second coercive voltages can be the same or different.

[0187] Furthermore, when a voltage exceeding the coercive voltage is applied to the ferroelectric layer, its polarization tends to reverse. In FeFETs, if polarization reversal of the ferroelectric layer used as a gate insulating layer is not desired, the voltage applied between the gate and source (also known as the "gate voltage" or "Vg") can be set to be above -Vc and below Vc. To control the on and off states of the FeFET without using polarization reversal of the ferroelectric layer used as a gate insulating layer, a large absolute value of the coercive voltage is preferable.

[0188] Furthermore, the maximum value of polarization when no voltage is applied to the ferroelectric layer (at 0V) is called "residual polarization Pr", and the minimum value is called "residual polarization -Pr". Additionally, the absolute value of the difference between residual polarization Pr and residual polarization -Pr is called "residual polarization 2Pr". The larger the residual polarization 2Pr, the greater the variation in the threshold voltage for polarization reversal. Therefore, a larger residual polarization 2Pr is better.

[0189] As a functional layer 118, a charge accumulation layer can be used instead of a ferroelectric layer. For example, as a functional layer 118, a transistor that can be used as a storage cell to store data by holding charge in the charge accumulation layer can be realized by using a stacked structure of a barrier layer, a charge accumulation layer, and a tunneling layer.

[0190] Such memory cells are sometimes referred to by various names depending on the stacked structure from the control gate to the semiconductor. For example, when the control gate, barrier layer, charge accumulation layer, tunneling layer, and semiconductor layer are made of metal, oxide, nitride, oxide, and semiconductor, the memory cell is called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell.

[0191] Alternatively, the memory cell can be a SONOS (Silicon Oxide Nitride Oxide Semiconductor) type memory cell that uses n-type silicon or p-type silicon as the control gate, a TANOS (Tantalum nitride Aluminium oxide Nitride Oxide Semiconductor) type memory cell that uses tantalum nitride as the control gate and aluminum oxide as the barrier layer, or a THNOS (Tantalum nitride Hafnium oxide Nitride Oxide Semiconductor) type memory cell that uses tantalum nitride as the control gate and hafnium oxide as the barrier layer.

[0192] For example, the functional layer 118 can be a stacked structure consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film from the semiconductor layer 112 side. In this case, the silicon nitride film is used as a charge storage layer.

[0193] Figure 11A , Figure 11B A memory string 100A including a back gate is shown. The main difference between memory string 100A and memory string 100 described above is that memory string 100A includes a conductive layer 106 and an insulating layer 111. The structure 110A included in memory string 100A includes a conductive layer 106, an insulating layer 111, a semiconductor layer 112, and a functional layer 118.

[0194] The memory string 100A includes a conductive layer 106 located on a central axis, and an insulating layer 111, a semiconductor layer 112, and a functional layer 118 arranged in concentric circles around the conductive layer 106.

[0195] The conductive layer 106 is used as the back gate of the transistor Tr. The insulating layer 111 is used as the back gate insulator of the transistor Tr.

[0196] exist Figure 11B In this configuration, the back gates of transistors Tr (Tr_1 to Tr_n) are electrically connected to wiring SL via wiring BGL. Note that conductive layer 106 can be used as wiring BGL. That is, the back gate of each transistor Tr is supplied with the potential of wiring SL. Therefore, compared to the case without a back gate, the threshold voltage of each transistor Tr is stable, enabling more reliable write and erase operations.

[0197] [Semiconductor Devices]

[0198] Next, a more specific structural example of the semiconductor device with two memory devices shown in Embodiment 1 will be described.

[0199] Figure 12Examples of cross-sectional structures for layers 11 and 12 are shown. Figure 14 Examples of cross-sectional structures for layers 12 and 13 are shown.

[0200] use Figure 12 and Figure 14 The following situations are explained: Layer 11 is suitable for circuits that use a single-crystal silicon substrate as the substrate; Layer 12 is suitable for storage devices including NAND-type memory with a three-dimensional structure; and Layer 13 is suitable for storage devices including OS transistors.

[0201] exist Figure 12 In the middle, layer 11 is equipped with transistor 300, and layer 12 is equipped with multiple memory strings.

[0202] Each memory string disposed in layer 12 includes transistor 141, multiple transistors 142, and transistor 143. Note that when describing the structure of layer 12, detailed descriptions of the memory string 100 shown in Figure 9 above are omitted, and only the differences are described.

[0203] <Layer 11>

[0204] The transistor 300 in layer 11 is disposed on the substrate 311 and includes a conductive layer 316, an insulating layer 315, a semiconductor region 313 formed by a portion of the substrate 311, a low-resistance region 314a used as a source region or a drain region, and a low-resistance region 314b. Figure 12 The cross-section of transistor 300 along its channel length is shown.

[0205] Transistor 300 is preferably a so-called Fin-type transistor, wherein in a cross-section along the channel width direction, conductive layer 316 covers the top surface of semiconductor region 313 and the side surface along the channel width direction, separated by insulating layer 315. This increases the effective channel width, thereby improving the on-state characteristics of transistor 300. Furthermore, since the influence of the electric field at the gate electrode can be reduced, the off-state characteristics of transistor 300 can be improved.

[0206] In addition, transistor 300 can be a p-channel transistor or an n-channel transistor.

[0207] The channel formation region of semiconductor region 313, the region theren, and the low-resistance regions 314a and 314b used as source or drain regions preferably contain semiconductors such as silicon-based semiconductors, and more preferably contain single-crystal silicon. Alternatively, materials containing Ge (germanium), SiGe (silicon-germanium), GaAs (gallium arsenide), GaN (gallium nitride), GaAlAs (gallium aluminum arsenide), etc., may be used. Silicon, in which lattice stress is applied to change the interplanar spacing to control the effective quality, can be used. Furthermore, transistor 300 may also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0208] In the low resistance regions 314a and 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements such as arsenic and phosphorus that impart n-type conductivity or elements such as boron that impart p-type conductivity are also included.

[0209] As the conductive layer 316 used as the gate electrode, conductive materials such as semiconductor materials, metal materials, alloy materials, or metal oxide materials containing elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron, can be used.

[0210] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage (Vth) of the transistor can be adjusted by changing the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as conductors. In order to combine conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductor, especially tungsten, which is preferred in terms of heat resistance.

[0211] Notice, Figure 12 The structure of transistor 300 shown is just an example and is not limited to the above structure. Appropriate transistors can be used according to the circuit structure, driving method, etc.

[0212] Insulating layer 320, insulating layer 322, insulating layer 324 and insulating layer 326 are stacked sequentially to cover transistor 300.

[0213] For example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, and aluminum nitride can be used as insulating layers 320, 322, 324, and 326.

[0214] The insulating layer 322 can also be used as a planarization film to flatten the steps caused by the transistor 300 and the like disposed beneath it. For example, the top surface of the insulating layer 322 can also be planarized by a planarization process such as chemical mechanical polishing (CMP) to improve flatness.

[0215] As the insulating layer 324, it is preferable to use a barrier film that can prevent hydrogen, impurities, etc. from diffusing from the substrate 311 or the transistor 300 to the area where the transistor 141 is disposed.

[0216] As an example of a hydrogen-barrier film, silicon nitride formed by CVD can be used. Here, hydrogen sometimes diffuses into semiconductor devices with oxide semiconductors, such as transistor 141, causing a deterioration in the characteristics of the semiconductor device. Therefore, it is preferable to provide a film that suppresses hydrogen diffusion between transistor 141 and transistor 300. Specifically, a film that suppresses hydrogen diffusion refers to a film with a low amount of hydrogen detachment.

[0217] The amount of hydrogen removed can be analyzed, for example, using thermal desorption spectroscopy (TDS). For instance, in TDS analysis within the membrane surface temperature range of 50°C to 500°C, when converting the amount of hydrogen removed (converted to hydrogen atoms) to the amount per unit area of ​​the insulating layer 324, the preferred amount of hydrogen removed from the insulating layer 324 is 10 × 10⁻⁶. 15 atoms / cm 2 The following is more preferably 5×10 15 atoms / cm 2 That's all.

[0218] Note that the dielectric constant of insulating layer 326 is preferably lower than that of insulating layer 324. For example, the relative dielectric constant of insulating layer 326 is preferably less than 4, more preferably less than 3. For example, the relative dielectric constant of insulating layer 326 is preferably less than 0.7 times that of insulating layer 324, more preferably less than 0.6 times. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0219] Furthermore, conductive layers 328 and 330 are embedded in insulating layers 320, 322, 324, and 326. The conductive layers 328 and 330 are used as plugs or wiring. Note that sometimes the same symbol is used to represent multiple conductors that function as plugs or wiring. Furthermore, in this specification, wiring and plugs connected to wiring can also be considered as a single component. That is, a portion of a conductor is sometimes used as wiring, and a portion of a conductor is sometimes used as a plug.

[0220] As materials for the plugs and wiring (conductive layer 328 and conductive layer 330, etc.), single layers or stacks of conductive materials such as metals, alloys, metal nitrides, or metal oxides can be used. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred; tungsten is particularly favored. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0221] Although Figure 12 The wiring layer is omitted, but it is also possible to provide a wiring layer on the insulating layer 326 and the conductive layer 330. For example, it is preferable to provide an insulator with hydrogen-blocking properties, similar to that of the insulating layer 324, on the insulating layer 326 and the conductive layer 330, and to form a hydrogen-blocking conductor on the insulator. By forming a hydrogen-blocking conductor in the openings included in the hydrogen-blocking insulator, the barrier layer can be used to separate the transistor 300 from the transistor 141, thereby suppressing hydrogen diffusion from the transistor 300 to the transistor 141, etc.

[0222] As a conductor with hydrogen-blocking properties, tantalum nitride is preferably used, for example. Furthermore, by layering tantalum nitride and highly conductive tungsten, hydrogen diffusion from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, the hydrogen-blocking tantalum nitride layer is preferably in contact with a hydrogen-blocking insulator. Note that in Figure 12 In the middle, an insulating layer 350 with hydrogen-blocking properties is provided on the insulating layer 326 and the conductive layer 330.

[0223] <Layer 12>

[0224] Layer 12 includes conductive layer 125, multiple conductive layers 103, conductive layer 126, conductive layer 127, insulating layer 121, insulating layer 122, functional layer 118, semiconductor layer 112, conductive layer 101, conductive layer 104, etc.

[0225] Insulating layer 121 is used as the gate insulating layer of transistor 142, and insulating layer 122 is used as the gate insulating layer of transistor 143. Conductive layer 125 is used for wiring. Conductive layer 126 is used as the gate of transistor 142, and conductive layer 127 is used as the gate of transistor 143.

[0226] An insulating layer 384 is provided on the insulating layer 105. A conductive layer 386 is provided in the insulating layer 105 and the insulating layer 384, extending to the conductive layer 104. The conductive layer 386 is used as a plug.

[0227] As the conductive layer 125, materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium can be used. Furthermore, highly conductive semiconductors, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used. Additionally, conductive materials containing metallic elements such as titanium and tantalum, as well as nitrogen, can also be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, can also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can also be used. Furthermore, indium gallium zinc oxide containing nitrogen can also be used. By using such materials, hydrogen or water mixed in from surrounding insulators can sometimes be trapped.

[0228] There are no particular restrictions on the method for forming the conductive layer 125. For example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE (Molecular Beam Epitaxy), ALD (Atomic Layer Deposition), PLD (Pulsed Laser Deposition), etc. can be used.

[0229] The insulating layer 102 is preferably made of a material with a low dielectric constant. This reduces the capacitance between the conductive layer 126 and the conductive layer 103, between the conductive layers 103 and 103, or between the conductive layers 103 and 127, thereby increasing the driving speed of the semiconductor device.

[0230] As the insulating layer 102, materials comprising silicon oxide or silicon oxynitride can be used, for example. Furthermore, for example, a single layer or stack of insulators comprising materials selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc., can be used. The insulating layer 102 can be deposited, for example, using deposition methods such as sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, PLD, etc.

[0231] The same materials as conductive layer 125 can be used for conductive layer 103, conductive layer 126 and conductive layer 127.

[0232] As conductive layers 101 and 104, silicon with diffused impurities is preferably used, for example. As this impurity, an n-type impurity (donor) can be used. Examples of n-type impurities include phosphorus and arsenic. Alternatively, a p-type impurity (acceptor) can be used. Examples of p-type impurities include boron, aluminum, and gallium. Furthermore, as silicon, monocrystalline silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used. Additionally, as conductive layers 101 and 104, metal oxides with high carrier density may sometimes be used besides silicon. Furthermore, compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, and SiGe may sometimes be used.

[0233] The materials used for conductive layer 101 and conductive layer 104 are preferably the same as those used for semiconductor layer 112. In this case, the carrier density of conductive layer 101 and conductive layer 104 is preferably higher than that of semiconductor layer 112.

[0234] Silicon is preferably used as the semiconductor layer 112. Other types of silicon, such as monocrystalline silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon, can also be used. In addition to silicon, metal oxides can also be used as the semiconductor layer 112. Furthermore, compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, and SiGe can sometimes be used.

[0235] Examples of metal oxides that can be used in semiconductor layer 112 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. Furthermore, the metal oxide preferably contains two or three elements selected from In, element M, and Zn. Note that element M is a metallic or half-metallic element with a high bond energy with oxygen, such as a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specific examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably any one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred.

[0236] When using In-M-Zn oxides as metal oxides, the atomic ratio of In in the In-M-Zn oxide is preferably greater than or equal to the atomic ratio of M. Examples of such atomic ratios of the metal elements in In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions close to these. Note that "close to" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in metal oxides, the on-state current or field-effect mobility of transistors can be improved.

[0237] In In-M-Zn oxides, the atomic ratio of In can also be less than the atomic ratio of element M. For example, examples of such In-M-Zn oxides include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions close to these ratios. By increasing the atomic ratio of M in the metal oxide, the formation of oxygen vacancies can be suppressed.

[0238] The semiconductor layer 112 can be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc. Additionally, Ga-Zn oxide can also be used. Using a Zn-free material such as indium oxide improves the affinity with the LSI manufacturing process, making it preferred. On the other hand, using a Zn-containing material easily improves crystallinity, making it preferred as well.

[0239] In particular, by using In-Zn oxides with an atomic ratio of In:Zn=4:1, In:Zn=2:1 or similar, or In-Sn-Zn oxides with an atomic ratio of In:Sn:Zn=4:0.1:1, In:Sn:Zn=2:0.1:1 or similar, the field-effect mobility of transistors can be appropriately improved, and therefore it is preferred.

[0240] Metal oxides can also replace indium or contain one or more metal elements with high period numbers in addition to indium. The greater the overlap of the orbitals of the metal element, the greater the carrier conduction in the metal oxide. Therefore, by including metal elements with high period numbers, the field-effect mobility of transistors can sometimes be improved. Examples of metal elements with high period numbers include those belonging to the 5th period and those belonging to the 6th period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are referred to as light rare earth elements.

[0241] In addition, metal oxides can also contain one or more non-metallic elements. The inclusion of non-metallic elements in metal oxides can sometimes improve the field-effect mobility of transistors. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0242] Metal oxides can be formed appropriately using sputtering or atomic layer deposition (ALD). In particular, ALD deposition, which offers excellent coverage, is preferred for metal oxides. Note that when metal oxides are formed using sputtering, the composition of the deposited metal oxide sometimes differs from that of the target material. Specifically, the zinc content in the deposited metal oxide may sometimes decrease to about 50% of the zinc content in the target material.

[0243] In this specification, the content of a certain metal oxide in a metal element refers to the proportion of the number of atoms of that element relative to the total number of atoms of the metal element contained in the metal oxide. For example, in a metal oxide containing metal element X, metal element Y, and metal element Z, the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A, respectively. X A Y A Z When the content of metallic element X is expressed as A, the percentage of X can be represented as A. X / (A X +A Y +A Z Furthermore, when the ratio of the number of atoms of metal elements X, Y, and Z in a metal oxide (atomic ratio) is expressed as B... X B Y B Z When the content of metallic element X is such that B is used, the percentage of X can be expressed as B. X / (B) X +B Y +B Z ).

[0244] For example, when using metal oxides containing In, transistors with high on-state current can be achieved by increasing the In content.

[0245] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 112, a transistor with high reliability under forward bias can be realized. That is, a transistor with small fluctuations in the threshold voltage during PBTS (Positive Bias Temperature Stress) testing can be achieved. Furthermore, when using a Ga-containing metal oxide, the Ga content is preferably lower than the In content. Thus, a transistor with both high mobility and high reliability can be realized.

[0246] On the other hand, by increasing the Ga content, transistors with high reliability for light can be achieved. In other words, transistors with small threshold voltage variations during NBTIS (Negative Bias Temperature Illumination Stress) testing can be realized. Specifically, metal oxides with a higher Ga atomic number than those with a higher In atomic number have larger band gaps, which can reduce the threshold voltage variation during NBTIS testing of the transistor.

[0247] Furthermore, by increasing the Zn content, the crystallinity of the metal oxide is improved, which can suppress the diffusion of impurities in the metal oxide. Therefore, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0248] Semiconductor layer 112 may also have a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers included in semiconductor layer 112 may be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs. Note that a stacked structure of two or more oxide semiconductor layers with different compositions can also be used. Furthermore, by utilizing the ALD method, metal oxide layers with compositions continuously varying in the thickness direction can be formed. Therefore, compared to using a film with a predetermined composition, not only can the range of design choices be expanded, but the formation of interface states, etc., between two layers with different compositions can also be prevented, thus improving electrical characteristics and reliability.

[0249] Semiconductor layer 112 is preferably made of a crystalline metal oxide layer. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a nano-crystal (nc: nano-crystal) structure, etc., can be used. By using a crystalline metal oxide layer in semiconductor layer 112, the defect state density in semiconductor layer 112 can be reduced, thereby enabling a highly reliable semiconductor device.

[0250] The higher the crystallinity of the metal oxide layer used for semiconductor layer 112, the lower the defect state density in semiconductor layer 112 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0251] For information on functional layer 118, please refer to the above description. Figure 12 Examples of using dielectrics exhibiting ferroelectricity are shown.

[0252] in addition, Figure 13 An example of replacing the functional layer 118 is a stacked structure having insulating layers 131, 132, and 133. For example, insulating layer 132 is used as a charge accumulation layer. For example, insulating layer 131 can be a silicon oxide film, insulating layer 132 can be a silicon nitride film, and insulating layer 133 can be a silicon oxide film. Figure 13 The transistor 141 shown is used as a charge-trapping type unit transistor. Note that it is not limited to this; a floating-gate type unit transistor can also be used.

[0253] <Layer 13>

[0254] like Figure 14 As shown, layer 13 is disposed on layer 12. Layer 13 includes transistor 200 and capacitor 250.

[0255] Transistor 200 is a metal-oxide-semiconductor (OS transistor) containing a metal-oxide-semiconductor in the channel formation region. Transistor 200 includes a pair of gates such that the semiconductor forming the channel is sandwiched between them. Transistor 200 has the characteristic of extremely low off-state current. For example, data written to the memory cell OMC can be retained for a long time using transistor M11 in the above embodiment. Alternatively, transistor M12 can also be used. Additionally, capacitor 250 can be used with capacitor C11 or capacitor C12 in the above embodiment.

[0256] In layer 13, insulating films such as insulating layers 210, 212, 214, 216, 220, 222, 240, 244, 241, 242, 246, and 248 are stacked on insulating layer 384. Insulating layers 212, 216, 240, 241, 246, and 248 are used as interlayer insulating films and can be made of the same material as insulating layer 102. Furthermore, insulating layers 210, 214, 220, 222, 244, and 242 are preferably barrier insulating films that can prevent the diffusion of hydrogen, impurities, etc.

[0257] A conductive layer 218 is provided embedded within insulating layers 210, 212, 214, and 216. The conductive layer 218 is used as a plug. Figure 14 In the middle, the conductive layer 218 and the conductive layer 386 are disposed in contact.

[0258] The transistor 200 includes a conductive layer 205 disposed in insulating layers 214 and 216, insulating layers 220 and 222 on insulating layers 216 and conductive layers 205, insulating layer 224 on insulating layer 222, semiconductor layer 201 on insulating layer 224, a pair of conductive layers 204 disposed on semiconductor layer 201, an insulating layer 240 located on conductive layer 204 and having a trench reaching semiconductor layer 201, and insulating layer 203 and conductive layer 202 disposed in insulating layer 240.

[0259] One of the pair of conductive layers 204 is used as the source electrode, and the other is used as the drain electrode. Conductive layer 202 is used as the first gate electrode, and insulating layer 203 is used as the first gate insulating layer. Conductive layer 205 is used as the second gate electrode, and insulating layers 220, 222, and 224 are used as the second gate insulating layers.

[0260] As insulating layers 224 and 203 in contact with semiconductor layer 201, oxides are preferably used. For example, oxides such as silicon oxide, silicon oxynitride, aluminum oxide, and hafnium oxide are preferred. In addition, nitrides such as silicon nitride, silicon oxynitride, and aluminum nitride can also be used. Furthermore, single layers or stacks of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide are preferred. With the miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating film. Therefore, by using a high-k material as the insulator used as the gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0261] As the insulating layer 203, a laminated film consisting of multiple insulating films is preferably used. For example, a laminated film consisting of two, three, or four or more layers of the above-mentioned insulating material is preferred.

[0262] Furthermore, as the insulating layer 203, a thin film containing a ferroelectric material, as shown in Embodiment 1, is preferably used. This allows the transistor 200 to be used as a non-volatile storage element. In this case, a structure without the capacitor 250 can also be employed.

[0263] The insulating layer 234 is provided to cover the conductive layer 204 and has the function of suppressing the oxidation of the conductive layer 204. At this time, the insulating layer 234 is provided to cover the side surface of the semiconductor layer 201 and the side surface of the insulating layer 224 and to contact the insulating layer 222. As the insulating layer 234, it is preferable to use an insulating film with barrier properties that can prevent the diffusion of hydrogen, impurities, etc.

[0264] A capacitor 250 is disposed on an insulating layer 246. The capacitor 250 includes a conductive layer 251, a conductive layer 252, and an insulating layer 253 located between them. The capacitor 250 is a so-called MIM (Metal-Insulator-Metal) capacitor.

[0265] As the insulating layer 253, a single layer or a stack of insulators comprising the aforementioned high-k material is preferably used. Alternatively, the ferroelectric material shown in Embodiment 1 can also be used as the insulating layer 253. Thus, the capacitor 250 can be used as a ferroelectric capacitor, and a non-volatile memory cell can be realized by combining it with the transistor 200.

[0266] Alternatively, a conductive layer 254 for wiring may be included on the insulating layer 246. The conductive layer 254 can be formed by processing the same conductive film as the conductive layer 251.

[0267] Conductive layer 254 and conductive layer 204 are connected by conductive layers 236 and 238. Conductive layers 236 and 238 are used as connectors. The same materials as conductive layers 328 and 330 can be used for conductive layers 236 and 238.

[0268] Figure 15 Examples of different structures for layer 13 are shown. Figure 15 In the middle layer 13, transistors 400a and 400b are provided. Both transistors 400a and 400b are vertical transistors.

[0269] Transistor 400a and transistor 400b both include a semiconductor layer 401, a conductive layer 402 serving as a gate electrode, an insulating layer 403 serving as a gate insulating layer, a conductive layer 404 serving as one of the source electrode and drain electrode, and a conductive layer 406 serving as the other of the source electrode and drain electrode.

[0270] The structure of transistor 400b will be described. A conductive layer 407 is disposed on insulating layer 216, a conductive layer 406 is disposed on conductive layer 407, and an insulating layer 410 is disposed to cover conductive layer 406. A conductive layer 405 is disposed on insulating layer 410, and a conductive layer 404 is disposed on conductive layer 405. Openings leading to conductive layer 406 are provided in conductive layer 404, conductive layer 405, and insulating layer 410. Semiconductor layer 401 is in contact with conductive layer 404 and conductive layer 406 and with the side of the opening in insulating layer 410. Insulating layer 403 is disposed to cover semiconductor layer 401, and conductive layer 402 is disposed to fill the opening.

[0271] In one or both of transistors 400a and 400b, the insulating layer 403, as shown in Embodiment 1, can be a thin film containing a ferroelectric material, serving as the gate insulating layer. In particular, it is preferable to use such a thin film for the insulating layer 403 of transistor 400b. Thus, transistor 400b can be used as a non-volatile memory element.

[0272] Because the channel length of transistor 400b can be precisely controlled according to the thickness of insulating layer 410, the non-uniformity of channel length can be minimized compared to planar transistors. Furthermore, by thinning insulating layer 410, transistors with extremely small channel lengths can also be manufactured. For example, transistors with channel lengths of less than 2μm, less than 1μm, less than 500nm, less than 300nm, less than 200nm, less than 100nm, less than 50nm, less than 30nm, or less than 20nm but greater than 5nm, greater than 7nm, or greater than 10nm can be manufactured. Therefore, transistors with channel lengths less than 10nm can be realized without using the very expensive exposure equipment used in the most advanced LSI technology.

[0273] Semiconductor layer 401 can be made of various semiconductor materials, with oxide semiconductors containing metal oxides being particularly preferred. By using oxide semiconductors formed under appropriate conditions, transistors with both large on-state current and extremely small off-state current can be realized at low cost. Below, unless otherwise specified, preferred structural examples of using oxide semiconductors in semiconductor layer 401 are described.

[0274] The top surfaces of conductive layers 404 and 406 are in contact with the semiconductor layer 401. Therefore, when an oxide semiconductor is used for the semiconductor layer 401, there is a concern that oxidation may occur near the surfaces of conductive layers 404 and 406 due to the deposition process of the semiconductor film that forms the semiconductor layer 401 or the effects of subsequent heat application, resulting in the formation of an insulating oxide film between the conductive layers 404 and 406 and the semiconductor layer 401, leading to increased contact resistance. Therefore, it is preferable to use an oxide conductor containing a conductive oxide at least on the uppermost part of conductive layers 404 and 406. This prevents an increase in contact resistance due to oxidation of the surfaces of conductive layers 404 and 406. Conductive layers 404 and 406 may also be referred to as oxide layers, metal oxide layers, or oxide conductor layers, etc.

[0275] Conductive layer 405 can be used as one of the source and drain wiring. Furthermore, a portion of conductive layer 407 can be used as the other of the source and drain wiring. Thus, by providing conductive layers 405 and 407 in contact with conductive layers 404 and 406 respectively, the wiring resistance can be reduced. As conductive layers 405 and 407, materials with higher conductivity than oxide conductors, such as metals, alloys, or their nitrides, are preferably used.

[0276] The semiconductor layer 401 is disposed in contact with the inner wall of the opening in the insulating layer 410. An oxide insulating film is preferably used as the insulating layer 410. In particular, an oxide insulating film that releases oxygen upon heating is preferred. Furthermore, the insulating layer 410 preferably employs a stacked structure of three or more layers, i.e., a structure in which an oxide insulating film is sandwiched between insulating films with oxygen-barrier properties (e.g., nitride insulating films). This allows oxygen contained in the oxide insulating film to be confined within the region surrounded by a pair of nitride insulating films and the semiconductor layer 401, preventing oxygen in the oxide insulating film from escaping and decreasing during processing, thus enabling more efficient oxygen supply to the semiconductor layer 401.

[0277] Transistor 400a includes an insulating layer 414 and a conductive layer 402, which replace the insulating layer 410 and the conductive layer 406 of transistor 400b, respectively. Otherwise, its structure is largely the same as that of transistor 400b.

[0278] The gate electrode of transistor 400b also serves as one of the source and drain electrodes of transistor 400a. For example, transistor 400a is equivalent to... Figure 7B In the structure shown, transistor M11 and transistor 400b are equivalent to transistor M12.

[0279] Insulating layers 410, 414, and 418 are used as interlayer insulating films. As insulating layers 412, 416, etc., insulating films that have the ability to block hydrogen, impurities, etc. are preferably used.

[0280] In a transistor with the above structure, the source and drain electrodes are located at different heights, so the current flowing through the semiconductor flows in the height direction. That is, it can be said that the channel length direction has a height (vertical) component; therefore, a transistor according to one aspect of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc. In the above transistor, the source electrode, semiconductor, and drain electrode can be stacked, so compared to so-called planar transistors (also called lateral transistors, LFETs, etc.) where the semiconductor is arranged on a plane, the occupied area can be significantly reduced.

[0281] Figure 16 Showing part of the structure and Figure 15 Different examples. Figure 16 The layer 13 shown includes a transistor 400 having the same structure as transistor 400a and includes a capacitor 420 instead of transistor 400b.

[0282] The capacitor 420 includes a conductive layer 421, a conductive layer 422, and an insulating layer 423 sandwiched between them. The insulating layer 423 serves as the dielectric layer of the capacitor 420. Additionally, a conductive layer 407 is disposed in contact with the conductive layer 421 and serves as wiring.

[0283] An opening is provided in the insulating layer 410 to reach the conductive layer 407. A conductive layer 421 is provided in such a way that it contacts the top surface of the insulating layer 410, the side surface located in the opening, and the top surface of the conductive layer 407 located at the bottom of the opening. An insulating layer 423 is provided in such a way that it covers the conductive layer 421. A conductive layer 422 is provided in such a way that it covers the insulating layer 423.

[0284] As the insulating layer 423, a single layer or a stack of insulators comprising the aforementioned high-k material is preferably used. Alternatively, the ferroelectric material shown in Embodiment 1 can also be used as the insulating layer 423. Thus, the capacitor 420 can be used as a ferroelectric capacitor, and a non-volatile memory cell can be realized by combining it with the transistor 400.

[0285] For example, transistor 400 is equivalent to Figure 7C In the structure shown, transistor M13 and capacitor 420 are equivalent to capacitor C12.

[0286] Thus, by employing a structure of stacked vertical transistors and vertical capacitors, the footprint of the memory cells can be made extremely small. Therefore, it is possible to realize highly integrated and large-capacity memory devices.

[0287] Note that the above diagram shows a structure with layer 13 disposed on layer 12; it can also be a structure with layer 12 disposed on layer 13. For example, Figure 17 An example is shown where layer 13, including transistor 200, is arranged below layer 12. Additionally, Figure 18 An example is shown where layer 13, including transistors 400a and 400b, is arranged on the underside of layer 12. Figure 17 and Figure 18 An example is shown where layer 13 includes conductive layers 260 and 460, which respectively serve as plugs. Layer 11 (not shown), located below layer 13, can be connected to layer 12 on top of layer 13 via conductive layers 260 or 460. Additionally, Figure 19 An example is shown where layer 13, including transistor 400 and capacitor 420, is arranged on the underside of layer 12.

[0288] The structural examples shown in this embodiment and at least a portion of the corresponding drawings can be appropriately combined with other structural examples or drawings.

[0289] (Implementation Method 3)

[0290] In this embodiment, a semiconductor device 900 according to an embodiment of the present invention, different from the embodiments described above, will be described. The semiconductor device 900 can be used as a storage device. Hereinafter, a semiconductor device in which the memory cell section MCL or memory cell section OMCL shown in Embodiment 1 can be applied will be described.

[0291] Figure 20 This is a block diagram illustrating a structural example of a semiconductor device 900. Figure 20 The semiconductor device 900 shown includes a driving circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 20 An example of a memory array 920 including multiple memory cells 950 configured in a matrix is ​​shown.

[0292] As the storage unit 950, the storage unit section MCL or storage unit section OMCL exemplified in the above embodiments can be used.

[0293] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and peripheral circuit 915. The peripheral circuit 915 includes peripheral circuit 911, control circuit 912, and voltage generation circuit 928.

[0294] In the semiconductor device 900, the aforementioned circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0295] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can also be generated in the control circuit 912.

[0296] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 to execute the aforementioned operating mode.

[0297] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 928. For example, when the signal WAKE is given a signal of level H, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0298] The peripheral circuit 911 is used to write and read data from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0299] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row to be connected to by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0300] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data signal output from output circuit 926 is signal RDA.

[0301] PSW931 controls the supply of V to the external circuit 915. DD The PSW932 has the function of controlling the supply of V to the line driver 923. HM The function of the semiconductor device 900. Here, the high supply voltage of the semiconductor device 900 is V. DD The low supply voltage is GND (ground potential). Additionally, V HM It is a high power supply voltage used to make the word line high, which is higher than V. DD The PSW931 is controlled to turn on / off using signal PON1, and the PSW932 is controlled to turn on / off using signal PON2. Figure 20 In the middle, the peripheral circuit 915 is supplied with V DD The number of power domains can be 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0302] Reference Figures 21A to 21H This section describes structural examples of other storage units that can be used in storage unit 950.

[0303] The following discussion of connecting two components includes cases where they are electrically connected via circuit elements (transistors, switches, diodes, resistors, etc.). An electrical connection refers to a state where current can flow between two components. Furthermore, when two components are connected via a switch or transistor, current can flow even when the switch or transistor is in the ON state, and therefore this is also included in the scope of an electrical connection.

[0304] [DOSRAM]

[0305] Figure 21A An example circuit structure of a DRAM-type memory cell is shown. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.

[0306] Transistor M1 may also include a front gate (sometimes simply referred to as the gate) and a back gate. In this case, the back gate may also be connected to a wiring supplied with a constant potential or signal, and the front gate and the back gate may also be connected.

[0307] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL.

[0308] The BIL (Bite Line) is used as the bit line, and the WOL (Word Line) is used as the word line. The CAL (Chip Line) is used to apply a specified potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL.

[0309] Data writing and reading are performed by applying a high-level potential to the wiring WOL to turn on the transistor M1, thereby making the wiring BIL and the first terminal of the capacitor CA conductive (allowing current to flow).

[0310] Furthermore, the memory cell that can be used as memory cell 950 is not limited to memory cell 951, and the circuit structure can be changed. For example, it can also be used as... Figure 21B The structure of memory cell 952 is shown. Memory cell 952 is an example excluding capacitor CA and wiring CAL. The first terminal of transistor M1 is in a floating state.

[0311] In memory cell 952, the potential written by transistor M1 is maintained in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0312] An OS transistor is preferably used as transistor M1. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. That is, transistor M1 can hold written data for a long time, thereby reducing the refresh frequency of the memory cell. Furthermore, the memory cell refresh operation can be omitted. In addition, due to the very low leakage current, multi-valued data or analog data can be held in memory cells 951 and 952.

[0313] [NOSRAM]

[0314] Figure 21C An example circuit structure of a gain-cell type memory cell including two transistors and one capacitor is shown. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and the like, a memory device including a gain-cell type memory cell that uses transistor OS for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0315] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; and transistor M2's gate is connected to wiring WOL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0316] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes called the reference potential) to wiring CAL.

[0317] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M2 and thus connects wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL, which turns off transistor M2, thereby maintaining the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0318] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0319] For example, a structure that combines the wiring WBL and wiring RBL into a single wiring BIL can also be adopted. Figure 21D An example of the circuit structure of the memory cell in this case is shown. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0320] Figure 21E The memory cell 955 shown is an example where the capacitor CB and wiring CAL of memory cell 953 are omitted. Furthermore, Figure 21F The memory cell 956 shown is an example of omitting the capacitor CB and wiring CAL found in memory cell 954. This structure improves the integration density of the memory cells.

[0321] Note that it is preferable to use the OS transistor as at least as transistor M2. In particular, it is preferable to use the OS transistor as both transistor M2 and transistor M3.

[0322] Because the OS transistor has extremely low off-state current, transistor M2 can hold written data for an extended period, thereby reducing the refresh frequency of the memory cells. Furthermore, the memory cell refresh operation can be omitted. Additionally, due to the very low leakage current, multi-valued or analog data can be held in memory cells 953, 954, 955, and 956.

[0323] The memory cells 953, 954, 955, and 956, which use OS transistors as transistor M2, are a type of NOSRAM.

[0324] Si transistors can also be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing the freedom of circuit design.

[0325] Furthermore, when an OS transistor is used as transistor M3, the memory cell can be composed of only n-type transistors.

[0326] also, Figure 21G A gain-cell type memory cell 957 with three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and capacitor CC.

[0327] Transistor M4's first terminal is connected to capacitor CC's first terminal; transistor M4's second terminal is connected to wiring BIL; and transistor M4's gate is connected to wiring WOL. Capacitor CC's second terminal is connected to transistor M5's first terminal and wiring GNDL. Transistor M5's second terminal is connected to transistor M6's first terminal; transistor M5's gate is connected to capacitor CC's first terminal. Transistor M6's second terminal is connected to wiring BIL; and transistor M6's gate is connected to wiring RWL.

[0328] The BIL (Bite Line) is used as the bit line, the WOL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line. The GNDL (Ground Node Line) is used to supply a low-level potential.

[0329] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M4 and connects wiring BIL to the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to wiring WOL, which turns off transistor M4, thereby maintaining the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0330] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. By making the wiring RWL high, transistor M6 is turned on, and the wiring BIL and the second terminal of transistor M5 are connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0331] Note that it is preferable to use the OS transistor as at least transistor M4.

[0332] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystal state of the silicon used in the semiconductor layer.

[0333] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be composed of only n-type transistors.

[0334] [OS-SRAM]

[0335] Figure 21H An example of SRAM (Static Random Access Memory) using OS transistors is shown. In this specification, etc., SRAM using OS transistors will be referred to as OS-SRAM (Oxide Semiconductor-SRAM). Furthermore, Figure 21H The storage unit 958 shown is an SRAM-type storage unit capable of backup.

[0336] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1, and capacitor CD2. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0337] Transistor M7's first terminal is connected to wiring BIL. Transistor M7's second terminal is connected to the first terminal of transistors MS1 and MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. Transistor M7's gate is connected to wiring WOL. Transistor M8's first terminal is connected to wiring BILB. Transistor M8's second terminal is connected to the first terminal of transistors MS2 and MS4, the gate of transistor MS1 and MS3, and the first terminal of transistor M9. Transistor M8's gate is connected to wiring WOL.

[0338] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0339] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to the wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to the wiring BRL.

[0340] The second terminal of capacitor CD1 is connected to wiring GNDL, and the second terminal of capacitor CD2 is also connected to wiring GNDL.

[0341] The BIL and BILB wirings are used as bit lines, the WOL wiring is used as word lines, and the BRL wiring is used to control the on and off states of transistors M9 and M10.

[0342] Wiring VDL provides a high-level potential, and wiring GNDL provides a low-level potential.

[0343] Data is written by applying a high-level potential to the wiring WOL and the wiring BRL. Specifically, when transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the second terminal side of transistor M10.

[0344] Storage cell 958 uses transistors MS1 to MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to this potential is input to the second terminal of transistor M8. Since transistor M8 is in the on state, the potential applied to wiring BIL, that is, the inverted signal of the signal input to wiring BIL, is output to wiring BILB. In addition, since transistors M9 and M10 are in the on state, the potentials of the second terminals of transistor M7 and transistor M8 are maintained by the first terminals of capacitor CD2 and capacitor CD1, respectively. Then, by applying a low-level potential to wiring WOL and a low-level potential to wiring BRL to turn off transistors M7 to M10, the potentials of the first terminals of capacitor CD1 and capacitor CD2 are maintained.

[0345] Data readout is performed as follows: First, the wiring BIL and wiring BILB are pre-charged to a predetermined potential. Then, a high-level potential is applied to wiring WOL and wiring BRL. This causes the potential of the first terminal of capacitor CD1 to be refreshed by the inverter loop of storage cell 958 and output to wiring BILB. Similarly, the potential of the first terminal of capacitor CD2 is refreshed by the inverter loop of storage cell 958 and output to wiring BIL. Since wiring BIL and wiring BILB change from their pre-charged potentials to the potentials of the first terminals of capacitor CD2 and capacitor CD1, respectively, the potential held by the storage cell can be read from the potentials of wiring BIL or wiring BILB.

[0346] Transistors M7 to M10 are preferably OS transistors. This allows transistors M7 to M10 to hold written data for an extended period, thus reducing the refresh frequency of the memory cells. Alternatively, memory cell refresh can be omitted.

[0347] Furthermore, Si transistors are preferably used as transistors MS1 to MS4.

[0348] The driving circuitry 910 and memory array 920 included in the semiconductor device 900 can also be disposed on the same plane. Furthermore, as... Figure 22A As shown, the driving circuit 910 and the memory array 920 can also overlap. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. Figure 22B As shown, multiple memory arrays 920 can also be stacked on the drive circuit 910.

[0349] Next, an example of a computing processing device that may include the aforementioned storage device or other semiconductor device will be described.

[0350] Figure 23 This is a block diagram of the arithmetic unit 960. Figure 23 The computing device 960 shown can be used, for example, as a CPU (Central Processing Unit). Furthermore, the computing device 960 can also be used with processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which have more (tens to hundreds) processor cores than a CPU capable of parallel processing.

[0351] Figure 23 The illustrated arithmetic unit 960, on a substrate 990, includes: an ALU 991 (ALU: Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be located on different chips.

[0352] Cache 999 is connected to the main memory located on different chips via cache interface 989. Cache interface 989 has the function of supplying a portion of the data stored in the main memory to cache 999. In addition, cache interface 989 has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996, etc., via bus interface 998.

[0353] As described later, the memory array 920 can be arranged in a manner that stacks on the computing device 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 can have the function of supplying data held in the memory array 920 to the cache 999. Furthermore, in this case, it is preferable that a portion of the cache interface 989 includes a drive circuit 910.

[0354] Note that you can also use memory array 920 as a cache instead of setting cache 999.

[0355] Figure 23 The arithmetic device 960 shown is merely an example with a simplified structure; therefore, the actual arithmetic device 960 has various structures depending on its application. For example, it is preferable to include... Figure 23 The computing device 960 shown has a multi-core structure, which consists of a single core and multiple cores that operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0356] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993 and, after being decoded, are input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0357] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority, mask state, etc. The register controller 997 generates the address of register 996 and performs read, write, and other operations on register 996 according to the state of the arithmetic unit 960.

[0358] Furthermore, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0359] exist Figure 23 In the illustrated arithmetic unit 960, the register controller 997 selects the holding operation of register 996 according to instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cells included in register 996 by flip-flops or by capacitors. When data is held by flip-flops, a power supply potential is supplied to the memory cells in register 996. When data is held by capacitors, the data is overwritten to the capacitors, and the power supply voltage to the memory cells in register 996 can be stopped.

[0360] The memory array 920 and the arithmetic unit 960 can be arranged overlappingly. Figure 24A and Figure 24B This is a perspective view of semiconductor device 970A. Semiconductor device 970A includes a layer 930 on a computing device 960, on which memory arrays are disposed. Layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory array have overlapping areas. To facilitate understanding of the structure of semiconductor device 970A, in... Figure 24B The computing device 960 and the layer 930 are shown separately in the middle.

[0361] By overlapping the layer 930, which includes the memory array, and the computing device 960, the connection distance between them can be shortened. This improves the communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0362] As a stacking method for the layer 930 including the memory array and the computing device 960, the following methods can be used: directly stacking the layer 930 including the memory array on the computing device 960 (also known as monolithic stacking); or forming the computing device 960 and the layer 930 on different substrates, bonding the two substrates together, and connecting them using bonding techniques such as through-holes or conductive films (Cu-Cu bonding, etc.). The former method does not require consideration of misalignment during bonding, thus reducing both chip size and manufacturing costs.

[0363] Here, the memory arrays 920L1, 920L2, and 920L3, which do not include cache 999 in the arithmetic unit 960 and are disposed in layer 930, can all be used as caches. For example, memory arrays 920L1, 920L2, and 920L3 can be used as L1 cache (also called level 1 cache), L2 cache (also called level 2 cache), and L3 cache (also called level 3 cache), respectively. Among the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, memory array 920L1 has the smallest capacity and the highest access frequency.

[0364] Note that when the cache 999 in the arithmetic unit 960 is used as an L1 cache, the memory arrays in layer 930 can be used as lower-level caches or main memory. Main memory is memory with a larger capacity and lower access frequency than cache.

[0365] In addition, such as Figure 24B As shown, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0366] Note that although the case shown here is a three-array memory array used as a cache, it can also be one, two, or more than four.

[0367] When the memory array 920L1 is used as a cache, the driver circuit 910L1 can also be used as part of the cache interface 989, and the driver circuit 910L1 can also be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 can also be used as part of the cache interface 989 or connected to a part of the cache interface 989.

[0368] Whether the memory array 920 is used as cache or as main memory depends on the control circuit 912 included in each drive circuit 910. The control circuit 912 can use a portion of the multiple memory cells 950 contained in the semiconductor device 900 as RAM based on signals supplied from the arithmetic unit 960.

[0369] In the semiconductor device 900, a portion of the multiple storage cells 950 can be used as cache and the remainder as main memory. That is, the semiconductor device 900 can function as both cache and main memory. The semiconductor device 900 according to one embodiment of the invention can, for example, be used as a general-purpose memory.

[0370] Alternatively, a layer 930 including a memory array 920 may be provided in a manner that overlaps with the computing device 960. Figure 25A This is a 3D view of the semiconductor device 970B.

[0371] In the semiconductor device 970B, a memory array 920 can be divided into multiple regions and assigned different functions for use. Figure 25A This shows an example of using region L1, region L2, and region L3 as L1 cache, L2 cache, and L3 cache, respectively.

[0372] Furthermore, in the semiconductor device 970B, the capacity of each of regions L1 to L3 can be changed according to the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​region L1. By adopting this structure, efficient computational processing can be achieved, thereby increasing processing speed.

[0373] In addition, multiple memory arrays can be stacked. Figure 25B This is a 3D view of the semiconductor device 970C.

[0374] Semiconductor device 970C includes a layer 930L1 comprising a memory array 920L1, a layer 930L2 comprising a memory array 920L2, and a layer 930L3 comprising a memory array 920L3. The memory array 920L1, physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, furthest from the arithmetic unit 960, can be used as a lower-level cache or main memory. By employing this structure, the capacity of each memory array can be increased, thus further improving processing power.

[0375] At least a portion of the structural examples shown in this embodiment and the corresponding drawings can be appropriately combined with other structural examples or drawings.

[0376] Implementation Method 4

[0377] This embodiment illustrates an example of the application of a storage device according to one aspect of the present invention.

[0378] Generally speaking, various storage devices are used in semiconductor devices such as computers, depending on their purpose. Figure 26A The various memory devices used in semiconductor devices are shown in a hierarchical manner. Higher-level memory devices are required to operate at faster speeds, while lower-level memory devices are required to have larger storage capacities and higher recording densities. Figure 26A In this system, from the topmost level, the cache includes memory installed as registers in processing devices such as the CPU, L1 cache, L2 cache, L3 cache, main memory, and storage. Note that although an example including up to L3 cache is shown here, it may also include caches at lower levels.

[0379] Because the memory installed along with registers in arithmetic processing devices such as CPUs is used for temporary storage of calculation results, it is accessed frequently by the processing device. Therefore, a faster operating speed is required compared to storage capacity. In addition, registers also have the function of holding settings information of the processing device.

[0380] A cache is a system that copies and maintains a portion of the information held in main memory. By copying frequently used data into the cache, the speed of data access can be improved. A cache requires less storage capacity than main memory, but its operating speed is higher. Furthermore, data that is modified in the cache is copied and fed back to main memory.

[0381] Main memory has the function of holding programs, data, etc. read from storage.

[0382] Storage serves to hold data that needs to be preserved long-term and various programs used by computing devices. Therefore, compared to faster operating speeds, storage requires larger storage capacities and higher recording densities. For example, high-capacity non-volatile storage devices such as 3D NAND can be used.

[0383] Because the storage device according to one aspect of the present invention includes a storage device with large storage capacity and a storage device with high operating speed, it can be applied to... Figure 26A The hierarchy where the storage is located and the hierarchy where the main memory is located.

[0384] According to one aspect of the present invention, a storage device using oxide semiconductors (OS memory) operates at high speed and can retain data for long periods. Therefore, as Figure 26A As shown, a storage device according to one aspect of the present invention can be used for both a cache hierarchy and a main memory hierarchy.

[0385] also, Figure 26B Examples are shown of cases where SRAM is used for one part of the cache and OS memory of one aspect of the present invention is used for another part.

[0386] The lowest level cache can be referred to as an LLC (Last Level cache). LLCs do not require faster operating speeds than their parent caches, but are required to have larger storage capacity. One embodiment of the OS memory of this invention has a fast operating speed and can retain data for long periods, making it suitable for use with LLCs. Note that one embodiment of the OS memory of this invention can also be used with FLCs (Final Level caches).

[0387] For example, such as Figure 26B As shown, SRAM can be used for higher-level caches (L1 cache, L2 cache, etc.) and the OS memory of one embodiment of the present invention can be used for LLC. Furthermore, as... Figure 26B As shown, DRAM can also be used in main memory in addition to OS memory.

[0388] The structural examples shown in this embodiment and at least a portion of the corresponding drawings can be appropriately combined with other structural examples or drawings.

[0389] (Implementation Method 5)

[0390] This embodiment illustrates an example of the application of a storage device according to one aspect of the present invention.

[0391] The storage device of one aspect of the present invention can be applied, for example, to storage devices in various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras, video recording devices, navigation systems, and game consoles). Furthermore, it can be used in image sensors, IoT (Internet of Things), and medical applications. Here, computers include tablets, laptops, desktop computers, and mainframe computers such as server systems.

[0392] An example of an electronic device having a storage device according to one aspect of the present invention will be described. Figures 27A to 27J and Figures 28A to 28E This illustrates an example where an electronic component 700 with a storage device is included in various electronic devices.

[0393] [Mobile phone]

[0394] Figure 27A The information terminal 5500 shown is a mobile phone (smartphone), one type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. The display unit 5511 has a touch panel as an input interface, and buttons are provided on the housing 5510.

[0395] By applying a storage device according to one aspect of the present invention to an information terminal 5500, documents temporarily generated during program execution (e.g., cache when using a web browser) can be stored.

[0396] Wearable devices

[0397] also, Figure 27B An example of a wearable terminal, information terminal 5900, is shown. Information terminal 5900 includes a housing 5901, a display unit 5902, an operation switch 5903, an operation switch 5904, a watch strap 5905, etc.

[0398] Similar to the aforementioned information terminal 5500, by applying a storage device according to one aspect of the present invention to a wearable terminal, documents temporarily generated during the execution of application software can be stored.

[0399] [Information Terminal]

[0400] Figure 27C A desktop information terminal 5300 is shown. The desktop information terminal 5300 includes an information terminal body 5301, a display unit 5302, and a keyboard 5303.

[0401] Similar to the aforementioned information terminal 5500, by applying a storage device according to one aspect of the present invention to the desktop information terminal 5300, documents temporarily generated during the execution of application software can be stored.

[0402] Note that, although in Figures 27A to 27C The term "electronic device" refers to smartphones, wearable devices, and desktop information terminals. However, other information terminals could be cited, such as PDAs (Personal Digital Assistants), laptops, and workstations.

[0403] [Electrical Products]

[0404] Figure 27D An example of an electrical appliance is shown: an electric refrigerator / freezer 5800. The electric refrigerator / freezer 5800 includes a housing 5801, a refrigerator door 5802, and a freezer door 5803, etc. For example, the electric refrigerator / freezer 5800 is an electric refrigerator / freezer corresponding to the Internet of Things (IoT).

[0405] The storage device according to one aspect of the present invention can be applied to an electric refrigerator / freezer 5800. For example, by utilizing the Internet, the electric refrigerator / freezer 5800 can send and receive information such as the food stored in the electric refrigerator / freezer 5800 or the expiration date of the food to an information terminal or the like. The electric refrigerator / freezer 5800 can store documents temporarily generated when sending such information in the storage device according to one aspect of the present invention.

[0406] exist Figure 27D In this context, the product description includes electric refrigerators and freezers. However, other electrical appliances that can be included include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners (including air conditioners with heating and cooling), washing machines, dryers, and audio-visual equipment.

[0407] [Game console]

[0408] also, Figure 27E A portable game console 5200 is shown as an example of a game console. The portable game console 5200 includes a casing 5201, a display unit 5202, and buttons 5203, etc.

[0409] also, Figure 27F A stationary game console 7500 is shown as an example of a game console. Specifically, the stationary game console 7500 can be considered a home stationary game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The main unit 7520 can be connected to the controller 7522 wirelessly or via a wired connection. Furthermore, although in Figure 27F Although not shown in the figure, the controller 7522 may include a display unit for displaying game images, a touch panel and joystick as input interfaces other than buttons, a rotating gripper, a sliding gripper, etc. Furthermore, the controller 7522 is not limited to... Figure 27F The shape shown can also be changed depending on the type of game. For example, in shooting games such as FPS (First Person Shooter), a controller shaped like a gun can be used as the trigger button. Furthermore, in games such as music games, a controller shaped like a musical instrument or other musical device can be used. Moreover, stationary game consoles can also be equipped with one or more of a camera, depth sensor, microphone, etc., allowing the player to operate the controller using gestures or voice commands.

[0410] Furthermore, the images from the aforementioned game consoles can be output from display devices such as television sets, personal computer monitors, game displays, and head-mounted displays.

[0411] By using the storage device of one aspect of the present invention in a portable game console 5200 or a stationary game console 7500, power consumption can be reduced. Furthermore, by reducing power consumption, heat generation from the circuitry can be reduced, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuitry, and modules.

[0412] Furthermore, by using the storage device of one aspect of the present invention in a portable game console 5200 or a stationary game console 7500, it is possible to store calculation files temporarily generated during game execution.

[0413] exist Figure 27E and Figure 27F The examples shown are portable game consoles and home stationary game consoles, but other examples of game consoles include arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.) and ball-throwing machines installed in sports facilities.

[0414] [Moving Object]

[0415] One aspect of the storage device of the present invention can be applied to a car as a mobile body and to the vicinity of the driver's seat of the car.

[0416] Figure 27G The car 5700 is shown as an example of a moving body.

[0417] The driver's seat of the car 5700 is equipped with an instrument panel that displays various information such as speedometer, tachometer, distance traveled, fuel level, gear position, and air conditioning settings. Alternatively, a display device showing the aforementioned information may also be installed near the driver's seat.

[0418] In particular, by displaying images captured by a camera device (not shown) installed on the vehicle 5700 on the aforementioned display device, obstructions to the field of vision such as pillars and blind spots from the driver's seat can be compensated for, thereby improving safety. In other words, by displaying images captured by a camera device installed on the outside of the vehicle 5700, the field of vision can be supplemented to avoid blind spots and improve safety.

[0419] One embodiment of the storage device of the present invention can temporarily store data. For example, this storage device can be used in the autonomous driving system of a car 5700 to temporarily store necessary data for navigation, hazard prediction, and other systems. Furthermore, one embodiment of the storage device of the present invention can also store recordings from a dashcam installed in the car 5700.

[0420] While the above example illustrates a moving object like a car, moving objects are not limited to cars. Examples of moving objects include trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets), etc.

[0421] [camera]

[0422] One embodiment of the storage device of the present invention can be applied to a camera.

[0423] Figure 27H A digital camera 6240 is shown as an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and is equipped with a detachable lens 6246. Here, the digital camera 6240 employs a structure in which the lens 6246 can be detached from the housing 6241; however, the lens 6246 and the housing 6241 can also be formed as a single unit. Furthermore, the digital camera 6240 may also include separately mounted flash and viewfinder, etc.

[0424] By using the storage device of one aspect of the present invention in a digital camera 6240, power consumption can be reduced. Furthermore, by reducing power consumption, heat generation from the circuitry can be reduced, thereby minimizing the negative impact of heat generation on the circuitry itself, peripheral circuitry, and modules.

[0425] [Video Camera]

[0426] One embodiment of the storage device of the present invention can be applied to a video camera.

[0427] Figure 27I A video camera 6300 is shown as an example of a camera device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, and a connecting part 6306. The operation switch 6304 and the lens 6305 are disposed on the first housing 6301, and the display unit 6303 is disposed on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connecting part 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting part 6306. The image on the display unit 6303 can also be switched according to the angle between the first housing 6301 and the second housing 6302 in the connecting part 6306.

[0428] When recording images captured by the video camera 6300, encoding is required according to the data recording method. Using a storage device according to one aspect of the present invention, the video camera 6300 can store documents temporarily generated during encoding.

[0429] [ICD]

[0430] One embodiment of the storage device of the present invention can be applied to an implantable cardioverter defibrillator (ICD).

[0431] Figure 27J This is a cross-sectional schematic diagram showing an example of an ICD. The ICD body 5400 includes at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a metal wire 5402 extending to the right atrium, and a metal wire 5403 extending to the right ventricle.

[0432] The ICD body 5400 is surgically implanted in the body. Two metal wires pass through the subclavian vein 5405 and the superior vena cava 5406, with the tip of one metal wire placed in the right ventricle and the tip of the other metal wire placed in the right atrium.

[0433] The ICD main unit 5400 has the function of a cardiac pacemaker, pacing the heart when the heart rhythm is outside the prescribed range. In addition, it can be used for defibrillation treatment when the heart rhythm does not improve even when pacing is performed (such as rapid ventricular pulse or ventricular fibrillation).

[0434] In order to perform pacing and defibrillation appropriately, the ICD body 5400 needs to monitor the heart rhythm frequently. Therefore, the ICD body 5400 includes a sensor for detecting the heart rhythm. In addition, the ICD body 5400 can store data on the heart rhythm measured by the sensor, the number of times pacing therapy was performed, the duration, etc., in the electronic component 700.

[0435] Furthermore, power is received by antenna 5404 and this power is used to charge battery 5401. Additionally, by including multiple batteries in the ICD body 5400, safety can be improved. Specifically, even if some batteries in the ICD body 5400 fail, the other batteries can function and be used as auxiliary power.

[0436] In addition to the antenna 5404, which can receive power, it may also include an antenna capable of transmitting physiological signals. For example, it may also constitute a system for monitoring cardiac activity that can be confirmed by an external monitoring device with physiological signals such as pulse, respiratory rate, heart rate and body temperature.

[0437] [PC Expansion Devices]

[0438] One embodiment of the storage device of the present invention can be applied to expansion devices for computers and information terminals such as PCs (Personal Computers).

[0439] Figure 28AAn example of such an expansion device is shown: a portable expansion device 6100 external to a PC, equipped with a chip capable of storing data. The expansion device 6100 is connected to the PC, for example, via USB (Universal Serial Bus), and can utilize the chip to store data. Note that although... Figure 28A A portable extension device 6100 is shown, but the extension device according to one aspect of the invention is not limited thereto; for example, an extension device with a larger structure for mounting a cooling fan may also be used.

[0440] The expansion device 6100 includes a housing 6101, a cover 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is housed within the housing 6101. For example, the substrate 6104 is provided with circuitry for driving a storage device or the like according to one aspect of the present invention. For example, the substrate 6104 is mounted with electronic components 700 and a controller chip 6106. The USB connector 6103 serves as an interface for connecting to an external device.

[0441] [SD card]

[0442] One aspect of the storage device of the present invention can be applied to an SD card that can be installed in electronic devices such as information terminals or digital cameras.

[0443] Figure 28B This is a schematic diagram of the SD card's appearance. Figure 28C This is a schematic diagram of the internal structure of an SD card. The SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 has an interface for connecting to an external device. The substrate 5113 is housed within the housing 5111. The substrate 5113 is provided with a storage device and circuitry for driving the storage device. For example, an electronic component 700 and a controller chip 5115 are mounted on the substrate 5113. Furthermore, the circuit structures of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit structures can be appropriately modified as needed. For example, the write circuit, line driver, read circuit, etc., provided by the electronic component may be mounted on the controller chip 5115 instead of on the electronic component 700.

[0444] By also providing electronic components 700 on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and allows for reading and writing data from the electronic components 700.

[0445] [SSD]

[0446] One aspect of the present invention provides a storage device that can be applied to SSDs (Solid State Drives) that can be installed in electronic devices such as information terminals.

[0447] Figure 28D This is a schematic diagram of the SSD's appearance. Figure 28E This is a schematic diagram of the internal structure of an SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed within the housing 5151. The substrate 5153 houses a storage device and circuitry for driving that storage device. For example, the substrate 5153 may house an electronic component 700, a memory chip 5155, and a controller chip 5156. By also housing the electronic component 700 on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. The memory chip 5155 houses the working memory. For example, a DRAM chip can be used for the memory chip 5155. The controller chip 5156 houses a processor, ECC (Error-Correcting Code) circuitry, etc. Note that the circuit structures of the electronic component 700, the memory chip 5155, and the controller chip 5156 are not limited to those described above and can be appropriately modified as needed. For example, the controller chip 5156 can also be configured with a memory used as working memory.

[0448] [computer]

[0449] Figure 29A The computer 5600 shown is an example of a mainframe computer. In computer 5600, multiple rack-mounted computers 5620 are housed in rack 5610.

[0450] Computer 5620, for example, can have Figure 29B The structure shown in the 3D diagram. In Figure 29B In the computer 5620, a motherboard 5630 is included, which includes multiple slots 5631 and multiple connection terminals. A personal computer card 5621 is inserted into the slots 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0451] Figure 29C The personal computer card 5621 shown is an example of a processing board including a CPU, GPU, and storage devices. The personal computer card 5621 has a board 5622. Furthermore, the board 5622 includes connection terminals 5623, 5624, and 5625, semiconductor devices 5626, 5627, and 5628, and a connection terminal 5629. Note that... Figure 29C Semiconductor devices other than semiconductor devices 5626, 5627 and 5628 are shown. For a description of these semiconductor devices, please refer to the description of semiconductor devices 5626, 5627 and 5628 described below.

[0452] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 on the motherboard 5630. The connection terminal 5629 is used as an interface for connecting the personal computer card 5621 to the motherboard 5630. Examples of specifications for the connection terminal 5629 include PCIe.

[0453] Connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for powering or inputting signals to the personal computer card 5621. Furthermore, they can be used, for example, as interfaces for outputting signals calculated by the personal computer card 5621. Examples of the specifications for each of connection terminals 5623, 5624, and 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of the specifications include HDMI (registered trademark).

[0454] Semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting these terminals into a socket (not shown) included in board 5622, semiconductor device 5626 and board 5622 can be electrically connected.

[0455] Semiconductor device 5627 includes multiple terminals, which can be electrically connected to board 5622 by reflow soldering the terminals to wiring included in board 5622. Examples of semiconductor devices 5627 include FPGA (Field Programmable Gate Array), GPU, and CPU.

[0456] Semiconductor device 5628 includes multiple terminals, which can be electrically connected to board 5622 by reflow soldering the terminals to wiring provided on board 5622. For example, a memory device can be used as semiconductor device 5628. Electronic component 700 can also be used as semiconductor device 5628.

[0457] The Computer 5600 can be used as a parallel computer. By using the Computer 5600 as a parallel computer, large-scale computations required for artificial intelligence learning and inference can be performed, for example.

[0458] By using the storage device of one aspect of the present invention in the aforementioned various electronic devices, miniaturization and low power consumption of electronic devices can be achieved. Furthermore, the storage device of one aspect of the present invention consumes little power, thereby reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Moreover, by using the storage device of one aspect of the present invention, electronic devices can operate stably even in high-temperature environments. This improves the reliability of electronic devices.

[0459] At least a portion of the structural examples shown in this embodiment and the corresponding drawings can be appropriately combined with other structural examples or drawings.

[0460] (Implementation Method 6)

[0461] In this embodiment, using Figure 30 Specific examples are given of applying a semiconductor device according to one aspect of the present invention to space equipment.

[0462] One aspect of the semiconductor device of the present invention includes an OS transistor. The OS transistor exhibits minimal change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, and therefore can be suitably used in environments where radiation may be incident. For example, the OS transistor can be suitably used in applications requiring space travel.

[0463] exist Figure 30 The image shows an artificial satellite 6800 as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control unit 6807. Furthermore, Figure 30 An example of a planet 6804 in outer space is shown. Note that outer space, for example, refers to an altitude of 100 km or higher, but outer space as described in this specification may also include one or more of the thermosphere, mesosphere, and stratosphere.

[0464] Furthermore, outer space is an environment where the radiation dose is more than 100 times that of the Earth's surface. Examples of radiation include electromagnetic waves (electromagnetic radiation), represented by X-rays and gamma rays; and particle radiation, represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0465] The solar panel 6802 generates the power required for the satellite 6800 to operate when sunlight shines on it. However, the generated power decreases, for example, when sunlight does not reach the solar panel or when the amount of sunlight reaching the solar panel is low. Therefore, it is possible that the power required for the satellite 6800 to operate may not be generated. In order to enable the satellite 6800 to operate even when the generated power is low, it is preferable to provide a secondary battery 6805 in the satellite 6800. Furthermore, the solar panel is sometimes referred to as a solar cell module.

[0466] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received, for example, by a ground receiver or other satellites. By receiving the signal transmitted by satellite 6800, the position of the receiver can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0467] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 may use one or more components selected from CPU, GPU, and storage devices. Moreover, the control device 6807 preferably uses a semiconductor device including an OS transistor according to one aspect of the present invention. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to radiation exposure. In other words, OS transistors have high reliability and can be appropriately used even in environments where radiation may be incident.

[0468] Furthermore, satellite 6800 may include sensors. For example, by including a visible light sensor, satellite 6800 may be able to detect sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, satellite 6800 may be able to detect thermal infrared radiation emitted from the Earth's surface. Thus, satellite 6800 can be used, for example, as an Earth observation satellite.

[0469] Note that in this embodiment, an artificial satellite is shown as an example of a space device, but the invention is not limited thereto. For example, a semiconductor device according to one aspect of the invention can be suitably applied to space devices such as spacecraft, space capsules, and space probes.

[0470] At least a portion of the structural examples shown in this embodiment and the corresponding drawings can be appropriately combined with other structural examples or drawings.

[0471] [Symbol Explanation]

[0472] 10: Semiconductor device; 11: Layer; 12: Layer; 13: Layer; 21: Storage device; 22: Terminal; 23: Plug; 31: Storage device; 32: Connector; 33: Plug; 42: Drive circuit; 43: Drive circuit; 45: Wiring; 50: Insulating layer; 51: Conductive layer; 52: Conductive layer; 53: Conductive layer; 54: Conductive layer; 55: Conductive layer; 56: Plug; 57: Conductive layer; 60: Memory string; 65: Memory cell; 71: Curve; 72: Curve; 100A: Memory string; 100: Memory string; 101: Conductive layer; 102_1: Insulating layer; 102_m: Insulating layer; 102: Insulating layer; 103_ 1: Conductive layer, 103_n: Conductive layer, 103: Conductive layer, 104: Conductive layer, 105: Insulating layer, 106: Conductive layer, 110: Structure, 111: Insulating layer, 112: Semiconductor layer, 118: Functional layer, 120: Central axis, 121: Insulating layer, 122: Insulating layer, 125: Conductive layer, 126: Conductive layer, 127: Conductive layer, 131: Insulating layer, 132: Insulating layer, 133: Insulating layer, 141: Transistor, 142: Transistor, 143: Transistor, 200: Transistor, 201: Semiconductor layer, 202: Conductive layer, 203: Insulating layer, 204: Conductive layer, 205: Conductive layer, 210: Insulating layer 212: Insulating layer, 214: Insulating layer, 216: Insulating layer, 218: Conductive layer, 220: Insulating layer, 222: Insulating layer, 224: Insulating layer, 234: Insulating layer, 236: Conductive layer, 238: Conductive layer, 240: Insulating layer, 241: Insulating layer, 242: Insulating layer, 244: Insulating layer, 246: Insulating layer, 248: Insulating layer, 250: Capacitor, 251: Conductive layer, 252: Conductive layer, 253: Insulating layer, 254: Conductive layer, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulating layer, 316: Conductive layer, 320: Insulating layer, 322: Insulating layer, 324: Insulating layer, 326: Insulating layer, 328: Conductive layer, 330: Conductive layer, 350: Insulating layer, 384: Insulating layer, 386: Conductive layer, 400a: Transistor, 400b: Transistor, 400: Transistor, 401: Semiconductor layer, 402: Conductive layer, 403: Insulating layer, 404: Conductive layer, 405: Conductive layer, 406: Conductive layer, 407: Conductive layer, 410: Insulating layer, 412: Insulating layer, 414: Insulating layer, 416: Insulating layer, 418: Insulating layer, 420: Capacitor, 421: Conductive layer, 422: Conductive layer, 423: Insulating layer.

Claims

1. A semiconductor device having a memory string, The memory string has multiple first conductive layers, multiple first insulating layers, a second insulating layer, and an oxide semiconductor layer. The plurality of first conductive layers and the plurality of first insulating layers are alternately arranged in a first direction, which is the normal direction relative to the surface of the semiconductor device in which the memory string is formed. The second insulating layer and the oxide semiconductor layer extend along the first direction. The second insulating layer is disposed between the oxide semiconductor layer and the plurality of first conductive layers.

2. The semiconductor device according to claim 1, wherein The memory string also has a second conductive layer and a third conductive layer. The second insulating layer and the oxide semiconductor layer are disposed between the second conductive layer and the third conductive layer in the first direction. The second conductive layer and the third conductive layer are electrically connected to the oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein The memory string also has a fourth conductive layer and a third insulating layer. The fourth conductive layer and the third insulating layer extend in the first direction. The third insulating layer is disposed outside the fourth conductive layer. The oxide semiconductor layer is disposed on the outside of the third insulating layer. The second insulating layer is disposed on the outside of the oxide semiconductor layer.

4. A semiconductor device, With memory string, The memory string has multiple first conductive layers, multiple first insulating layers, a second insulating layer, and an oxide semiconductor layer. The plurality of first conductive layers and the plurality of first insulating layers are alternately arranged in a first direction. The second insulating layer and the oxide semiconductor layer extend along the first direction. The second insulating layer is disposed between the oxide semiconductor layer and the plurality of first conductive layers in a manner that surrounds the oxide semiconductor layer.

5. The semiconductor device according to claim 4, wherein The oxide semiconductor layer and the second insulating layer are configured to penetrate the plurality of first conductive layers and the plurality of first insulating layers.

6. A semiconductor device, With memory string, The memory string has multiple first conductive layers, multiple first insulating layers, a second insulating layer, and an oxide semiconductor layer. The plurality of first conductive layers and the plurality of first insulating layers are alternately arranged in a first direction. The second insulating layer and the oxide semiconductor layer extend along the first direction. The second insulating layer is disposed between the oxide semiconductor layer and the plurality of first conductive layers. The memory string also has a second conductive layer, a third conductive layer, and multiple fourth conductive layers. The oxide semiconductor layer is disposed between the second conductive layer and the third conductive layer in the first direction. The second conductive layer is used as the source line. The third conductive layer is used as a bit line. The plurality of first conductive layers are used as control gate lines. The plurality of first conductive layers are electrically connected to one of the plurality of fourth conductive layers via a plug.

7. The semiconductor device according to any one of claims 1 to 6, wherein The second insulating layer is a ferroelectric layer.

8. The semiconductor device according to claim 7, wherein The ferroelectric layer includes hafnium oxide, zirconium oxide, or hafnium zirconium oxide.

9. The semiconductor device according to claim 8, wherein The ferroelectric layer also includes scandium, yttrium, silicon, aluminum, gadolinium, and one or more of the lanthanides.

10. The semiconductor device according to any one of claims 1 to 6, wherein The second insulating layer has a stacked structure consisting of multiple layers.

11. The semiconductor device of claim 10, wherein The plurality of layers of the second insulating layer include a charge storage layer.

12. The semiconductor device of claim 10, wherein The plurality of layers of the second insulating layer include a silicon oxide layer and a silicon nitride layer.

13. The semiconductor device according to any one of claims 1 to 6, wherein The oxide semiconductor layer contains indium.

14. The semiconductor device according to any one of claims 1 to 6, wherein The oxide semiconductor layer contains indium oxide.

15. The semiconductor device according to any one of claims 1 to 6, wherein The memory string can hold multiple values ​​of data.

16. The semiconductor device according to any one of claims 1 to 6, wherein The memory string can hold analog data.

17. The semiconductor device according to any one of claims 1 to 6, wherein The memory string is used as a series connection of multiple transistors. The plurality of transistors operate with normally-on characteristics.

18. The semiconductor device according to any one of claims 1 to 6, wherein The memory string is used as a series connection of multiple transistors. The plurality of transistors change the threshold voltage by applying a voltage to the plurality of first conductive layers.

19. The semiconductor device according to claim 2 or 6, wherein The plurality of first conductive layers contain tungsten. The plurality of first insulating layers comprise silicon. The second conductive layer contains molybdenum. The oxide semiconductor layer contains indium, gallium, and zinc.

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