A semiconductor device and a manufacturing method thereof

Abstract

A semiconductor device and a manufacturing method thereof, the manufacturing method comprising: providing a semiconductor substrate; forming a sacrificial material layer on the semiconductor substrate; patterning the sacrificial material layer to form a recess in the sacrificial material layer; forming a conductive layer only on sidewalls of the recess. Thus, a conductive layer with high resistance and narrow line width is prepared, and the area occupied by the conductive layer is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method. Background Technology

[0002] In the operation of semiconductor devices, resistor structures are often used for current limiting, voltage division, or as sampling resistors. Therefore, a large number of resistor structures need to be fabricated during the fabrication of semiconductor devices.

[0003] In related technologies, a flat, high-resistivity metal structure is used as the main body of the resistor structure. However, the flat metal structure has a wide linewidth and a large cross-sectional size, which is not conducive to reducing the area of ​​the resistor structure. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, the first aspect of this invention provides a method for manufacturing a semiconductor device, the method comprising:

[0006] Provide semiconductor substrates;

[0007] A sacrificial material layer is formed on a semiconductor substrate;

[0008] The sacrificial material layer is patterned to form grooves within it;

[0009] A conductive layer is formed only on the sidewalls of the groove.

[0010] In some embodiments of this application, a conductive layer is formed only on the sidewalls of the groove, including:

[0011] A conductive material layer is deposited, which covers the upper surface of the sacrificial material layer, the bottom surface of the groove, and the sidewalls.

[0012] Remove the conductive material layer from the upper surface of the sacrificial material layer and the bottom surface of the groove. The portion of the conductive material layer that remains is the conductive layer.

[0013] In some embodiments of this application, the first groove has at least two outwardly protruding protrusions spaced apart from each other, and the third sacrificial layer fills the protrusions so that the second groove has no protrusions.

[0014] In some embodiments of this application, an atomic layer deposition method is used to deposit a conductive material layer.

[0015] In some embodiments of this application, the groove includes at least two groove portions spaced apart from each other, the conductive layer in the groove portion constitutes a contact portion, and the conductive layer on the groove sidewall between two adjacent contact portions constitutes a connecting line connecting the two adjacent contact portions.

[0016] Wherein, the width of the connecting line is defined as d1, and the width of the contact part is defined as d2. Then, d1 and d2 satisfy the relationship: d1<d2≤2×d1.

[0017] In some embodiments of this application, the semiconductor substrate includes a first dielectric layer in which at least two contact plugs are formed;

[0018] Each contact plug corresponds to a groove and a contact portion, with the top of each contact plug exposed in the corresponding groove to connect to the corresponding contact portion.

[0019] In some embodiments of this application, the manufacturing method further includes:

[0020] Remove the conductive layer from part of the groove sidewall to disconnect part of the connecting wires.

[0021] A second aspect of this invention provides a method for manufacturing a semiconductor device, the method comprising:

[0022] A first sacrificial layer is formed on a semiconductor substrate;

[0023] A second sacrificial layer with a first groove is formed on the first sacrificial layer;

[0024] A third sacrificial layer is conventionally formed in the first groove to form a second groove in the third sacrificial layer;

[0025] A fourth sacrificial layer is filled into the second groove;

[0026] Remove the portion of the third sacrificial layer not covered by the fourth sacrificial layer to expose the surface of the first sacrificial layer;

[0027] Remove the exposed portion of the first sacrificial layer to form an annular groove in the first sacrificial layer;

[0028] A conductive layer is formed in the annular groove.

[0029] In some embodiments of this application, the process for forming the third sacrificial layer includes atomic layer deposition.

[0030] In some embodiments of this application, the third sacrificial layer also covers the upper surface of the second sacrificial layer;

[0031] A fourth sacrificial layer is filled into the second groove, comprising:

[0032] A fourth sacrificial material layer is formed on the third sacrificial layer, and the fourth sacrificial material layer fills the second groove;

[0033] The portion of the fourth sacrificial material layer located outside the second groove is removed, and the portion remaining inside the second groove is the fourth sacrificial layer.

[0034] In some embodiments of this application, after removing the exposed portion of the first sacrificial layer, the manufacturing method further includes removing the fourth sacrificial layer.

[0035] In some embodiments of this application, forming a conductive layer in the annular groove includes:

[0036] A conductive material layer is formed, which at least covers the upper surfaces of the second and third sacrificial layers, and the conductive material layer also fills an annular groove.

[0037] The portion of the conductive material layer located outside the annular groove, as well as the second and third sacrificial layers, are removed. The portion of the conductive material layer remaining in the annular groove is the conductive layer.

[0038] In some embodiments of this application, the annular groove includes at least two outwardly protruding groove portions that are spaced apart from each other;

[0039] The groove is filled with a conductive layer to form a contact portion, and the conductive layer between two adjacent contact portions forms a connecting line connecting the two adjacent contact portions.

[0040] Wherein, the width of the connecting line is defined as d1, and the width of the contact part is defined as d2. Then, d1 and d2 satisfy the relationship: d1<d2≤2×d1.

[0041] A third aspect of the present invention provides a semiconductor device, which is prepared by any of the above-described semiconductor device manufacturing methods.

[0042] According to the semiconductor device and manufacturing method provided by the present invention, a patterned sacrificial material layer is used to form a groove in the sacrificial material layer, and a conductive layer is formed only on the sidewalls of the groove; or a third sacrificial layer is conformally formed in a first groove to form a second groove in the third sacrificial layer, the portion of the third sacrificial layer not covered by a fourth sacrificial layer is removed to expose the surface of the first sacrificial layer, and then the exposed portion of the first sacrificial layer is removed to form an annular groove in the first sacrificial layer, and then a conductive layer is formed in the annular groove. This facilitates the fabrication of a conductive layer with high resistance and narrow linewidth, and helps to reduce the area occupied by the conductive layer. Attached Figure Description

[0043] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0044] In the attached image:

[0045] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0046] Figures 2A to 2H Cross-sectional and top views of each step in a method for manufacturing a semiconductor device according to a specific embodiment of the present invention are shown respectively.

[0047] Figure 2I A top view schematic diagram of a conductive layer prepared according to another specific embodiment of the present invention is shown;

[0048] Figure 3 A schematic flowchart of a method for manufacturing a semiconductor device according to another specific embodiment of the present invention is shown;

[0049] Figures 4A to 4M Cross-sectional and top views of each step in a method for manufacturing a semiconductor device according to a specific embodiment of the present invention are shown respectively.

[0050] Figure 4N A top view schematic diagram of a conductive layer prepared according to another specific embodiment of the present invention is shown. Detailed Implementation

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0052] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0053] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0054] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] To address at least some of the technical problems described above, this application proposes the following embodiments.

[0057] Example 1

[0058] refer to Figure 1This invention provides a method for manufacturing a semiconductor device, which mainly includes the following steps:

[0059] In S101, a semiconductor substrate is provided;

[0060] In S102, a sacrificial material layer is formed on the semiconductor substrate;

[0061] In S103, the sacrificial material layer is patterned to form grooves in the sacrificial material layer.

[0062] In S104, a conductive layer is formed only on the sidewall of the first groove.

[0063] The specific technical effects and principles are as follows: Existing technology uses a planar high-resistivity metal structure as the main body of the conductive layer. However, the planar metal structure has a wide linewidth and a large cross-sectional size. To increase the resistance of the conductive layer without reducing the cross-sectional size, the length of the planar metal structure must be extended to produce a high-resistivity conductive layer. However, extending the length of the planar metal structure increases the area occupied by the conductive layer, which is not conducive to reducing the area of ​​the conductive layer.

[0064] In the embodiments described above, a patterned sacrificial material layer is used to form grooves within the sacrificial material layer, and a conductive layer is formed only on the sidewalls of the grooves. This facilitates the fabrication of a conductive layer with high resistance and narrow linewidth, which helps to reduce the area occupied by the conductive layer. During the fabrication process, a narrow-linewidth conductive layer can be formed on the sidewalls of the grooves using sidewall methods such as, but not limited to, thin film deposition. This can be applied to miniaturization techniques. For example, when fabricating a resistor structure based on the conductive layer, it helps to reduce the linewidth of the resistor structure, thereby fabricating a resistor structure with extremely small linewidth and reducing the area occupied by the resistor structure.

[0065] Below, for reference Figures 2A to 2H The manufacturing method of the semiconductor device according to embodiments of the present invention will be described in detail.

[0066] First, refer to Figure 2A A semiconductor substrate 201 is provided, which can be of any type. Exemplarily, the semiconductor substrate 201 may contain partial or complete structures such as, but not limited to, metal lines, contact plugs, and transistors. For example, refer to... Figure 2A Contact plugs 202 for electrically connecting conductive layers can be formed in the semiconductor substrate 201. Of course, in other embodiments, refer to... Figure 2H The contact plug 202 for electrically connecting the conductive layer 206 may not be fabricated in the semiconductor substrate 201. After the conductive layer 206 is fabricated, the contact plug 210 is provided on top of the conductive layer 206 for lead-out.

[0067] For example, the semiconductor substrate 201 may be, but is not limited to, an SOI (Silicon-On-Insulator) substrate. For example, see reference... Figure 2A The surface of the semiconductor substrate 201 may be an interlayer dielectric layer formed of, but not limited to, oxides, in which contact plugs 202 are formed.

[0068] Next, refer to Figure 2B A sacrificial material layer 203 is formed on a semiconductor substrate 201. In some embodiments, the sacrificial material layer 203 may be used as a sacrificial material, and the remaining sacrificial material layer 203 may be removed after the conductive layer is formed. In other embodiments, the remaining sacrificial material layer 203 may not need to be removed after the conductive layer is formed. Exemplarily, the material of the sacrificial material layer 203 may be different from the material of the surface of the semiconductor substrate 201, thereby having a different etching selectivity to facilitate the subsequent removal of the remaining sacrificial material layer 203. Exemplarily, the material of the sacrificial material layer 203 may be a polysilicon layer (A-silicon).

[0069] Next, refer to Figures 2C1 to 2C4 The sacrificial material layer 203 is patterned to form a groove 204 within it. Various patterning processes can be employed, such as, but not limited to, etching. The etching process can be, but not limited to, photolithography, wet etching, or dry etching. Regarding the shape of the groove 204, it can be any groove-like structure formed within the sacrificial material layer 203 with a closed outline. Some exemplary configurations of the groove 204 are described below.

[0070] For example, the groove 204 may include at least two groove portions 204b spaced apart from each other, and a conductive layer subsequently formed in the groove portion 204b constitutes a contact portion. A conductive layer subsequently formed on the sidewall of the groove 204 between two adjacent contact portions constitutes a connecting line connecting the two adjacent contact portions, thereby creating a resistor structure composed of the connecting line and at least two contact portions.

[0071] For example, the width of the connecting line can be defined as d1, and the width of the contact portion as d2. Then, d1 and d2 satisfy the relationship: d1 < d2 ≤ 2 × d1. Not only can the connecting line width be extremely small by using the sidewall method, thus making it applicable to miniaturization technology, but it also forms a wider contact portion extending from the connecting line, which facilitates the electrical connection between the connecting line and the contact plug through the contact portion, and is beneficial for the lead-out of the connecting line.

[0072] For example, the groove 204 includes at least two first groove portions and a second groove portion disposed spaced apart from each other. The first groove portion is used as a first pre-formed contact plug region to connect a first contact portion formed therein with a first contact plug. The second groove portion is used as a second pre-formed contact plug region to connect a second contact portion formed therein with a second contact plug.

[0073] Regarding the shape of the groove 204, various closed contour shapes can be adopted. Some examples are described below.

[0074] For example, refer to Figures 2C1 to 2C4 The groove 204 may include a main groove area 204a and at least two groove portions 204b that are connected to and spaced apart from the main groove area 204a. The groove portions 204b are convex outwards relative to the main groove area 204a. The distance between two opposite sidewalls on the groove portion 204b is equal to the width of the contact portion formed in the groove portion 204b, and can be defined as d2. The minimum distance between two opposite sidewalls on the main groove area 204a is a first predetermined distance, and the maximum distance between two opposite sidewalls on the groove portion 204b is a second predetermined distance. The first predetermined distance is greater than the second predetermined distance. Specifically, refer to... Figure 2C1 The minimum distance between two opposite sidewalls on the main groove area 204a is the first set distance d3, and the maximum distance between two opposite sidewalls on the groove part 204b is the second set distance d2. Then d3 > d2.

[0075] By adopting the above configuration, the distance between two opposite sidewalls at any position on the main groove area 204a is greater than the distance between two opposite sidewalls at any position on the groove portion 204b, which facilitates the formation of connecting lines of the conductive layer on the sidewalls of the main groove area 204a and the formation of contact portions of the conductive layer in the groove portion 204b.

[0076] Regarding the shape of the main recessed area 204a, various large shapes can be adopted. For example, refer to... Figures 2C1 to 2C2 The main recessed area 204a is a large rectangle. (Reference) Figure 2C3 and Figure 2C4 The main groove area 204a can also be in the shape of a larger E-shape.

[0077] Regarding the arrangement of the groove portion 204b, it communicates with the main groove area 204a, and different groove portions 204b are spaced apart. Regarding the number of groove portions 204b, it can be at least two, specifically equal to the number of contact portions required. For example, refer to... Figures 2C1 to 2C3There are two recessed portions 204b, namely a first recessed portion and a second recessed portion, which can be disposed at any mutually spaced positions in the main recessed area 204a. For example, refer to... Figure 2C4 There are three grooves 204b, which can be set at any mutually spaced positions in the main groove area 204a.

[0078] Next, refer to Figures 2D to 2G4 The conductive layer 206 is formed only on the sidewalls of the groove 204. The process of forming the conductive layer 206 on the sidewalls of the groove 204 can employ various types of sidewall processes, including, but not limited to, thin film deposition processes and etching processes. Some methods are illustrated below.

[0079] For example, forming a conductive layer 206 only on the sidewalls of the groove 204 may include:

[0080] refer to Figure 2D A conductive material layer 205 is deposited, which covers the upper surface of the sacrificial material layer 203, the bottom surface of the groove 204, and the sidewalls.

[0081] refer to Figure 2E Remove the upper surface of the sacrificial material layer 203 and the bottom surface of the groove 204 of the conductive material layer 205, and the part of the conductive material layer 205 that is retained is the conductive layer 206.

[0082] For example, refer to Figure 2D A conductive material layer 205 is deposited on the bottom and sidewalls of the groove 204 and on the surface of the sacrificial material layer 203. It should be noted that the deposition thickness of the conductive material layer 205 is equal to the width d1 of the connecting line; therefore, the deposition thickness of the conductive material layer 205 and the width of the connecting line can both be defined as d1. The deposition thickness d1 of the conductive material layer 205 can be greater than or equal to half of the second predetermined spacing d2 and less than half of the first predetermined spacing d3, that is... 1 / 2×d2≤d1< 1 / 2×d3.

[0083] refer to Figure 2E The conductive material layer 205 is etched to remove the portion located on the surface of the sacrificial material layer 203 and at the bottom of the main recess region 204a. The portion remaining in the sidewalls of the main recess region 204a and in the recess portion 204b forms the conductive layer 206. Specifically, the portion remaining in the sidewalls of the main recess region 204a forms the connecting line 206a, and the portion remaining in the recess portion 204b forms the contact portion 206b.

[0084] The material of the conductive material layer 205 can be any material used to make the resistor. For example, the resistor of the conductive material layer 205 can be a metal material with high resistivity.

[0085] For example, the process of depositing to form the conductive material layer 205 can employ any type of thin film deposition process, such as, but not limited to, atomic layer deposition or chemical vapor deposition.

[0086] It should be noted that the deposition thickness d1 of the conductive material layer 205 is not the maximum thickness of the conductive material layer 205. Due to the different dimensions of the grooves 204 at different locations during the thin film deposition process, the actual thickness of the conductive material layer 205 at different locations may vary. The deposition thickness d1 of the conductive material layer 205 can be determined by controlling the deposition process, or the thickness of the conductive material layer 205 formed on the upper surface of the sacrificial material layer 203 can be used as the deposition thickness d1. Of course, since the spacing of the main groove regions 204a is relatively large, the thickness of the conductive material layer 205 covering the sidewalls of the main groove regions 204a can also be used as the deposition thickness d1. However, since the sidewall spacing of the groove portions 204b is relatively small, the actual thickness of the conductive material layer 205 at the location of the groove portion 204b is greater than the deposition thickness d1.

[0087] By employing a thin-film deposition process, a conductive material layer 205 of uniform thickness can be easily formed, which facilitates precise control over the consistency of the linewidth of the final connected line 206a. By ensuring that the deposition thickness d1 of the conductive material layer 205 is greater than or equal to half of the second predetermined spacing d2 (i.e., d2 ≤ 2 × d1), the conductive material layer 205 fills the groove portion 204b, thereby improving the reliability of the contact portion 206b finally formed in the groove portion 204b. By ensuring that the deposition thickness d1 of the conductive material layer 205 is less than half of the first predetermined spacing d3, contact between the portions of the conductive material layer 205 covering the two opposite sidewalls on the main groove region 204a is avoided, thus preventing short-circuit defects.

[0088] In some embodiments, reference Figure 2D This allows the deposition thickness d1 of the conductive material layer 205 to be less than the second set spacing d2, thereby making the line width d1 of the fabricated connecting line 206a smaller than the line width d2 of the extended contact portion 206b. While reducing the line width d1 of the connecting line 206a, the difficulty of leading out the conductive layer 206 is not affected, making it easier to set a larger area contact portion 206b. This simplifies the difficulty of aligning the contact plug and the contact portion 206b for electrical connection and improves the reliability of the electrical connection between the two.

[0089] In some embodiments, reference is made to Figure 2DThis allows the deposition thickness d1 of the conductive material layer 205 to satisfy the relationship d2 between the two opposite sidewalls of the groove 204b: d1 < d2 ≤ 2 × d1. By growing the conductive material layer 205 on the left and right sidewalls of the groove 204b using the sidewall method, the conductive material layers 205 grown on both sides can merge. This means that while forming a thinner connecting line in one step, a wider contact area can also be formed, improving the reliability of the electrical connection. (Reference) Figure 2I If d2 > 2 × d1, since the total width (2 × d1) of the conductive layer 206 grown on the left and right sidewalls of the groove 204b is less than the width d2 of the groove 204b, the conductive layer 206 grown on the left and right sidewalls of the groove 204b cannot merge when the conductive layer 206 is grown by the sidewall method, resulting in a defect in the formed contact portion.

[0090] For example, the conductive layers 206 in the first and second recesses respectively form a first contact and a second contact. The conductive layers 206 on the sidewalls of the recesses 204 between the first and second contactes respectively constitute a first connecting line and a second connecting line connecting the first and second contactes. Specifically, a conductive layer 206 is formed in the recess 204. The conductive layer 206 includes a connecting line 206a covering the sidewalls 204 of the recess 204, and at least two contact portions 206b extending from and spaced apart from the connecting line 206a. The contact portions 206b are used for electrically connecting to contact plugs in semiconductor devices.

[0091] For example, refer to Figures 2E to 2F After the conductive layer 206 is formed, the remaining sacrificial material layer 203 can be removed. At this point, refer to... Figure 2F The thickness h of the conductive layer 206 is equal to the depth of the groove 204. Therefore, the thickness h of the conductive layer 206 can be adjusted by controlling the depth of the groove 204. The sacrificial material layer 203 can be removed by methods such as, but not limited to, wet etching and dry etching.

[0092] For example, refer to Figures 2E to 2G4 The semiconductor substrate 201 may include a first dielectric layer, in which at least two contact plugs 202 are formed. Each contact plug 202 includes a first contact plug whose top is exposed in a first recess to connect to a first contact portion, and a second contact plug whose top is exposed in a second recess to connect to a second contact portion. This enables the lead-out of the connecting wires in the conductive layer 206 and improves the reliability of the connection between the contact plugs 202 and the contact portions.

[0093] For example, refer to Figures 2G1 to 2G4The manufacturing method may further include removing a portion of the conductive layer 206 on the sidewall of the groove 204 to disconnect the first connecting line or the second connecting line. Specifically, either the first connecting line or the second connecting line may be disconnected. Some methods are illustrated below.

[0094] For example, refer to Figures 2G1 to 2G4 At least two contact portions 206b may include a first contact portion 206b1 and a second contact portion 206b2, and the connecting line 206a includes a first connecting line 206a1 and a second connecting line 206a2 connected in parallel between the first contact portion 206b1 and the second contact portion 206b2. At this time, refer to... Figures 2G1 to 2G4 The manufacturing method may further include: forming a first cut-off point 207 on the first connecting line 206a1 to disconnect the first connecting line 206a1. The length of the first connecting line 206a1 is not greater than the length of the second connecting line 206a2. For details, refer to... Figure 2G1 The length of the first connecting line 206a1 can be equal to the length of the second connecting line 206a2, or, refer to... Figures 2G2 to 2G4 The length of the first connecting line 206a1 is less than the length of the second connecting line 206a2.

[0095] By forming a first cut-off point 207 on the first connecting line 206a1, the parallel connection between the first contact portion 206b1 and the second contact portion 206b2 via the first connecting line 206a1 and the second connecting line 206a2 is changed to a series connection via the second connecting line 206a2. This can increase the resistance value between the first contact portion 206b1 and the second contact portion 206b2, which is beneficial for preparing a high-resistance conductive layer 206.

[0096] For example, refer to Figure 2G4At least two contact portions 206b also include a third contact portion 206b3 extending to the second connecting line 206a2. Through the third contact portion 206b3 extending to the second connecting line 206a2, the second connecting line 206a2 includes a first segment connecting the first contact portion 206b1 and the third contact portion 206b3, and also includes a second segment connecting the second contact portion 206b2 and the third contact portion 206b3. Thus, in addition to providing a first resistor with a relatively large resistance value based on the second connecting line 206a2 as two output terminals of the conductive layer 206, the first contact portion 206b1 and the third contact portion 206b3 can also provide a second resistor with a smaller resistance value compared to the first resistor, based on the first segment of the second connecting line 206a2, as two output terminals of the conductive layer 206. Alternatively, the second contact 206b2 and the third contact 206b3 can be used as two output terminals of the conductive layer 206 to provide a third resistor with a resistance value smaller than the first resistor, based on the second segment of the second connecting line 206a2. For example, by adjusting the line lengths of the first and second segments, the resistance values ​​of the second and third resistors can be made unequal, thereby realizing a resistor device providing three different resistance values ​​based on a single conductive layer 206.

[0097] For example, the manufacturing method may further include: forming an interlayer dielectric layer that at least covers the conductive layer 206; forming at least two contact plugs connected in the interlayer dielectric layer, each contact plug corresponding to a contact portion and electrically connected to the corresponding contact portion. For example, the at least two contact plugs may include: a first contact plug connected to a first contact portion, and a second contact plug connected to a second contact portion.

[0098] For example, refer to Figure 2H When no contact plug 202 is provided in the semiconductor substrate 201, after the conductive layer 206 is fabricated, a contact plug 210 can be provided above the conductive layer 206 for lead-out. Specifically, an interlayer dielectric layer 208 covering the conductive layer 206 can be formed first, then a through-hole contact plug 210 can be formed in the interlayer dielectric layer 208 to electrically connect the conductive layer 206, and then a conductive structure 209 can be provided on the interlayer dielectric layer 208 to achieve lead-out of the conductive layer 206.

[0099] Thus, the process steps of the semiconductor device manufacturing method according to an embodiment of the present invention are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0100] Example 2

[0101] Another embodiment of the present invention also provides a method for manufacturing another semiconductor device, referencing Figure 3 The manufacturing method mainly includes the following steps:

[0102] In S301, a first sacrificial layer is formed on the semiconductor substrate;

[0103] In S302, a second sacrificial layer having a first groove is formed on the first sacrificial layer;

[0104] In S303, a third sacrificial layer is conformally formed in the first groove to form a second groove in the third sacrificial layer;

[0105] In S304, a fourth sacrificial layer is filled into the second groove;

[0106] In S305, the portion of the third sacrificial layer not covered by the fourth sacrificial layer is removed, exposing the surface of the first sacrificial layer;

[0107] In S306, the exposed portion of the first sacrificial layer is removed to form an annular groove in the first sacrificial layer;

[0108] In S307, a conductive layer is formed in the annular groove.

[0109] The specific technical effects and principles are as follows: Compared with the prior art, the above embodiments of this application form a third sacrificial layer conformally in the first groove to form a second groove in the third sacrificial layer. The portion of the third sacrificial layer not covered by the fourth sacrificial layer is removed to expose the surface of the first sacrificial layer. Then, the exposed portion of the first sacrificial layer is removed to form an annular groove in the first sacrificial layer. Finally, a conductive layer is formed in the annular groove. This facilitates the fabrication of a conductive layer with high resistance and narrow linewidth, and helps to reduce the area occupied by the conductive layer.

[0110] Furthermore, when the linewidth of the connecting lines in the resistor structure is relatively thin, the connecting lines may drift or change in profile during the manufacturing process, resulting in a change in the actual width w of the connecting lines. For example, existing processes and the thin film deposition and etching processes in Embodiment 1 above easily form connecting lines with a sloping cross-section, causing the actual width of the connecting lines to drift, thereby affecting the resistance stability of the conductive layer.

[0111] Regarding the impact of actual width drift of interconnects on resistance drift risk, the influence of interconnect width consistency on the resistance stability of the conductive layer when the line width is thin can be explained based on the following assumptions. Assume the line width of both the contact and the interconnect is w, the length of the contact is a, the length of the interconnect is 2b+c, and the height of both the interconnect and the contact is h. When two interconnects of equal length are connected in parallel between the two contacts, based on the resistance calculation formula R = ρL / S (ρ resistivity, L length, S cross-sectional area), the parallel resistance R1 = ρ(2a+b+c / 2) / wh and the series resistance R2 = ρ(2a+2b+c) / wh are obtained when the conductive layer is connected in parallel. When the actual width w of the interconnect changes, the resistance of the resistor structure will drift compared to the designed resistance, affecting the resistance stability of the conductive layer. Therefore, controlling process factors that affect interconnect width consistency, such as the etching process of the interconnect, is particularly important.

[0112] Compared to Embodiment 1 above, in this embodiment, when removing the exposed portion of the first sacrificial layer to form an annular groove in the first sacrificial layer, a process with better conformability, such as but not limited to wet etching, can be used. This allows for better conformability of the groove wall of the annular groove (better preservation of the contour morphology). Subsequently, the conformability of the conductive layer formed in the annular groove is also better, ensuring the integrity of the cross-sectional contour in the conductive layer. This is beneficial for improving the consistency of the linewidth of the connecting lines, thereby ensuring that the width of the connecting lines in the resistor structure prepared based on the conductive layer does not drift or the drift amount is small. In turn, it ensures that the resistance value of the conductive layer does not drift or the drift amount is small, reducing the risk of resistance drift of the conductive layer caused by poor linewidth consistency of the connecting lines.

[0113] Below, for reference Figures 4A to 4M The manufacturing method of the semiconductor device according to embodiments of the present invention will be described in detail.

[0114] First, refer to Figure 4A A semiconductor substrate 401 is provided. The type of semiconductor substrate 401 can be referred to the description in the foregoing embodiments, and will not be repeated here. For example, refer to... Figure 4A A contact plug 402 may be provided in the semiconductor substrate 401 for electrical connection with the conductive layer formed on the semiconductor substrate 401.

[0115] Next, refer to Figure 4B A first sacrificial layer 403 is formed on a semiconductor substrate 401. The process for forming the first sacrificial layer 403 can be such as, but not limited to, deposition, growth, etc.

[0116] Next, refer to Figures 4B to 4C4 A second sacrificial layer 404 with a first groove 405 is formed on the first sacrificial layer 403. This can be achieved in various ways. Some methods are illustrated below.

[0117] For example, a second sacrificial layer 404 can be deposited on a semiconductor substrate 401 first, and then the second sacrificial layer 404 can be patterned to form a first groove 405 in the second sacrificial layer 404. The patterning process can be such as, but not limited to, photolithography, wet etching, dry etching, etc.

[0118] Regarding the shape of the first groove 405, it is basically the same as the groove in Embodiment 1, and can specifically be any groove-shaped structure formed in the second sacrificial layer 404 with a closed outline. Some methods are described below by example.

[0119] For example, refer to Figures 4C1 to 4C4 The first groove 405 may include at least two outwardly protruding protrusions 405b spaced apart from each other. The protrusions 405b will be conformally retained in the annular groove as groove portions in the annular groove, so that the conductive layer subsequently formed in the groove portion in the annular groove constitutes a contact portion. The conductive layer subsequently formed in the annular groove between two adjacent groove portions constitutes a connecting line connecting the two adjacent contact portions, thereby creating a resistor structure composed of connecting line + at least two contact portions.

[0120] For example, refer to Figures 4C1 to 4C4 The first groove 405 includes at least two first protrusions and a second protrusion spaced apart from each other. The first protrusion serves as a first groove portion in the pre-formed annular groove, so that a first contact portion subsequently formed in the first groove portion connects with a first contact plug. The second protrusion serves as a second groove portion in the pre-formed annular groove, so that a second contact portion subsequently formed in the second groove portion connects with a second contact plug.

[0121] Regarding the shape of the first groove 405, various closed contour shapes can be adopted. Some examples are described below.

[0122] For example, refer to Figures 4C1 to 4C4 The first groove 405 may include a main groove region 405a and at least two protrusions 405b that are connected to and spaced apart from the main groove region 405a. The protrusions 405b are convex outwards relative to the main groove region 405a. The distance between two opposite sidewalls on the protrusions 405b is equal to the width of the contact portion in the conductive layer, and can be defined as d2. The minimum distance between two opposite sidewalls on the main groove region 405a is a first predetermined distance, and the maximum distance between two opposite sidewalls on the protrusions 405b is a second predetermined distance. The first predetermined distance is greater than the second predetermined distance. Specifically, refer to... Figure 4C1The minimum distance between two opposite sidewalls on the main groove area 405a is the first set distance d3, and the maximum distance between two opposite sidewalls on the protrusion 405b is the second set distance d2. Then d3 > d2.

[0123] By adopting the above configuration, the distance between two opposite sidewalls at any position on the main groove area 405a is greater than the distance between two opposite sidewalls at any position on the protrusion 405b, which facilitates the formation of the main body of the annular groove based on the sidewalls of the main groove area 405a, and also facilitates the formation of the groove portion of the annular groove based on the protrusion 405b.

[0124] Regarding the shape of the main recessed area 405a, various large shapes can be adopted. For example, refer to... Figures 4C1 to 4C2 The main recessed area 405a is a large rectangle. (Reference) Figure 4C3 and Figure 4C4 The main groove area 405a can also be in the shape of a larger E-shape.

[0125] Regarding the arrangement of the protrusion 405b, it communicates with the main groove area 405a, and different protrusions 405b are spaced apart. Regarding the number of protrusions 405b, it can be at least two, specifically equal to the number of contact portions required. For example, refer to... Figures 4C1 to 4C3 There are two protrusions 405b, namely a first protrusion and a second protrusion, which can be disposed at any mutually spaced positions in the main groove area 405a. For example, refer to... Figure 4C4 There are three protrusions 405b, which can be set at any mutually spaced positions in the main groove area 405a.

[0126] Next, refer to Figure 4D A third sacrificial layer 406 is conformally formed in the first groove 405 to form a second groove 407 in the third sacrificial layer 406. It should be noted that the shape of the second groove 407 is determined based on the shape and size of the first groove 405 and the deposition thickness of the third sacrificial layer 406. The size of the second groove is smaller than the size of the first groove, and the shape of the second groove may have a variation relative to the shape of the first groove.

[0127] In some embodiments, reference Figure 4C1 and Figure 4DThe first groove 405 has at least two outwardly protruding protrusions 405b spaced apart from each other. In this case, the third sacrificial layer 406 can fill the protrusions 405b in the first groove 405, so that the second groove 407 has no protrusions 405b. Specifically, by adjusting the thickness of the third sacrificial layer 406, the size of the main groove region 405a in the first groove 405, and the size of the protrusions 405b, the third sacrificial layer 406 can fill the protrusions 405b in the first groove 405, so that the second groove 407 no longer has protrusions 405b. This facilitates the subsequent formation of an annular groove with outwardly protruding groove portions based on the third sacrificial layer 406, thereby enabling the formation of a conductive layer with contact portions.

[0128] There are various ways to conformally form the third sacrificial layer 406 in the first groove 405, such as, but not limited to, thin film deposition, growth and other processes.

[0129] For example, the formation process of the third sacrificial layer 406 may include an atomic layer deposition process. By utilizing the good thickness uniformity characteristic of the atomic layer deposition process, the thickness uniformity of the third sacrificial layer 406 is improved, thereby making the groove width of the subsequently formed annular groove more consistent, so as to facilitate the complete cross-sectional profile and uniform line width of the conductive layer.

[0130] For example, a third sacrificial layer 406 can be formed using processes such as, but not limited to, thin film deposition, such that the third sacrificial layer 406 not only covers the sidewalls and bottom of the first groove 405 to form the second groove 407 in the third sacrificial layer 406, but also covers the upper surface of the second sacrificial layer 404. Because the third sacrificial layer 406 is relatively thin, when it is deposited on the groove wall of the first groove 405, a second groove 407 with a modified shape and smaller size can be formed in the third sacrificial layer 406.

[0131] For example, refer to Figure 4D The deposition thickness of the third sacrificial layer 406 is equal to the width d1 of the connecting line. It can be defined that both the deposition thickness of the third sacrificial layer 406 and the width of the connecting line are d1. For example, the deposition thickness d1 of the third sacrificial layer 406 can be greater than or equal to half of the second predetermined spacing d2, and less than half of the first predetermined spacing d3, that is... 1 / 2×d2≤d1< 1 / 2×d3.

[0132] Next, refer to Figure 4E and Figure 4F A fourth sacrificial layer 409 is filled into the second groove 407. The fourth sacrificial layer 409 can be filled into the second groove 407 in various ways, some of which are exemplarily described below.

[0133] For example, filling the second groove 407 with the fourth sacrificial layer 409 may include:

[0134] refer to Figure 4E A fourth sacrificial material layer 408 is formed on the third sacrificial layer 406. The fourth sacrificial material layer 408 fills the second groove 407. Specifically, the fourth sacrificial material layer 408 can fill the second groove 407.

[0135] refer to Figure 4F The portion of the fourth sacrificial material layer 408 located outside the second groove 407 is removed, and the portion remaining inside the second groove 407 is the fourth sacrificial layer 409.

[0136] The removal of the portion of the fourth sacrificial material layer 408 located outside the second groove 407 can be achieved through various methods, such as, but not limited to, etching and planarization processes. The planarization process can employ, but is not limited to, chemical mechanical polishing (CMP). This ensures that the fourth sacrificial layer 409 only covers the portion of the third sacrificial layer 406 located at the bottom of the second groove, without covering the rest of the third sacrificial layer 406. This allows for subsequent selective etching to remove the portion of the third sacrificial layer 406 not covered by the fourth sacrificial layer 409, facilitating the formation of a shape-preserving annular groove.

[0137] Next, refer to Figure 4G The portion of the third sacrificial layer 406 not covered by the fourth sacrificial layer 409 is removed, exposing the surface of the first sacrificial layer 403. Various methods can be used to remove the portion of the third sacrificial layer 406 not covered by the fourth sacrificial layer 409.

[0138] In some embodiments, reference Figure 4G Selective wet etching can be used to remove the portion of the third sacrificial layer 406 not covered by the fourth sacrificial layer 409. Utilizing the good conformality of wet etching, a well-formed annular groove 410 is formed between the fourth sacrificial layer 409 and the second sacrificial layer 404, thereby improving the integrity of the cross-sectional profile of the final conductive layer, reducing the risk of resistance drift, and enhancing resistance stability. Furthermore, a portion of the surface of the first sacrificial layer 403 is exposed to the annular groove 410 formed by the second sacrificial layer 404 and the fourth sacrificial layer 409. This facilitates subsequent etching of the remaining portion of the first sacrificial layer 403 using a conformality-preserving etching process, extending the annular groove 410 formed by the second sacrificial layer 404 and the fourth sacrificial layer 409 downwards into the first sacrificial layer 403, thus achieving the formation of the annular groove 410 within the first sacrificial layer 403.

[0139] It should be noted that the reference Figure 4DThe deposition thickness d1 of the third sacrificial layer 406 is not the maximum thickness of the third sacrificial layer 406. Because the dimensions of different positions in the first groove 405 vary during the thin film deposition process, the actual thickness of the third sacrificial layer 406 at different positions may differ. The deposition thickness d1 of the third sacrificial layer 406 can be determined by controlling the deposition process, or the thickness of the third sacrificial layer 406 formed on the upper surface of the second sacrificial layer 404 can be used as the deposition thickness d1. Of course, because the spacing of the main groove regions 405a is relatively large, the thickness of the third sacrificial layer 406 covering the sidewalls of the main groove regions 405a can also be used as the deposition thickness d1 of the third sacrificial layer 406. However, because the sidewall spacing of the protrusions 405b is relatively small, the actual thickness of the third sacrificial layer 406 at the protrusion 405b position is greater than the deposition thickness d1 of the third sacrificial layer 406.

[0140] refer to Figure 4D By employing a thin-film deposition process, a uniformly thick third sacrificial layer 406 can be easily formed, which facilitates precise control over the consistency of the linewidth of the final interconnect. By ensuring that the deposition thickness d1 of the third sacrificial layer 406 is greater than or equal to half of the second predetermined spacing d2 (i.e., d2 ≤ 2 × d1), the third sacrificial layer fills the protrusion 405b, thereby conformally retaining the protrusion 405b within the annular groove 410. This means the formed annular groove 410 includes the groove portion 410b, improving the reliability of the contact portion finally formed in the groove portion 410b. By ensuring that the deposition thickness d1 of the third sacrificial layer 406 is less than half of the first predetermined spacing d3, contact between the portions of the third sacrificial layer 406 covering the two opposite sidewalls of the main groove region 405a is avoided, preventing the formation of the groove portion 410b in the annular groove 410.

[0141] In some embodiments, reference Figure 4D This allows the deposition thickness d1 of the third sacrificial layer 406 to be less than the second set spacing d2, thereby making the line width d1 of the fabricated connecting line smaller than the line width d2 of the extended contact portion. While reducing the line width d1 of the connecting line, it also ensures that the difficulty of leading out the conductive layer is not affected, making it easier to set a larger area contact portion. This simplifies the difficulty of aligning the contact plug and the contact portion for electrical connection and improves the reliability of the electrical connection between the two.

[0142] In some embodiments, reference is made to Figure 4DThis allows the deposition thickness d1 of the third sacrificial layer 406 to satisfy the relationship d2 between the two opposing sidewalls on the protrusion 405b: d1 < d2 ≤ 2 × d1. By growing the third sacrificial layer 406 on the left and right sidewalls of the protrusion 405b using the sidewall method, the third sacrificial layers 406 grown on both sides can merge, thus conformally retaining the protrusion 405b in the first groove 405 into the annular groove 410, serving as the groove portion 410b of the annular groove 410. This enables the formation of a thinner connecting line in one step while simultaneously creating a wider contact area, improving the reliability of the electrical connection. (Reference) Figure 4I If d2 > 2 × d1, since the total width (2 × d1) of the third sacrificial layer 406 grown on the left and right sidewalls of the protrusion 405b is less than the width d2 of the protrusion 405b, the third sacrificial layer 406 grown on the left and right sidewalls of the protrusion 405b cannot merge when the third sacrificial layer 406 is grown by the sidewall method. As a result, the protrusion 405b in the first groove 405 cannot be conformally retained in the groove portion 410b of the annular groove 410, resulting in a defect in the formed contact portion.

[0143] Next, refer to Figure 4H The exposed portion of the first sacrificial layer 403 is removed to form an annular groove 410 within the first sacrificial layer 403. In this step, a process such as, but not limited to, selective wet etching can be used to etch the exposed portion of the first sacrificial layer 403, extending the annular groove 410 formed by the second sacrificial layer 404 and the fourth sacrificial layer 409 downwards into the first sacrificial layer 403. Utilizing the good conformal properties of wet etching, it is beneficial to form a well-conformal annular groove 410 in the first sacrificial layer 403, thereby improving the integrity of the cross-sectional profile of the final conductive layer, reducing the risk of resistance drift in the resistive structure, and improving resistance stability.

[0144] In some embodiments, the annular groove 410 includes at least two outwardly protruding groove portions 410b that are spaced apart from each other; the groove portions 410b are filled with a conductive layer to form a contact portion, and the conductive layer between two adjacent contact portions forms a connecting line connecting the two adjacent contact portions; wherein, the width of the connecting line is defined as d1, and the width of the contact portion is defined as d2, then d1 and d2 satisfy the relationship: d1<d2≤2×d1.

[0145] For example, during the fabrication process, the width of the non-grooved portion of the annular groove 410 can be determined as d1 based on the width d1 of the connecting line, and the width of the grooved portion 410b of the annular groove 410 can be determined as d2 based on the width d2 of the contact portion. Since the annular groove 410 is related to the thickness of the third sacrificial layer 406 and the shape of the first groove 405, the annular groove 410 fabricated using the sidewall method has an extremely small linewidth, resulting in an extremely small linewidth for the connecting line. This allows it to be applied in miniaturization techniques. Furthermore, a wider contact portion extending from the connecting line is formed, facilitating electrical connection between the connecting line and the contact plug through the contact portion, which is beneficial for the lead-out of the connecting line.

[0146] In some embodiments, reference Figure 4H After removing the exposed portion of the first sacrificial layer 403, the manufacturing method may further include removing the fourth sacrificial layer 409. On the one hand, this can reduce the depth of the annular groove 410, thereby facilitating the formation of a conductive layer with fewer pores in the annular groove 410, improving the quality of the conductive layer, and thus improving the resistance stability of the final conductive structure.

[0147] For example, the materials of the first sacrificial layer 403 to the fourth sacrificial layer 409 may all be different and different from the material of the semiconductor substrate 401 surface, thereby having different etching selectivity ratios to facilitate the subsequent removal of the remaining sacrificial layers.

[0148] Of course, in other embodiments, some materials of the first sacrificial layer 403 to the fourth sacrificial layer 409 are the same, while some materials are different, as long as selective etching can be achieved in the corresponding steps. For example, the material of the first sacrificial layer 403 can be silicon nitride, the material of the second sacrificial layer 404 can be silicon (specifically, polysilicon (A-silicon)), the material of the third sacrificial layer 406 can be oxide, and the material of the fourth sacrificial layer 409 can be silicon (specifically, polysilicon (A-silicon)).

[0149] Next, refer to Figure 4I and Figure 4J A conductive layer 412 is formed in the annular groove 410. Various methods can be used to form the conductive layer 412 in the annular groove 410.

[0150] In some embodiments, if the fourth sacrificial layer 409 is removed before forming the conductive layer 412 in the annular groove 410, forming the conductive layer 412 in the annular groove 410 may include:

[0151] refer to Figure 4I A conductive material layer 411 is formed, which at least covers the upper surfaces of the second sacrificial layer 404 and the third sacrificial layer 406, and the conductive material layer 411 also fills the annular groove 410.

[0152] refer to Figure 4J Remove the portion of the conductive material layer 411 located outside the annular groove 410, as well as the second sacrificial layer 404 and the third sacrificial layer 406. The portion of the conductive material layer 411 remaining in the annular groove 410 is the conductive layer 412.

[0153] The process of removing the portion of the conductive material layer 411 located outside the annular groove 410, as well as the second sacrificial layer 404 and the third sacrificial layer 406, can employ processes such as, but not limited to, etching and planarization. A preferred embodiment may employ chemical mechanical polishing (CMP) to remove the portion of the conductive material layer 411 located outside the annular groove 410, as well as the second sacrificial layer 404 and the third sacrificial layer 406, thereby improving the flatness of the upper surface of the conductive layer 412.

[0154] In other embodiments, before forming the conductive layer 412 in the annular groove 410, after removing the fourth sacrificial layer 409, the second sacrificial layer 404 and the third sacrificial layer 406 can be further removed to further reduce the depth of the annular groove 410. This is more conducive to improving the quality of the conductive layer 412 subsequently formed in the annular groove 410, thereby improving the resistance stability of the final formed resistor structure. In this case, forming the conductive layer 412 in the annular groove 410 may include: forming a conductive material layer that at least covers the upper surface of the first sacrificial layer 403 and also fills the annular groove 410; removing the portion of the conductive material layer located outside the annular groove 410, leaving the portion of the conductive material layer remaining in the annular groove 410 as the conductive layer 412.

[0155] The process of removing the portion of the conductive material layer located outside the annular groove 410 can employ techniques such as, but not limited to, etching and planarization. A preferred embodiment may employ chemical mechanical polishing (CMP) to remove the portion of the conductive material layer located outside the annular groove 410, thereby improving the flatness of the upper surface of the conductive layer 412.

[0156] Of course, in some embodiments, the fourth sacrificial layer 409 may not be removed before forming the conductive layer 412 in the annular groove 410. In this case, forming the conductive layer 412 in the annular groove 410 may include: forming a conductive material layer that at least covers the upper surfaces of the second sacrificial layer 404 and the fourth sacrificial layer 409, and the conductive material layer also fills the annular groove 410; removing the portion of the conductive material layer located outside the annular groove 410, as well as the second sacrificial layer 404, the third sacrificial layer 406, and the fourth sacrificial layer 409, and the portion of the conductive material layer remaining in the annular groove 410 is the conductive layer 412.

[0157] The process of removing the portion of the conductive material layer located outside the annular groove 410, as well as the second sacrificial layer 404, the third sacrificial layer 406, and the fourth sacrificial layer 409, can employ processes such as, but not limited to, etching and planarization. A preferred embodiment may employ chemical mechanical polishing (CMP) to remove the portion of the conductive material layer located outside the annular groove 410, as well as the second sacrificial layer 404, the third sacrificial layer 406, and the fourth sacrificial layer 409, thereby improving the flatness of the upper surface of the conductive layer 412.

[0158] For example, the conductive layer 412 formed in the annular groove 410 may include a connecting line 412a and at least two contact portions 412b extending from and spaced apart from the connecting line 412a, the contact portions 412b being used to electrically connect to contact plugs in semiconductor devices.

[0159] For example, refer to Figure 4G The third sacrificial layer 406 in the first and second groove portions is conformally retained in the annular groove 410, serving as the first and second groove portions of the annular groove 410. (Reference) Figure 4K Thus, the final conductive layer 412 includes a first contact portion and a second contact portion, and the conductive layer 412 in the annular groove 410 between the first contact portion and the second contact portion respectively constitutes a first connecting line and a second connecting line connecting the first contact portion and the second contact portion.

[0160] For example, refer to Figures 4J to 4K After the conductive layer 412 is formed, the remaining first sacrificial layer 403 can be removed. At this time, reference... Figure 4K The thickness h of the conductive layer 412 is equal to the depth of the annular groove 410. Therefore, the thickness h of the conductive layer 412 can be adjusted by controlling the depth of the annular groove 410. The first sacrificial layer 403 can be removed by methods such as, but not limited to, wet etching and dry etching.

[0161] For example, refer to Figures 4K to 4L4 The semiconductor substrate 401 may include a first dielectric layer, in which at least two contact plugs 402 are formed. Each contact plug 402 includes a first contact plug whose top is exposed in a first recess of an annular groove 410 to connect to a first contact portion, and a second contact plug whose top is exposed in a second recess of the annular groove 410 to connect to a second contact portion. This facilitates the routing of connecting lines in the conductive layer 412 and improves the reliability of the connection between the contact plugs and the contact portions.

[0162] For example, refer to Figures 4L1 to 4L4The manufacturing method may further include removing a portion of the conductive layer 412 to disconnect the first connecting line or the second connecting line. Specifically, either the first connecting line or the second connecting line may be disconnected. Some methods are illustrated below.

[0163] For example, refer to Figures 4L1 to 4L4 At least two contact portions 412b may include a first contact portion 412b1 and a second contact portion 412b2, and the connecting line 412a includes a first connecting line 412a1 and a second connecting line 412a2 connected in parallel between the first contact portion 412b1 and the second contact portion 412b2. At this time, refer to... Figures 4L1 to 4L4 The manufacturing method may further include: forming a second cut-off point 413 on the first connecting line 412a1 to disconnect the first connecting line 412a1. The length of the first connecting line 412a1 is not greater than the length of the second connecting line 412a2. For details, refer to... Figure 4L1 The length of the first connecting line 412a1 can be equal to the length of the second connecting line 412a2, or, refer to... Figures 4L2 to 4L4 The length of the first connecting line 412a1 is less than the length of the second connecting line 412a2.

[0164] By forming a second cut-off point 413 on the first connecting line 412a1, the parallel connection between the first contact portion 412b1 and the second contact portion 412b2 via the first connecting line 412a1 and the second connecting line 412a2 is changed to a series connection via the second connecting line 412a2. This can increase the resistance value between the first contact portion 412b1 and the second contact portion 412b2, which is beneficial for preparing a high-resistance conductive layer 412.

[0165] For example, refer to Figure 4L4At least two contact portions 412b also include a third contact portion 412b3 extending to the second connecting line 412a2. Through the third contact portion 412b3 extending to the second connecting line 412a2, the second connecting line 412a2 includes a first segment connecting the first contact portion 412b1 and the third contact portion 412b3, and also includes a second segment connecting the second contact portion 412b2 and the third contact portion 412b3. Thus, in addition to providing a first resistor with a relatively large resistance value based on the second connecting line 412a2 as two output terminals of the conductive layer 412, the first contact portion 412b1 and the second contact portion 412b2 can also provide a second resistor with a smaller resistance value compared to the first resistor, based on the first segment of the second connecting line 412a2, as two output terminals of the conductive layer 412. Alternatively, the second contact portion 412b2 and the third contact portion 412b3 can be used as two output terminals of the conductive layer 412 to provide a third resistor with a resistance value smaller than the first resistor, based on the second segment of the second connecting line 412a2. For example, by adjusting the line lengths of the first and second segments, the resistance values ​​of the second and third resistors can be made unequal, thereby realizing a resistor device providing three different resistance values ​​based on a single conductive layer 412.

[0166] For example, the manufacturing method may further include: forming an interlayer dielectric layer that at least covers a conductive layer; forming at least two contact plugs connected in the interlayer dielectric layer, each contact plug corresponding to a contact portion and electrically connected to the corresponding contact portion. For example, the at least two contact plugs may include: a first contact plug connected to a first contact portion, and a second contact plug connected to a second contact portion.

[0167] For example, refer to Figure 4M When no contact plug 402 is provided in the semiconductor substrate 401, after the conductive layer 412 is fabricated, a contact plug 416 can be provided above the conductive layer 412 for lead-out. Specifically, an interlayer dielectric layer 414 covering the conductive layer 412 can be formed first, and then a through contact plug 416 can be formed in the interlayer dielectric layer 414 to electrically connect the conductive layer 412. Afterward, a conductive structure 415 can be provided on the interlayer dielectric layer 414 to realize the lead-out of the conductive layer 412.

[0168] Thus, the process steps of the semiconductor device manufacturing method according to an embodiment of the present invention are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0169] Example 3

[0170] In another embodiment of the present invention, a semiconductor device is provided, which is prepared by the manufacturing method of the semiconductor device shown in Embodiment 1 or Embodiment 2 above.

[0171] Example 4

[0172] In another embodiment of the present invention, an electronic device is provided, which includes the aforementioned semiconductor device. This electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device of this embodiment of the present invention, due to the use of the aforementioned semiconductor device, has better performance.

[0173] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide semiconductor substrates; A sacrificial material layer is formed on the semiconductor substrate; The sacrificial material layer is patterned to form grooves in the sacrificial material layer; A conductive layer is formed only on the sidewalls of the groove.

2. The manufacturing method as described in claim 1, characterized in that, The method of forming a conductive layer only on the sidewalls of the groove includes: A conductive material layer is deposited, which covers the upper surface of the sacrificial material layer, the bottom surface of the groove, and the sidewalls; Remove the conductive material layer from the upper surface of the sacrificial material layer and the bottom surface of the groove, leaving the conductive material layer as the remaining portion.

3. The manufacturing method as described in claim 2, characterized in that, The conductive material layer is deposited using atomic layer deposition.

4. The manufacturing method as described in claim 1, characterized in that, The groove includes at least two groove portions spaced apart from each other, the conductive layer in the groove portion constitutes a contact portion, and the conductive layer on the sidewall of the groove between two adjacent contact portions constitutes a connecting line connecting the two adjacent contact portions. Wherein, the width of the connecting line is defined as d1, and the width of the contact portion is defined as d2. Then, d1 and d2 satisfy the relationship: d1<d2≤2×d1.

5. The manufacturing method as described in claim 4, characterized in that, The semiconductor substrate includes a first dielectric layer, in which at least two contact plugs are formed; Each of the contact plugs corresponds to one of the grooves and one of the contact portions, with the top of each contact plug exposed in the corresponding groove to connect to the corresponding contact portion.

6. The manufacturing method as described in claim 4, characterized in that, Also includes: Remove a portion of the conductive layer on the sidewall of the groove to disconnect a portion of the connecting wire.

7. A method for manufacturing a semiconductor device, characterized in that, include: A first sacrificial layer is formed on a semiconductor substrate; A second sacrificial layer with a first groove is formed on the first sacrificial layer; A third sacrificial layer is conformally formed in the first groove to form a second groove in the third sacrificial layer; The second groove is filled with a fourth sacrificial layer; Remove the portion of the third sacrificial layer not covered by the fourth sacrificial layer to expose the surface of the first sacrificial layer; Remove the exposed portion of the first sacrificial layer to form an annular groove in the first sacrificial layer; A conductive layer is formed in the annular groove.

8. The manufacturing method as described in claim 7, characterized in that, The first groove has at least two outwardly protruding protrusions spaced apart from each other, and the third sacrificial layer fills the protrusions so that the second groove does not have the protrusions.

9. The manufacturing method as described in claim 7, characterized in that, The formation process of the third sacrificial layer includes atomic layer deposition.

10. The manufacturing method as described in claim 7, characterized in that, The third sacrificial layer also covers the upper surface of the second sacrificial layer; The step of filling the second groove with a fourth sacrificial layer includes: A fourth sacrificial material layer is formed on the third sacrificial layer, and the fourth sacrificial material layer fills the second groove; The portion of the fourth sacrificial material layer located outside the second groove is removed, and the portion remaining inside the second groove constitutes the fourth sacrificial layer.

11. The manufacturing method as described in claim 7, characterized in that, After removing the exposed portion of the first sacrificial layer, the manufacturing method further includes removing the fourth sacrificial layer.

12. The manufacturing method as described in claim 11, characterized in that, The formation of a conductive layer in the annular groove includes: A conductive material layer is formed, the conductive material layer at least covering the upper surfaces of the second sacrificial layer and the third sacrificial layer, and the conductive material layer also fills the annular groove; The portion of the conductive material layer located outside the annular groove, as well as the second sacrificial layer and the third sacrificial layer, are removed. The portion of the conductive material layer remaining in the annular groove is the conductive layer.

13. The manufacturing method as described in claim 7, characterized in that, The annular groove includes at least two outwardly protruding groove portions that are spaced apart from each other; The groove is filled with the conductive layer to form a contact portion, and the conductive layer located between two adjacent contact portions forms a connecting line connecting the two adjacent contact portions. Wherein, the width of the connecting line is defined as d1, and the width of the contact portion is defined as d2. Then, d1 and d2 satisfy the relationship: d1<d2≤2×d1.

14. A semiconductor device, characterized in that, The semiconductor device is prepared using the semiconductor device manufacturing method as described in any one of claims 1 to 13.

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