A resistance unit, a resistance testing system, and a method

Abstract

The application provides a resistance test unit, system and method, and relates to the technical field of semiconductors. The test unit comprises: a laminated structure; a dielectric layer; the dielectric layer is formed on the laminated structure; two test through holes; the two test through holes penetrate the dielectric layer and are in contact with the laminated structure, and are used for testing the resistance of the laminated structure; the laminated structure has a preset layer number in the region between the two test through holes in the direction perpendicular to the thickness of the laminated structure; wherein the preset layer number is less than or equal to the layer number of the film in the laminated structure. The application can measure the contact resistance between the film layers in the laminated structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a resistor unit, a resistance testing system, and a method. Background Technology

[0002] The resistance of multilayer structures in semiconductor devices is mainly divided into two categories: sheet resistance and contact resistance. However, current resistance testing methods often collect the overall resistance of the multilayer structure, without extracting the contact resistance between the individual thin films. Yet, when layers come into contact in a multilayer structure, alloys, dislocations, point defects, or interface states form, all of which ultimately manifest in the contact resistance and sheet resistance. Therefore, current resistance measurement methods cannot obtain the contact resistance between layers, and consequently, cannot accurately determine whether defects exist between the layers. Summary of the Invention

[0003] This application provides a resistance testing unit, system, and method for providing a technical solution capable of measuring the contact resistance between film layers in a semiconductor structure.

[0004] In a first aspect, this application provides a resistance testing unit, comprising:

[0005] Layered structure;

[0006] Dielectric layer; the dielectric layer is formed on the stacked structure;

[0007] Two test vias; the two test vias penetrate the dielectric layer and are in contact with the stacked structure, for testing the resistance of the stacked structure;

[0008] Along a direction perpendicular to the thickness of the stacked structure, the stacked structure has a preset number of layers in the region between the two test vias; wherein the preset number of layers is less than or equal to the number of film layers in the stacked structure.

[0009] In one optional embodiment, the stacked structure includes n layers of film stacked together; the preset number of layers includes one to n layers.

[0010] In one optional embodiment, the stacked structure includes one of the following: a stacked structure formed by multiple semiconductor layers, a stacked structure formed by at least one semiconductor layer and at least one metal layer, and a stacked structure formed by multiple metal layers.

[0011] Secondly, this application also provides a resistance testing system, comprising:

[0012] Multiple groups of resistor units; each group of resistor units includes resistor units as described in any of the first aspects;

[0013] And a test unit; the test unit is used to calculate the contact resistance between each film layer and adjacent film layers in each of the stacked structures based on the measured resistance of the stacked structures in the plurality of resistor unit groups.

[0014] In an optional embodiment, each of the resistor unit groups includes a plurality of resistor units. In the same resistor unit group, the stacked structure of the plurality of resistor units includes the same film layer, and, along the direction perpendicular to the thickness of the resistor unit, the stacked structure of each resistor unit has the same number of layers in the region between the two test vias.

[0015] The test unit is used to obtain the measured resistance of the stacked structure in multiple resistor units within the same resistor unit group, and to calculate the contact resistance of the stacked structure corresponding to the resistor unit group based on the multiple measured resistances; wherein the resistance values ​​of the multiple measured resistances are different.

[0016] In one alternative implementation, the distance between two test vias in different resistor cells within the same group of resistor cells is different.

[0017] In one alternative implementation, in the same group of resistor units, the same film layer in multiple resistor units is made of the same material.

[0018] In an optional implementation, the test unit is further configured to calculate the sheet resistance of each film layer in each of the stacked structures based on the measured resistance of the stacked structures in the plurality of resistor unit groups.

[0019] In an alternative implementation, in different groups of resistor units, the stacked structure of the resistor units comprises the same film layer, and, along a direction perpendicular to the thickness of the resistor unit, the stacked structure of the resistor units has a different number of layers in the region between the two test vias.

[0020] In one optional embodiment, the stacked structure of the resistor unit includes one of the following: a stacked structure formed by multiple semiconductor layers, a stacked structure formed by at least one semiconductor layer and at least one metal layer, and a stacked structure formed by multiple metal layers.

[0021] In an optional embodiment, the film layer in the stacked structure comprises a single film layer or a stack formed by multiple film layers.

[0022] Thirdly, this application also provides a resistance testing method, applied in the test unit of the resistance testing system according to any one of the second aspects, the method comprising:

[0023] Based on the resistance of the stacked structures in the plurality of resistor unit groups, the contact resistance between each film layer and the adjacent film layer in each stacked structure is calculated.

[0024] Fourthly, this application also provides a resistance testing device, including: a processor, and a memory communicatively connected to the processor;

[0025] The memory stores computer-executed instructions;

[0026] The processor executes computer execution instructions stored in the memory to implement the method as described in the third aspect.

[0027] Fifthly, this application also provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method described in the third aspect.

[0028] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the method described in the third aspect.

[0029] With the above technical solution adopted, the resistor unit provided in this application includes a stacked structure, a dielectric layer, and two test vias; and along the direction perpendicular to the thickness of the stacked structure, the stacked structure has a preset number of layers in the region between the two test vias. Based on this, by setting a preset number of layers in the region between the two test vias, this application can realize layer-by-layer testing of the stacked structure, thereby obtaining the contact resistance between adjacent layers in the stacked structure. It should be understood that the contact resistance between adjacent layers in the stacked structure can reflect whether there are microstructural problems such as alloys, dislocations, point defects, or interface states between adjacent film layers in the stacked structure, providing an important basis for defect detection and process optimization of semiconductor devices, and helping to improve device performance and reliability.

[0030] Furthermore, by adjusting the position of the test vias and the preset number of layers, this application can adapt to stacked structures with different numbers of layers and structures, exhibiting high versatility and scalability, and can be applied to a variety of semiconductor devices. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0032] Figure 1 A structural diagram of a resistor unit provided in an embodiment of this application;

[0033] Figure 2 This is a structural diagram of another resistor unit provided in an embodiment of this application;

[0034] Figure 3 This is a structural diagram of another resistor unit provided in an embodiment of this application;

[0035] Figure 4 This is a schematic diagram of the structure of a first type of resistor unit in a resistor unit group provided in an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of the structure of a second type of resistor unit in a resistor unit group provided in an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of the structure of a third type of resistor unit in a resistor unit group provided in an embodiment of this application;

[0038] Figure 7 A fitting curve for measuring the resistance of multiple resistor units in the same group and the distance between two corresponding test vias is provided for an embodiment of this application.

[0039] Figure 8 This application provides a schematic diagram of a process for fabricating multiple resistor units using a single photomask. Figure 1 ;

[0040] Figure 9 This application provides a schematic diagram of a process for fabricating multiple resistor units using a single photomask. Figure 2 ;

[0041] Figure 10 This application provides a schematic diagram of a process for fabricating multiple resistor units using the same photomask layer, as illustrated in an embodiment of the present application. Figure 3 ;

[0042] Figure 11 This application provides a schematic diagram of a process for forming multiple resistor units on the same substrate. Figure 1 ;

[0043] Figure 12 This application provides a schematic diagram of a process for forming multiple resistor units on the same substrate. Figure 2 ;

[0044] Figure 13 This application provides a schematic diagram of a process for forming multiple resistor units on the same substrate. Figure 3 ;

[0045] Figure 14 This application provides a schematic diagram of a process for forming multiple resistor units on the same substrate. Figure 4 ;

[0046] Figure 15 This is a schematic diagram of the structure of a resistance testing device provided in an embodiment of this application.

[0047] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. It is understood that the terms “first,” “second,” etc., as used herein may be used to describe various information or data, but these elements are not limited by these terms. These terms are only used to distinguish first information from another type of information. For example, without departing from the scope of this application, first action information may be referred to as second action information, and similarly, second action information may be referred to as first action information. Both first action information and second action information are action information, but they are not the same action information.

[0050] First, the technical terms involved in the embodiments of this application will be explained:

[0051] Sheet resistance: a parameter used to describe the resistive properties of thin-film materials, widely used in semiconductor manufacturing, materials science, and electronic engineering. It is a two-dimensional unit of resistance measurement, representing the resistance per unit area, independent of specific geometric dimensions (such as length and width).

[0052] Contact resistance: refers to the resistance at the interface between two conductive materials.

[0053] Layered structures are structures composed of multiple layers of materials or components stacked together. In the electronics industry, layered structures are commonly used to manufacture integrated circuits, printed circuit boards (PCBs), and other semiconductor devices. These structures typically consist of alternating conductive, insulating, and semiconductor layers to achieve complex circuit functions.

[0054] Thin film: A thin film typically refers to a thin layer of material, usually ranging in thickness from nanometers to micrometers. In the electronics industry, thin film technology is used to manufacture various devices, such as thin-film transistors (TFTs), capacitors, and sensors. These thin films are typically made of conductive, semiconductor, or insulating materials to achieve specific electrical properties.

[0055] The resistance of multilayer structures in semiconductor devices is mainly divided into two categories: sheet resistance and contact resistance. However, existing resistance testing methods typically only measure the overall resistance of the multilayer structure and cannot accurately extract the contact resistance between individual film layers. In actual multilayer structures, microstructural changes such as alloying, dislocations, point defects, or interface states occur when film layers come into contact. These changes are ultimately reflected in the contact resistance and sheet resistance of the multilayer structure. Due to the limitations of existing testing methods, the contact resistance between film layers cannot be accurately obtained, making it difficult to effectively determine whether defects exist between film layers.

[0056] This technical limitation restricts the accurate evaluation of semiconductor device performance and process optimization. Therefore, there is an urgent need to develop a method to measure the contact resistance between layers in a stacked thin film, which is of great significance for improving the performance and reliability of semiconductor devices.

[0057] Based on this, the technical concept of this application is to provide a technical solution in which the number of test layers in the stacked structure can be preset and the distance between test vias can be preset, so as to achieve the technical effect of being able to measure the contact resistance between each film layer in the stacked thin film, and thus effectively determine whether there are defects between each film layer.

[0058] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0059] In a first aspect, embodiments of this application provide a resistor unit, including:

[0060] A stacked structure may be included; the stacked structure may include a substrate layer and at least one film layer formed on the substrate layer. It should be understood that the stacked structure may be a stacked structure in any semiconductor device or structure, and the embodiments of this application do not impose any special limitations on it.

[0061] Optionally, the stacked structure can be a stacked structure in devices such as FinFET (Fin Field-Effect Transistor) and GAAFET (Gate-All-Around Field-Effect Transistor).

[0062] A dielectric layer; the dielectric layer is formed on the stacked structure.

[0063] The dielectric layer can be made of insulating materials, such as silicon dioxide, silicon nitride, or materials with low dielectric constant. The dielectric layer can be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) to ensure good interfacial properties with the multilayer structure.

[0064] Two test vias are provided; these two test vias penetrate the dielectric layer and are in contact with the stacked structure, for testing the resistance of the stacked structure. The dielectric layer provides support for the test vias.

[0065] The two test vias are formed by an etching process. They are used to apply current to the stacked structure and measure the voltage to obtain the resistance value of the stacked structure.

[0066] In the embodiments of this application, the positions of the two test holes can be set according to specific needs, and no special limitation is made thereto.

[0067] In this embodiment of the application, the stacked structure has a preset number of layers in the region between the two test vias along a direction perpendicular to the thickness of the stacked structure; wherein the preset number of layers is less than or equal to the number of film layers in the stacked structure.

[0068] Based on this, it can be understood that the region between the two test vias can have any number of layers, such as one, two, ... . Therefore, by having a pre-defined number of layers in the test vias and the region between them, layer-by-layer testing can be performed on the stacked structure to obtain multiple resistances. Based on these multiple resistances, the contact resistance between adjacent film layers in the stacked structure can be calculated.

[0069] For example, when the stacked structure includes n film layers; the preset number of layers includes one to n layers.

[0070] In one alternative embodiment, the stacked structure includes one of the following: a stacked structure formed by multiple semiconductor layers, a stacked structure formed by at least one semiconductor layer and at least one metal layer, and a stacked structure formed by multiple metal layers.

[0071] For example, in measuring the contact resistance between layers in a stacked structure in a high-frequency power device, the stacked structure can be a quantum well structure, including alternating layers of aluminum gallium nitride (AlGaN) and gallium nitride (GaN).

[0072] For example, when applied to measuring the contact resistance between layers in a CMOS gate stack, the stack structure may include a stack structure formed by a high-k dielectric (HfO2) and a metal gate (TiN / TaN).

[0073] For example, in the application of measuring the contact resistance between the film layers in a MEMS piezoelectric sensor stack, the stack structure may include a bottom electrode (Pt / Ti), a piezoelectric layer (AlN or PZT, 1 μm thick) and a top electrode (Al or Au).

[0074] As a concrete example, refer to Figure 1 , Figure 2 or Figure 3 The diagram shows a structural schematic of three resistor units provided in this application having different preset layers in the region between the corresponding two test vias (201 and 202).

[0075] The stacked structure 10 of the three resistor units has the same film layers (101, 102, 103), but the number of layers in the stacked structure of the three resistor units differs in the region between the two test vias (201 and 202). Specifically, in... Figure 1 In this resistor unit, there are three film layers (101, 102, and 102) in the region between the two test vias (201 and 202). Figure 2 In this resistor unit, there are two film layers (101 and 102) in the region between the two test vias (201 and 202). Figure 3 In this resistor unit, a film layer (101) is provided in the region between the two test vias (201 and 202).

[0076] It should be understood that the resistive element has different numbers of film layers in the region between the two test vias, resulting in different stacked structures in the resistive element. As a result, the resistance of the different resistive elements measured from the two test vias is also different.

[0077] The resistance of the resistance unit measured from the two test vias includes the contact resistance between the film layers, the contact resistance between the top film layer and the test via, and the sum of the product of the parallel sheet resistance of the film layers in the region between the two test vias and the length of the region between the two test vias (assuming the width of the region between the two test vias is a unit value). Based on this, the contact resistance between the film layers can be separated from the measured resistance of the resistance unit.

[0078] It should be further understood that the contact resistance between film layers is usually concentrated in a localized area of ​​the contact interface. If the contact area is too large, the contact resistance may be masked by the overall resistance, making it difficult to accurately separate and measure. A smaller contact area can highlight the contribution of the contact resistance, allowing it to occupy a larger proportion of the total resistance, thereby improving the sensitivity of the measurement.

[0079] Therefore, in this embodiment, the test via can be set at or near the edge of the film layer, and part of the film layer in the area between two measurement vias can be etched away, so that the film layer area under the contact via is smaller, so as to better separate the contact resistance from the measured resistance.

[0080] The following describes the number of separable contact resistances in multiple resistive units that have the same number of film layers but different numbers of film layers in the region between two contact vias.

[0081] Reference Figure 1 In this resistor unit, the region between the two contact vias has three film layers (101, 102 and 103), which is the same number of film layers as in the stacked structure 10. The contact resistance between the top film layer 103 and the measuring via can be separated from the measuring resistance of the stacked structure.

[0082] Reference Figure 2 In this resistor unit, the area between the two contact vias has two film layers (101 and 102), which is less than the number of film layers in the stacked structure 10. The contact resistance between film layer 103 and the measurement via, as well as the total contact resistance formed by the contact resistance between film layer 103 and film layer 102, can be separated from the measurement resistance of the stacked structure.

[0083] Reference Figure 3 In this resistor unit, the area between the two contact vias has a film layer (101), which is less than the number of film layers in the stacked structure 10. The contact resistance between the film layer 103 and the measurement via, the contact resistance between the film layer 103 and the film layer 102, and the total contact resistance formed by the contact resistance between the film layers 102 and the film layers 102 can be separated from the measurement resistance of the stacked structure.

[0084] Based on the above description, the resistor unit provided in this application includes a stacked structure, a dielectric layer, and two test vias. Along a direction perpendicular to the thickness of the stacked structure, the stacked structure has a preset number of layers in the region between the two test vias. Therefore, by setting a preset number of layers in the region between the two test vias, this application can perform layer-by-layer testing on the stacked structure, thereby obtaining the contact resistance between adjacent layers in the stacked structure. It should be understood that the contact resistance between adjacent film layers in the stacked structure can reflect whether there are microstructural problems such as alloying defects, dislocations, point defects, or interface states between adjacent film layers in the stacked structure. This provides an important basis for defect detection and process optimization of semiconductor devices, and helps to improve device performance and reliability.

[0085] Furthermore, by adjusting the position of the test vias and the preset number of layers, this application can adapt to semiconductor stacks with different numbers of layers and structures, exhibiting high versatility and scalability, and can be applied to a variety of semiconductor materials and devices.

[0086] Secondly, embodiments of this application also provide a resistance testing system, including:

[0087] Multiple resistor unit groups; each resistor unit group includes resistor units as described in the first aspect.

[0088] Each resistor unit group may include multiple resistor units. Within the same resistor unit group, the multiple resistor units have the same film layer. That is, within the same resistor unit group, each resistor unit includes the same number of film layers, and the film layers located in the same layer are made of the same material. Furthermore, within the same resistor unit group, along the direction perpendicular to the thickness of the resistor unit, the stacked structure of each resistor unit has the same number of layers in the region between the two test vias.

[0089] It's important to understand here that the resistance measured using two test vias is a single, comprehensive value. This value includes the product of the contact resistance between the corresponding film layers, the parallel sheet resistance of the film layers, and the length of the region between the test vias (assuming the width of the region between the two test vias is 1). Since multiple resistor units in the same resistor unit group have the structure described above, by measuring the multiple resistances corresponding to multiple resistor units in the same resistor unit group, a curve can be fitted between the measured resistance, the length of the region between the test vias, and the contact resistance between the corresponding film layers. This allows us to obtain the contact resistance between the corresponding film layers of the resistor unit group.

[0090] For further explanation, refer to Figures 1 to 3 The length of the region between the test vias can be represented as L, and the width of the region between the test vias is the dimension in the direction perpendicular to the length L in a plane parallel to the surface of each film layer.

[0091] The resistance testing system also includes a test unit, which is used to calculate the contact resistance between each film layer and adjacent film layers in the stacked structure based on the measured resistance of the stacked structure in multiple resistance unit groups.

[0092] As mentioned above, multiple measured resistors of the stacked structure can be obtained from each resistor unit group. Based on these multiple measured resistors, the corresponding interlayer contact resistance and sheet resistance can be calculated.

[0093] As a specific example, if the structure of the resistor unit in the resistor unit group is as follows: Figure 1 As shown, the corresponding interlayer contact resistance calculated at this time is the contact resistance between the two test vias (201 and 202) and the membrane 103.

[0094] If the structure of the resistor unit in the resistor unit group is as follows Figure 2 As shown, the corresponding contact resistance between the membrane layers is calculated as the sum of the contact resistance between the two test vias (201 and 202) and membrane layer 103 and the contact resistance between membrane layer 103 and membrane layer 102.

[0095] If the structure of the resistor unit in the resistor unit group is as follows Figure 3 As shown, the corresponding contact resistance between the membrane layers calculated at this time is the sum of the contact resistance between the two test vias (201 and 202) and membrane layer 103, the contact resistance between membrane layer 103 and membrane layer 102, and the contact resistance between membrane layer 102 and membrane layer 101.

[0096] Based on this, the test unit is used to obtain the measured resistance of the stacked structure in multiple resistor units in the same resistor unit group, and to calculate the contact resistance and sheet resistance of the stacked structure in the corresponding test unit group based on the multiple measured resistances; wherein, the resistance values ​​of the multiple measured resistances are different.

[0097] In the same resistor unit group, the distance between two test vias in different resistor units needs to be set differently. At this time, due to the different distances, the resistance values ​​of the corresponding measured resistors will also be different.

[0098] It should be understood that, given the known distance between the two test vias and the known measured resistance value, the contact resistance between the corresponding film layers in the resistance unit group can be calculated separately. The corresponding film layers can be understood with reference to the explanation above, and will not be repeated here.

[0099] Furthermore, refer to Figures 1-3The test unit can calculate the contact resistance between the two test vias (201 and 202) and the film layer 103, the contact resistance between the film layer 103 and the film layer 102, and the contact resistance between the film layer 102 and the film layer 101 based on the contact resistance of the three different resistive unit groups.

[0100] This can be further summarized as follows: the test unit is used to calculate the contact resistance between the etched film layer and the adjacent film layer in the region between two test vias, based on the contact resistance of multiple resistance unit groups and the structure of the stacked structure in each resistance unit group.

[0101] As a specific example, refer to Figure 2 The etched film may include 103, see reference. Figure 3 The etched film layers include 103 and 102.

[0102] It should be understood that in order to calculate the contact resistance between the layers of the semiconductor stack of the target resistor unit, in different resistor unit groups, the stack structure of the resistor unit includes the same layers, but the stack structure of the resistor unit has a different number of layers in the region between the two test vias along the direction perpendicular to the thickness of the resistor unit.

[0103] As a specific example, refer to Figure 1 The resistor unit includes three film layers (101, 102 and 103), and along the direction perpendicular to the thickness of the resistor unit, the stacked structure has three film layers (101, 102 and 103) in the region between the two contact vias.

[0104] Reference Figure 2 The resistor unit includes three film layers (101, 102 and 103), and along the direction perpendicular to the thickness of the resistor unit, the stacked structure has two film layers (101 and 102) in the region between the two contact vias, and film layer 103 has been etched away.

[0105] Reference Figure 3 The resistor unit includes three film layers (101, 102 and 103), and along the direction perpendicular to the thickness of the resistor unit, the stacked structure has one film layer (101) in the region between the two contact vias, and two film layers (102 and 103) are etched away.

[0106] As described above, in the same resistor unit group, the stacked structure of multiple resistor units includes the same film layer, and along the direction perpendicular to the thickness of the resistor unit, the stacked structure of each resistor unit has the same number of layers in the region between the two test vias. However, the distance between the two test vias of each resistor unit in the same resistor unit group is different, so that the contact resistance of the stacked structure can be calculated by measuring the resistance of the stacked structure in different resistor units. As a specific example, refer to... Figure 4 , Figure 5 and Figure 6 This shows three resistor cells in the same resistor cell group with different distances between the two test vias.

[0107] Reference Figure 4 The distance between the two test vias in this resistor unit is L1. (Refer to...) Figure 5 The distance between the two test vias in this resistor unit is L2. (Refer to...) Figure 6 The distance between the two test vias in this resistor unit is L3.

[0108] Through the Figure 4 , Figure 5 as well as Figure 6 The resistance unit is tested to obtain the measured resistance R1 corresponding to distance L1, the measured resistance R2 corresponding to distance L2, and the measured resistance R3 corresponding to distance L3. It should be understood that the measured resistance R = Rc + Rs × L (assuming the width of all stacked structures is 1), where Rc is the contact resistance and Rs is the sheet resistance. Based on the measured resistance values ​​R1, R2, and R3 and the corresponding distances L1, L2, and L3, a plot can be drawn as follows: Figure 7 The curve described above, when fitted, yields y = kx + b. Furthermore, we obtain... Figure 4 , Figure 5 as well as Figure 6 The sheet resistance k2 and contact resistance b2 of the medium resistance unit. Figures 4-6 In the process, the corresponding contact resistance of the stacked structure is the contact resistance between film layer 103 and the test via, and the contact resistance between film layer 103 and film layer 102.

[0109] Similarly, following the same method, we can obtain the result from... Figure 1 The sheet resistance k1 and contact resistance b1 of the resistance unit group formed by the middle resistance unit; and the sheet resistance k1 and contact resistance b1 of the resistance unit group formed by the middle resistance unit; Figure 3 The sheet resistance k3 and contact resistance b3 are formed by the resistance unit group in the middle resistance unit.

[0110] Reference Figure 1 , Figure 2 and Figure 3b1 is twice RC1, b2 is twice RC1 + RC2, and b3 is twice RC1 + RC2 + RC3. Here, RC1 is the contact resistance between film layer 103 and the test via, RC2 is the contact resistance between film layer 103 and film layer 102, and RC3 is the contact resistance between film layer 102 and film layer 101. The contact resistance between each film layer can be calculated.

[0111] The sheet resistance k3 is RS3, 1 / k2 = 1 / RS2 + 1 / RS3, 1 / k1 = 1 / RS1 + 1 / RS2 + 1 / RS3. Where RS1 is the sheet resistance of film layer 103, RS2 is the sheet resistance of film layer 102, and RS3 is the sheet resistance of film layer 103. The sheet resistance of each film layer (101, 102, and 103) can be obtained by calculating using the above formulas.

[0112] In some examples, depending on the actual needs, the film layers in the stacked structure of each resistor unit may include single-layer film layers or stacked layers formed by multiple film layers.

[0113] For example, the stack can be a metal gate stack structure of NMOS.

[0114] The fabrication process of the resistor unit in this application is described below with specific examples.

[0115] In one optional example, refer to Figures 8-10 A single photomask can be used to form various resistive units on multiple substrates (201, 301, and 401), each with a different structure. (See reference...) Figure 8 The first type of resistor unit's stacked structure includes a single film layer 202. (Refer to...) Figure 9 The second type of resistor unit's stacked structure includes two stacked film layers 302 and 303. (Refer to...) Figure 10 The third type of resistor unit stacked structure includes three layers of film 402, film 403 and film 405 stacked together.

[0116] In another alternative example, refer to Figures 11-14 Multiple photomasks can be used to form multiple resistor units on the same substrate. For example, these multiple photomasks may include POLY (polysilicon) photomasks, NMG (N-type doped mask) photomasks, and photomasks for forming PMG (P-type doped mask).

[0117] Reference Figure 11 First, a first film layer 502 is deposited on the substrate 501.

[0118] Reference Figure 12Three distinct regions are defined on the substrate using a first photomask via photolithography. The photomask transfers the design pattern onto the photoresist, which is then etched to form the desired regional structure. A second photomask is then used to open the middle and right-side regions, and a second film layer 503 is deposited in these regions. Each region is isolated by an insulating dielectric layer 504.

[0119] Reference Figure 13 The middle region is opened using a third photomask, and a third film layer 505 is deposited in the middle region. Then, an insulating dielectric layer 504 is deposited on the third film layer.

[0120] Reference Figure 14 Test vias 506 are formed in the left area, test vias 508 are formed in the middle area, and test vias 507 are formed in the right area to measure the contact resistance of the corresponding resistance structure.

[0121] It should be understood that the fabrication process of the above-mentioned resistor unit and each film layer are illustrative. This application can use existing photomasks to combine any film layers and calculate the contact resistance between different film layers.

[0122] Thirdly, embodiments of this application also provide a resistance testing method, applied in the test unit of the resistance testing system of the second aspect, the method comprising:

[0123] Calculate the contact resistance between each film layer and adjacent film layers in each stacked structure based on the resistance of the stacked structure in multiple resistance unit groups.

[0124] Optionally, each of the resistor unit groups includes multiple resistor units. In the same resistor unit group, the stacked structure of the multiple resistor units includes the same film layer, and along the direction perpendicular to the thickness of the resistor unit, the stacked structure of each resistor unit has the same number of layers in the region between the two test vias.

[0125] The method further includes:

[0126] Obtain the measured resistance of the stacked structure in multiple resistor units within the same resistor unit group;

[0127] The contact resistance of the stacked structure corresponding to the test unit group is calculated based on the plurality of measured resistors; wherein the resistance values ​​of the plurality of measured resistors are different.

[0128] Optionally, the method further includes:

[0129] In each of the resistor unit groups, the sheet resistance of each film layer in the corresponding resistor unit group is calculated based on the plurality of measured resistors.

[0130] Fourthly, this application also provides a resistance testing device. Figure 15 This is a schematic diagram of the resistance testing device provided in an embodiment of this application. Figure 15 As shown, the resistance testing device may include: transceiver 121, processor 122, and memory 123.

[0131] Processor 122 executes computer execution instructions stored in memory, causing processor 122 to perform the scheme in the above method embodiments. Processor 122 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0132] The memory 123 is connected to the processor 122 via the system bus and completes communication between them. The memory 123 is used to store computer program instructions.

[0133] Transceiver 121 can be used to obtain the task to be run and its configuration information.

[0134] The system bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The system bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus. Transceivers are used to enable communication between database access devices and other computers (e.g., clients, read-write libraries, and read-only libraries). Memory may include random access memory (RAM) and may also include non-volatile memory.

[0135] This application also provides a chip for executing instructions, which is used to execute the resistance testing method described in the above embodiments.

[0136] Fifthly, embodiments of this application also provide a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the computer to perform the technical solution of the resistance testing method described in the above embodiments.

[0137] Sixthly, embodiments of this application also provide a computer program product, which includes a computer program stored in a computer-readable storage medium. At least one processor can read the computer program from the computer-readable storage medium, and when the at least one processor executes the computer program, it can implement the technical solution of the resistance testing method in the above embodiments.

[0138] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0139] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to implement the solution of this embodiment according to actual needs.

[0140] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit composed of the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0141] The integrated modules described above, implemented as software functional modules, can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods of the various embodiments of this application.

[0142] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0143] The memory may include high-speed RAM, and may also include non-volatile storage (NVM), such as at least one disk storage device, and may also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.

[0144] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0145] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0146] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. The processor and storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic control unit or main control device.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A resistor unit, characterized in that, include: Layered structure; Dielectric layer; The dielectric layer is formed on the stacked structure; Two test vias; The two test vias penetrate the dielectric layer and are in contact with the stacked structure, and are used to test the resistance of the stacked structure; Along a direction perpendicular to the thickness of the stacked structure, the stacked structure has a preset number of layers in the region between the two test vias; wherein the preset number of layers is less than or equal to the number of film layers in the stacked structure.

2. The resistor unit according to claim 1, characterized in that, The stacked structure includes n layers of film stacked together; the preset number of layers includes one to n layers.

3. The resistor unit according to claim 1, characterized in that, The stacked structure includes one of the following: a stacked structure formed by multiple semiconductor layers, a stacked structure formed by at least one semiconductor layer and at least one metal layer, and a stacked structure formed by multiple metal layers.

4. A resistance testing system, characterized in that, include: Multiple groups of resistor units; each group of resistor units includes a resistor unit as described in any one of claims 1-3; and test units; The test unit is used to calculate the contact resistance between each film layer and adjacent film layers in each of the stacked structures based on the measured resistance of the stacked structures in the plurality of resistance unit groups.

5. The system according to claim 4, characterized in that, Each of the resistor unit groups includes multiple resistor units. In the same resistor unit group, the stacked structure of the multiple resistor units includes the same film layer, and, along the direction perpendicular to the thickness of the resistor unit, the stacked structure of each resistor unit has the same number of layers in the region between the two test vias. The test unit is used to obtain the measured resistance of the stacked structure in multiple resistor units within the same resistor unit group, and to calculate the contact resistance of the stacked structure corresponding to the resistor unit group based on the multiple measured resistances; wherein the resistance values ​​of the multiple measured resistances are different.

6. The system according to claim 5, characterized in that, In the same group of resistor units, the distance between two test vias in different resistor units is different.

7. The system according to claim 5, characterized in that, In the same group of resistor units, the same film layer in multiple resistor units is made of the same material.

8. The system according to claim 5, characterized in that, The test unit is also used to calculate the sheet resistance of each film layer in each of the stacked structures based on the measured resistance of the stacked structures in the plurality of resistor unit groups.

9. The system according to any one of claims 4-8, characterized in that, In different groups of resistor units, the stacked structure of the resistor units includes the same film layers, and, along the direction perpendicular to the thickness of the resistor unit, the stacked structure of the resistor units has a different number of layers in the region between the two test vias.

10. The system according to any one of claims 4-8, characterized in that, The stacked structure of the resistor unit includes one of the following: a stacked structure formed by multiple semiconductor layers, a stacked structure formed by at least one semiconductor layer and at least one metal layer, and a stacked structure formed by multiple metal layers.

11. The system according to any one of claims 4-8, characterized in that, The membrane layer in the stacked structure includes a single membrane layer or a stack formed by multiple membrane layers.

12. A resistance testing method, applied in a test unit of the resistance testing system according to any one of claims 4-11, the method comprising: Based on the resistance of the stacked structures in the plurality of resistor unit groups, the contact resistance between each film layer and the adjacent film layer in each stacked structure is calculated.

13. A resistance testing device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in claim 12.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in claim 12.

15. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of claim 12.

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