Capacitor, method of manufacturing the same, integrated circuit, and electronic device

Abstract

The embodiment of the present application provides a capacitor and a preparation method thereof, an integrated circuit and an electronic device, relates to the technical field of semiconductors, and is used for reducing the contact resistance of the capacitor. The capacitor comprises a plurality of metal layers and a plurality of dielectric layers which are arranged in a stack. The plurality of metal layers comprises a first metal layer, a second metal layer and a third metal layer. The plurality of dielectric layers comprises a first dielectric layer between the first metal layer and the second metal layer and a second dielectric layer between the second metal layer and the third metal layer. The capacitor further comprises a conductive post, and the conductive post comprises a first conductive post penetrating through the first metal layer and the third metal layer and a second conductive post penetrating through the second metal layer. At least one metal layer has a convex part, and at least part of the side surface of the conductive post is adjacent to the convex part.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a capacitor and its preparation method, an integrated circuit, and an electronic device. Background Technology

[0002] According to Moore's Law, chips are increasingly miniaturized, with manufacturing processes shrinking until they reach physical limits. To overcome the limitations of Moore's Law, chip packaging technology has evolved from planar packaging to vertically stacked packaging, enabling 3D IC packaging and 2.5D IC packaging technologies. For example, chip packaging structures can include chip-on-wafer (COW), chip-on-chip (COC), and wafer-on-wafer (WOW). WOW, in particular, enables efficient and low-cost heterogeneous integration, providing higher bandwidth and lower power consumption in 3D IC packaging structures.

[0003] However, 3D IC packaging structures have high requirements for process technology and can also affect the efficiency of power supply networks due to power integrity (PI) issues. Summary of the Invention

[0004] This application provides a capacitor and its manufacturing method, an integrated circuit, and an electronic device for reducing the contact resistance of the capacitor.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] A first aspect of this application provides a capacitor comprising multiple layers of metal layers and multiple layers of dielectric layers stacked together. The multiple metal layers include a first metal layer, a second metal layer, and a third metal layer. The multiple dielectric layers include a first dielectric layer located between the first and second metal layers and a second dielectric layer located between the second and third metal layers. The capacitor further includes conductive posts, including a first conductive post penetrating through the first and third metal layers and a second conductive post penetrating through the second metal layer. At least one metal layer includes a metal body and a protrusion disposed on the surface of the metal body, and at least a portion of the side surface of the conductive post is adjacent to the protrusion.

[0007] The capacitor provided in this application embodiment has at least one metal layer with a protrusion. This is equivalent to the metal layer with the protrusion being thicker than the metal layer without the protrusion, thus achieving a localized thickening of the metal layer. When the conductive post penetrates the metal layer, at least a portion of the side of the conductive post is adjacent to the protrusion. That is, the metal layer containing the protrusion adjacent to the conductive post is thicker, meaning the metal layer in contact with at least a portion of the side of the conductive post is thicker. Therefore, the contact area between the conductive post and the metal layer is larger, reducing the contact resistance between the conductive post and the metal layer, thereby increasing the resonant frequency and capacitance density of the capacitor. Furthermore, the solution provided in this application embodiment can increase the contact area between the conductive post and the metal layer and reduce the contact resistance without increasing the number of conductive posts, thereby increasing the resonant frequency and capacitance density of the capacitor.

[0008] In one possible implementation, the thickness of the metal layer with the protrusion is greater than the thickness of the metal body. This increases the contact area between the conductive post and the metal layer.

[0009] In one possible implementation, at least a portion of the side surface of the first conductive post is adjacent to the protrusion; along the extension direction of the metal layer, the size of the protrusion is larger than the size of the first conductive post. This allows all the side surfaces of the first conductive post to contact the protrusion, increasing the contact area between the first conductive post and the metal layer, reducing the contact resistance between the first conductive post and the metal layer, thereby increasing the resonant frequency of the capacitor and improving the capacitance density of the capacitor.

[0010] In one possible implementation, at least a portion of the side surface of the second conductive post is adjacent to the protrusion; along the extension direction of the metal layer, the size of the protrusion is larger than the size of the second conductive post. This allows all sides of the second conductive post to contact the protrusion, increasing the contact area between the second conductive post and the metal layer, reducing the contact resistance between the second conductive post and the metal layer, thereby increasing the resonant frequency of the capacitor and improving the capacitance density of the capacitor.

[0011] In one possible implementation, the thickness of the protrusion is greater than 5% of the thickness of the metal body. This increases the contact area between the conductive post and the metal layer, reduces the contact resistance, and thus increases the resonant frequency of the capacitor and the capacitance density of the capacitor.

[0012] In one possible implementation, the thickness of the metal body is the same along the extension direction of the metal layer. This avoids increasing the thickness of other parts of the metal layer and thus does not affect the capacitor.

[0013] In one possible implementation, the protrusion and the metal body are integrally formed. This makes fabrication convenient and the process simple.

[0014] In one possible implementation, the first metal layer has a first protrusion; at least a portion of the side of the first conductive post is also adjacent to the first protrusion. In this way, the equivalent thickness of the portion of the first metal layer with the first protrusion is greater than the thickness of the first metal layer without the first protrusion, thus achieving a localized thickening of the first metal layer. This increases the thickness of the first metal layer in contact with the first conductive post, thereby increasing the contact area between the first conductive post and the first metal layer, reducing the contact resistance between the first conductive post and the first metal layer, and consequently improving the resonant frequency of the capacitor and increasing the capacitance density of the capacitor.

[0015] In one possible implementation, the surface of the first metal layer facing away from the first dielectric layer protrudes to form a first protrusion. This makes fabrication convenient and the process simple.

[0016] In one possible implementation, the second metal layer has a second protrusion; at least a portion of the side of the second conductive post is also adjacent to the second protrusion. In this way, the equivalent thickness of the portion of the second metal layer with the second protrusion is greater than the thickness of the second metal layer without the second protrusion, thus achieving a localized thickening of the second metal layer. This increases the thickness of the second metal layer in contact with the second conductive post, thereby increasing the contact area between the second conductive post and the second metal layer, reducing the contact resistance between the second conductive post and the second metal layer, and consequently improving the resonant frequency of the capacitor and increasing the capacitance density of the capacitor.

[0017] In one possible implementation, the third metal layer has a third protrusion; at least a portion of the side of the first conductive post is also adjacent to the third protrusion. In this way, the thickness of the portion of the third metal layer with the third protrusion is equivalent to being thicker than the thickness of the third metal layer without the third protrusion, thus achieving a localized thickening of the third metal layer. This increases the thickness of the third metal layer in contact with the first conductive post, thereby increasing the contact area between the first conductive post and the third metal layer, reducing the contact resistance between the first conductive post and the third metal layer, and consequently improving the resonant frequency of the capacitor and increasing the capacitance density of the capacitor.

[0018] In one possible implementation, the capacitor further includes a third dielectric layer and a fourth metal layer; the third dielectric layer is disposed on the side of the third metal layer away from the second dielectric layer; the fourth metal layer is disposed on the side of the third dielectric layer away from the third metal layer; the fourth metal layer has a fourth protrusion; the second conductive post also penetrates the fourth metal layer; at least a portion of the side of the second conductive post is adjacent to the fourth protrusion. In this way, the capacitor can be equivalent to multiple parallel capacitors. Furthermore, the thickness of the portion of the third metal layer with the third protrusion is greater than the thickness of the third metal layer without the third protrusion, achieving a localized thickening of the fourth metal layer. This increases the thickness of the fourth metal layer in contact with the second conductive post, thereby increasing the contact area between the second conductive post and the fourth metal layer, reducing the contact resistance between the second conductive post and the fourth metal layer, and thus improving the resonant frequency of the capacitor and increasing the capacitance density of the capacitor.

[0019] A second aspect of this application provides a method for fabricating a capacitor, comprising: forming a multilayer metal layer and a multilayer dielectric layer stacked together; and forming a conductive post penetrating at least one metal layer. Each metal layer includes a metal body and a protrusion; the protrusion is formed on the surface of the metal body; at least a portion of the side surface of the conductive post is adjacent to the protrusion. Forming the multilayer metal layer and the multilayer dielectric layer stacked together includes: forming a first metal layer; forming a first dielectric layer on the first metal layer; forming a second metal layer on a side of the first dielectric layer away from the first metal layer; forming a second dielectric layer on a side of the second metal layer away from the first dielectric layer; and forming a third metal layer on a side of the second dielectric layer away from the second metal layer. Forming a conductive post penetrating at least one metal layer includes: forming a first conductive post and a second conductive post, the first conductive post penetrating the first metal layer and the third metal layer; and the second conductive post penetrating the second metal layer. At least one of the first metal layer, the second metal layer, and the third metal layer has a protrusion, and at least a portion of the side surface of the first conductive post or the second conductive post is adjacent to the protrusion.

[0020] The capacitor fabrication method provided in this application provides at least one metal layer with a protrusion. This is equivalent to the metal layer with the protrusion being thicker than the metal layer without the protrusion, thus achieving localized thickening of the metal layer. When the first or second conductive post penetrates the metal layer, at least a portion of the side of the conductive post is adjacent to the protrusion. That is, the metal layer containing the protrusion adjacent to the conductive post is thicker, meaning the metal layer in contact with at least a portion of the side of the conductive post is thicker. Therefore, the contact area between the conductive post and the metal layer is larger, reducing the contact resistance between the conductive post and the metal layer, thereby increasing the resonant frequency and capacitance density of the capacitor. Furthermore, the solution provided in this application does not require increasing the number of conductive posts, ensuring the feasibility of the conductive post fabrication process. It also achieves increased contact area between the conductive post and the metal layer and reduced contact resistance without increasing the number of conductive posts, thereby increasing the resonant frequency and capacitance density of the capacitor.

[0021] In one possible implementation, forming the first metal layer with the first protrusion includes: providing a semiconductor layer, forming a first groove on the semiconductor layer; forming the first metal layer on the semiconductor layer; the portion of the first metal layer filling the first groove serving as the first protrusion, and the portion of the first metal layer located on the surface of the semiconductor layer serving as the first metal body; the fabrication method further includes: removing the semiconductor layer. This provides a method for fabricating the first metal layer that is convenient and has a simple process.

[0022] In one possible implementation, after forming the first dielectric layer and before forming the second metal layer, the fabrication method further includes: forming a second groove extending from the first dielectric layer into the semiconductor layer; forming a second metal layer on the side of the first dielectric layer away from the semiconductor layer, the second metal layer also filling the second groove; the portion of the second metal layer filling the second groove serving as a second protrusion; and forming a second conductive post, including at least a portion of the side surface of the second conductive post abutting the second protrusion. In this way, the abutment of at least a portion of the side surface of the second conductive post with the second protrusion of the second metal layer increases the contact area between the second conductive post and the second metal layer, reduces the contact resistance between the second conductive post and the second metal layer, and thereby improves the resonant frequency of the capacitor.

[0023] A third aspect of this application provides an integrated circuit, comprising: a capacitor as described in any of the first aspects, and a first metal wiring and a second metal wiring stacked thereon; the capacitor is disposed between the first metal wiring and the second metal wiring; and a first conductive post is electrically connected to the first metal wiring and the second metal wiring.

[0024] The integrated circuit provided in the third aspect of the embodiments of this application includes the capacitor of any one of the first aspects, and its beneficial effects are the same as those of the capacitor, which will not be repeated here.

[0025] In one possible implementation, the first metal wiring includes pads. In this way, capacitors can also be disposed between the pads and the metal wiring layer.

[0026] A fourth aspect of this application provides an electronic device, including an integrated circuit and a printed circuit board as described in the third aspect, wherein the integrated circuit and the printed circuit board are electrically connected.

[0027] The electronic device provided in the fourth aspect of the embodiments of this application includes the integrated circuit of the third aspect, and its beneficial effects are the same as those of the integrated circuit, which will not be repeated here. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0029] Figure 2 This is a schematic diagram illustrating the structure of a capacitor according to an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the structure of a capacitor provided in an embodiment of this application;

[0031] Figure 4 A schematic flowchart illustrating a method for manufacturing a capacitor according to an embodiment of this application;

[0032] Figures 5A-5O A schematic diagram illustrating a method for manufacturing a capacitor according to an embodiment of this application;

[0033] Figure 6A This is a schematic diagram of another capacitor structure provided in an embodiment of this application;

[0034] Figure 6B This is a schematic diagram of the structure of another capacitor provided in an embodiment of this application;

[0035] Figure 7 This is a schematic diagram of the structure of another capacitor provided in an embodiment of this application;

[0036] Figure 8 This is a schematic diagram of the structure of another capacitor provided in an embodiment of this application;

[0037] Figure 9 This is a schematic diagram of the structure of another capacitor provided in an embodiment of this application;

[0038] Figure 10 This is a schematic diagram of an integrated circuit structure provided in an embodiment of this application.

[0039] Figure Labels

[0040] 1-Electronic device; 2-Display module; 3-Middle frame; 4-Housing; 5-Cover plate; 10-Capacitor; 20-Integrated circuit; 11-First metal wiring; 12-Second metal wiring; 100-Metal layer; 110-First metal layer; 110'-First metal film; 111-First metal body; 120-Second metal layer; 130-Third metal layer; 140-Fourth metal layer; 200-Dielectric layer; 210-First dielectric layer; 220 - Second dielectric layer; 230 - Third dielectric layer; 300 - Conductor post; 310 - First conductor post; 320 - Second conductor post; 400 - Semiconductor layer; 410 - First groove; 420 - Second groove; 510 - First mask layer; 520 - Second mask layer; 530 - Third mask layer; 101 - First protrusion; 102 - Second protrusion; 103 - Third protrusion; 104 - Fourth protrusion; 301 - First via; 302 - Second via. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0042] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0043] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0044] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0045] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0046] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, or a financial terminal product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle DVDs, etc. Financial terminal products include ATMs, self-service terminals, etc. This application does not impose special limitations on the specific form of the above-mentioned electronic device. For ease of explanation, the following embodiments all use mobile phones as an example for illustration.

[0047] Example of the structure of an electronic device, such as Figure 1 As shown, the electronic device 1 mainly includes a display module 2, a middle frame 3, a housing (or battery cover, back cover) 4, and a cover plate 5.

[0048] The display module 2 has a light-emitting side that allows the display image to be seen and a non-light-emitting side that is opposite to the light-emitting side. The back of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.

[0049] The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, a cover glass (CG), which can have a certain degree of toughness.

[0050] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to mount internal components such as batteries, printed circuit boards (PCBs), cameras, and antennas. After the housing 4 is closed with the middle frame 3, the aforementioned internal components are located between the housing 4 and the middle frame 3.

[0051] The aforementioned display module 2 includes a display panel (DP).

[0052] The aforementioned electronic device 1 may further include an integrated circuit disposed on a printed circuit board. The printed circuit board is used to carry the integrated circuit and is electrically connected to the integrated circuit to enable signal communication.

[0053] For example, an integrated circuit may include circuit modules for implementing a single function, or it may include multiple circuit modules for implementing different functions. The circuit modules can be circuits with arbitrary functions, such as driver circuits, pixel circuits, amplifier circuits, power management circuits, charging protection circuits, control circuits (e.g., a central processing unit (CPU)), and image sensor circuits. It is clarified here that integrated circuits can be packaged and applied to electronic devices in the form of chips. Of course, they can also be applied directly to electronic devices without packaging.

[0054] For example, at least one transistor is integrated on an integrated circuit, which may be a field-effect transistor (FET).

[0055] It is clarified here that field-effect transistors can include planar transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or junction field-effect transistors (JFETs), and can also include three-dimensional transistors such as fin field-effect transistors (FinFETs), gate all-around field-effect transistors (GAAFETs), or forksheet field-effect transistors (forksheet FETs or FSFETs). This application does not limit the scope of the field-effect transistors.

[0056] With the development of semiconductor technology, the functions of electronic devices 1 are becoming increasingly diverse and comprehensive. This leads to the integration of integrated circuits (ICs) for different functions within electronic devices 1, increasing the demand for IC integration on printed circuit boards within these devices. As the performance of ICs needs improvement, the requirements for ICs are also becoming increasingly stringent.

[0057] Taking chips as an example, according to Moore's Law, chips are gradually becoming miniaturized, with the manufacturing process shrinking until it reaches its physical limits. To overcome the limitations of Moore's Law, chip packaging technology has evolved from planar packaging to vertically stacked packaging, thereby enabling 3D IC packaging and 2.5D IC packaging technologies. For example, chip packaging structures can include chip-on-wafer (COW), chip-on-chip (COC), and wafer-on-wafer (WOW). Among these, WOW enables efficient and low-cost heterogeneous integration, providing a 3D IC packaging structure with higher bandwidth and lower power consumption.

[0058] However, 3D IC packaging structures have high requirements for process technology and can also affect the efficiency of power supply networks due to power integrity (PI) issues.

[0059] To address the power network efficiency issues caused by power integrity, frontside power delivery network (FSPDN) and backside power delivery network (BSPDN) technologies can be used to power integrated circuits such as chips.

[0060] However, FSPDN and BSPDN technologies require long power supply lines, which can lead to voltage drop, limiting the integration of 3D IC packaging structures and power supply networks.

[0061] Therefore, in order to improve the power supply network, capacitors can be used to suppress current noise and voltage drop in the circuit to obtain a stable power supply output.

[0062] Capacitors can be used in integrated circuits such as chip packaging structures and semiconductor devices, as well as in radio frequency circuits.

[0063] This diagram illustrates a metal-insulator-metal (MIM) capacitor used for noise reduction. For example, the capacitor has its lowest impedance at a specific resonant frequency, possessing a certain capacitance (also known as capacitive capacitance), thus serving the function of "passing AC while blocking DC".

[0064] In other words, capacitors can be used to remove some noise at specific frequencies. Theoretically, the larger the capacitance of a capacitor, the smaller its impedance, and the higher the frequency it can pass through. The bandwidth (cutoff frequency) f of a capacitor satisfies the following relationship with its resistance R: f = 1 / 2πRC.

[0065] This illustrates a type of capacitor, such as Figure 2 As shown, the capacitor includes three stacked metal layers and two dielectric layers. The capacitor also includes a via penetrating the three metal layers.

[0066] like Figure 2 As shown, the capacitor includes two through holes. Through hole 1 is electrically connected to the two metal layers (metal layer 1 and metal layer 3) of the capacitor, and through hole 2 is electrically connected to metal layer 2 of the capacitor. This allows the capacitor to be equivalent to two capacitors connected in parallel, thereby doubling the capacitance value of the capacitor.

[0067] Through-holes and metal layers achieve electrical connection through contact, creating contact resistance between them. This contact resistance is related to the area. However, due to limitations in the thickness of the metal layer (e.g., a thickness of...),... This results in a limited contact area between the via and the metal layer, leading to a relatively high contact resistance. Furthermore, due to capacitor size limitations, it's impossible to create more vias on the capacitor's metal layer to reduce contact resistance. This results in poor high-frequency performance, with the capacitance decaying at a faster rate with frequency, making it impossible to obtain sufficient capacitance within a given frequency band. This negatively impacts power integrity.

[0068] Based on this, in order to reduce the contact resistance between the via and the metal layer in the capacitor, embodiments of this application also provide a capacitor, such as... Figure 3 As shown, the capacitor 10 includes multiple layers of metal layers 100 and multiple layers of dielectric layers 200 stacked together. The multiple metal layers 100 include a first metal layer 110, a second metal layer 120, and a third metal layer 130. The multiple dielectric layers 200 include a first dielectric layer 210 located between the first metal layer 110 and the second metal layer 120, and a second dielectric layer 220 located between the second metal layer 120 and the third metal layer 130. The capacitor 10 also includes conductive posts 300, including a first conductive post 310 penetrating the first metal layer 110 and the third metal layer 130, and a second conductive post 320 penetrating the second metal layer 120. At least one metal layer 100 includes a metal body and a protrusion disposed on the surface of the metal body, and at least a portion of the side surface of the conductive post 300 is adjacent to the protrusion.

[0069] This application also provides a method for manufacturing a capacitor, such as... Figure 4 As shown, it includes:

[0070] S1, such as Figure 5A and Figure 5B As shown, a semiconductor layer 400 is provided, and a first groove 410 is formed on the semiconductor layer 400.

[0071] In some embodiments, step S1 includes:

[0072] S11, such as Figure 5A As shown, a semiconductor layer 400 is provided.

[0073] For example, such as Figure 5A As shown, the semiconductor layer 400 can be a dielectric material within the wiring layer.

[0074] The semiconductor layer 400 may include a first metal wiring 11 and a dielectric material located on the first metal wiring 11.

[0075] The method for forming the semiconductor layer 400 may include: first forming a first metal wiring 11, and then sequentially forming a nitride layer and an oxide layer on the surface of the first metal wiring 11. In this embodiment, the number of nitride layers and oxide layers is not limited; they can be reasonably set according to actual conditions.

[0076] Alternatively, for example, the semiconductor layer 400 may also be a substrate or a wafer, etc.

[0077] The material of the semiconductor layer 400 is not limited in this embodiment. For example, the material of the semiconductor layer 400 may include an oxide material or a semiconductor material, such as silicon oxide, silicon carbide, bulk silicon, bulk germanium, or silicon-germanium.

[0078] S12, such as Figure 5B As shown, a first mask layer 510 is formed on the semiconductor layer 400.

[0079] like Figure 5B As shown, the first mask layer 510 exposes the area where the first groove 410 is to be formed.

[0080] S13, such as Figure 5B As shown, the semiconductor layer 400 is etched to form the first groove 410.

[0081] It should be noted here that the depth of the first groove 410 is the same as the thickness of the first protrusion to be formed. This embodiment does not impose a limitation on this; it can be set reasonably according to the actual situation.

[0082] S14, such as Figure 5B As shown, the first mask layer 510 is removed.

[0083] Thus, as Figure 5B As shown, a semiconductor layer 400 with a first groove 410 is formed.

[0084] S2, such as Figure 5C As shown, a first metal layer 110 is formed on the semiconductor layer 400.

[0085] An exemplary method for forming the first metal layer 110 includes:

[0086] S21, Form the first metal film 110'.

[0087] like Figure 5C As shown, a first metal film 110' is formed on the surface of the semiconductor layer 400, and the first metal film 110' also fills the first groove 410. The portion of the first metal film 110' filling the first groove 410 serves as the first protrusion 101.

[0088] For example, the material of the first metal film 110' may include metals such as titanium nitride, titanium, tantalum, or nickel.

[0089] S22, Form the first metal layer 110.

[0090] For example, the surface of the first metal film 110' is polished by a chemical mechanical polishing (CMP) process, so that at least a portion of the first metal film 110' is retained on the surface of the semiconductor layer 400. In this case, the remaining portion of the first metal film 110' serves as the first metal layer 110.

[0091] In this way, by treating the surface of the first metal film 110' through CMP process, the surface of the first metal layer 110 can be made smoother, increasing the smoothness of the surface of the first metal layer 110, which is beneficial to the subsequent formation of the first dielectric layer.

[0092] In this embodiment, the thickness of the remaining first metal layer 110 on the surface of the semiconductor layer 400 is not limited; it can be set reasonably according to the actual situation. It should be noted that the portion of the first metal layer 110 without the first protrusion 101 has the same thickness.

[0093] In some embodiments, such as Figure 5D As shown, step S2 further includes:

[0094] S23. Pattern the first metal layer 110.

[0095] For example, such as Figure 5D As shown, a mask pattern is formed on the surface of the first metal layer 110, exposing a portion of the surface of the first metal layer 110. Then, the exposed portion of the first metal layer 110 is removed to expose the semiconductor layer 400.

[0096] In order to subsequently form a second metal layer with protrusions, a portion of the semiconductor layer 400 may be exposed.

[0097] S3, such as Figure 5E As shown, a first dielectric layer 210 is formed on the first metal layer 110.

[0098] like Figure 5E As shown, the first dielectric layer 210 is formed on the side of the first metal layer 110 away from the semiconductor layer 400. For example, the first dielectric layer 210 is formed on the surface of the first metal layer 110 away from the semiconductor layer 400.

[0099] For example, a first dielectric film 210' is first formed on the surface of the first metal layer 110 away from the semiconductor layer 400. At this time, the exposed surface of the semiconductor layer 400 is also formed with the first dielectric film 210'. Then, a portion of the first dielectric film 210' located on the surface of the semiconductor layer 400 is removed using a mask pattern, and the remaining portion of the first dielectric film 210' serves as the first dielectric layer 210.

[0100] For example, the material of the first dielectric layer 210 may include a high dielectric constant material, such as silicon oxide.

[0101] It is clarified here that the capacitor fabrication method provided in this application embodiment can first perform step S23 to pattern the first metal layer 110, and then perform step S3 to form the first dielectric layer 210. Alternatively, the process step of forming the first dielectric film 210' in step S3 can be performed first, and then the first dielectric film 210' and the first metal layer 110 can be patterned to form the first dielectric layer 210.

[0102] S4, such as Figure 5F As shown, a second metal layer 120 is formed.

[0103] For example, such as Figure 5F As shown, a second metal layer 120 is formed on the side of the first dielectric layer 210 away from the semiconductor layer 400.

[0104] That is, the second metal layer 120 is formed on the side of the first dielectric layer 210 away from the semiconductor layer 400. For example, the second metal layer 120 is formed on the surface of the first dielectric layer 210 away from the semiconductor layer 400.

[0105] For example, the material of the second metal layer 120 may include metals such as titanium nitride, titanium, tantalum, or nickel. The materials of the second metal layer 120 and the first metal layer 110 may be the same or different. This application embodiment does not impose such a limitation; it can be reasonably set according to the actual situation.

[0106] In some embodiments, such as Figure 5F As shown, the second metal layer 120 has a second protrusion 102, and the second protrusion 102 extends into the semiconductor layer 400. At this time, step S4 includes:

[0107] S41, Open the second groove 420.

[0108] For example, such as Figure 5FAs shown, the second groove 420 extends from the first dielectric layer 210 into the semiconductor layer 400.

[0109] The depth of the second groove 420 is the same as the thickness of the second protrusion 102 to be formed. This embodiment does not impose a limitation on this; it can be set reasonably according to the actual situation.

[0110] S42, Form a second metal film 120'.

[0111] like Figure 5F As shown, a second metal film 120' is formed on the surface of the first dielectric layer 210 away from the semiconductor layer 400, and the second metal film 120' also fills the second groove 420. The portion of the second metal film 120' filling the second groove 420 serves as a second protrusion 102.

[0112] S43, Form the second metal layer 120.

[0113] For example, the surface of the second metal film 120' is polished by a chemical mechanical polishing process, so that at least a portion of the second metal film 120' remains on the surface of the first dielectric layer 210. In this case, the remaining portion of the second metal film 120' serves as the second metal layer 120.

[0114] In this way, after the surface of the second metal film 120' is treated by CMP process, the surface of the formed second metal layer 120 can be made smoother, which is conducive to the subsequent formation of the second dielectric layer.

[0115] In this embodiment, the thickness of the remaining second metal layer 120 on the surface of the first dielectric layer 210 is not limited; it can be reasonably set according to the actual situation. It should be noted that the portion of the second metal layer 120 without the second protrusion 102 has the same thickness.

[0116] In other embodiments, such as Figure 5G As shown, the second metal layer 120 is flat, for example, the thickness of the second metal layer 120 is uniform.

[0117] At this point, there is no need to create a second groove in the semiconductor layer 400; the steps S42 and S43 can be performed to form the second metal layer 120.

[0118] In some other embodiments, such as Figure 5H As shown, the second metal layer 120 has a second protrusion 102, and the second protrusion 102 is located on the side of the second metal layer 120 away from the semiconductor layer 400.

[0119] At this time, such as Figure 5HAs shown, the method for forming the second metal layer 120 may include: forming a second metal film 120' on the surface of the first dielectric layer 210, then forming a second mask layer 520 on the surface of the second metal film 120', the second mask layer 520 covering the area where the second protrusion 102 is to be formed, then etching the portion of the second metal film 120' not covered by the second mask layer 520 to form the second metal layer 120 having the second protrusion 102, and finally removing the mask layer.

[0120] In some embodiments, such as Figure 5I As shown, step S4 further includes: patterning the second metal layer 120.

[0121] The description of patterning the second metal layer 120 in this embodiment is the same as the description of patterning the first metal layer 110 described above. For details, please refer to the description of step S23 above.

[0122] S5, such as Figure 5J As shown, a second dielectric layer 220 is formed.

[0123] like Figure 5J As shown, the second dielectric layer 220 is formed on the side of the second metal layer 120 away from the semiconductor layer 400. For example, the second dielectric layer 220 is formed on the surface of the second metal layer 120 away from the semiconductor layer 400.

[0124] For example, the material of the second dielectric layer 220 may include a high dielectric constant material, such as silicon oxide. The materials of the second dielectric layer 220 and the first dielectric layer 210 may be the same or different. This embodiment does not impose a limitation on this; it can be reasonably set according to the actual situation.

[0125] S6, such as Figure 5K As shown, a third metal layer 130 is formed.

[0126] For example, such as Figure 5K As shown, a third metal layer 130 is formed on the side of the second dielectric layer 220 away from the semiconductor layer 400.

[0127] That is, the third metal layer 130 is formed on the side of the second dielectric layer 220 away from the semiconductor layer 400. For example, the third metal layer 130 is formed on the surface of the second dielectric layer 220 away from the semiconductor layer 400.

[0128] For example, the material of the third metal layer 130 may include metals such as titanium nitride, titanium, tantalum, or nickel. The materials of the third metal layer 130 and the first metal layer 110 may be the same or different. This embodiment does not impose any limitation on this; it can be reasonably set according to the actual situation.

[0129] In some embodiments, such as Figure 5K As shown, the thickness of the third metal layer 130 is uniform.

[0130] At this point, a metal material is deposited on the surface of the second dielectric layer 220 away from the semiconductor layer 400 to form a third metal layer 130.

[0131] In other implementations, such as Figure 5L As shown, the third metal layer 130 has a third protrusion 103.

[0132] At this point, the method for forming the third metal layer 130 may include:

[0133] S61, Form a third metal film 130'.

[0134] like Figure 5L As shown, the third metal film 130' is formed on the surface of the second dielectric layer 220 away from the semiconductor layer 400.

[0135] S62. A third mask layer 530 is formed on the third metal film 130'.

[0136] The third mask layer 530 covers the area where the third protrusion 103 is to be formed.

[0137] S63. Remove part of the third metal film 130' to form a third metal layer 130.

[0138] For example, the portion of the third metal film 130' not covered by the third mask layer 530 is etched to form a third metal layer 130 having a third protrusion 103.

[0139] S64, Remove the third mask layer 530.

[0140] In this embodiment, the thickness of the third metal layer 130 is not limited; it can be set reasonably according to the actual situation. It should be noted that the portion of the third metal layer 130 without the third protrusion 103 has the same thickness.

[0141] For example, such as Figure 5M As shown, step S6 further includes: patterning the third metal layer 130.

[0142] The description of patterning the third metal layer 130 in this embodiment is the same as the description of patterning the first metal layer 110 described above. For details, please refer to the description of step S23 above.

[0143] It is clarified here that the second conductive post 320 to be formed penetrates the second metal layer 120 and does not connect to the third metal layer 130. Therefore, the third metal layer 130 at the location where the second conductive post 320 is to be formed can be removed, or an annular groove can be formed at the location of the third metal layer 130 where the second conductive post 320 is to be formed, so that the third metal layer 130 is isolated from the third metal layer 130 in contact with the second conductive post 320.

[0144] S7, such as Figure 5N As shown, a first conductive post 310 and a second conductive post 320 are formed.

[0145] In some embodiments, step S7 includes:

[0146] S71, forming the first via 301 and the second via 302.

[0147] For example, such as Figure 5N As shown, the first via 301 penetrates the first metal layer 110, the first dielectric layer 210, the second dielectric layer 220 and the third metal layer 130, and the first via 301 passes through the first protrusion 101 of the first metal layer 110.

[0148] The second via 302 penetrates the second metal layer 120 and passes through the second protrusion 102 of the second metal layer 120.

[0149] S72, forming the first conductive post 310 and the second conductive post 320.

[0150] like Figure 5N As shown, a first conductive post 310 is formed in the first via 301, and a second conductive post 320 is formed in the second via 302.

[0151] At this point, the first conductive post 310 penetrates the first metal layer 110 and the third metal layer 130, and the side of the first conductive post 310 is also adjacent to the first metal layer 110 and the third metal layer 130. For example, the side of the first conductive post 310 is adjacent to the first protrusion 101 and the third metal layer 130.

[0152] It should be clarified here that the first conductive post 310 is adjacent to the first protrusion 101, which can be understood as the first conductive post 310 being in direct contact with the first protrusion 101 and having an electrical connection.

[0153] The second conductive post 320 penetrates the second metal layer 120, and the side of the second conductive post 320 is adjacent to the second metal layer 120. For example, the side of the second conductive post 320 is adjacent to the second protrusion 102.

[0154] It is clarified here that the first conductive post 310 and the second conductive post 320 can be formed in the same process step, or they can be formed in different process steps. That is, the first conductive post 310 is formed first, and then the second conductive post 320 is formed. Alternatively, the second conductive post 320 is formed first, and then the first conductive post 310 is formed. This embodiment of the application does not limit this, and it can be reasonably set according to the actual situation.

[0155] In this embodiment, the metal layer adjacent to the first conductive post 310 and the second conductive post 320 is not limited.

[0156] In some embodiments, the preparation method further includes removing the semiconductor layer 400.

[0157] This completes the fabrication of capacitor 10.

[0158] In some embodiments, the capacitor 10 is formed in a dielectric material between wiring layers. For example, as... Figure 5O As shown, a dielectric material is first formed to cover the surface of the third metal layer 130, and then a first via 301 and a second via 302 are formed, exposing the first metal wiring 11. Then a first conductive post 310 and a second conductive post 320 are formed, and finally a second metal wiring 12 connecting the first conductive post 310 and the second conductive post 320 is formed.

[0159] It should be noted that the capacitor fabrication method provided in this application is not limited to the above steps. Other steps may be added or some of the above steps may be omitted as needed. It is not limited to including every step, nor is it limited to including only the above steps. In addition, the order of steps in the above fabrication method is only illustrative and does not impose any restrictions on the order of steps. It can be adjusted and changed as needed.

[0160] The capacitor fabrication method provided in this application provides a method for forming a first metal layer 110 including a first protrusion 101. This is equivalent to the portion of the first metal layer 110 having the first protrusion 101 being thicker than the portion of the first metal layer 110 without the first protrusion 101, thus achieving a localized thickening of the first metal layer 110. When the first conductive post 310 penetrates the first metal layer 110 and the third metal layer 130, at least a portion of the side surface of the first conductive post 310 is also adjacent to the first protrusion 101. That is, the portion of the first conductive post 310 in contact with the first metal layer 110 is thicker, increasing the thickness of the first metal layer 110 in contact with the first conductive post 310. Therefore, the contact area between the first conductive post 310 and the first metal layer 110 is larger, which can reduce the contact resistance between the first conductive post 310 and the first metal layer 110. The solution provided in this application embodiment does not require increasing the number of first conductive pillars 310, ensuring the feasibility of the process for preparing the first conductive pillars 310. Moreover, it can increase the contact area between the first conductive pillars 310 and the first metal layer 110 and reduce the contact resistance without increasing the number of first conductive pillars 310, thereby increasing the resonant frequency of the capacitor 10 and increasing the capacitance density of the capacitor 10.

[0161] Based on this, such as Figure 6A As shown in the figure, this application embodiment also provides a capacitor 10, which can be fabricated using the capacitor fabrication method described above. The capacitor 10 mainly includes a first metal layer 110, a second metal layer 120, and a third metal layer 130 stacked together. The first metal layer 110 has a first protrusion 101. The capacitor also includes a first dielectric layer 210 located between the first metal layer 110 and the second metal layer 120, a second dielectric layer 220 located between the second metal layer 120 and the third metal layer 130, a first conductive post 310 penetrating the first metal layer 110 and the third metal layer 130, and a second conductive post 320 penetrating the second metal layer 120. At least a portion of the side surface of the first conductive post 310 is adjacent to the first protrusion 101.

[0162] like Figure 6A As shown, the first metal layer 110 includes a first metal body 111 and a first protrusion 101 disposed on the surface of the first metal body 111.

[0163] For example, the thickness of the portion of the first metal layer 110 having the first protrusion 101 is greater than the thickness of the first metal body 111. That is, the first protrusion 101 can increase the thickness of the first metal layer 110.

[0164] In this way, the first metal layer 110 with the first protrusion 101 is thicker, achieving a local thickening of the first metal layer 110. When the first conductive post 310 penetrates the first metal layer 110 and the third metal layer 130, at least a portion of the side surface of the first conductive post 310 is adjacent to the first protrusion 101, which can increase the contact area between the first conductive post 310 and the first metal layer 110.

[0165] The first protrusion 101 and the first metal body 111 can be integrally formed.

[0166] In this way, the preparation process of the first metal layer 110 is simple and easy to form.

[0167] For example, the thickness of the first protrusion 101 is greater than 5% of the thickness of the first metal body 111.

[0168] This increases the contact area between the first conductive post 310 and the first metal layer 110, and reduces the contact resistance between the first conductive post 310 and the first metal layer 110.

[0169] Along the extension direction of the first metal layer 110, the thickness of the first metal body 111 is the same.

[0170] For example, such as Figure 6A As shown, a portion of the side of the first conductive post 310 is adjacent to the first protrusion 101.

[0171] It should be clarified here that the first conductive post 310 is adjacent to the first protrusion 101, which can be understood as the first conductive post 310 being in direct contact with the first protrusion 101 and having an electrical connection.

[0172] In other words, the first conductive post 310 penetrates the first protrusion 101. For example, one side of the first conductive post 310 is adjacent to the first protrusion 101. That is, the first metal layer 110 on one side of the first conductive post 310 is thicker.

[0173] Or, for example, such as Figure 6B As shown, the sides of the first conductive post 310 are all adjacent to the first protrusion 101.

[0174] In other words, the first conductive post 310 extends entirely through the first protrusion 101, and the first conductive post 310 is located within the first protrusion 101. For example, the thickness of the first metal layer 110 on the side of the first conductive post 310 is relatively thick.

[0175] In some embodiments, along the extending direction of the first metal layer 110, the size of the first protrusion 101 is larger than the size of the first conductive post 310.

[0176] In this way, the sides of the first conductive post 310 are all adjacent to the first protrusion 101, making the thickness of the first metal layer 110 on the sides of the first conductive post 310 relatively thick, thereby increasing the contact area between the first conductive post 310 and the first metal layer 110.

[0177] Regarding the position of the first protrusion 101, for example, as shown in... Figure 6B As shown, the first protrusion 101 can be disposed on the side of the first metal layer 110 away from the second metal layer 120.

[0178] That is, the surface of the first metal layer 110 facing away from the first dielectric layer 210 protrudes to form the first protrusion 101.

[0179] For example, the first protrusion 101 is provided on the surface of the first metal body 111 away from the first metal layer 110.

[0180] This makes preparation convenient and the preparation process simple. At the same time, it also ensures that the surface of the first dielectric layer 210 close to the first metal layer 110 is flat.

[0181] Alternatively, for example, the first protrusion 101 may also be disposed on the side of the first metal layer 110 near the second metal layer 120.

[0182] The protrusion on the surface of the first metal layer 110 near the second metal layer 120 can be regarded as the first protrusion 101.

[0183] In this embodiment, at least one side of the first conductive post 310 and the second conductive post 320 is adjacent to a protrusion of the metal layer. For example, the first metal layer 110 has a first protrusion 101, and the side of the first conductive post 310 is adjacent to the first protrusion 101 of the first metal layer 110.

[0184] In some embodiments, continue to refer to Figure 6B The second metal layer 120 has a second protrusion 102.

[0185] For example, the second metal layer 120 may include a second metal body ( Figure 6B (Not shown in the diagram) and a second protrusion 102. The second protrusion 102 is disposed on the surface of the second metal body.

[0186] For example, the thickness of the portion of the second metal layer 120 having the second protrusion 102 is greater than the thickness of the second metal body. That is, the second protrusion 102 can increase the thickness of the second metal layer 120.

[0187] In this way, the second metal layer 120 with the second protrusion 102 is thicker, achieving a localized thickening of the second metal layer 120. When the second conductive post 320 penetrates the second metal layer 120, at least a portion of the side surface of the second conductive post 320 is adjacent to the second protrusion 102, which can increase the contact area between the second conductive post 320 and the second metal layer 120.

[0188] The second protrusion 102 and the second metal body can be integrally formed.

[0189] In this way, the preparation process of the second metal layer 120 is simple and easy to form.

[0190] For example, the thickness of the second protrusion 102 is greater than 5% of the thickness of the second metal body.

[0191] This increases the contact area between the second conductive post 320 and the second metal layer 120, and reduces the contact resistance between the second conductive post 320 and the second metal layer 120.

[0192] The thickness of the second metal body is the same along the extension direction of the second metal layer 120.

[0193] In some embodiments, such as Figure 6B As shown, at least a portion of the side surface of the second conductive post 320 is adjacent to the second protrusion 102.

[0194] This increases the contact area between the second conductive post 320 and the second metal layer 120, thereby reducing the contact resistance and increasing the resonant frequency of the capacitor 10.

[0195] For example, a portion of the side of the second conductive post 320 is adjacent to the second protrusion 102.

[0196] In other words, the second conductive post 320 penetrates the second protrusion 102. For example, one side of the second conductive post 320 is adjacent to the second protrusion 102. That is, the second metal layer 120 on one side of the second conductive post 320 is thicker.

[0197] Or, for example, such as Figure 6B As shown, the sides of the second conductive post 320 are all adjacent to the second protrusion 102.

[0198] In other words, the second conductive post 320 extends entirely through the second protrusion 102, and is located within the second protrusion 102. For example, the second metal layer 120 on the side of the second conductive post 320 is relatively thick.

[0199] In some embodiments, along the extending direction of the second metal layer 120, the size of the second protrusion 102 is larger than the size of the second conductive post 320.

[0200] In this way, the sides of the second conductive post 320 can be adjacent to the second protrusion 102, making the thickness of the second metal layer 120 on the sides of the second conductive post 320 thicker, thereby increasing the contact area between the second conductive post 320 and the second metal layer 120.

[0201] Regarding the position of the second protrusion 102, for example, as shown in... Figure 6B As shown, the second protrusion 102 can be disposed on the side of the second metal layer 120 away from the third metal layer 130.

[0202] The protrusion on the surface of the second metal layer 120 facing away from the third metal layer 130 can be regarded as the second protrusion 102.

[0203] This makes preparation convenient and the preparation process simple. At the same time, it also ensures that the surface of the second dielectric layer 220 adjacent to the second metal layer 120 is flat.

[0204] Alternatively, the second protrusion 102 may be disposed on the side of the second metal layer 120 near the third metal layer 130.

[0205] The protrusion on the surface of the second metal layer 120 facing away from the first metal layer 110 can be regarded as the second protrusion 102.

[0206] This application does not impose any limitations on this aspect; it can be set reasonably according to the actual situation.

[0207] In some embodiments, such as Figure 7 As shown, the third metal layer 130 has a third protrusion 103.

[0208] For example, the third metal layer 130 may include a third metal body ( Figure 7 (Not shown in the diagram) and a third protrusion 103. The third protrusion 103 is provided on the surface of the third metal body.

[0209] For example, the thickness of the portion of the third metal layer 130 having the third protrusion 103 is greater than the thickness of the third metal body. That is, the third protrusion 103 can increase the thickness of the third metal layer 130.

[0210] In this way, the third metal layer 130 with the third protrusion 103 is thicker, achieving a localized thickening of the third metal layer 130. When the first conductive post 310 penetrates the first metal layer 110 and the third metal layer 130, at least a portion of the side surface of the first conductive post 310 is adjacent to the third protrusion 103, which can increase the contact area between the first conductive post 310 and the third metal layer 130, further increasing the contact area between the first conductive post 310 and the metal layers (first metal layer 110 and third metal layer 130), further reducing the contact resistance between the first conductive post 310 and the metal layers, further increasing the resonant frequency of the capacitor 10, and increasing the capacitance density of the capacitor 10.

[0211] The third protrusion 103 and the third metal body can be integrally formed.

[0212] In this way, the preparation process of the third metal layer 130 is simple and easy to form.

[0213] For example, the thickness of the third protrusion 103 is greater than 5% of the thickness of the third metal body.

[0214] This increases the contact area between the first conductive post 310 and the third metal layer 130, and reduces the contact resistance between the first conductive post 310 and the third metal layer 130.

[0215] The thickness of the third metal body is the same along the extension direction of the third metal layer 130.

[0216] For example, such as Figure 7 As shown, at least a portion of the side surface of the first conductive post 310 is adjacent to the third protrusion 103.

[0217] This increases the contact area between the first conductive post 310 and the third metal layer 130, thereby reducing the contact resistance and increasing the resonant frequency of the capacitor 10.

[0218] In other words, a portion of the side of the first conductive post 310 is adjacent to the third protrusion 103. For example, one side of the first conductive post 310 is adjacent to the third protrusion 103. That is, the third metal layer 130 on one side of the first conductive post 310 is thicker.

[0219] Alternatively, the sides of the first conductive post 310 may be adjacent to the third protrusion 103. For example, the thickness of the third metal layer 130 on the sides of the first conductive post 310 may be relatively thick. In this case, it can be considered that the first conductive post 310 completely penetrates the third protrusion 103 of the third metal layer 130.

[0220] For example, the projections of the first protrusion 101 onto the first metal layer 110 and the projections of the third protrusion 103 onto the first metal layer 110 may overlap, partially overlap, or not overlap. It is clarified here that the first protrusion 101 and the third protrusion 103 are not limited in this application, and the dimensions of the first protrusion 101 and the third protrusion 103 may be the same or different.

[0221] In some embodiments, along the extending direction of the third metal layer 130, the size of the third protrusion 103 is larger than the size of the first conductive post 310.

[0222] In this way, the sides of the first conductive post 310 are all adjacent to the third protrusion 103, making the thickness of the third metal layer 130 on the sides of the first conductive post 310 thicker, thereby increasing the contact area between the first conductive post 310 and the third metal layer 130.

[0223] Regarding the position of the third protrusion 103, for example, as shown in... Figure 7 As shown, the third protrusion 103 can be disposed on the side of the third metal layer 130 away from the second metal layer 120.

[0224] The protrusion on the surface of the third metal layer 130 facing away from the second metal layer 120 can be regarded as the third protrusion 103.

[0225] This makes preparation convenient and the preparation process simple.

[0226] Alternatively, for example, the third protrusion 103 may be disposed on the third metal layer 130 on the side near the second metal layer 120.

[0227] The protrusion on the surface of the third metal layer 130 near the side opposite to the second metal layer 120 can be regarded as the third protrusion 103.

[0228] This application does not impose any limitations on this aspect; it can be set reasonably according to the actual situation.

[0229] In some embodiments, such as Figure 8 As shown, capacitor 10 also includes a third dielectric layer 230 and a fourth metal layer 140.

[0230] The third dielectric layer 230 is disposed on the side of the third metal layer 130 away from the second dielectric layer 220, and the fourth metal layer 140 is disposed on the side of the third dielectric layer 230 away from the third metal layer 130.

[0231] The second conductive post 320 also penetrates the fourth metal layer 140, that is, the second conductive post 320 penetrates both the second metal layer 120 and the fourth metal layer 140.

[0232] In this way, capacitor 10 can be equivalent to multiple capacitors connected in parallel, which can increase the capacitance density of capacitor 10.

[0233] For example, such as Figure 8 As shown, the fourth metal layer 140 has a fourth protrusion 104.

[0234] At this time, the second conductive post 320 also penetrates the fourth metal layer 140, and at least a portion of the side surface of the second conductive post 320 is adjacent to the fourth protrusion 104.

[0235] For example, the fourth metal layer 140 may include a fourth metal body ( Figure 8 (Not shown in the diagram) and a fourth protrusion 104. The fourth protrusion 104 is provided on the surface of the fourth metal body.

[0236] For example, the thickness of the portion of the fourth metal layer 140 having the fourth protrusion 104 is greater than the thickness of the fourth metal body. That is, the fourth protrusion 104 can increase the thickness of the fourth metal layer 140.

[0237] In this way, the fourth metal layer 140 with the fourth protrusion 104 is thicker, achieving a localized thickening of the fourth metal layer 140. When the second conductive post 320 penetrates the fourth metal layer 140, at least a portion of the side surface of the second conductive post 320 is adjacent to the fourth protrusion 104, which can increase the contact area between the second conductive post 320 and the fourth metal layer 140.

[0238] The fourth protrusion 104 and the fourth metal body can be integrally formed.

[0239] In this way, the preparation process of the fourth metal layer 140 is simple and easy to form.

[0240] For example, the thickness of the fourth protrusion 104 is greater than 5% of the thickness of the fourth metal body.

[0241] This increases the contact area between the second conductive post 320 and the fourth metal layer 140, and reduces the contact resistance between the second conductive post 320 and the fourth metal layer 140.

[0242] The thickness of the fourth metal body is the same along the extension direction of the fourth metal layer 140.

[0243] In some embodiments, such as Figure 8 As shown, at least a portion of the side surface of the second conductive post 320 is adjacent to the fourth protrusion 104.

[0244] This increases the contact area between the second conductive post 320 and the fourth metal layer 140, thereby reducing the contact resistance and increasing the resonant frequency of the capacitor 10.

[0245] For example, a portion of the side of the second conductive post 320 is adjacent to the fourth protrusion 104.

[0246] In other words, the second conductive post 320 penetrates the fourth protrusion 104. For example, one side of the second conductive post 320 is adjacent to the second protrusion 102. That is, the fourth metal layer 140 on one side of the second conductive post 320 is thicker.

[0247] Or, for example, such as Figure 8 As shown, the sides of the second conductive post 320 are all adjacent to the fourth protrusion 104.

[0248] In other words, the second conductive post 320 extends entirely through the fourth protrusion 104, and is located within the fourth protrusion 104. For example, the fourth metal layer 140 on the side of the second conductive post 320 is relatively thick.

[0249] For example, the projections of the second protrusion 102 onto the first metal layer 110 and the projections of the fourth protrusion 104 onto the first metal layer 110 may coincide, partially coincide, or not coincide. It is clarified here that the second protrusion 102 and the fourth protrusion 104 are not limited in this application embodiment, and the dimensions of the second protrusion 102 and the fourth protrusion 104 may be the same or different.

[0250] In some embodiments, along the extending direction of the fourth metal layer 140, the size of the fourth protrusion 104 is larger than the size of the second conductive post 320.

[0251] In this way, the sides of the second conductive post 320 can be adjacent to the fourth protrusion 104, making the thickness of the fourth metal layer 140 on the sides of the second conductive post 320 thicker, thereby increasing the contact area between the second conductive post 320 and the fourth metal layer 140.

[0252] Regarding the location of the fourth protrusion 104, for example, the fourth protrusion 104 may be disposed on the side of the fourth metal layer 140 away from the third metal layer 130.

[0253] The protrusion on the surface of the fourth metal layer 140 facing away from the third metal layer 130 can be regarded as the fourth protrusion 104.

[0254] This makes preparation convenient and the preparation process simple. At the same time, it also ensures that the surface of the second dielectric layer 220 near the fourth metal layer 140 is flat.

[0255] Or, such as Figure 8 As shown, the fourth protrusion 104 can be disposed on the side of the fourth metal layer 140 near the third metal layer 130.

[0256] The protrusion on the surface of the fourth metal layer 140 near the third metal layer 130 can be regarded as the fourth protrusion 104.

[0257] This application does not impose any limitations on this aspect; it can be set reasonably according to the actual situation.

[0258] In this embodiment, the number of first conductive posts 310 and second conductive posts 320, as well as the number of metal layers they penetrate, are not limited. For example, the capacitor 10 provided in this embodiment may further include multiple first conductive posts 310 and multiple second conductive posts 320. For instance, the first metal layer 110 has multiple first protrusions 101, and the multiple first conductive posts 310 are respectively adjacent to the multiple first protrusions 101. Alternatively, for example, the second metal layer has multiple second protrusions 102, and the multiple second conductive posts 320 are respectively adjacent to the multiple second protrusions 102.

[0259] The capacitor 10 in this embodiment may include three metal layers, four metal layers, or multiple metal layers. This embodiment is not limited in this respect; it can be reasonably configured according to the actual situation.

[0260] In this embodiment, the metal layer through which the first conductive post 310 and the second conductive post 320 pass is not limited, as long as it can make the capacitor 10 equivalent to multiple capacitors connected in parallel.

[0261] The capacitor 10 provided in this application embodiment has at least one metal layer 100 with a protrusion. This is equivalent to the portion of the metal layer 100 with the protrusion being thicker than the portion of the metal layer 100 without the protrusion, thus achieving a local thickening of the metal layer 100. When the conducting post 300 penetrates the metal layer 100, at least a portion of the side surface of the conducting post 300 is also adjacent to the protrusion. That is, the metal layer 100 where the protrusion adjacent to the conducting post 300 is located is thicker, i.e., the metal layer 100 in contact with at least a portion of the side surface of the conducting post 300 is thicker. Therefore, the contact area between the conducting post 300 and the metal layer 100 is larger, which can reduce the contact resistance between the conducting post 300 and the metal layer 100, thereby increasing the resonant frequency of the capacitor 10 and increasing the capacitance density of the capacitor 10. Furthermore, the solution provided in this application embodiment can increase the contact area between the conductive post 300 and the metal layer 100 without increasing the number of conductive posts 300, thereby reducing the contact resistance and thus improving the resonant frequency of the capacitor 10 and increasing the capacitance density of the capacitor 10.

[0262] For example, the first metal layer 110 has a first protrusion 101, which is equivalent to the portion of the first metal layer 110 with the first protrusion 101 being thicker than the portion of the first metal layer 110 without the first protrusion 101, thus achieving a local thickening of the first metal layer 110. When the first conductive post 310 penetrates the first metal layer 110 and the third metal layer 130, at least a portion of the side of the first conductive post 310 is also adjacent to the first protrusion 101. That is, the portion of the first conductive post 310 in contact with the first metal layer 110 is thicker, increasing the thickness of the first metal layer 110 in contact with the first conductive post 310. Therefore, the contact area between the first conductive post 310 and the first metal layer 110 is larger, which can reduce the contact resistance between the first conductive post 310 and the first metal layer 110.

[0263] In some embodiments, this application also provides a capacitor 10. For example... Figure 9 As shown, capacitor 10 includes a first metal layer 110, a second metal layer 120, and a third metal layer 130 stacked together. The second metal layer 120 has a second protrusion 102. The capacitor also includes a first dielectric layer 210 located between the first metal layer 110 and the second metal layer 120, a second dielectric layer 220 located between the second metal layer 120 and the third metal layer 130, a first conductive post 310 penetrating the first metal layer 110 and the third metal layer 130, and a second conductive post 320 penetrating the second metal layer 120. At least a portion of the side surface of the second conductive post 320 is adjacent to the second protrusion 102.

[0264] In this way, the second metal layer 120 has a second protrusion 102, which is equivalent to the second metal layer 120 with the second protrusion 102 being thicker than the second metal layer 120 without the second protrusion 102, thus achieving a local thickening of the second metal layer 120. When the second conductive post 320 penetrates the second metal layer 120, at least a portion of the side of the second conductive post 320 is also adjacent to the second protrusion 102. That is, the thickness of the portion of the second conductive post 320 in contact with the second metal layer 120 is thicker, increasing the thickness of the second metal layer 120 in contact with the second conductive post 320. Therefore, the contact area between the second conductive post 320 and the second metal layer 120 is larger, which can reduce the contact resistance between the second conductive post 320 and the second metal layer 120.

[0265] The description of each structure in capacitor 10 is similar to that in the above embodiments. For details, please refer to the description of each structure in capacitor 10 in the above embodiments.

[0266] Based on this, such as Figure 10 As shown, this application embodiment also provides an integrated circuit 20. The integrated circuit 20 includes a first metal wiring 11, a second metal wiring 12, and the aforementioned capacitor 10.

[0267] The capacitor 10 is disposed between the first metal wire 11 and the second metal wire 12.

[0268] For example, the first conductive post 310 and the second conductive post 320 of the capacitor 10 are both electrically connected to the first metal wiring 11 and the second metal wiring 12.

[0269] The capacitor 10 provided in this application embodiment can be applied between wiring layers, and also between metal wiring and pads. For example, the first metal wiring 11 may include pads. Alternatively, for example, the capacitor 10 provided in this application embodiment can also be applied to chip packaging and chip fabrication.

[0270] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A capacitor, characterized in that, include: Multilayer metal layers and multilayer dielectric layers; The multilayer metal layer includes a first metal layer, a second metal layer, and a third metal layer stacked together. The second metal layer is disposed between the first metal layer and the third metal layer; The multilayer dielectric layer includes a first dielectric layer and a second dielectric layer; The first dielectric layer is disposed between the first metal layer and the second metal layer; The second dielectric layer is disposed between the second metal layer and the third metal layer; The conductive post includes a first conductive post and a second conductive post; the first conductive post penetrates the first metal layer and the third metal layer; the second conductive post penetrates the second metal layer; The metal layer includes a metal body and a protrusion; the protrusion is disposed on the surface of the metal body; at least a portion of the side of the conductive post is adjacent to the protrusion.

2. The capacitor according to claim 1, characterized in that, The thickness of the metal layer having the protrusion is greater than the thickness of the metal body.

3. The capacitor according to claim 1 or 2, characterized in that, At least a portion of the side of the first conductive post is adjacent to the protrusion; along the extension direction of the metal layer, the size of the protrusion is larger than the size of the first conductive post; or, At least a portion of the side of the second conductive post is adjacent to the protrusion; along the extension direction of the metal layer, the size of the protrusion is larger than the size of the second conductive post.

4. The capacitor according to any one of claims 1-3, characterized in that, The thickness of the protrusion is greater than 5% of the thickness of the metal body.

5. The capacitor according to any one of claims 1-4, characterized in that, The thickness of the metal body is the same along the extension direction of the metal layer.

6. The capacitor according to any one of claims 1-5, characterized in that, The protrusion and the metal body are integrally formed.

7. The capacitor according to any one of claims 1-6, characterized in that, The first metal layer has a first protrusion; at least a portion of the side surface of the first conductive post is adjacent to the first protrusion; and / or; The second metal layer has a second protrusion; at least a portion of the side surface of the second conductive post is also adjacent to the second protrusion; and / or; The third metal layer has a third protrusion; at least a portion of the side surface of the first conductive post is also adjacent to the third protrusion.

8. The capacitor according to claim 7, characterized in that, The surface of the first metal layer facing away from the first dielectric layer protrudes to form the first protrusion.

9. The capacitor according to any one of claims 1-8, characterized in that, The capacitor further includes a third dielectric layer and a fourth metal layer; the third dielectric layer is disposed on the side of the third metal layer away from the second dielectric layer; the fourth metal layer is disposed on the side of the third dielectric layer away from the third metal layer; the fourth metal layer has a fourth protrusion; The second conductive post also penetrates the fourth metal layer; at least a portion of the side surface of the second conductive post is adjacent to the fourth protrusion.

10. A method for manufacturing a capacitor, characterized in that, include: Forming a multilayer metal layer and a multilayer dielectric layer stacked together, including; Form the first metal layer; A first dielectric layer is formed on the first metal layer; A second metal layer is formed on the side of the first dielectric layer away from the first metal layer; A second dielectric layer is formed on the side of the second metal layer away from the first dielectric layer; A third metal layer is formed on the side of the second dielectric layer away from the second metal layer; Forming the conductive post penetrating at least one of the metal layers includes: A first conductive post and a second conductive post are formed, wherein the first conductive post penetrates the first metal layer and the third metal layer; and the second conductive post penetrates the second metal layer. The metal layer includes a metal body and a protrusion; the protrusion is formed on the surface of the metal body; at least a portion of the side surface of the conductive post is adjacent to the protrusion.

11. The method for preparing a capacitor according to claim 10, characterized in that, Forming the first metal layer having a first protrusion includes: A semiconductor layer is provided, wherein a first groove is formed on the semiconductor layer; A first metal layer is formed on the semiconductor layer; the portion of the first metal layer filling the first groove serves as the first protrusion, and the portion of the first metal layer located on the surface of the semiconductor layer serves as the first metal body. The preparation method further includes: Remove the semiconductor layer.

12. The method for preparing a capacitor according to claim 11, characterized in that, After the formation of the first dielectric layer and before the formation of the second metal layer, the preparation method further includes: A second groove is formed, the second groove extending from the first dielectric layer into the semiconductor layer; A second metal layer is formed on the side of the first dielectric layer away from the semiconductor layer, and the second metal layer also fills the second groove; the portion of the second metal layer filling the second groove serves as a second protrusion. Forming a second conductive post includes: at least a portion of the side surface of the second conductive post is adjacent to the second protrusion.

13. An integrated circuit, characterized in that, include: The first and second metal wirings are stacked together; The capacitor as described in any one of claims 1-9; the capacitor is disposed between the first metal wiring and the second metal wiring; the first conductive post is electrically connected to the first metal wiring and the second metal wiring.

14. The integrated circuit according to claim 13, characterized in that, The first metal wiring includes pads.

15. An electronic device, characterized in that, include: The integrated circuit and the printed circuit board as described in claim 13 or 14; the integrated circuit and the printed circuit board are electrically connected.

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