Capacitor manufacturing method and memory device manufacturing method

Abstract

A capacitor manufacturing method of the present application includes forming a plurality of lower electrodes and a support layer supporting the lower electrodes on a substrate; etching the lower electrodes to expand a top cell distance (TCD) of the lower electrodes; forming a dielectric layer on the lower electrodes and the support layer; and forming an upper electrode on the dielectric layer.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0045785, filed on April 8, 2026, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This invention relates to a method for manufacturing capacitors and a method for manufacturing storage devices, and more specifically, to a method for manufacturing capacitors and a method for manufacturing storage devices with improved profile perpendicularity. Background Technology

[0003] As the integration density of semiconductor devices continues to increase, the precision of capacitor design, including metal-insulator-metal (MIM) structures, is becoming increasingly important for ensuring device performance and reliability.

[0004] In particular, as integration density increases, the area that capacitors can occupy continues to decrease, necessitating that the lower electrode be formed with a high aspect ratio to ensure sufficient capacitance. To guarantee high capacitance within a limited space, the height of the lower electrode needs to be further increased. Therefore, obtaining an etching technique that can maintain contour perpendicularity while ensuring etching depth has become a key challenge.

[0005] However, as the aspect ratio increases, the etching process becomes more difficult. Typically, the space (opening) for forming the lower electrode is created by etching a stack of mold layers and support layers; ideally, a cylindrical structure with a vertical profile is desirable. However, as the etching depth increases, the number of ions and free radicals reaching the bottom decreases, potentially resulting in an inverted conical structure that is wider at the top and narrower at the bottom. Furthermore, the verticality of the structure is further reduced when bowing occurs due to over-etching of the sidewalls.

[0006] This suboptimal etching profile results in an excessively narrow top-to-bottom spacing (TCD) between the lower electrodes, which can lead to various problems such as a decrease in dielectric constant, localized variations in film thickness, inter-cell interference, and an increase in localized leakage current during subsequent dielectric film deposition. Therefore, to ensure profile perpendicularity during the etching process, a process is needed that can adequately guarantee the top-to-bottom spacing between the lower electrodes.

[0007] Furthermore, since high aspect ratio structures are at risk of collapse or loss in subsequent processes, a supporting structure must be formed simultaneously to stably support the lower electrode. However, in plasma-based etching methods, problems such as reduced etching selectivity, increased surface roughness, and structural damage frequently occur, limiting precise structural control. To overcome this, atomic layer etching (ALE) technology has recently attracted attention. Because each cycle of ALE is self-limiting, it precisely removes the target layer without over-etching, minimizing surface damage and increased roughness, especially when applied to damage-sensitive structures such as lower electrodes composed of metallic materials.

[0008] Therefore, a high-precision selective etching process is required, especially an ALE-based process, which can ensure the perpendicularity of the contour and extend the upper spacing without damaging the support layer. Summary of the Invention

[0009] The purpose of this invention is to provide a capacitor manufacturing method and a memory device manufacturing method that can effectively extend the upper spacing (TCD) of the lower electrode in a high aspect ratio structure to improve the profile perpendicularity.

[0010] Another object of the present invention is to provide a method for manufacturing a capacitor and a method for manufacturing a memory device that can selectively etch the electrodes without damaging the support layer.

[0011] Another object of the present invention is to provide a capacitor manufacturing method and a memory device manufacturing method that can improve the surface roughness of the lower electrode to improve the uniformity of subsequent dielectric film deposition and dielectric constant characteristics.

[0012] Another object of the present invention is to provide a method for manufacturing capacitors and a method for manufacturing storage devices that can improve reliability.

[0013] The purpose of this invention is not limited to those described above. Other purposes not mentioned herein will become clear to those skilled in the art from this specification and the accompanying drawings.

[0014] According to one embodiment of the present invention, a capacitor manufacturing method includes: forming a plurality of lower electrodes and a support layer supporting the lower electrodes on a substrate; etching the lower electrodes to extend the upper spacing (TCD) of the lower electrodes; forming a dielectric layer on the lower electrodes and the support layer; and forming an upper electrode on the dielectric layer, wherein, in the step of extending the upper spacing of the lower electrodes, the etching amount of the upper region of the lower electrodes is greater than the etching amount of the lower region of the lower electrodes.

[0015] The step of etching the lower electrode can be an ALE (atomic layer etching) process and may include: supplying a reactant into a cavity in which the substrate is placed; purging the interior of the cavity; supplying an etchant into the interior of the cavity; and purging the interior of the cavity.

[0016] The reactants and etchants can be adsorbed relatively more in the upper region of the lower electrode, and as the concentration decreases, they are adsorbed relatively less towards the lower region.

[0017] The reactants can be any one of O2, O3, H2O and H2O2 alone, or a mixture of at least two of O2, O3, H2O and H2O2.

[0018] The etchant can be at least one of dimethylformamide-dimethyl acetal and 1-chloromethyl ethyl ether.

[0019] In the step of etching the lower electrode, the support layer may have etching selectivity for the lower electrode.

[0020] The step of etching the lower electrode can increase the aspect ratio of the lower electrode.

[0021] The method may further include, between the step of expanding the upper spacing of the lower electrode and the step of forming the dielectric layer: forming an insulating layer on the lower electrode and the support layer; and etching the insulating layer from the surface of the support layer.

[0022] During the etching step, the insulating layer can be selectively removed from the surface of the support layer.

[0023] The lower electrode can have a high aspect ratio of 1:10 or greater.

[0024] The lower electrode may include metal, metal nitride, metal silicon nitride, conductive metal oxide, metal silicide, noble metal, or a combination thereof.

[0025] The support layer may include silicon nitride (Si3N4), silicon carbonitride (SiCN), silicon boronitride, or a combination thereof.

[0026] The dielectric layer may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanate (SrTiO3), or combinations thereof or stacked structures.

[0027] The insulating layer may include niobium oxide, niobium nitride, niobium oxynitride, tantalum oxide, yttrium oxide, or lanthanum oxide, or combinations thereof.

[0028] After the step of expanding the upper spacing of the lower electrode, the lower electrode may have a tapered shape, wherein the upper spacing (TCD) of the lower electrode is greater than the lower spacing (BCD) of the lower electrode.

[0029] According to one embodiment of the present invention, a method for manufacturing a storage device may include the above-described method for manufacturing a capacitor.

[0030] According to one embodiment of the present invention, the capacitor manufacturing method can effectively ensure profile perpendicularity through an ALE (atomic layer etching) based etching process, thereby achieving an ideal etch profile even in high aspect ratio structures. Compared with conventional processes, deeper and more uniform openings can be formed without changing the conventional opening formation process, and the thickness variation during dielectric film deposition can be reduced and dielectric constant characteristics improved.

[0031] According to one embodiment of the present invention, the capacitor manufacturing method can extend the upper spacing of the lower electrode and improve the surface roughness of the lower electrode to ensure the reliability of subsequent processes (e.g., dielectric film deposition). This can improve the performance and manufacturing yield of the semiconductor device.

[0032] According to one embodiment of the present invention, the capacitor manufacturing method can selectively etch the electrodes without damaging the support structure. Attached Figure Description

[0033] Figures 1A to 1F This is a schematic view illustrating a conventional capacitor manufacturing process.

[0034] Figures 2A to 2C This is a schematic view illustrating a capacitor manufacturing method according to an embodiment of the present invention.

[0035] Figure 3 This is a schematic diagram illustrating the supply cycle according to an embodiment of the present invention.

[0036] Figure 4 The TEM analysis results of titanium nitride (TiN) films before and after the ALE process according to an embodiment of the present invention are shown.

[0037] Figure 5 The TEM analysis results of silicon carbonitride (SiCN) films before and after the ALE process according to an embodiment of the present invention are shown.

[0038] Figure 6 This is a view comparing various types of electrodes.

[0039] Figure 7 The TEM analysis results of titanium nitride (TiN) films before and after the ALE process according to the experimental example of the present invention are shown.

[0040] Figure 8 The TEM analysis results of titanium nitride (TiN) films before and after the ALE process according to the experimental example of the present invention are shown.

[0041] Figure 9 The TEM analysis results of titanium nitride (TiN) films before and after the ALE process according to the experimental example of the present invention are shown.

[0042] Figures 10A to 10C This is a schematic view illustrating a method for manufacturing a capacitor according to another embodiment of the present invention.

[0043] Figures 11A to 11C This is a schematic view illustrating a method for manufacturing a capacitor according to another embodiment of the present invention. Detailed Implementation

[0044] The following will refer to the appendix. Figures 1A to 11C Preferred embodiments of the invention will be described in more detail below. The embodiments of the invention can be modified in various ways, and the scope of the invention should not be construed as limited to the following embodiments. These embodiments are provided to explain the invention in more detail to those skilled in the art to which this invention pertains. Therefore, the shapes of the elements shown in the figures may be exaggerated for clarity.

[0045] Figures 1A to 1F This is a schematic view illustrating a conventional capacitor manufacturing process. (e.g.) Figure 1A As shown, the capacitor may include a lower structure. The lower structure may be a stacked structure including a substrate 101 and an interlayer insulating layer 102 on the substrate 101.

[0046] Substrate 101 may include materials suitable for semiconductor processing. For example, substrate 101 may include a semiconductor substrate, which may be made of a silicon-containing material. The semiconductor substrate may include silicon (Si), monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium (Si-Ge), monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayer structures thereof. The semiconductor substrate may include other semiconductor materials, such as germanium (Ge). The semiconductor substrate may include group III / V semiconductor substrates, such as compound semiconductor substrates, such as gallium arsenide (GaAs). The semiconductor substrate may include a silicon-on-insulator (SOI) substrate.

[0047] The interlayer insulating layer 102 may include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), or spin-coated glass (SOG).

[0048] The lower structure may include a plurality of contact plugs 103, which may be referred to as memory node contact plugs. The contact plugs 103 are formed in an interlayer insulating layer 102 and can be connected to the substrate 101 through the interlayer insulating layer 102. The contact plugs 103 may include polysilicon, metal, metal nitride, metal silicide, or combinations thereof or stacked structures. For example, the contact plugs 103 may include polysilicon, tungsten, tungsten nitride, titanium nitride, titanium silicon nitride, titanium silicide, cobalt silicide, or combinations thereof. In another embodiment, the contact plugs 103 may be stacked in the order of semiconductor material, metal silicide, metal nitride, and metal.

[0049] Although not shown, multiple word lines and bit lines may be formed on and / or in the substrate 101. An interlayer insulating layer 102 may be formed to cover the word lines and bit lines. Impurity regions (not shown) may be formed in the substrate 101 on both sides of each word line, and each contact plug 103 may be connected to one of the impurity regions.

[0050] A mold stack layer MS can be formed on the lower structure. The mold stack layer MS includes an etch stop layer 104, mold layers 105, 107, 109, and support layers 106S, 108S, and 110S. For example, the mold stack layer MS can be stacked in the following order: lower mold layer 105, lower support layer 106S, middle mold layer 107, middle support layer 108S, upper mold layer 109, and upper support layer 110S on the etch stop layer 104. The etch stop layer 104 can be formed on the interlayer insulating layer 102 and the contact plug 103, and the etch stop layer 104 may include silicon nitride.

[0051] Mold layers 105, 107, and 109 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Mold layers 105, 107, and 109 may comprise phosphorus-doped silicon oxide or boron-doped silicon oxide, and the mold layers may comprise USG, PSG, BSG, BPSG, FSG, or combinations thereof. The lower mold layer 105, middle mold layer 107, and upper mold layer 109 can be different in subsequent processes with different etch rates.

[0052] The support layers 106S, 108S, and 110S can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The support layers 106S, 108S, and 110S can include materials that are etch-selective for the mold layers 105, 107, and 109. Specifically, the support layers 106S, 108S, and 110S can include silicon nitride (Si3N4), silicon carbonitride (SiCN), silicon boron nitride, or combinations thereof, and the thicknesses of the lower support layer 106S, the middle support layer 108S, and the upper support layer 110S can be different.

[0053] like Figure 1B As shown, multiple openings 111 can be formed in the mold stack layer MS. The openings 111 can be formed by etching the mold stack layer MS using a mask layer (not shown). To form the openings 111, the mask layer can be used as an etching barrier to sequentially etch the upper support layer 110S, the upper mold layer 109, the middle support layer 108S, the middle mold layer 107, the lower support layer 106S, and the lower mold layer 105. The etching process for forming the openings 111 may stop at the etching stop layer 104.

[0054] To form the opening 111, dry etching, wet etching, or a combination thereof can be used. Furthermore, as the etching gas for forming the opening, a mixed gas plasma of two or more of the following can be used: fluorinated hydrocarbon gas, fluorinated methane gas, argon, hydrogen (H2), and carbon dioxide (CO2).

[0055] The opening 111 may be referred to as the aperture where the lower electrode (or memory node) will be formed. The opening 111 may have a high aspect ratio, which may be at least 1:1 or greater. For example, the opening 111 may have a high aspect ratio of 1:10 or greater. Aspect ratio may refer to the ratio of width to height. Subsequently, the etch stop layer 104 may be etched to expose the upper surface of each contact plug 103 below the opening 111.

[0056] At the same time, such as Figure 1B As shown, there is a problem that the lower part W2 of the opening 111 is smaller than its upper part W1 (W1>W2). This is because dry etching is usually used in the etching process that forms the opening 111, and due to the etching characteristics of the dry etching method, the etching efficiency decreases as the etching proceeds towards the lower part of the opening 111.

[0057] like Figure 1C As shown, a lower electrode 112 can be formed in each opening 111, and the lower electrode 112 can be cylindrical. The lower electrode 112 can fill the interior of the opening 111 and can be electrically connected to the substrate 101 via a contact plug 103.

[0058] The lower electrode 112 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The lower electrode 112 may include a metal, a metal nitride, a metal silicon nitride, a conductive metal oxide, a metal silicide, a noble metal, or a combination thereof. The lower electrode 112 may include at least one of titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), or a combination thereof.

[0059] like Figure 1C As shown, the upper spacing (TCD) of the conventional lower electrode 112 is very narrow compared to the lower spacing (BCD), following the shape of the opening 111.

[0060] like Figure 1D As shown, mold layers 105, 107, and 109 can be removed using a wet removal process, thereby exposing the surface of the etch stop layer 104. The wet removal process for removing mold layers 105, 107, and 109 can be performed using wet chemicals capable of selectively removing mold layers 105, 107, and 109. The wet chemicals can be one or more chemicals such as HF, NH4F / NH4OH, H2O2, HCl, HNO3, H2SO4, and BOE (buffered oxide etchant) solution.

[0061] With the removal of mold layers 105, 107, and 109, the outer wall of the lower electrode 112 may be partially exposed. When removing mold layers 105, 107, and 109, the support layers 106S, 108S, and 110S, which are etch-selective for mold layers 105, 107, and 109, may be retained and not removed, and the outer wall of the lower electrode 112 may be supported by the support layers 106S, 108S, and 110S.

[0062] like Figure 1E As shown, a dielectric layer 113 can be formed. The dielectric layer 113 can be formed on the lower electrode 112 and the support layers 106S, 108S, and 110S, and a portion of the dielectric layer 113 may cover the underlying structure.

[0063] like Figure 1F As shown, an upper electrode 114 can be formed on the dielectric layer 113. The upper electrode 114 can fill the space between adjacent lower electrodes 112. The upper electrode 114 can extend to cover the upper part of the lower electrode 112.

[0064] Meanwhile, in conventional capacitor manufacturing methods, the gaps between dielectric layers 113 become very narrow, following the shape of the lower electrode 112. This reduces the actual area covered by the dielectric layer, leading to a loss of dielectric constant and increased inter-cell interference. Furthermore, the uneven thickness of the dielectric layer 113 results in increased leakage current, leading to reduced cell reliability and yield.

[0065] Figures 2A to 2C This is a schematic view illustrating a capacitor manufacturing method according to an embodiment of the present invention. Only the parts that differ from the foregoing description are described below; omitted descriptions can be replaced by the foregoing description.

[0066] like Figure 2A As shown, with the removal of the mold layer, the outer wall of the lower electrode 212 may be partially exposed. The support layers 206S, 208S, and 210S, which have etching selectivity for the mold layer, may be retained and not removed. The outer wall of the lower electrode 212 may be supported by the support layers 206S, 208S, and 210S.

[0067] Subsequently, the lower electrode 212 can be etched to improve its profile. The etching of the lower electrode 212 can be performed using ALE (atomic layer etching). The aspect ratio of the lower electrode 212 can be increased by etching; for example, the lower electrode 212 can have a high aspect ratio of 1:10 or greater.

[0068] Specifically, in one embodiment of this application, the lower electrode 212 can be etched using an ALE process employing one of O3, O2, H2O, or H2O2 as a reactant and one of dimethylformamide-dimethyl acetal and 1-chloromethyl ethyl ether as an etchant. The reactant and etchant used in the ALE process are over-adsorbed at the top, and their diffusion and concentration decrease towards the bottom, similar to the behavior of a precursor. Therefore, the etching amount at the top of the lower electrode 212 is greater than that at the bottom, which effectively improves the reverse conical structure or bowing phenomenon that occurs in conventional opening formation processes, ensuring profile perpendicularity. Furthermore, since each cycle of the ALE process is self-limiting, the lower electrode 212 can be selectively etched without damaging the support layers 206S, 208S, and 210S, thereby improving the profile of the lower electrode 212 to form a deeper, larger aspect ratio opening 211 than in conventional processes. The uniformity of subsequent dielectric film deposition and the dielectric constant characteristics described below can also be improved.

[0069] Subsequently, as Figure 2BAs shown, a dielectric layer 213 can be formed. The dielectric layer 213 can be formed on the lower electrode 212 and the support layers 206S, 208S, and 210S, and a portion of the dielectric layer 213 may cover the underlying structure. The dielectric layer 213 can include a high-k material with a higher dielectric constant than silicon oxide. High-k materials can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). The dielectric layer 213 can also include combinations or stacked structures thereof. In addition, the dielectric layer 213 may include ZAZ (ZrO2 / Al2O3 / ZrO2) stack, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, ZAZAT (ZrO2 / Al2O3 / ZrO2 / Al2O3 / TiO2) stack, HAH (HfO2 / Al2O3 / HfO2) stack, TZAZ (TiO2 / ZrO2 / Al2O3 / ZrO2) stack, TiO2 / HfO2 / Al2O3 / HfO2 stack, Ta2O5 / ZrO2 / Al2O3 / ZrO2 stack, or Ta2O5 / HfO2 / Al2O3 / HfO2 stack.

[0070] Subsequently, as Figure 2C As shown, an upper electrode 214 can be formed on the dielectric layer 213. The upper electrode 214 can fill the space between adjacent lower electrodes 212. The upper electrode 214 can extend to cover the upper portion of the lower electrode 212. The upper electrode 214 can include polysilicon, silicon germanium, metal, metal nitride, metal silicon nitride, conductive metal oxide, metal silicide, noble metal, or a combination thereof. The upper electrode 214 can include at least one of titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), or a combination thereof.

[0071] As explained above, a conformal dielectric layer can be formed, increasing the effective area and thereby improving the reliability of the capacitor by increasing the dielectric constant and reducing leakage current.

[0072] Figure 3 This is a schematic diagram illustrating a supply cycle according to an embodiment of the present invention. First, a semiconductor device with a mold layer removed by a previous process is placed inside a chamber, and the reactant supplied to the chamber is exposed to the semiconductor device.

[0073] The reactant can be provided individually of any one of O2, O3, H2O, and H2O2, or as a mixture of at least two of O2, O3, H2O, and H2O2. Specifically, the reactant can include at least one selected from the group consisting of O2, O3, H2O, and H2O2, and if desired, can be provided as a mixture of at least two of O2, O3, H2O, and H2O2.

[0074] Subsequently, a purge gas (such as an inert gas like Ar) is supplied to the interior of the chamber to remove or purify any remaining reactants or byproducts.

[0075] Subsequently, the etchant (or reactive gas) supplied to the inside of the chamber is exposed to the semiconductor device, and etching is activated by the etchant.

[0076] As an etchant, either dimethylformamide-dimethyl acetal or 1-chloromethyl ethyl ether can be used. However, this is merely an example and should not be construed as limiting. Any suitable material having a similar structure or performing a similar function to dimethylformamide-dimethyl acetal or 1-chloromethyl ethyl ether can be used as an etchant. Specifically, bis(dimethylamino)methoxymethane, trimethyl orthoformic acid, trimethyl orthoacetic acid, and / or dichloromethyl methyl ether, having a similar structure or similar function to dimethylformamide-dimethyl acetal or 1-chloromethyl ethyl ether, are also suitable as etchants of this invention. Subsequently, a purge gas (e.g., an inert gas such as Ar) is supplied to the interior of the chamber to remove or purify any residual etchant or byproducts.

[0077] Simultaneously, the reactants and etchants are over-adsorbed at the top, and their diffusion and concentration decrease towards the bottom, similar to the behavior of precursors. Therefore, the upper spacing (TCD) of the lower electrode 212 can be extended compared to conventional processes. Specific details and their effects before and after the ALE process will be explained below.

[0078] According to one embodiment of this application, the reactant may include reactive species activated in a plasma state. For example, O2 plasma can be used as a reactant. A reactant in a plasma state can improve reactivity and enable the process under cryogenic process conditions.

[0079] Specifically, O2 plasma can be generated using various plasma generation methods. For example, O2 plasma can be generated by applying capacitively coupled plasma (CCP), inductively coupled plasma (ICP), and / or other plasma generation methods.

[0080] Furthermore, plasma can be provided via remote plasma methods or direct plasma methods.

[0081] By using a reactant in a plasma state, this invention is applicable not only to ALD processes using thermal reactions, but also to plasma-enhanced atomic layer deposition (PEALD) and atomic layer etching (ALE) processes. The type and supply method of the reactant can be selectively adjusted according to process conditions and desired film properties.

[0082] The following will refer to Figure 4 and Figure 5 Describe the etching characteristics and selectivity of the ALE process for each material.

[0083] Figure 4 The TEM analysis results of titanium nitride (TiN) films before and after the ALE process according to an embodiment of the present invention are shown. Figure 5 The TEM analysis results of silicon carbonitride (SiCN) films before and after the ALE process according to an embodiment of the present invention are shown.

[0084] A titanium nitride (TiN) film deposited on a silicon oxide substrate and a silicon carbonitride (SiCN) film deposited on a silicon substrate are simultaneously loaded into the chamber. According to Figure 3 The supply cycle used O3 as a reactant and dimethylformamide-dimethyl acetal as an etchant, and the ALE process was performed at a process temperature of 300 degrees Celsius, with etching performed by repeating 50 cycles.

[0085] like Figure 4 As shown, it was confirmed that the titanium nitride (TiN) film was etched to 11.7 Å using the ALE process. Since the EPC (etch per cycle) of ALE is approximately 0.23 Å / cycle, the thickness decreased linearly, confirming that the thickness of the TiN film can be precisely controlled by adjusting the number of ALE process cycles. Furthermore, it was confirmed that the roughness (Rq) of the TiN film was improved from 0.8 nm to 0.6 nm using the ALE process.

[0086] like Figure 5 As shown, in the case of silicon carbonitride (SiCN) film, the thickness change before and after the ALE process is at the level of 1.2 Å, which is not significant. Furthermore, the roughness (Rq) of the silicon carbonitride (SiCN) film was confirmed to be 0.2 nm before the ALE process and 0.21 nm afterward, confirming almost no surface damage or change.

[0087] The results above demonstrate that the ALE process can precisely control the thickness of the titanium nitride (TiN) film, achieving a constant etch charge (EPC) per cycle, while exhibiting high etch selectivity for the silicon carbonitride (SiCN) film, where etching is almost nonexistent. This is due to the self-limiting nature of the ALE process, where each reaction cycle is limited to surface reactions, thus suppressing over-etching. Therefore, when the ALE process is applied to practical high aspect ratio structures, it can be seen as a basis for selectively etching only the lower electrode 212 without damaging the support layers 206S, 208S, and 210S. Based on this difference in etch selectivity, the titanium nitride (TiN) film can be used as the lower electrode 212 selectively etched by the ALE process, and the silicon carbonitride (SiCN) film can be used as the support layers 206S, 208S, and 210S that stably support the structure in the ALE process without being etched. Furthermore, as described below... Figures 7 to 9 As shown, even when the ALE process is applied to actual high aspect ratio hole pattern wafers, the effects of increased top pitch (TCD) of the lower electrode and improved step coverage are experimentally confirmed.

[0088] Figure 6 This is a comparison view of various types of lower electrodes. (a) shows a lower electrode (aspect ratio 1:10) (W=15 nm, H=150 nm) resulting from the limitations of conventional aperture etching processes. (b) shows a lower electrode (aspect ratio 1:10) where, due to the limitations of conventional aperture etching processes, neither the height (H) nor the width (W) can be selectively increased, and the aspect ratio is the same as in (a) (W=16 nm, H=160 nm). (c) shows a lower electrode (W=15 nm, H=160 nm) with an improved aspect ratio (aspect ratio 1:10.7) obtained by etching the lower electrode of (b) according to an embodiment of the invention. Specifically, Figure 6 Table 1 below is a schematic view illustrating the improvement in the aspect ratio of the lower electrode when applied using the ALE process according to the invention. According to one embodiment of the invention, the aspect ratio and profile perpendicularity are improved by etching the lower electrode (b), thereby increasing the effective area and improving the dielectric film. Table 1 below shows... Figure 6 The width / height and aspect ratio of the lower electrode are shown. Table 1

[0089] Meanwhile, as described below Figures 7 to 9 The purpose is to demonstrate, through experiments using actual hole-patterned wafers, that the effects of the present invention can be achieved under extremely high aspect ratio conditions of 1:30 to 1:50.

[0090] The following is for reference Figures 7 to 9 The effects of various combinations of reactants and etchants on the ALE process under more extreme high aspect ratio conditions will be described. Figures 7 to 9 In the figure, (a) and (b) show the top and bottom TEM images of the state before the ALE process (reference), and (c) and (d) show the top and bottom TEM images of the state after the ALE process (experimental example). Specifically, Figures 7 to 9 The TEM data in the table is based on the data interpreted from the top.

[0091] Figure 7 TEM analysis results before and after the ALE process under a certain aspect ratio condition are shown in the present invention (Experimental Example 1). In Experimental Example 1, the ALE process was carried out at a process temperature of 300 degrees Celsius, using 1-chloromethylethyl ether as the etchant and an aqueous H2O2 solution as the reactant. The etchant was supplied to the chamber at a rate of 0.1 g / min via an LFM (liquid flow meter) method. The reactant was supplied via a steam method, and the temperature of the storage container was maintained at 40 degrees Celsius.

[0092] The patterned wafer used has a top CD pitch of approximately 52 nanometers and a hole structure with an aspect ratio of 1:30. Table 2 below shows the results based on... Figure 7 TEM analysis results before and after ALE process. Table 2

[0093] As shown in Table 2, the thickness of the upper TiN film of the lower electrode decreased from 62.2 Å before the ALE process to 48.8 Å after the ALE process, confirming an opening expansion of approximately 26 Å (about twice the change in upper TiN film thickness (13.4 Å)). The pattern step coverage was 90.7% before the ALE process, but increased to 100.2% after the ALE process, indicating improved step coverage. Furthermore, based on the thickness reduction of the ALE process, the upper-to-lower etching ratio was approximately 56%, confirming that etching mainly occurred in the upper region. Therefore, it is confirmed that by applying the atomic layer etching process proposed in this invention, the upper spacing in the lower electrode structure can be expanded, and the perpendicularity of the pattern contour can be improved.

[0094] Figure 8 TEM analysis results before and after the ALE process according to Experimental Example (Experimental Example 2) of the present invention are shown. In Experimental Example 2, the ALE process was carried out at a process temperature of 300 degrees Celsius, using 1-chloromethylethyl ether as an etchant and 140 g / m³ of O3 as a reactant. The etchant was supplied to the chamber at a rate of 0.1 g / min via the LFM method. The patterned wafer used had a top CD pitch of approximately 30 nm and a hole structure with an aspect ratio of 1:50. Table 3 below shows the results according to... Figure 8 TEM analysis results before and after ALE process. Table 3

[0095] like Figure 8 As shown, the thickness of the upper TiN film decreased from 75.7 Å to 61.5 Å before the ALE process, confirming an opening expansion of approximately 28 Å (about twice the change in upper TiN film thickness (14.2 Å)). The pattern step coverage was 67.1% before the ALE process, but increased to 82.1% after the ALE process, indicating improved step coverage. Furthermore, based on the thickness reduction of the ALE process, the etching ratio of the upper part to the lower part was approximately 2%, confirming that etching was primarily performed in the upper region. Therefore, it is confirmed that by applying the atomic layer etching process proposed in this invention, the upper spacing in the lower electrode structure can be expanded, and the verticality of the pattern contour can be improved.

[0096] Figure 9 TEM analysis results before and after the ALE process according to Experimental Example (Experimental Example 3) of the present invention are shown. In Experimental Example 3, the ALE process was carried out at a process temperature of 320 degrees Celsius, using dimethylformamide-dimethyl acetal as the etchant and 120 g / m³ of O3 as the reactant. The etchant was supplied to the chamber at a rate of 0.1 g / min via the LFM method. The patterned wafer used had a top CD pitch of approximately 30 nm and a hole structure with an aspect ratio of 1:50. Reference figure of Experimental Example 3 [ Figure 9 [a)(b)] The same patterned wafer as in Experimental Example 2 was used. Table 4 below shows the results according to... Figure 9 TEM analysis results before and after the ALE process. Table 4

[0097] like Figure 9 As shown, the thickness of the upper TiN film decreased from 75.7 Å to 62.6 Å before the ALE process, confirming an opening expansion of approximately 26 Å (about twice the change in upper TiN film thickness (13.1 Å)). The pattern step coverage was 67.1% before the ALE process, but increased to 81.0% after the ALE process, indicating improved step coverage. Furthermore, based on the thickness reduction of the ALE process, the upper-to-lower etching ratio was approximately 1%, confirming that etching was primarily performed in the upper region. Therefore, it is confirmed that by applying the atomic layer etching process proposed in this invention, the upper spacing in the lower electrode structure can be expanded, and the perpendicularity of the pattern contour can be improved.

[0098] Table 5 below compares the ALE process conditions and TiN patterned wafer analysis results based on Experimental Examples 1 to 3.

[0099] Table 5

[0100] The results from Examples 1 to 3 demonstrate that regardless of the combination of reactant (H₂O₂ or O₃) and etchant (1-chloromethylethyl ether or dimethylformamide-dimethyl acetal), even under extremely high aspect ratio conditions of 1:30 to 1:50, the ALE process can extend the upper spacing (TCD) of the lower electrode and improve step coverage. Specifically, in all three examples, the TiN thickness of the bottom TEM of the lower electrode (d) was confirmed to remain at a similar level to the reference, while etching mainly occurred only at the top (c). This is attributed to the characteristic of the ALE process where the reactant and etchant are over-adsorbed at the top and their concentration decreases towards the bottom. Furthermore, Examples 2 and 3, using O₃ as the reactant (etching ratios of 2% and 1%, respectively), exhibited higher upper selectivity compared to Example 1 (56%), which used H₂O₂, indicating that the type of reactant affects the upper selectivity of the ALE process.

[0101] Summarize Figures 7 to 9 As a result, the TiN / SiCN etching selectivity confirmed at the blank film level through the ALE process can be effectively achieved in practical high aspect ratio hole pattern structures.

[0102] Figures 7 to 9 This was further extended to extreme aspect ratio conditions of 1:30 (Example 1) and 1:50 (Examples 2 and 3), and verified by diversifying the etchant combination to 1-chloromethylethyl ether (Examples 1 and 2) and dimethylformamide-dimethyl acetal (Example 3). In all three examples, the upper TiN film thickness decreased after the ALE process, the opening expanded, and the step coverage improved. In particular, the lower TiN thickness remained at a similar level to the reference, confirming that primarily upper-selective etching occurred. This is attributed to the inherent behavior of the ALE process, where the reactants and etchants are over-adsorbed at the top and the concentration decreases towards the bottom, indicating that this concentration gradient effect becomes more pronounced with increasing aspect ratio.

[0103] The results above demonstrate that the ALE process proposed in this invention can adjust the degree of upper selectivity according to the combination of reactants and etchants, and can stably achieve the effects of expanding the upper spacing (TCD) of the lower electrode and improving the step coverage even under extremely high aspect ratio conditions in the aspect ratio range of 1:30 to 1:50.

[0104] Conventional plasma-based etching methods suffer from the problem that the upper distance between the lower electrodes (TCD) becomes excessively narrow because ions and free radicals cannot uniformly reach the lower part of the high aspect ratio structure. Optimizing process conditions to overcome this problem presents technical challenges. Specifically, when the TCD between the lower electrodes narrows, thickness variations occur during subsequent dielectric film deposition, leading to a decrease in dielectric constant, increased inter-cell interference and leakage current, directly impacting capacitor reliability.

[0105] In contrast, according to one embodiment of this application, the reactants and etchants used in the ALE process exhibit characteristics of over-adsorption in the upper part of the high aspect ratio structure, with their diffusion and concentration decreasing towards the lower part, similar to precursor behavior. Therefore, in the etching step that extends the upper pitch (TCD) of the lower electrode, the etching amount in the upper region of the lower electrode is greater than the etching amount in the lower region of the lower electrode. Specifically, as... Figures 7 to 9 As shown, based on the thickness reduction achieved by the ALE process in Examples 1 to 3, the etching ratios of the upper region relative to the lower region were approximately 56%, 2%, and 1%, respectively. The experiments confirmed that regardless of the combination of reactants and etchants, etching of the upper region predominates and preferentially occurs over the lower region. Due to this upper-preferred etching behavior, the upper electrode spacing (TCD) is selectively extended to improve profile perpendicularity, and even under extremely high aspect ratio conditions within the 1:30 to 1:50 aspect ratio range, it provides improved uniformity and dielectric constant properties of the subsequent dielectric film deposition.

[0106] Figures 10A to 10C This is a schematic view illustrating a method for manufacturing a capacitor according to another embodiment of the present invention. Only the parts that differ from the foregoing description are described below; omitted descriptions can be replaced by the foregoing description.

[0107] As described above, with the removal of the mold layer, the outer wall of the lower electrode 312 may be partially exposed. The support layers 306S, 308S, and 310S, which are etch-selective for the mold layer, may be retained and not removed. The outer wall of the lower electrode 312 may be supported by the support layers 306S, 308S, and 310S.

[0108] Subsequently, as Figure 10A As shown, an insulating layer 313A can be formed on the lower electrode 312 to improve interface characteristics. Generally, the interface characteristics of the lower electrode surface can affect the uniformity of subsequent dielectric layer deposition and leakage current characteristics. Therefore, by selectively forming the insulating layer 313A on the surface of the lower electrode 312, interface characteristics can be improved and the reliability of dielectric layer 313B deposition can be enhanced. The insulating layer 313A may include niobium oxide (NbO₂). x ), niobium nitride, niobium oxynitride, tantalum oxide (Ta-oxide, TaO)x Yttrium oxide or lanthanum oxide. In this case, the thickness of the insulating layer 313A on the surface of the support layers 306S, 308S, and 310S may be thinner than the thickness on the surface of the lower electrode 312, and may be formed by selective deposition.

[0109] For example, selective deposition of the insulating layer 313A can use a surface passivation material. Specifically, selective deposition of the insulating layer 313A may include the injection and purging of the surface passivation material, the injection and purging of the precursor, the injection and purging of the reactant gas, and the injection and purging of the precursor and the reactant gas may be repeated for 1 to 100 cycles. The surface passivation material may include an organic compound containing hydrogen or a hydrocarbon. The purging gas may include a rare gas such as argon, and the reactant gas may be any one of H2O, O3, H2O2, or O2.

[0110] Subsequently, an etching-back process (e.g., ALE process) can be performed to etch the insulating layer 313A. Since the thickness of the insulating layer 313A on the surface of the support layers 306S, 308S, and 310S may be thinner than the thickness on the surface of the lower electrode 312, the insulating layer 313A may be removed from the surface of the support layers 306S, 308S, and 310S.

[0111] Subsequently, as Figure 10B As shown, a dielectric layer 313B can be formed. The dielectric layer 313B can be formed on the lower electrode 312 and the support layers 306S, 308S, and 310S, and a portion of the dielectric layer 313B may cover the underlying structure. The dielectric layer 313B can include a high-k material with a higher dielectric constant than silicon oxide. High-k materials can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). The dielectric layer 313B can also include combinations or stacked structures thereof. In addition, the dielectric layer 313B may include ZAZ (ZrO2 / Al2O3 / ZrO2) stack, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, ZAZAT (ZrO2 / Al2O3 / ZrO2 / Al2O3 / TiO2) stack, HAH (HfO2 / Al2O3 / HfO2) stack, TZAZ (TiO2 / ZrO2 / Al2O3 / ZrO2) stack, TiO2 / HfO2 / Al2O3 / HfO2 stack, Ta2O5 / ZrO2 / Al2O3 / ZrO2 stack, or Ta2O5 / HfO2 / Al2O3 / HfO2 stack.

[0112] Subsequently, as Figure 10CAs shown, an upper electrode 314 can be formed on the dielectric layer 313B. The upper electrode 314 can fill the space between adjacent lower electrodes 312. The upper electrode 314 can extend to cover the upper portion of the lower electrode 312. The upper electrode 314 can include polysilicon, silicon germanium, metal, metal nitride, metal silicon nitride, conductive metal oxide, metal silicide, noble metal, or a combination thereof. The upper electrode 314 can include at least one of titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), or a combination thereof.

[0113] As described above, the insulating layer 313A uniformly modifies the chemical properties of the surface of the lower electrode 312, thereby stabilizing the nucleation behavior during the subsequent deposition of the dielectric layer 313B. This allows for a conformal dielectric layer, where the dielectric layer 313B is formed to a uniform thickness across the entire surface of the lower electrode 312. Furthermore, since the insulating layer 313A is removed from the surfaces of the support layers 306S, 308S, and 310S through etch-back, the dielectric layer 313B is directly deposited on the surfaces of the support layers and the lower electrode, enabling conformal coverage throughout the entire structure. Therefore, the effective area increases, thereby improving the reliability of the capacitor through an increase in dielectric constant and a reduction in leakage current.

[0114] Figures 11A to 11C This is a schematic view illustrating a method for manufacturing a capacitor according to another embodiment of the present invention. Only the parts that differ from the foregoing description are described below; omitted descriptions can be replaced by the foregoing description.

[0115] like Figure 11A As shown, with the removal of the mold layer, the outer wall of the lower electrode 412 may be partially exposed. The support layers 406S, 408S, and 410S, which have etching selectivity for the mold layer, may be retained and not removed. The outer wall of the lower electrode 412 may be supported by the support layers 406S, 408S, and 410S.

[0116] Subsequently, the lower electrode 412 can be etched to improve its profile. The etching of the lower electrode 412 can be performed by ALE (atomic layer etching). At this time, the support layers 406S, 408S, and 410S, which have etch selectivity for the lower electrode 412, may not be damaged.

[0117] Meanwhile, as mentioned above Figure 3As mentioned, the etching of the lower electrode 412 can be performed by sequentially supplying an etchant and a reactant. The etchant and reactant are over-adsorbed at the top, and their diffusion and concentration decrease towards the bottom, similar to the behavior of precursors. Therefore, compared to conventional processes, the upper pitch (TCD) of the lower electrode 412 can be expanded. By repeating the process of sequentially supplying the etchant and reactant an appropriate number of cycles, a lower electrode 412 with a tapered shape can be formed, wherein the upper pitch (TCD) is greater than the lower pitch (BCD).

[0118] Subsequently, as Figure 11B As shown, a dielectric layer 413 can be formed. The dielectric layer 413 can be formed on the lower electrode 412 and the support layers 406S, 408S, and 410S, and a portion of the dielectric layer 413 may cover the underlying structure. The dielectric layer 413 can include a high-k material with a higher dielectric constant than silicon oxide. High-k materials can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). The dielectric layer 413 can also include combinations or stacked structures thereof. In addition, the dielectric layer 413 may include ZAZ (ZrO2 / Al2O3 / ZrO2) stack, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, ZAZAT (ZrO2 / Al2O3 / ZrO2 / Al2O3 / TiO2) stack, HAH (HfO2 / Al2O3 / HfO2) stack, TZAZ (TiO2 / ZrO2 / Al2O3 / ZrO2) stack, TiO2 / HfO2 / Al2O3 / HfO2 stack, Ta2O5 / ZrO2 / Al2O3 / ZrO2 stack, or Ta2O5 / HfO2 / Al2O3 / HfO2 stack.

[0119] Subsequently, as Figure 11C As shown, an upper electrode 414 can be formed on the dielectric layer 413. The upper electrode 414 can fill the space between adjacent lower electrodes 412. The upper electrode 414 can extend to cover the upper portion of the lower electrode 412. The upper electrode 414 can include polysilicon, silicon germanium, metal, metal nitride, metal silicon nitride, conductive metal oxide, metal silicide, noble metal, or a combination thereof. The upper electrode 414 can include at least one of titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), or a combination thereof.

[0120] As explained above, a conformal dielectric layer can be formed, increasing the effective area and thus the dielectric constant. Even if the dielectric layer 413 is excessively adsorbed on the upper part of the lower electrode 412 and the step coverage becomes 100% or less, in the final state of forming the upper electrode 414, the upper / middle / lower units can be formed relatively uniformly, thereby improving the reliability of the capacitor.

[0121] Although the present invention has been described in detail above with reference to the embodiments described above, other embodiments are also possible. Therefore, the technical concept and scope of the following claims are not limited to these embodiments.

Claims

1. A method for manufacturing a capacitor, comprising: Multiple lower electrodes and a support layer supporting the lower electrodes are formed on the substrate; The lower electrode is etched to extend the upper spacing (TCD) of the lower electrode; A dielectric layer is formed on the lower electrode and the support layer; and an upper electrode is formed on the dielectric layer, wherein, in the step of expanding the upper spacing of the lower electrode, the etching amount of the upper region of the lower electrode is greater than the etching amount of the lower region of the lower electrode.

2. The capacitor manufacturing method according to claim 1, wherein the step of etching the lower electrode is an ALE (Atomic Layer Etching) process, comprising: The reactant is supplied into the cavity where the substrate is placed; Purge the interior of the chamber; The etchant is supplied to the interior of the chamber; And to purge the interior of the chamber.

3. The capacitor manufacturing method according to claim 2, wherein the reactant and the etchant are adsorbed relatively more extensively in the upper region of the lower electrode, and adsorbed relatively less towards the lower region as the concentration decreases.

4. The capacitor manufacturing method according to claim 2, wherein the reactant can be any one of O2, O3, H2O and H2O2 alone, or a mixture of at least two of O2, O3, H2O and H2O2.

5. The capacitor manufacturing method according to claim 2, wherein the etchant may be at least one of dimethylformamide-dimethyl acetal and 1-chloromethyl ethyl ether.

6. The capacitor manufacturing method according to claim 1, wherein in the step of etching the lower electrode, the support layer may have etching selectivity for the lower electrode.

7. The capacitor manufacturing method according to claim 1, wherein the step of etching the lower electrode can increase the aspect ratio of the lower electrode.

8. The capacitor manufacturing method according to claim 1, the method may further include, between the step of expanding the upper spacing of the lower electrode and the step of forming the dielectric layer: forming an insulating layer on the lower electrode and the support layer; and etching the insulating layer from the surface of the support layer.

9. The capacitor manufacturing method according to claim 8, wherein in the step of etching the insulating layer, the insulating layer can be selectively removed from the surface of the support layer.

10. The capacitor manufacturing method according to claim 1, wherein the lower electrode may have a high aspect ratio of 1:10 or greater.

11. The capacitor manufacturing method according to claim 1, wherein the lower electrode may comprise a metal, a metal nitride, a metal silicon nitride, a conductive metal oxide, a metal silicide, a noble metal, or a combination thereof.

12. The capacitor manufacturing method according to claim 1, wherein the support layer may comprise silicon nitride (Si3N4), silicon carbonitride (SiCN), silicon boron nitride, or a combination thereof.

13. The capacitor manufacturing method according to claim 1, wherein the dielectric layer may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanate (SrTiO3), or combinations thereof or stacked structures.

14. The capacitor manufacturing method according to claim 8, wherein the insulating layer may comprise niobium oxide, niobium nitride, niobium oxynitride, tantalum oxide, yttrium oxide, or lanthanum oxide or a combination thereof.

15. The capacitor manufacturing method according to claim 1, wherein after the step of expanding the upper spacing of the lower electrode, the lower electrode may have a tapered shape, wherein the upper spacing (TCD) of the lower electrode is greater than the lower spacing (BCD) of the lower electrode.

16. A method for manufacturing a storage device, comprising the capacitor manufacturing method of claim 1.

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