A GaN Schottky diode and a preparation method thereof

Abstract

The application belongs to the technical field of semiconductors, and discloses a GaN Schottky diode and a preparation method thereof. The preparation method comprises the following steps: sequentially epitaxially forming an AlN nucleation layer, a GaN buffer layer, a heavily doped GaN transport layer, an AlGaN insertion layer and a lightly doped GaN drift layer on a substrate arrangement surface; selectively etching the lightly doped GaN drift layer to form a nano-pillar structure, sequentially depositing an AlN layer and a Ga2O3 layer on the nano-pillar and the lightly doped GaN drift layer to form a composite dielectric layer; etching to form a cathode groove; etching to expose the top end of the nano-pillar, depositing an ohmic contact metal layer on the bottom of the groove and the top of the nano-pillar, and finally depositing a Schottky contact metal layer on the surface of the composite dielectric layer on the sidewall of the nano-pillar to obtain the GaN Schottky diode. The application effectively balances two key indicators of the GaN Schottky diode, namely forward conduction and reverse blocking, reduces the conduction loss, significantly suppresses the reverse leakage current, and improves the breakdown voltage.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and specifically relates to a GaN Schottky diode and its fabrication method. Background Technology

[0002] GaN Schottky diodes, leveraging the excellent electrical properties of wide-bandgap semiconductors, are widely used in power electronics applications such as new energy power distribution, high-power fast charging, and industrial power rectification, making them an important research and development category in the current power semiconductor device field. Currently, many GaN Schottky diodes manufactured in the industry incorporate columnar structures in the drift layer region to optimize the internal electric field distribution. These columnar structures are typically fabricated using dry etching processes. The high-energy ion bombardment during etching can easily damage the semiconductor sidewall lattice, generating numerous interface defects. These defects can form hidden leakage channels within the device, ultimately leading to high reverse leakage current. When the device withstands high reverse voltage, leakage current runaway can occur, and in severe cases, partial short-circuit failure may result. To mitigate the defects caused by etching, most existing solutions use a single-layer dielectric material to passivate the semiconductor surface. However, the lattice compatibility between a single-layer dielectric and the damaged semiconductor surface is poor, failing to adequately seal various interface defects. This makes it difficult to effectively improve the reverse breakdown voltage while simultaneously reducing the device's forward turn-on voltage, making it challenging to simultaneously optimize the device's forward conduction performance and reverse withstand voltage performance. In addition, conventional Schottky diodes lack an internal conductive structure that can uniformly distribute lateral current. This leads to localized carrier accumulation in the active region, causing current congestion, increasing on-resistance and operating temperature, and resulting in poor stability under continuous high-current operation. The anode contact configuration of existing devices also has design limitations, failing to simultaneously meet the requirements of low-resistance conduction and high-voltage isolation, further amplifying performance defects. Furthermore, the poor consistency of existing fabrication processes makes mass production difficult, and ensuring consistent device parameters after batch fabrication is challenging. The devices also exhibit weak reliability under high-temperature operating conditions, hindering the large-scale adoption of GaN Schottky diodes in high-voltage, high-power applications. Summary of the Invention

[0003] This application aims to improve at least one technical problem in the background art.

[0004] The first aspect of this application provides a method for fabricating a GaN Schottky diode, comprising the following steps: Obtain a substrate, with one side of the substrate serving as the arrangement surface; An AlN nucleation layer, a GaN buffer layer, a heavily doped GaN transport layer, an AlGaN insertion layer, and a lightly doped GaN drift layer are sequentially epitaxially grown on the arrangement surface. Etching removes a portion of the lightly doped GaN drift layer, forming multiple nanopillars; An AlN layer and a Ga2O3 layer are sequentially deposited on the top and sidewalls of the nanopillar and on the surface of the lightly doped GaN drift layer, and the AlN layer and the Ga2O3 layer constitute a composite dielectric layer; Etching removes a portion of the composite dielectric layer, lightly doped GaN drift layer, and AlGaN insertion layer to form trenches; Etching removes the composite dielectric layer covering the top of the nanopillars; A first ohmic contact metal layer is deposited at the bottom of the trench; A second ohmic contact metal layer is deposited on top of the nanopillar; A Schottky contact metal layer is deposited to form a composite dielectric layer covering the sidewalls of the nanopillars, thereby obtaining the GaN Schottky diode.

[0005] In some embodiments, the thickness of the AlGaN insertion layer is 10nm-20nm.

[0006] In some embodiments, the doping concentration of the heavily doped GaN transport layer is 1 × 10⁻⁶. 18 cm -3 -1×10 19 cm -3 The doping concentration of the lightly doped GaN drift layer is 1×10⁻⁶. 16 cm -3 -1×10 17 cm -3 .

[0007] In some embodiments, after forming multiple nanopillars, the nanopillars are immersed in a tetramethylammonium hydroxide solution at 75°C-90°C for 60-120 minutes.

[0008] In some embodiments, the thickness of the AlN layer is 2nm-4nm, and the thickness of the Ga2O3 layer is 3nm-5nm.

[0009] In some embodiments, both the first ohmic contact metal layer and the second ohmic contact metal layer are Ti / Al / Ni / Au.

[0010] In some embodiments, after the first ohmic contact metal layer and the second ohmic contact metal layer are deposited, a first thermal annealing treatment is performed at a temperature of 750°C-800°C for 20s-60s.

[0011] In some embodiments, the Schottky contact metal layer is Ni / Au.

[0012] In some embodiments, after the Schottky contact metal layer is deposited, a second thermal annealing treatment is performed at a temperature of 280°C-320°C for 3 min-10 min.

[0013] The second aspect of this application discloses a GaN Schottky diode, which is prepared by the above-described preparation method.

[0014] The beneficial effects of this application are as follows: Through the synergistic optimization of the overall structure and fabrication process, this application improves the comprehensive electrical performance of GaN Schottky diodes from multiple dimensions, including the core conductive architecture, surface defect control, and anode contact design. It effectively balances the two key indicators of forward conduction and reverse blocking of the GaN Schottky diode, reducing conduction losses and significantly suppressing reverse leakage current and improving breakdown voltage. At the same time, the internal current distribution of the GaN Schottky diode is more uniform, alleviating the heat generation problem under high current conditions, greatly improving the working stability under high temperature environments, and broadening the application scenarios of the GaN Schottky diode in various high-power power conversion equipment. Attached Figure Description

[0015] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 A schematic diagram of the structure of a GaN Schottky diode according to one embodiment; Figure 2 for Figure 1 Enlarged view of point A in the middle. Detailed Implementation

[0016] The present application will be further described below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the application. Furthermore, it should be understood that after reading the contents of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope defined by the appended claims.

[0017] This application provides a method for fabricating a GaN Schottky diode, comprising the following steps: Obtain a substrate, with one side of the substrate serving as the arrangement surface; An AlN nucleation layer, a GaN buffer layer, a heavily doped GaN transport layer, an AlGaN insertion layer, and a lightly doped GaN drift layer are sequentially epitaxially grown on the arrangement surface. Etching removes a portion of the lightly doped GaN drift layer, forming multiple nanopillars; An AlN layer and a Ga2O3 layer are sequentially deposited on the top and sidewalls of the nanopillar and on the surface of the lightly doped GaN drift layer, and the AlN layer and the Ga2O3 layer constitute a composite dielectric layer; Etching removes a portion of the composite dielectric layer, lightly doped GaN drift layer, and AlGaN insertion layer to form trenches; Etching removes the composite dielectric layer covering the top of the nanopillars; A first ohmic contact metal layer is deposited at the bottom of the trench; A second ohmic contact metal layer is deposited on top of the nanopillar; A Schottky contact metal layer is deposited to form a composite dielectric layer covering the sidewalls of the nanopillars, thus obtaining the GaN Schottky diode (e.g., Figures 1-2 As shown in the attached figure: 100 - substrate; 210 - AlN nucleation layer; 220 - GaN buffer layer; 230 - heavily doped GaN transport layer; 240 - AlGaN insertion layer; 250 - lightly doped GaN drift layer; 300 - nanopillar; 410 - AlN layer; 420 - Ga2O3 layer; 500 - trench; 600 - first ohmic contact metal layer; 700 - second ohmic contact metal layer; 800 - Schottky contact metal layer.

[0018] The fabrication method of this GaN Schottky diode first involves epitaxially growing an AlN nucleation layer, a GaN buffer layer, a heavily doped GaN transport layer, an AlGaN insertion layer, and a lightly doped GaN drift layer sequentially from bottom to top on a substrate. These multiple epitaxial films are tightly stacked to form the semiconductor substrate of the device. The AlGaN insertion layer, sandwiched between the heavily doped GaN transport layer and the lightly doped GaN drift layer, utilizes the polarization effect of the heterojunction to generate a two-dimensional electron gas conductive path at the interface of the two semiconductor layers. This improves the lateral current diffusion effect at the device structure level and alleviates the problem of high conduction loss caused by local current accumulation. After the epitaxial substrate is fabricated, the lightly doped GaN drift layer on the surface is selectively etched. By removing part of the lightly doped GaN drift layer, multiple nanopillars are formed on the AlGaN insertion layer (i.e., the lightly doped GaN drift layer at the nanopillar positions is retained, while the lightly doped GaN drift layer around the nanopillars is removed). These multiple nanopillars form a nanopillar array, and the internal electric field arrangement of the device is optimized through this nanopillar array structure. Then, AlN and Ga2O3 layers are deposited sequentially on the top, sidewalls, and surface of the remaining lightly doped GaN drift layer that has not been etched away from the nanopillars. The AlN and Ga2O3 layers stack together to form a composite dielectric layer structure. This composite dielectric layer can passivate surface defects generated after semiconductor etching, block interface defect channels that are prone to leakage, and suppress leakage current in the reverse operating state of the device through the inherent barrier characteristics of the two dielectric materials. After the composite dielectric layer is constructed, an etching operation is performed again. Generally, the edge region of the device is selected as the cathode region, and the composite dielectric layer (Ga2O3 layer and AlN layer), lightly doped GaN drift layer, and AlGaN insertion layer are etched down layer by layer until the heavily doped GaN transport layer is exposed, thereby forming a trench structure that can accommodate the cathode electrode. Then, the top of each nanopillar is etched to remove only the composite dielectric layer covering the top of the nanopillar, exposing the semiconductor substrate (lightly doped GaN drift layer) at the top of the nanopillar. Subsequently, a first ohmic contact metal layer is deposited on the exposed heavily doped GaN layer at the bottom of the trench. This metal layer constitutes the cathode electrode of the device. A second ohmic contact metal layer is then deposited on the top of the nanopillar, serving as the ohmic conduction section of the anode structure. Finally, a Schottky contact metal layer is deposited on the sidewall of the nanopillar, covering the composite dielectric layer on the sidewall. The Schottky contact metal layer on the sidewall of the nanopillar forms a Schottky barrier structure with the sidewall through the composite dielectric, and together with the second ohmic contact metal layer at the top of the pillar, forms the composite anode.

[0019] The GaN Schottky diodes fabricated using the above method achieve comprehensive performance improvement through the synergy of various functional layers and the three-dimensional structure. The two-dimensional electron gas formed by the AlGaN insertion layer arranged between the two GaN layers can broaden the current transmission path, improve the current distribution state inside the device, and reduce conduction losses from the root. The nanopillar array plays a regulating role in the internal electric field of the device, enabling full depletion when a reverse voltage is applied, effectively avoiding problems such as leakage and short circuit. The bilayer composite dielectric can repair surface lattice defects caused by the etching process, and continuously control the reverse leakage current by relying on the potential barrier advantage of the bilayer dielectric. The composite anode, composed of the second ohmic contact metal and the Schottky contact metal, breaks through the performance limitations of the single electrode structure, optimizing forward conduction characteristics, reducing the turn-on voltage, and improving the reverse voltage resistance of the device. The overall fabrication process uses industry-standard epitaxial, etching, and metal deposition processes, with excellent process compatibility, facilitating industrial mass production.

[0020] In this specific embodiment, a 2-inch C-side (0001) sapphire was selected as the substrate. The substrate was ultrasonically cleaned for 10 minutes each with acetone, anhydrous ethanol, and deionized water to remove organic contaminants and particulate impurities from the substrate surface. Subsequently, the substrate was boiled with dilute hydrochloric acid solution for 5 minutes to remove the natural oxide layer on the surface. After being dried with high-purity nitrogen, it was finally heated to 1050°C and baked at a constant temperature for 10 minutes in a hydrogen atmosphere to further remove residual impurities and water molecules from the substrate surface, obtaining a clean, low-defect substrate surface (arrangement plane), providing a stable foundation for subsequent high-quality epitaxial growth.

[0021] In this specific embodiment, MOCVD (Metal-Organic Chemical Vapor Deposition) process is used. The substrate is placed in the reaction chamber of the MOCVD equipment, and an AlN nucleation layer, a GaN buffer layer, a heavily doped GaN transport layer, an AlGaN insertion layer, and a lightly doped GaN drift layer are epitaxially grown sequentially on the substrate surface. The substrate is not removed midway and is not exposed to air throughout the process.

[0022] In this specific embodiment, the epitaxial growth of the AlN nucleation layer uses trimethylaluminum (flow rate of 100 mL / min) and ammonia (flow rate of 10 L / min) as reaction sources, hydrogen / nitrogen (volume ratio of 1:3) as carrier gas, growth pressure of 50 Torr, growth temperature of 1100℃, and AlN nucleation layer thickness of 20 nm.

[0023] In this specific embodiment, the epitaxial growth of the GaN buffer layer uses trimethylgallium (flow rate of 100 mL / min) and ammonia (flow rate of 10 L / min) as reaction sources, hydrogen / nitrogen (volume ratio of 1:3) as carrier gas, growth pressure of 50 Torr, growth temperature of 1100℃, and GaN buffer layer thickness of 1 μm.

[0024] In this specific embodiment, the epitaxial growth of the heavily doped GaN transport layer uses trimethylgallium (flow rate 100 mL / min) and ammonia (flow rate 10 L / min) as the reaction source, hydrogen / nitrogen (volume ratio 1:3) as the carrier gas, and silane as the N-type silicon doping source with a doping concentration of 1 × 10⁻⁶. 18 cm -3 The growth pressure was 50 Torr, the growth temperature was 1100℃, and the thickness of the heavily doped GaN transport layer was 2 μm.

[0025] In other embodiments, the doping concentration of the heavily doped GaN transport layer can also be 2 × 10⁻⁶. 18 cm -3 3×10 18 cm -3 5×10 18 cm -3 8×10 18 cm -3 and 1×10 18 cm -3 -1×10 19 cm -3 Any point value within the range.

[0026] In this specific embodiment, the epitaxial growth of the AlGaN intercalation layer uses trimethylgallium (flow rate of 100 mL / min), trimethylaluminum (flow rate of 100 mL / min) and ammonia (flow rate of 10 L / min) as reaction sources, hydrogen / nitrogen (volume ratio of 1:3) as carrier gas, growth pressure of 50 Torr, growth temperature of 1100 °C, aluminum composition of the AlGaN intercalation layer of 0.2, and thickness of the AlGaN intercalation layer of 15 nm.

[0027] In other implementations, the thickness of the AlGaN insertion layer can also be any value within the range of 11nm, 12nm, 14nm, 16nm, 18nm, and 10nm-20nm.

[0028] In this specific embodiment, the epitaxial growth of the lightly doped GaN drift layer uses trimethylgallium (flow rate 100 mL / min) and ammonia (flow rate 10 L / min) as the reaction source, hydrogen / nitrogen (volume ratio 1:3) as the carrier gas, and silane as the N-type silicon doping source with a doping concentration of 1 × 10⁻⁶. 16 cm -3 The growth pressure was 50 Torr, the growth temperature was 1100℃, and the thickness of the lightly doped GaN drift layer was 5 μm.

[0029] In other embodiments, the doping concentration of the lightly doped GaN drift layer can also be 2 × 10⁻⁶. 16 cm-3 3×10 16 cm -3 5×10 16 cm -3 8×10 16 cm -3 and 1×10 16 cm -3 -1×10 17 cm -3 Any point value within the range.

[0030] In some embodiments, the etching process removes a portion of the lightly doped GaN drift layer to form multiple nanopillars, comprising the following steps: defining a nanopillar array pattern on the surface of the lightly doped GaN drift layer using ultraviolet lithography; and using an inductively coupled plasma etching (ICP-C) system with a Cl2 / Ar / BCl3 mixed gas as the etching source. The etching parameters are as follows: ICP-C source RF power of 300W-500W, bias power of 50W-100W, cavity gas pressure of 5mTorr-10mTorr, flow rates of Cl2, Ar, and BCl3 of 20mL / min, 30mL / min, and 10mL / min, respectively, and etching time of 150s to 200s. Under these parameters, a vertically regular nanopillar structure with low roughness and shallow etching damage can be obtained.

[0031] In this specific embodiment, the etching parameters are as follows: the inductively coupled plasma source RF power is 300W, the bias power is 50W, the cavity gas pressure is 5mTorr, the flow rates of Cl2, Ar and BCl3 are 20mL / min, 30mL / min and 10mL / min respectively, and the etching time is 150s.

[0032] In this specific embodiment, the nanopillars have a diameter of 150 nm, a height of 0.8 μm, and a center-to-center distance of 1 μm between two adjacent nanopillars.

[0033] In some embodiments, after forming multiple nanopillars, the nanopillars are immersed in a tetramethylammonium hydroxide solution at 75°C-90°C for 60-120 minutes. It is understood that the immersion treatment can also be performed at 76°C, 78°C, 80°C, 82°C (and any value within the range of 75°C-90°C); and the immersion time can also be any value within the range of 65-120 minutes. When nanopillars are formed by plasma dry etching, high-energy ion bombardment can easily induce surface defects such as lattice distortion and a large number of suspended chemical bonds on the sidewalls of the nanopillars. These defects can form hidden leakage paths inside the device, exacerbating the reverse leakage current problem. Immersion in tetramethylammonium hydroxide can repair the damaged surface of the nanopillars through chemical etching, remove the defective areas introduced by etching, smooth the sidewall surface, and effectively reduce the number of interface states. At the same time, the etching solution has an extremely low etching rate on the underlying AlGaN insertion layer. The process does not damage the AlGaN insertion layer structure or the two-dimensional electron gas conductive channels generated at the heterogeneous interface. Without changing the original epitaxial structure, the semiconductor surface state is optimized, which facilitates the subsequent close adhesion of the composite dielectric layer to the nanopillar surface, further enhancing the dielectric passivation effect and improving the defect of high leakage current in the device.

[0034] In this specific embodiment, the nanopillars were immersed in a 25% (v / v) tetramethylammonium hydroxide solution for 80 min at 80°C.

[0035] In some implementations, the AlN and Ga2O3 layers are formed using atomic layer deposition (ALD) with the following process parameters: deposition temperature of 350°C, working pressure of the chamber of 0.1 Torr-1 Torr, pulse period of 0.5s to 1s, and precursor purging time of 1s to 2s; to ensure that the AlN and Ga2O3 layers are uniform and dense with excellent step coverage.

[0036] In this specific embodiment, the above parameters are: deposition temperature of 350°C, working gas pressure in the cavity of 0.1 Torr, pulse period of 0.5s, and precursor purging time of 1s.

[0037] In some embodiments, the thickness of the AlN layer is 2nm-4nm, and the thickness of the Ga2O3 layer is 3nm-5nm. It is understood that the thickness of the AlN layer can also be any value within the range of 2.2nm, 2.5nm, 3nm, 3.5nm, and 2nm-4nm; the thickness of the Ga2O3 layer can also be any value within the range of 3.2nm, 3.5nm, 4nm, 4.5nm, and 3nm-5nm.

[0038] In this specific embodiment, the AlN layer has a thickness of 3 nm, and the Ga2O3 layer has a thickness of 4 nm. The stacking order of AlN as the lower layer and Ga2O3 as the upper layer has sufficient structural rationality. AlN and GaN have a higher lattice matching degree, and can be directly attached to the semiconductor surface to achieve defect passivation, stress matching, and dislocation leakage path blocking, thus making it suitable as the bottom interface layer. Ga2O3 has a higher barrier height and stronger gate dielectric breakdown characteristics. Placing it on the upper layer can further enhance the Schottky interface barrier and more effectively suppress reverse leakage. The combination of the two can simultaneously achieve interface repair and leakage suppression. The total thickness is controlled at 7nm, with the bottom AlN layer being 3nm thick and the top Ga2O3 layer being 4nm thick. This layering and total thickness have been optimized. The 3nm AlN layer can achieve sufficient interface defect repair without forming an excessively high tunneling barrier. The 4nm Ga2O3 layer can significantly improve the reverse blocking capability without being too thick to hinder electron transport. The total thickness of 7nm can achieve the optimal balance between tunneling efficiency and breakdown voltage capability, which can achieve strong interface passivation and significantly reduce leakage current without hindering forward electron tunneling, ensuring that the device maintains a low turn-on voltage and low on-resistance, so that the device has excellent forward conduction characteristics and reverse breakdown voltage characteristics.

[0039] In some embodiments, the etching process removes a portion of the composite dielectric layer, the lightly doped GaN drift layer, and the AlGaN insertion layer to form a trench. This includes the following steps: defining a cathode trench region on the surface of the composite dielectric layer using ultraviolet lithography; and etching using an inductively coupled plasma etching (ICP-C) system with Cl2 (flow rate 40 mL / min) and BCl3 (flow rate 25 mL / min) as etching sources until the heavily doped GaN transport layer is exposed (the bottom of the trench is the surface of the corresponding heavily doped GaN transport layer). The etching parameters are: ICP-C source RF power of 20 W-50 W and cavity gas pressure of 10 mTorr-15 mTorr.

[0040] In this specific embodiment, the above parameters are: the radio frequency power of the inductively coupled plasma source is 20W, and the cavity gas pressure is 10mTorr.

[0041] In some embodiments, the etching removes a portion of the composite dielectric layer, the lightly doped GaN drift layer, and the AlGaN insertion layer to form trenches. The etching endpoint can be jointly determined using optical emission spectroscopy combined with laser interferometry endpoint detection. Optical emission spectroscopy involves real-time acquisition and analysis of the emission signal of the etching plasma, monitoring the intensity of emission spectral lines at characteristic wavelengths such as Ga, N, and Al. When the upper material is completely etched and the intensity of the characteristic spectral lines changes abruptly, the interface change can be identified. Simultaneously, laser interferometry is used to monitor the periodic oscillations of the intensity of reflected light on the sample surface. When the amplitude of the reflected light oscillations decreases sharply and tends to stabilize, it is confirmed that the etching has reached the surface of the heavily doped GaN transport layer. The dual detection mechanism verifies each other, which can control the etching endpoint error within the nanometer range. On this basis, combined with the ultra-low power over-etching process, the over-etching amount is strictly controlled within 10 nm. This ensures complete removal of the material above and full exposure of the surface of the heavily doped GaN transport layer, while effectively avoiding sputtering damage and impurity contamination to the heavily doped GaN transport layer caused by over-etching. This ensures that the subsequent cathode ohmic electrode can form a stable, uniform, and low-resistance ohmic contact, improving the device's current spread capability and conductivity uniformity.

[0042] In some embodiments, the etching removal of the composite dielectric layer covering the top of the nanopillars includes the following steps: defining an etching region on the top of the nanopillars using ultraviolet lithography; and using an inductively coupled plasma etching (ICP-C) system with CF4 (flow rate 15 mL / min) and O2 (flow rate 5 mL / min) as etching sources. The etching parameters are: ICP-C source RF power of 50 W-80 W, chamber pressure of 10 mTorr-15 mTorr, and etching time of 30 s-45 s. During etching, the ion bombardment direction is perpendicular to the top of the nanopillars, effectively etching only the composite dielectric layer exposed vertically on the top of the nanopillars. This process also provides high selectivity for the photoresist, removing only the unprotected composite dielectric layer on the top of the nanopillars. The sidewalls covered by photoresist and the inter-nanopillar regions remain unaffected by ion etching, and their composite dielectric layers remain intact. After etching, the surface of the lightly doped GaN drift layer at the top of the nanopillar is fully exposed, while avoiding etching damage to the nanopillar structure, thus providing a clean and effective contact area for the subsequent fabrication of the ohmic electrode at the top of the nanopillar.

[0043] In this specific embodiment, the above parameters are: the radio frequency power of the inductively coupled plasma source is 50W, the cavity gas pressure is 10mTorr, and the etching time is 30s.

[0044] In this specific embodiment, both the first ohmic contact metal layer and the second ohmic contact metal layer are Ti / Al / Ni / Au. Both the first and second ohmic contact metal layers are deposited using an electron beam evaporation process, with thicknesses of Ti 20nm, Al 150nm, Ni 50nm, and Au 50nm, respectively.

[0045] In some embodiments, after the first ohmic contact metal layer and the second ohmic contact metal layer are deposited, a first thermal annealing treatment is performed at a temperature of 750°C-800°C for 20-60 seconds. It is understood that the temperature of the first thermal annealing treatment can also be any value within the range of 760°C, 770°C, 780°C, 790°C, and 750°C-800°C; the time of the first thermal annealing treatment can also be any value within the range of 25 seconds, 30 seconds, 40 seconds, 50 seconds, and 20-60 seconds. This high-temperature short-time annealing can promote the alloying reaction at the interface between the ohmic contact metal layer and the GaN semiconductor nanopillar, effectively reducing the contact resistance between the metal and the semiconductor and consolidating the ohmic conductivity. At the same time, the short holding time can constrain the longitudinal diffusion depth of metal atoms, and the interface reaction only occurs in the near-surface layer of the metal and semiconductor. The metal components cannot penetrate downwards into the epitaxial structure such as the lightly doped GaN layer and AlGaN insertion layer, and will not destroy the two-dimensional electron gas conductive channel formed by the AlGaN insertion layer. While optimizing the ohmic contact characteristics, the original electrical structure of the epitaxial layer is completely preserved.

[0046] In this specific embodiment, after the first ohmic contact metal layer and the second ohmic contact metal layer are deposited, a first thermal annealing treatment is performed at a temperature of 780°C for 30 seconds.

[0047] In this specific embodiment, the Schottky contact metal layer is Ni / Au. The Schottky contact metal layer is deposited using an electron beam evaporation process, and the thicknesses of each layer are 50 nm for Ni and 200 nm for Au.

[0048] In some embodiments, after the Schottky contact metal layer is deposited, a second thermal annealing treatment is performed at a temperature of 280°C-320°C for 3-10 minutes. It is understood that the temperature of the second thermal annealing treatment can also be any value within the range of 290°C, 300°C, 310°C, and 280°C-320°C; the time of the second thermal annealing treatment can also be any value within the range of 4 minutes, 5 minutes, 6 minutes, 8 minutes, and 3 minutes-10 minutes. Low-temperature annealing can correct interface defects between the Schottky contact metal layer and the composite dielectric layer, reduce the density of dangling bonds at the interface, and make the Schottky barrier distribution more uniform, thereby achieving further control of the reverse leakage current of the device. Using a low-temperature process can prevent the diffusion of Schottky metal atoms into the composite dielectric layer under high-temperature conditions, avoiding damage to the passivation structure and insulation properties of the composite dielectric layer, ensuring the leakage current suppression effect of the composite dielectric layer on the sidewalls of the nanopillars, and achieving the matching performance of low forward conduction loss and high reverse withstand voltage of the composite anode.

[0049] In this specific embodiment, after the Schottky contact metal layer is deposited, a second thermal annealing treatment is performed at a temperature of 300°C for 5 minutes.

[0050] In some implementations, the Schottky metal layer is further patterned using photolithography to form a self-aligned field plate structure. The field plate modulates the electric field at the junction edge, alleviating the electric field concentration effect under high reverse voltage, suppressing premature breakdown at the device edge, and significantly improving the device breakdown voltage and operational stability.

[0051] In some embodiments, a 200 nm thick silicon nitride passivation layer is further deposited on the entire surface of the GaN Schottky diode using plasma-enhanced chemical vapor deposition (PECVD) to achieve comprehensive protection and insulation of the GaN Schottky diode. Electron lead-out windows are opened at the corresponding positions of the passivation layer using photolithography and etching processes. Electron beam evaporation is used to thicken the electrode metal to improve conductivity and bonding reliability. Finally, the entire fabrication process of the GaN Schottky diode is completed through dicing, cleaving, appearance inspection, and electrical testing.

[0052] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature.

[0053] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and additions without departing from the method of this application, and these improvements and additions should also be considered within the scope of protection of this application.

Claims

1. A method for fabricating a GaN Schottky diode, characterized in that, Includes the following steps: Obtain a substrate, with one side of the substrate serving as the arrangement surface; An AlN nucleation layer, a GaN buffer layer, a heavily doped GaN transport layer, an AlGaN insertion layer, and a lightly doped GaN drift layer are sequentially epitaxially grown on the arrangement surface. Etching removes a portion of the lightly doped GaN drift layer, forming multiple nanopillars; An AlN layer and a Ga2O3 layer are sequentially deposited on the top and sidewalls of the nanopillar and on the surface of the lightly doped GaN drift layer, and the AlN layer and the Ga2O3 layer constitute a composite dielectric layer; Etching removes a portion of the composite dielectric layer, lightly doped GaN drift layer, and AlGaN insertion layer to form trenches; Etching removes the composite dielectric layer covering the top of the nanopillars; A first ohmic contact metal layer is deposited at the bottom of the trench; A second ohmic contact metal layer is deposited on top of the nanopillar; A Schottky contact metal layer is deposited to form a composite dielectric layer covering the sidewalls of the nanopillars, thereby obtaining the GaN Schottky diode.

2. The method for fabricating a GaN Schottky diode according to claim 1, characterized in that, The thickness of the AlGaN insertion layer is 10nm-20nm.

3. The method for fabricating a GaN Schottky diode according to claim 1, characterized in that, The doping concentration of the heavily doped GaN transport layer is 1×10⁻⁶. 18 cm -3 -1×10 19 cm -3 The doping concentration of the lightly doped GaN drift layer is 1×10⁻⁶. 16 cm -3 -1×10 17 cm -3 .

4. The method for fabricating a GaN Schottky diode according to claim 1, characterized in that, After forming multiple nanopillars, the nanopillars are immersed in a tetramethylammonium hydroxide solution at 75°C-90°C for 60-120 minutes.

5. The method for fabricating a GaN Schottky diode according to claim 1, characterized in that, The thickness of the AlN layer is 2nm-4nm, and the thickness of the Ga2O3 layer is 3nm-5nm.

6. The method for fabricating a GaN Schottky diode according to claim 1, characterized in that, Both the first ohmic contact metal layer and the second ohmic contact metal layer are Ti / Al / Ni / Au.

7. The method for fabricating a GaN Schottky diode according to claim 1, characterized in that, After the first ohmic contact metal layer and the second ohmic contact metal layer are deposited, a first thermal annealing treatment is performed at a temperature of 750℃-800℃ for 20s-60s.

8. The method for fabricating a GaN Schottky diode according to claim 1, characterized in that, The Schottky contact metal layer is Ni / Au.

9. The method for fabricating a GaN Schottky diode according to claim 1, characterized in that, After the Schottky contact metal layer is deposited, a second thermal annealing treatment is performed at a temperature of 280℃-320℃ for 3min-10min.

10. A GaN Schottky diode, characterized in that, The GaN Schottky diode is prepared by the method according to any one of claims 1-9.

Images