An ultra-low forward voltage drop planar process schottky rectifier diode and method thereof

Abstract

The application relates to the technical field of rectifier diodes, and discloses an ultra-low forward voltage drop planar process Schottky rectifier diode and a method thereof, wherein the method comprises the following steps: epitaxially growing an N-type lightly doped drift layer on an N-type heavily doped silicon substrate to obtain an epitaxial wafer; depositing a field oxide layer on the active region edge of the front surface of the epitaxial wafer and performing photoetching to open a window, so as to form a P-type guard ring on the active region edge; sequentially sputtering and depositing Ti and TiW layers to obtain a Schottky contact layer; sequentially depositing a PECVD silicon nitride passivation layer on the front surface of the Schottky contact layer and performing photoetching to open a contact hole, sputtering and depositing an AlSi interconnection metal layer and performing patterning to form a front surface electrode, and simultaneously performing thinning and depositing an Al / Ti / Ni / Ag metal stack to obtain the rectifier diode. The method improves the performance of the planar Schottky rectifier diode prepared by the application in terms of ultra-low forward voltage drop, low reverse leakage current, high breakdown voltage and high batch consistency.

Description

Technical Field

[0001] This invention relates to the field of rectifier diode technology, and more particularly to an ultra-low forward voltage drop planar Schottky rectifier diode and its method. Background Technology

[0002] Schottky rectifier diodes, with their majority carrier conduction mechanism and low reverse recovery time, are widely used in switching power supplies, frequency converters, and various power electronic devices. Existing planar Schottky rectifier diodes typically use a single metal evaporation deposition method to form the Schottky contact. The barrier height at the metal-silicon interface relies entirely on the inherent work function of the metal material, lacking active control methods. This results in a high forward voltage drop and significant batch-to-batch dispersion of barrier height. Furthermore, without strictly controlled heat treatment after the current metal deposition process, the reaction at the metal-silicon interface is uneven, and the silicide layer thickness and phase distribution are random. This leads to poor intra-wafer uniformity and batch-to-batch consistency of the forward voltage drop, failing to meet the process stability requirements for large-scale mass production. Summary of the Invention

[0003] This invention provides an ultra-low forward voltage drop planar Schottky rectifier diode and its method. This invention effectively suppresses the premature occurrence of edge breakdown and the leakage current deterioration caused by edge hot carrier effect, making the actual breakdown voltage close to the theoretical parallel plate breakdown voltage, improving the reliability of the device in high reverse voltage scenarios, and thus improving the performance of the planar Schottky rectifier diode prepared by this invention in terms of ultra-low forward voltage drop, low reverse leakage current, high breakdown voltage and high batch consistency.

[0004] In a first aspect, the present invention provides a Schottky rectification method for an ultra-low forward voltage drop planar process, the ultra-low forward voltage drop planar process Schottky rectification method comprising: An epitaxial wafer is obtained by epitaxially growing an N-type lightly doped drift layer on an N-type heavily doped silicon substrate. A field oxide layer is deposited at the edge of the active region on the front side of the epitaxial wafer, and a window is created by photolithography. A P-type protective ring is formed at the edge of the active region. A Ti layer and a TiW layer are sequentially sputtered and deposited on the front side of the epitaxial wafer forming the P-type protective ring to obtain a Schottky contact layer. A PECVD silicon nitride passivation layer is sequentially deposited on the front side of the Schottky contact layer, and contact holes are formed by photolithography. An AlSi interconnect metal layer is sputtered and patterned to form the front electrode. At the same time, the back side of the Schottky contact layer is thinned and an Al / Ti / Ni / Ag metal stack is deposited to obtain a rectifier diode.

[0005] In conjunction with the first aspect, in a first implementation of the first aspect of the present invention, the epitaxial growth of an N-type lightly doped drift layer on an N-type heavily doped silicon substrate to obtain an epitaxial wafer includes: Select resistivity ranging from 0.001 Ω·cm to 0.005 Ω·cm, with crystal orientation of... <100> On an N-type heavily doped arsenic silicon substrate, phosphorus is used as a dopant to perform chemical vapor deposition epitaxial growth with a doping concentration of 5 × 10⁻⁶. 14 cm -3 Up to 2×10 15 cm -3 An N-type lightly doped drift layer is used to obtain an epitaxial wafer.

[0006] In conjunction with the first aspect, in a second implementation of the first aspect of the present invention, the step of depositing a field oxide layer at the edge of the active region on the front side of the epitaxial wafer and photolithographically creating a window, and forming a P-type protective ring at the edge of the active region, includes: A field oxide layer is grown on the front side of the epitaxial wafer by thermal oxidation, and a protective ring injection window is defined at the edge of the active region by photolithography. With an injection energy of 80keV to 100keV and an injection dose of 5×10 12 cm -2 Up to 2×10 13 cm -2 Boron ions are injected into the protective ring injection window to obtain the protective ring injection region; The protective ring injection region was annealed for 30 minutes in a nitrogen atmosphere at 950°C to activate boron ions and form a P-type protective ring at the edge of the active region.

[0007] In conjunction with the first aspect, in a third implementation of the first aspect of the present invention, the step of annealing the protective ring injection region in a nitrogen atmosphere at 950°C for 30 minutes to activate boron ions and form a P-type protective ring at the edge of the active region includes: The protective ring injection region was annealed for 30 minutes in a nitrogen atmosphere at 950℃, so that the boron atoms in the protective ring injection region migrated from interstitial sites to substitution sites to complete the electroactivation and repair lattice defects. The sheet resistance of the active region of the guard ring was measured using the four-probe method. When the sheet resistance was within a preset range, the doping uniformity was confirmed to be qualified, resulting in a junction depth of 0.40 μm to 0.60 μm and a peak net doping concentration of 1 × 10⁻⁶. 17 cm -3 Up to 5×10 17 cm -3 The P-type protective ring.

[0008] In conjunction with the first aspect, in a fourth implementation of the first aspect of the present invention, the step of sequentially sputtering and depositing a Ti layer and a TiW layer on the front side of the epitaxial wafer forming the P-type guard ring to obtain a Schottky contact layer includes: The front side of the epitaxial wafer forming the P-type protective ring is sequentially subjected to RCA cleaning and dilute hydrofluoric acid deoxidation treatment. The treated epitaxial wafer is then loaded into a magnetron sputtering cavity to sequentially sputter and deposit a Ti layer and an in-situ sputtering TiW layer to obtain a Ti / TiW double-layer metal stack. The Ti / TiW bilayer metal stack is subjected to rapid thermal annealing, which causes a solid-state reaction between the Ti layer and the silicon interface to generate a continuous and uniform TiSi2 layer, thus obtaining a Schottky contact layer.

[0009] In conjunction with the first aspect, in the fifth implementation of the first aspect of the present invention, the epitaxial wafer forming the P-type guard ring is sequentially subjected to RCA cleaning and dilute hydrofluoric acid deoxidation treatment on its front side, and the treated epitaxial wafer is then placed into a magnetron sputtering cavity to sequentially sputter and deposit a Ti layer and an in-situ sputtering TiW layer to obtain a Ti / TiW bilayer metal stack, comprising: The front side of the epitaxial wafer with the P-type protective ring is sequentially cleaned with RCA solutions SC-1 and SC-2, and then soaked in dilute hydrofluoric acid with a volume ratio of 1:50 to obtain the treated epitaxial wafer. The processed epitaxial wafer was placed into the magnetron sputtering chamber, and high-purity argon gas was introduced to a working pressure of 3 mTorr to 5 mTorr, followed by a sputtering speed of 2 W / cm². 2 Up to 3W / cm 2 A Ti layer with a thickness of 50 nm to 80 nm is deposited by power density sputtering, and a TiW layer with a thickness of 100 nm to 150 nm is deposited by in-situ sputtering with a TiW target without disrupting the vacuum, thus obtaining a Ti / TiW bilayer metal stack.

[0010] In conjunction with the first aspect, in a sixth implementation of the first aspect of the present invention, the rapid thermal annealing of the Ti / TiW bilayer metal stack to induce a solid-state reaction between the Ti layer and the silicon interface to generate a continuous and uniform TiSi2 layer, thereby obtaining a Schottky contact layer, includes: The Ti / TiW bilayer metal stack is heated to 480°C to 520°C and held for 45s to 60s to allow the Ti layer to undergo a solid-state reaction with the silicon interface to generate a continuous and uniform TiSi2 layer with a thickness of 8nm to 12nm, thus obtaining a Ti / TiW / TiSi2 composite contact structure. The Ti / TiW / TiSi2 composite contact structure was cooled to room temperature, allowing the TiSi2 layer to maintain its C49 phase structure, thus obtaining a Schottky contact layer.

[0011] In conjunction with the first aspect, in the seventh implementation of the first aspect of the present invention, the step of sequentially depositing a PECVD silicon nitride passivation layer and photolithographically forming contact holes on the front side of the Schottky contact layer, sputtering and depositing an AlSi interconnect metal layer and patterning it to form a front electrode, while simultaneously thinning and depositing an Al / Ti / Ni / Ag metal stack on the back side of the Schottky contact layer to obtain a rectifier diode, includes: In the Schottky contact layer, a PECVD silicon nitride passivation layer is deposited at a SiH4 to NH3 flow ratio of 1:4 and a gas pressure of 1.5 Torr. Contact holes are opened by photolithography and dry etching with CF4 / O2 mixed gas. Then, an AlSi interconnect metal layer is sputtered and deposited and patterned by photolithography to form the front electrode. After the back side of the Schottky contact layer with the front electrode is thinned to 100μm to 120μm and deoxidized with dilute hydrofluoric acid at a volume ratio of 1:50, an Al / Ti / Ni / Ag metal stack is sputtered to form an ohmic back contact, thus obtaining a rectifier diode.

[0012] In conjunction with the first aspect, in the eighth implementation of the first aspect of the present invention, the step of depositing a PECVD silicon nitride passivation layer on the Schottky contact layer at a SiH4 to NH3 flow ratio of 1:4 and a gas pressure of 1.5 Torr, forming contact holes by photolithography and dry etching with a CF4 / O2 mixed gas, and then sputtering to deposit an AlSi interconnect metal layer and forming a front electrode by photolithography patterning, includes: A PECVD silicon nitride passivation layer was deposited on the front side of the Schottky contact layer at a deposition temperature of 280°C, a radio frequency power of 200W, a SiH4 to NH3 flow ratio of 1:4, and a gas pressure of 1.5 Torr. The PECVD silicon nitride passivation layer was dry etched with a CF4:O2 mixed gas with a volume ratio of 4:1 and 150W radio frequency power to form a contact hole above the active region of the Schottky contact layer, thus obtaining a silicon nitride passivation layer with a contact hole. An AlSi interconnect metal layer with a Si content of 1% by mass and a thickness of 1.5 μm to 2 μm is sputtered and deposited on the silicon nitride passivation layer with contact holes. The front electrode is then formed by photolithography and wet etching to obtain a Schottky contact layer with a front electrode.

[0013] Secondly, the present invention provides an ultra-low forward voltage drop planar Schottky rectifier diode, which is fabricated using the above-mentioned ultra-low forward voltage drop planar Schottky rectification method.

[0014] In the technical solution provided by this invention, Ti, which has a work function highly matched with that of N-type silicon, is selected as the Schottky contact metal. With strict control of the transfer time after removing the natural oxide layer with dilute hydrofluoric acid, Ti is ensured to form direct bonds with silicon. Rapid thermal annealing under a precise temperature window enables the formation of a continuous and uniform TiSi2 layer at the interface, effectively reducing the contact resistivity and stabilizing the barrier height within the target range. This fundamentally solves the problems of high forward voltage drop and poor batch consistency in the prior art. The introduction of the TiW layer as a diffusion barrier layer further protects the chemical stability of the Schottky contact interface in subsequent processes and prevents the interconnect metal from diffusing to the interface and damaging the barrier structure. The P-type guard ring formed by boron ion implantation disperses the electric field spike at the edge of the active region laterally to the outer edge of the guard ring under reverse bias. This effectively suppresses the premature occurrence of edge breakdown and the leakage current deterioration caused by edge hot carrier effects, making the actual breakdown voltage close to the theoretical parallel plate breakdown voltage. This improves the reliability of the device in high reverse voltage scenarios, thereby enhancing the performance of the planar Schottky rectifier diode prepared by this invention in terms of ultra-low forward voltage drop, low reverse leakage current, high breakdown voltage, and high batch consistency.

[0015] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an embodiment of the ultra-low forward voltage drop planar Schottky rectification method in this invention. Figure 2 This is a schematic diagram illustrating the steps of epitaxially growing an N-type lightly doped drift layer on an N-type heavily doped silicon substrate in an embodiment of the present invention. Figure 3 This is a schematic diagram illustrating the step of forming a P-type guard ring at the edge of the active region in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the steps of sputtering and depositing Ti and TiW layers in an embodiment of the present invention; Figure 5 This is a schematic diagram of the Al / Ti / Ni / Ag metal stack deposition steps in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The terms "comprising" and "having," and any variations thereof, used in the embodiments of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0020] To facilitate understanding of this embodiment, a detailed description of an ultra-low forward voltage drop planar Schottky rectification method disclosed in this embodiment of the invention will be provided first. For example... Figure 1 As shown, this method includes the following steps: 101. An epitaxial wafer is obtained by epitaxially growing a lightly doped N-type drift layer on an N-type heavily doped silicon substrate. 102. A field oxide layer is deposited at the edge of the active region on the front side of the epitaxial wafer and a window is created by photolithography, forming a P-type protective ring at the edge of the active region; 103. A Ti layer and a TiW layer are sequentially sputtered and deposited on the front side of the epitaxial wafer forming a P-type protective ring to obtain a Schottky contact layer; 104. A PECVD silicon nitride passivation layer is sequentially deposited on the front side of the Schottky contact layer, and contact holes are formed by photolithography. An AlSi interconnect metal layer is sputtered and patterned to form the front electrode. At the same time, the back side of the Schottky contact layer is thinned and an Al / Ti / Ni / Ag metal stack is deposited to obtain a rectifier diode.

[0021] In this embodiment of the invention, by selecting Ti, which has a work function highly matched with that of N-type silicon, as the Schottky contact metal, and by strictly controlling the transfer time after removing the native oxide layer with dilute hydrofluoric acid, direct bonding between Ti and silicon is ensured. Rapid thermal annealing within a precise temperature window enables the formation of a continuous and uniform TiSi2 layer at the interface, effectively reducing the contact resistivity and stabilizing the barrier height within the target range. This fundamentally solves the problems of high forward voltage drop and poor batch consistency in the prior art. The introduction of the TiW layer as a diffusion barrier layer further protects the chemical stability of the Schottky contact interface in subsequent processes, preventing the interconnect metal from diffusing to the interface and damaging the barrier structure. The P-type guard ring formed by boron ion implantation disperses the electric field spike at the edge of the active region laterally to the outer edge of the guard ring under reverse bias. This effectively suppresses the premature occurrence of edge breakdown and the leakage current deterioration caused by edge hot carrier effects, making the actual breakdown voltage close to the theoretical parallel plate breakdown voltage. This improves the reliability of the device in high reverse voltage scenarios, thereby enhancing the performance of the planar Schottky rectifier diode prepared by this invention in terms of ultra-low forward voltage drop, low reverse leakage current, high breakdown voltage, and high batch consistency.

[0022] In one specific embodiment, such as Figure 2 The process of executing step 101 may specifically include the following steps: 201. Select a resistivity of 0.001 Ω·cm to 0.005 Ω·cm and a crystal orientation of... <100> On an N-type heavily doped arsenic silicon substrate, a chemical vapor deposition epitaxial growth process with a doping concentration of 5 × 10⁻⁶ phosphorus was performed using phosphorus as a dopant. 14 cm -3 Up to 2×10 15 cm -3 An N-type lightly doped drift layer is used to obtain an epitaxial wafer.

[0023] Specifically, the basic structure of the epitaxial wafer is determined based on constraints such as the target breakdown voltage, forward voltage drop, and batch consistency of the device, and a resistivity of 0.001 Ω·cm to 0.005 Ω·cm and a crystal orientation of [missing information]. <100> The N-type heavily doped arsenic silicon substrate was used as the starting silicon wafer. The heavy arsenic doping was used to reduce the substrate bulk resistance and decrease the series voltage drop introduced by the substrate when the device was turned on. <100> Crystal orientation facilitates the formation of a mature and stable silicon epitaxial growth interface and ensures good intra-wafer uniformity during oxidation, photolithography, ion implantation, and metal contact processes. Before the substrate enters the epitaxial process, the silicon wafer undergoes incoming material verification to confirm that its conductivity type, resistivity range, crystal orientation, and surface condition meet the requirements. Then, routine cleaning removes surface particles, organic residues, and metal ion contamination. Surface oxide layers and contaminant residues are controlled before entering the epitaxial reaction chamber, ensuring the epitaxial layer can grow on a clean, continuous silicon lattice surface. The N-type heavily doped arsenic silicon substrate is loaded into a chemical vapor deposition epitaxial device and subjected to surface baking and in-situ purification under high-temperature hydrogen or inert protective environments. This removes adsorbed water vapor, slight oxides, and volatile impurities from the substrate surface, thereby reducing defect density and interface recombination centers in the epitaxial layer. After surface stabilization, a silicon-containing reaction source gas is introduced, along with a phosphorus dopant source. This allows silicon atoms to continue growing on the substrate surface according to their original crystal orientation, while phosphorus atoms enter silicon lattice substitution sites to form a lightly doped N-type drift layer. During epitaxy, the doping concentration of the lightly doped N-type drift layer was controlled at 5 × 10⁻⁶ by synergistic control of the reaction source flow rate, cavity pressure, temperature, and phosphorus doping source flow rate. 14 cm -3 Up to 2×10 15 cm -3 This design ensures that the material can effectively handle the main depletion region expansion and breakdown voltage under reverse bias, while avoiding excessively high forward voltage drop due to excessively low doping resistance in the drift region. Since the bottom substrate is N-type heavily doped arsenic silicon and the upper drift layer is N-type lightly doped phosphorus silicon, a continuous transition of the same conductivity type should be maintained between them to avoid unnecessary parasitic junctions or high-resistivity transition regions. A stable epitaxial growth rate is used to ensure uniform distribution of drift layer thickness and doping concentration throughout the silicon wafer. After epitaxial growth, the silicon wafer is cooled and unwound. The epitaxial layer is then inspected for thickness, surface defects, doping uniformity, and resistivity. If the epitaxial layer surface has no obvious haze defects, slip lines, epitaxial hillocks, or localized contamination, and the doping concentration falls within 5 × 10⁻⁶, the wafer is considered complete. 14 cm -3 Up to 2×10 15 cm -3 Within this range, it can be confirmed that the epitaxial layer can serve as the drift region of a Schottky rectifier diode.

[0024] In one specific embodiment, such as Figure 3 The process of executing step 102 can specifically include the following steps: 301. A field oxide layer is grown on the front side of the epitaxial wafer by thermal oxidation, and a guard ring injection window is defined at the edge of the active region by photolithography; 302. With an injection energy of 80keV to 100keV and an injection dose of 5×10⁻⁶, 12 cm -2 Up to 2×10 13 cm -2 Boron ions are injected into the guard ring injection window to obtain the guard ring injection region; 303. Anneal the injection region of the protective ring at 950℃ in a nitrogen atmosphere for 30 minutes to activate boron ions and form a P-type protective ring at the edge of the active region.

[0025] Specifically, an N-type epitaxial wafer is used as the processing object. Before entering the guard ring formation process, the front side of the epitaxial wafer is cleaned to ensure that particles, organic residues, and metal contaminants at the edge of the active region are within acceptable limits. The epitaxial wafer is then fed into a thermal oxidation apparatus to grow a field oxide layer on the front side, covering the edge of the active region and its outer region, and serving as a masking medium during boron ion implantation. After the field oxide layer is formed, photoresist is coated on the front side, and exposure and development are performed according to the terminal structure design at the edge of the active region. This ensures that the guard ring implantation window accurately falls at the edge of the active region, neither excessively intruding into the Schottky main contact region nor being too far from the active region to weaken the edge electric field modulation effect. After photolithography, etching is used to open the field oxide layer at the guard ring implantation window, exposing the silicon surface in that area. The area outside the window is still shielded by the field oxide layer and photoresist, thus limiting boron ions to only entering the predetermined guard ring region.

[0026] After defining the window, the window size, edge position, and etching residue are checked to ensure the guard ring implantation window is continuous, without breaks, and without significant offset. Then, the epitaxial wafer is sent to the ion implantation equipment, using boron ions as the P-type dopant source, and the implantation energy is controlled between 80keV and 100keV, and the implantation dose is controlled at 5 × 10⁻⁶. 12 cm -2 Up to 2×10 13 cm -2 This process allows boron ions to penetrate the guard ring injection window and enter the surface region of the lightly doped N-type drift layer, forming a guard ring injection region with a certain depth and lateral distribution. The injection energy range ensures sufficient penetration depth for the boron ions, enabling the subsequently formed P-type guard ring to laterally engage with the depletion region at the edge of the active region. The injection dose range ensures sufficient P-type doping concentration in the guard ring, allowing it to participate in edge electric field dispersion under reverse bias without causing excessive local junction strength, increased leakage current, or unfavorable coupling with the main Schottky region due to excessive dose.

[0027] After boron ion implantation, not all boron atoms in the implanted region are at effective substitution sites, and some implantation damage exists in the silicon lattice. Therefore, the epitaxial wafer is annealed at 950°C for 30 minutes in a nitrogen atmosphere to repair the implantation damage and electroactivate the boron ions, thereby forming a P-type guard ring at the edge of the active region. Since the annealing step directly affects the junction depth, activation degree, and lateral diffusion range of the guard ring, the annealing temperature, time, and atmosphere stability are mainly controlled at this stage to ensure that the guard ring forms a continuous P-type termination structure at the edge of the active region.

[0028] In one specific embodiment, the process of performing step 303 may specifically include the following steps: Annealing the protected ring injection region at 950℃ in a nitrogen atmosphere for 30 min allows boron atoms in the protected ring injection region to migrate from interstitial sites to substitution sites, thus completing electroactivation and repairing lattice defects. The sheet resistance of the active region of the guard ring was measured using the four-probe method. When the sheet resistance was within a preset range, the doping uniformity was confirmed to be acceptable, resulting in a junction depth of 0.40 μm to 0.60 μm and a peak net doping concentration of 1 × 10⁻⁶. 17 cm -3 Up to 5×10 17 cm -3 The P-type protective ring.

[0029] Specifically, after boron ion implantation and removal of unwanted photoresist residue, the epitaxial wafer with the guard ring implantation region is fed into an annealing apparatus. Under a nitrogen atmosphere, the annealing temperature is stably controlled at 950℃ and held for 30 minutes. This allows the boron atoms implanted into the silicon lattice to obtain sufficient thermal energy to migrate from interstitial sites to substitutional sites, forming an effective acceptor doping state with the silicon lattice, thus completing electrical activation. Simultaneously, this heat treatment process repairs lattice damage caused by ion implantation, reducing defect density and leakage risk within the implantation region. During annealing, it is crucial to ensure the cleanliness and temperature uniformity of the nitrogen atmosphere, ensuring that the guard ring implantation region achieves a similar thermal budget across the entire epitaxial wafer. This prevents insufficient boron activation in localized areas due to insufficient temperature, and also avoids excessive lateral diffusion of boron due to overly intense heat treatment, which could alter the design relationship between the guard ring and the active region edge.

[0030] After annealing, the epitaxial wafer is cooled to the temperature allowed for subsequent testing using a controlled cooling method. A thin-film resistance (TFT) test is then performed on the activated region of the guard ring. During the test, a four-probe method is used to select multiple measurement points in the corresponding area of ​​the guard ring. Test current is applied to the two outer probes, while the voltage response is collected by the two inner probes. The TFT resistance is calculated by the testing equipment and used to characterize the conductivity uniformity after guard ring doping activation. The preset range for TFT resistance can be set from 5kΩ / □ to 20kΩ / □. When the test results at each measurement point are within this range, and the intra-wafer fluctuation does not exceed the process allowable range, it can be confirmed that boron ion activation is sufficient, the guard ring doping distribution is uniform, and the activated region of the guard ring meets the terminal structure requirements. Subsequently, the junction depth and peak net doping concentration of the guard ring can be confirmed by process monitoring or sampling inspection, ensuring that the junction depth falls within 0.40μm to 0.60μm and the peak net doping concentration falls within 1×10⁻⁶. 17 cm -3 Up to 5×10 17 cm -3 This forms a P-type guard ring located at the edge of the active region. When the device is reverse biased, the P-type guard ring can form a lateral depletion structure together with the lightly doped N-type drift layer, which expands the electric field spike at the edge of the active region laterally, thereby reducing the risk of premature edge breakdown and edge leakage current degradation.

[0031] In one specific embodiment, such as Figure 4 The process of executing step 103 may specifically include the following steps: 401. The front side of the epitaxial wafer forming the P-type protective ring is sequentially subjected to RCA cleaning and dilute hydrofluoric acid deoxidation treatment. The treated epitaxial wafer is then loaded into a magnetron sputtering cavity to sequentially sputter and deposit a Ti layer and an in-situ sputtering TiW layer to obtain a Ti / TiW double-layer metal stack. 402. Rapid thermal annealing is performed on the Ti / TiW bilayer metal stack to cause a solid-state reaction between the Ti layer and the silicon interface to generate a continuous and uniform TiSi2 layer, thus obtaining a Schottky contact layer.

[0032] Specifically, after the P-type guard ring has been annealed and activated and passed necessary inspections, the epitaxial wafer front side is transferred back to the Schottky contact formation process, with a focus on controlling the cleanliness of the silicon surface, the degree of removal of the native oxide layer, and the vacuum continuity during the metal deposition process. The epitaxial wafer front side for forming the P-type guard ring is sequentially subjected to RCA cleaning to remove organic contaminants, particulate contaminants, and metal ion contaminants that may remain from the previous photolithography, implantation, and annealing processes, and to ensure that the silicon surface in the active region to be formed with the Schottky contact is in a stable and clean state. Dilute hydrofluoric acid is used for deoxidation treatment to remove the newly formed native oxide layer on the silicon surface, allowing the Ti layer to directly contact the surface of the lightly doped N-type drift layer, rather than forming an unstable interface through the SiO2 residual layer. After deoxidation, the epitaxial wafer is exposed to air for as little time as possible and then placed in a magnetron sputtering chamber. Vacuuming, high-purity argon gas, and a stable working pressure are used to ensure the sputtering environment meets the requirements for continuous metal film deposition. First, a Ti layer is sputtered, serving as the main contact metal for forming a Schottky contact with N-type silicon, covering the active silicon surface. The Ti layer thickness is controlled between 50 nm and 80 nm to ensure sufficient metal source for the interface reaction while avoiding unnecessary stress and subsequent etching burden caused by excessive metal thickness. After Ti layer deposition, the vacuum is not broken, and the process is switched to a TiW target to continue depositing a TiW layer. This TiW layer forms a barrier layer over the Ti layer, with a thickness controlled between 100 nm and 150 nm. Due to TiW's good thermal stability and diffusion barrier properties, it can protect the Ti / Si interface during heat treatment and front-side interconnect metal formation, reducing the risk of metals such as AlSi diffusing to the Schottky interface and damaging the barrier structure.

[0033] Rapid thermal annealing of Ti / TiW bilayer metal stacks induces a solid-state reaction between the Ti layer and the silicon interface under controlled thermal conditions, generating a continuous and uniform TiSi2 layer at the interface. The annealing temperature can be controlled between 480℃ and 520℃, and the holding time between 45s and 60s. This process ensures a stable silicide interface without excessive diffusion of Ti into silicon or alteration of the Schottky barrier due to overly intense heat treatment. The resulting TiSi2 layer thickness can be controlled between 8nm and 12nm, forming a Ti / TiW / TiSi2 composite contact structure together with the overlying Ti / TiW metal. This transforms the previously susceptible contact interface, which was easily affected by native oxide layers, interface states, and metal diffusion, into a more stable Schottky contact layer.

[0034] In one specific embodiment, the process of performing step 401 may specifically include the following steps: The front side of the epitaxial wafer with the P-type guard ring was sequentially cleaned with RCA solutions SC-1 and SC-2, and then soaked in dilute hydrofluoric acid with a volume ratio of 1:50 to obtain the treated epitaxial wafer. The processed epitaxial wafer was placed into the magnetron sputtering chamber, and high-purity argon gas was introduced to a working pressure of 3 mTorr to 5 mTorr, followed by a sputtering speed of 2 W / cm². 2 Up to 3W / cm 2 A Ti layer with a thickness of 50 nm to 80 nm is deposited by power density sputtering, and a TiW layer with a thickness of 100 nm to 150 nm is deposited by in-situ sputtering with a TiW target without disrupting the vacuum, thus obtaining a Ti / TiW bilayer metal stack.

[0035] Specifically, the epitaxial wafer front side, after the P-type guard ring has been formed and surface inspection completed, undergoes pre-metallization cleaning to remove as much residue as possible from the previous process on the active silicon surface where the Schottky contact will be formed. During cleaning, SC-1 solution can be used first to remove front-side particles, organic matter, and some oxidizable contaminants, followed by SC-2 solution treatment to reduce the impact of residual metal ions on the subsequent Ti / Si interface. After cleaning, the wafer is thoroughly rinsed with deionized water and dried. Subsequently, the epitaxial wafer front side is immersed in a 1:50 volume ratio of dilute hydrofluoric acid to remove the natural oxide layer on the active surface and to bring the silicon surface to a cleaner state more suitable for direct metal contact.

[0036] Since the Ti layer needs direct contact with the silicon interface to form a stable Schottky contact base, the air exposure time is reduced after dilute hydrofluoric acid treatment, and the treated epitaxial wafer is promptly loaded into the magnetron sputtering cavity to avoid re-oxidation of the surface and the formation of an interface isolation layer. After the epitaxial wafer is loaded, the cavity is evacuated and pre-stabilized, then high-purity argon gas is introduced, and the working pressure is controlled at 3 mTorr to 5 mTorr to ensure a relatively stable metal atom deposition flux after argon ion bombardment of the target. Ti target is used for sputtering, and the power density is controlled at 2 W / cm². 2 Up to 3W / cm 2 This process allows Ti atoms to be uniformly deposited on the front side of the epitaxial wafer, forming a Ti layer with a thickness of 50 nm to 80 nm. After the Ti layer deposition is complete, without disrupting the vacuum state, sputtering is directly switched in situ to a TiW target within the same cavity, allowing the TiW layer to cover the Ti layer, with the TiW layer thickness controlled between 100 nm and 150 nm. This in-situ switching method avoids oxidation or contaminant adsorption on the Ti layer surface during the transfer process, thus ensuring a continuous, clean, and stable Ti / TiW interface. Simultaneously, the TiW layer acts as a barrier layer, improving the stability of the stack during heat treatment and interconnect metal formation, and reducing the risk of diffusion of the upper metal layer to the Ti / Si interface. After deposition, a Ti / TiW bilayer metal stack consisting of a lower Ti layer and an upper TiW layer is obtained.

[0037] In one specific embodiment, the process of performing step 402 may specifically include the following steps: The Ti / TiW bilayer metal stack is heated to 480℃ to 520℃ and held for 45s to 60s to allow the Ti layer to undergo a solid-state reaction with the silicon interface to generate a continuous and uniform TiSi2 layer with a thickness of 8nm to 12nm, thus obtaining a Ti / TiW / TiSi2 composite contact structure. The Ti / TiW / TiSi2 composite contact structure was cooled to room temperature, allowing the TiSi2 layer to maintain its C49 phase structure, thus obtaining the Schottky contact layer.

[0038] Specifically, the epitaxial wafers with deposited Ti and TiW layers are transferred to a rapid thermal annealing apparatus. Before mounting, it is confirmed that the surface of the Ti / TiW bilayer metal stack is free of obvious particles, peeling, and oxidation contamination. Then, rapid heating is performed in a protective atmosphere such as nitrogen, raising the stack temperature to 480°C to 520°C and holding it for 45 to 60 seconds. Within this thermal budget, the lower Ti layer undergoes a controlled solid-state reaction with the N-type silicon surface. Ti atoms at the interface diffuse to the silicon side in a limited manner, while silicon atoms simultaneously participate in the reaction, thereby generating a continuous and uniform TiSi2 layer with a thickness of 8 nm to 12 nm between the Ti layer and the silicon interface. This process requires careful control of heating uniformity, holding time, and atmospheric cleanliness. If the temperature is too low or the holding time is insufficient, the interface silanization reaction will be discontinuous, leaving unreacted Ti / Si contact areas and resulting in uneven Schottky barrier distribution. On the other hand, if the temperature is too high or the holding time is too long, Ti may diffuse excessively into the silicon, causing the interface reaction depth to exceed the target range and adversely affecting the Schottky barrier height and reverse leakage current. Forming 8nm to 12nm TiSi2 thin layers at 480℃ to 520℃ for 45s to 60s improves interfacial contact consistency while preventing the barrier structure from becoming uncontrolled due to excessive silicide layer thickness. The TiW layer, located above the Ti layer, mainly plays a role in diffusion blocking and stack stabilization during annealing, preventing the upper metal environment from directly disturbing the Ti / Si interface reaction and ensuring good continuity and intra-wafer uniformity of the generated TiSi2 layer along the active region surface.

[0039] After the thermal insulation process, the Ti / TiW / TiSi2 composite contact structure was cooled to room temperature in a controlled manner to maintain the C49 phase structure of the TiSi2 layer formed at the interface and to avoid cracking, warping, or localized decrease in adhesion of the metal stack caused by sudden thermal stress changes during cooling. The resulting Schottky contact layer consists of an upper TiW barrier layer, a middle remaining Ti layer, and an interface TiSi2 layer. The TiSi2 layer is used to improve the uniformity of the Ti / Si interface reaction and contact stability, while the Ti / TiW stack is used to maintain metal contact and process compatibility.

[0040] In one specific embodiment, such as Figure 5 The process of executing step 104 can specifically include the following steps: 501. On the Schottky contact layer, a PECVD silicon nitride passivation layer is deposited at a SiH4 to NH3 flow ratio of 1:4 and a gas pressure of 1.5 Torr. Contact holes are opened by photolithography and dry etching with CF4 / O2 mixed gas. Then, an AlSi interconnect metal layer is sputtered and deposited and patterned by photolithography to form the front electrode. 502. After the back side of the Schottky contact layer with the front electrode is thinned to 100μm to 120μm and deoxidized with dilute hydrofluoric acid at a volume ratio of 1:50, an Al / Ti / Ni / Ag metal stack is sputtered to form an ohmic back contact, thus obtaining a rectifier diode.

[0041] Specifically, after the Schottky contact layer has completed the formation of the Ti / TiW / TiSi2 composite interface and cooled and stabilized, passivation and interconnection processing are performed on the front side to provide dielectric protection for the surface outside the active region, while reserving contact channels for the front electrode. The epitaxial wafer with the Schottky contact layer is fed into a PECVD equipment, where a silicon nitride passivation layer is deposited on the front side. The SiH4 to NH3 flow ratio is controlled at 1:4 and the gas pressure is controlled at 1.5 Torr, so that the silicon nitride film covers the Schottky contact area, the edge area of ​​the guard ring, and the surface of the field oxide layer, thereby reducing the impact of surface contamination, moisture intrusion, and interface states on reverse leakage current. After the passivation layer is formed, photoresist is coated on the front side. Exposure and development are then performed based on the contact positions between the front electrode and the active region, defining the areas requiring current extraction as contact hole patterns. The remaining areas remain protected by photoresist and silicon nitride. Subsequently, dry etching using a CF4 / O2 mixed gas is employed to open the silicon nitride within the contact hole areas, partially exposing the underlying Schottky contact layer. Over-etching damage to the Ti / TiW stack is avoided through controlled etching endpoints. After the contact holes are created, photoresist residue is removed and necessary surface cleaning is performed. Then, an AlSi interconnect metal layer is sputtered and deposited on the front side, covering the contact holes and forming an electrical connection with the Schottky contact layer. Simultaneously, the passivation layer surface serves as the metal base for subsequent front electrode patterning. The front electrode pattern is then defined again using photolithography, and appropriate etching processes are used to remove the AlSi metal from the non-electrode areas, creating an electrode structure on the front side that is conductive to the active region and isolated from the surrounding passivation areas.

[0042] After completing the front electrode, low-resistance ohmic contacts are fabricated on the back side of the device. First, the back side of the Schottky contact layer with the front electrode is thinned to a thickness of 100-120 μm to shorten the longitudinal current path and reduce the contribution of substrate series resistance. After thinning, the back side is cleaned and planarized, and the natural oxide layer is removed using a 1:50 volume ratio of dilute hydrofluoric acid, making the silicon surface suitable for direct metal contact. Subsequently, the epitaxial wafer is placed in the sputtering chamber, and an Al / Ti / Ni / Ag metal stack is sequentially deposited on the back side. The Al layer forms the ohmic contact base with the N-type silicon on the back side, the Ti layer enhances interlayer adhesion, the Ni layer improves barrier properties and solderability, and the Ag layer provides a good solderable surface. By combining the passivated interconnect on the front side with the low-resistance ohmic contact on the back side, the forward current of the device can enter the Schottky contact layer from the AlSi electrode on the front side, and then be conducted to the Al / Ti / Ni / Ag electrode on the back side through the N-type drift layer and the heavily doped substrate. At the same time, the silicon nitride passivation layer and the P-type guard ring together suppress the risk of edge leakage and surface failure, thus obtaining a planar Schottky rectifier diode.

[0043] In one specific embodiment, the process of performing step 501 may specifically include the following steps: A PECVD silicon nitride passivation layer was deposited on the front side of the Schottky contact layer at a deposition temperature of 280°C, a radio frequency power of 200W, a SiH4 to NH3 flow ratio of 1:4, and a gas pressure of 1.5 Torr. Dry etching of the PECVD silicon nitride passivation layer was performed using a mixed gas with a CF4:O2 volume ratio of 4:1 and 150W RF power. Contact holes were then formed above the active region of the Schottky contact layer to obtain a silicon nitride passivation layer with contact holes. An AlSi interconnect metal layer with a Si content of 1% by mass and a thickness of 1.5 μm to 2 μm is sputtered and deposited on a silicon nitride passivation layer with contact holes. The front electrode is then formed by photolithography and wet etching to obtain a Schottky contact layer with a front electrode.

[0044] Specifically, after the Schottky contact layer undergoes rapid thermal annealing to form a stable Ti / TiW / TiSi2 composite contact structure, the front side is inspected for particles and residues and then sent to a PECVD deposition equipment. Before deposition, the chamber is evacuated, the process gas is stabilized, and the substrate temperature is stabilized to ensure that the front metal stack and the edge of the active area are in a state suitable for low-temperature dielectric deposition. Then, a silicon nitride passivation layer is deposited at a deposition temperature of 280℃, a radio frequency power of 200W, a SiH4 to NH3 flow ratio of 1:4, and a gas pressure of 1.5 Torr. This allows the silicon nitride to continuously cover the surface of the Schottky contact layer, the edge of the protective ring, and the surrounding dielectric area, thereby isolating and protecting the metal interface and edge terminals, and reducing the impact of moisture, ion contamination, and surface states on reverse leakage current.

[0045] After the silicon nitride passivation layer is formed, photoresist is coated on its surface. Exposure and development are then performed according to the positions where the front electrode needs to be connected to the active region, ensuring the contact hole pattern is accurately positioned above the active region of the Schottky contact layer. Subsequently, a CF4:O2 mixed gas with a volume ratio of 4:1 is used as the etching gas, and dry etching is performed on the silicon nitride passivation layer at 150W RF power. This removes the silicon nitride in the contact hole area, exposing the underlying Schottky contact layer, while the non-contact areas remain covered and protected by silicon nitride. During the etching process, etching uniformity and endpoint are controlled to avoid incomplete opening of the contact holes, which could lead to increased contact resistance, and to prevent over-etching that could damage the underlying TiW layer or affect the passivation integrity of the active region edges.

[0046] After the contact holes are created, photoresist residue is removed and the surface is cleaned. Then, an AlSi interconnect metal layer with a Si content of 1% by mass and a thickness of 1.5 μm to 2 μm is sputtered and deposited on the silicon nitride passivation layer with the contact holes. This allows the AlSi metal to fill the contact holes and form a front-side electrical connection with the exposed Schottky contact layer, while simultaneously forming a continuous metal wiring base on the passivation layer surface. Photolithography is then performed again to define the pad area, lead-out area, and isolation boundary of the front electrode. The AlSi metal in the non-electrode areas is removed by wet etching, leaving the remaining AlSi layer to form the front electrode pattern. The silicon nitride passivation layer provides surface protection and suppresses edge leakage current; the contact holes act as channels for current to enter the Schottky contact layer from the front electrode; and the AlSi interconnect metal layer provides low-resistance lead-out and a foundation for solder connections, ultimately resulting in a Schottky contact layer with a front electrode.

[0047] The ultra-low forward voltage drop planar Schottky rectification method in the embodiments of the present invention has been described above. The ultra-low forward voltage drop planar Schottky rectifier diode in the embodiments of the present invention is described below. The ultra-low forward voltage drop planar Schottky rectifier diode in the embodiments of the present invention is prepared using the above-described ultra-low forward voltage drop planar Schottky rectification method.

[0048] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0049] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0050] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Schottky rectification method for ultra-low forward voltage drop planar processes, characterized in that, include: An epitaxial wafer is obtained by epitaxially growing an N-type lightly doped drift layer on an N-type heavily doped silicon substrate. A field oxide layer is deposited at the edge of the active region on the front side of the epitaxial wafer, and a window is created by photolithography. A P-type protective ring is formed at the edge of the active region. A Ti layer and a TiW layer are sequentially sputtered and deposited on the front side of the epitaxial wafer forming the P-type protective ring to obtain a Schottky contact layer. A PECVD silicon nitride passivation layer is sequentially deposited on the front side of the Schottky contact layer, and contact holes are formed by photolithography. An AlSi interconnect metal layer is sputtered and patterned to form the front electrode. At the same time, the back side of the Schottky contact layer is thinned and an Al / Ti / Ni / Ag metal stack is deposited to obtain a rectifier diode.

2. The ultra-low forward voltage drop planar Schottky rectification method according to claim 1, characterized in that, The epitaxial growth of an N-type lightly doped drift layer on an N-type heavily doped silicon substrate to obtain an epitaxial wafer includes: Select resistivity ranging from 0.001 Ω·cm to 0.005 Ω·cm, with crystal orientation of... <100> On an N-type heavily doped arsenic silicon substrate, phosphorus is used as a dopant to perform chemical vapor deposition epitaxial growth with a doping concentration of 5 × 10⁻⁶. 14 cm -3 Up to 2×10 15 cm -3 An N-type lightly doped drift layer is used to obtain an epitaxial wafer.

3. The ultra-low forward voltage drop planar Schottky rectification method according to claim 1, characterized in that, The process of depositing a field oxide layer at the edge of the active region on the front side of the epitaxial wafer and photolithographically creating a window, and forming a P-type protective ring at the edge of the active region, includes: A field oxide layer is grown on the front side of the epitaxial wafer by thermal oxidation, and a protective ring injection window is defined at the edge of the active region by photolithography. With an injection energy of 80keV to 100keV and an injection dose of 5×10 12 cm -2 Up to 2×10 13 cm -2 Boron ions are injected into the protective ring injection window to obtain the protective ring injection region; The protective ring injection region was annealed for 30 minutes in a nitrogen atmosphere at 950°C to activate boron ions and form a P-type protective ring at the edge of the active region.

4. The ultra-low forward voltage drop planar Schottky rectification method according to claim 3, characterized in that, The step of annealing the injection region of the protective ring at 950°C in a nitrogen atmosphere for 30 minutes to activate boron ions and form a P-type protective ring at the edge of the active region includes: The protective ring injection region was annealed for 30 minutes in a nitrogen atmosphere at 950℃, so that the boron atoms in the protective ring injection region migrated from interstitial sites to substitution sites to complete the electroactivation and repair lattice defects. The sheet resistance of the active region of the guard ring was measured using the four-probe method. When the sheet resistance was within a preset range, the doping uniformity was confirmed to be qualified, resulting in a junction depth of 0.40 μm to 0.60 μm and a peak net doping concentration of 1 × 10⁻⁶. 17 cm -3 Up to 5×10 17 cm -3 The P-type protective ring.

5. The ultra-low forward voltage drop planar Schottky rectification method according to claim 1, characterized in that, The process of sequentially sputtering and depositing a Ti layer and a TiW layer on the front side of the epitaxial wafer forming the P-type guard ring to obtain a Schottky contact layer includes: The front side of the epitaxial wafer forming the P-type protective ring is sequentially subjected to RCA cleaning and dilute hydrofluoric acid deoxidation treatment. The treated epitaxial wafer is then loaded into a magnetron sputtering cavity to sequentially sputter and deposit a Ti layer and an in-situ sputtering TiW layer to obtain a Ti / TiW double-layer metal stack. The Ti / TiW bilayer metal stack is subjected to rapid thermal annealing, which causes a solid-state reaction between the Ti layer and the silicon interface to generate a continuous and uniform TiSi2 layer, thus obtaining a Schottky contact layer.

6. The ultra-low forward voltage drop planar Schottky rectification method according to claim 5, characterized in that, The epitaxial wafer forming the P-type protective ring is subjected to RCA cleaning and dilute hydrofluoric acid deoxidation treatment on its front side. The treated epitaxial wafer is then placed into a magnetron sputtering cavity for sequential sputtering deposition of a Ti layer and in-situ sputtering deposition of a TiW layer, resulting in a Ti / TiW bilayer metal stack, including: The front side of the epitaxial wafer with the P-type protective ring is sequentially cleaned with RCA solutions SC-1 and SC-2, and then soaked in dilute hydrofluoric acid with a volume ratio of 1:50 to obtain the treated epitaxial wafer. The processed epitaxial wafer was placed into the magnetron sputtering chamber, and high-purity argon gas was introduced to a working pressure of 3 mTorr to 5 mTorr, followed by a sputtering speed of 2 W / cm². 2 Up to 3W / cm 2 A Ti layer with a thickness of 50 nm to 80 nm is deposited by power density sputtering, and a TiW layer with a thickness of 100 nm to 150 nm is deposited by in-situ sputtering with a TiW target without disrupting the vacuum, thus obtaining a Ti / TiW bilayer metal stack.

7. The ultra-low forward voltage drop planar Schottky rectification method according to claim 5, characterized in that, The rapid thermal annealing of the Ti / TiW bilayer metal stack, causing a solid-state reaction between the Ti layer and the silicon interface to generate a continuous and uniform TiSi2 layer, yields a Schottky contact layer, comprising: The Ti / TiW bilayer metal stack is heated to 480°C to 520°C and held for 45s to 60s to allow the Ti layer to undergo a solid-state reaction with the silicon interface to generate a continuous and uniform TiSi2 layer with a thickness of 8nm to 12nm, thus obtaining a Ti / TiW / TiSi2 composite contact structure. The Ti / TiW / TiSi2 composite contact structure was cooled to room temperature, allowing the TiSi2 layer to maintain its C49 phase structure, thus obtaining a Schottky contact layer.

8. The ultra-low forward voltage drop planar Schottky rectification method according to claim 5, characterized in that, The process involves sequentially depositing a PECVD silicon nitride passivation layer on the front side of the Schottky contact layer and photolithographically creating contact holes, sputtering and depositing an AlSi interconnect metal layer and patterning it to form the front electrode, while simultaneously thinning and depositing an Al / Ti / Ni / Ag metal stack on the back side of the Schottky contact layer to obtain a rectifier diode, comprising: In the Schottky contact layer, a PECVD silicon nitride passivation layer is deposited at a SiH4 to NH3 flow ratio of 1:4 and a gas pressure of 1.5 Torr. Contact holes are opened by photolithography and dry etching with CF4 / O2 mixed gas. Then, an AlSi interconnect metal layer is sputtered and deposited and patterned by photolithography to form the front electrode. After the back side of the Schottky contact layer with the front electrode is thinned to 100μm to 120μm and deoxidized with dilute hydrofluoric acid at a volume ratio of 1:50, an Al / Ti / Ni / Ag metal stack is sputtered to form an ohmic back contact, thus obtaining a rectifier diode.

9. The ultra-low forward voltage drop planar Schottky rectification method according to claim 5, characterized in that, The process involves depositing a PECVD silicon nitride passivation layer on the Schottky contact layer at a SiH4 to NH3 flow ratio of 1:4 and a gas pressure of 1.5 Torr, followed by photolithography and dry etching with a CF4 / O2 mixed gas to create contact holes, and then sputtering to deposit an AlSi interconnect metal layer and patterning it with photolithography to form the front electrode. The process includes: A PECVD silicon nitride passivation layer was deposited on the front side of the Schottky contact layer at a deposition temperature of 280°C, a radio frequency power of 200W, a SiH4 to NH3 flow ratio of 1:4, and a gas pressure of 1.5 Torr. The PECVD silicon nitride passivation layer was dry etched with a CF4:O2 mixed gas with a volume ratio of 4:1 and 150W radio frequency power to form a contact hole above the active region of the Schottky contact layer, thus obtaining a silicon nitride passivation layer with a contact hole. An AlSi interconnect metal layer with a Si content of 1% by mass and a thickness of 1.5 μm to 2 μm is sputtered and deposited on the silicon nitride passivation layer with contact holes. The front electrode is then formed by photolithography and wet etching to obtain a Schottky contact layer with a front electrode.

10. A Schottky rectifier diode with ultra-low forward voltage drop planar process, characterized in that, It is prepared using the ultra-low forward voltage drop planar process Schottky rectification method as described in any one of claims 1-9.

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