Lateral insulated gate bipolar transistor and method of manufacturing the same

Abstract

The present application relates to a kind of lateral insulated gate bipolar transistors and its manufacturing method, lateral insulated gate bipolar transistor includes: emission region;P well, emission region is located in P well;Collecting region;N well, collecting region is located in N well;Drift region, at least part of drift region is located between N well and P well;Isolation groove structure, segment setting and along the direction of the conductive channel length of lateral insulated gate bipolar transistor, isolation groove structure is provided with the opening for the drift region of two sides communication, P well is distributed in the two sides of the isolation groove structure, N well is distributed in the two sides of the isolation groove structure, collecting region is located in one side of isolation groove structure;First N type doped region, located in the other side of isolation groove structure, first N type doped region is short-circuit connection with collecting region;Gate, located on the region between emission region and collecting region top.This application can inhibit voltage return phenomenon while shortening current tail time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a lateral insulated gate bipolar transistor (LIGBT), and also to a method for manufacturing a LIGBT. Background Technology

[0002] Integrating LIGBTs (Laterally Insulated Gate Bipolar Transistors) into BCDs (Bipolar-CMOS-DMOS) offers a greater current advantage than LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistors). However, the excessive tail current of LIGBTs results in poor device turn-off speed. While LIGBTs with an anode short-circuit structure (i.e., SA-LIGBTs) can alleviate the current tailing phenomenon, they severely affect the device's on-state current and are prone to snapback.

[0003] The present invention aims to solve the problems of turn-off current tailing and on-state snapback in devices. Summary of the Invention

[0004] Therefore, it is necessary to provide a lateral insulated gate bipolar transistor with a short current tailing time during turn-off and a method for manufacturing the same.

[0005] A lateral insulated-gate bipolar transistor (LIGBT) includes: an emitter region; a P-well, the emitter region being located within the P-well; a collector region; an N-well, the collector region being located within the N-well; a drift region, at least a portion of which is located between the N-well and the P-well; an isolation trench structure, segmented and extending along the length of the conductive channel of the LIGBT, wherein the isolation trench structure has an opening in the drift region for communication between the two drift regions; the P-wells are distributed on both sides of the isolation trench structure; the N-wells are distributed on both sides of the isolation trench structure; the collector region is located on one side of the isolation trench structure; a first N-type doped region is located on the other side of the isolation trench structure, the doping concentration of the first N-type doped region is greater than the doping concentration of the N-well, and the first N-type doped region is short-circuited to the collector region; and a gate located above the region between the emitter region and the collector region.

[0006] In the aforementioned lateral insulated-gate bipolar transistor (LIGBT), when the device is turned off, a large number of electrons in the drift region flow through the drift region at the opening of the isolation trench structure to the first N-type doped region, while holes flow to the P-wells on both sides of the isolation trench structure, significantly shortening the tailing time of the LIGBT. During conductance modulation, due to the isolation trench structure, the drift region on the first N-type doped region side is unaffected by conductance modulation, resulting in a larger resistance in the drift region, which suppresses voltage foldback. Furthermore, in unipolar mode, the voltage difference between the N-well and the collector region on the first N-type doped region side is greater, meaning the emitter junction will turn on earlier under the same anode voltage. The isolation trench structure further suppresses voltage foldback in the unipolar-to-bipolar mode transition.

[0007] In one embodiment, the emitter region and the collector region are P-type regions, and the doping concentration of the emitter region is greater than the doping concentration of the P-well; the emitter region is distributed on both sides of the isolation trench structure.

[0008] In one embodiment, the isolation trench structure includes an insulating medium filled in the trench.

[0009] In one embodiment, the lateral insulated gate bipolar transistor further includes a second N-type doped region located in the P-well and on both sides of the isolation trench structure, the second N-type doped region being located between the emitter region and the gate; the emitter regions on both sides of the isolation trench structure are short-circuited and short-circuited with the second N-type doped regions on both sides of the isolation trench structure.

[0010] In one embodiment, the first N-type doped region serves as the drain region of the LDMOS, the second N-type doped region serves as the source region of the LDMOS, and the gate also serves as the gate of the LDMOS.

[0011] In one embodiment, the isolation trench structure includes a first segment, a second segment, and a third segment. The second segment is located in the drift region. The P-wells are distributed on both sides of the first segment. The emitter region is distributed on both sides of the first segment. The second N-type doped region is distributed on both sides of the first segment. The N-well is distributed on both sides of the third segment. The collector region is located on one side of the third segment, and the first N-type doped region is located on the other side of the third segment.

[0012] In one embodiment, the lateral insulated gate bipolar transistor further includes a field oxide layer located between the second N-type doped region and the collector region, the gate extending from the edge of the first N-type doped region onto the field oxide layer.

[0013] In one embodiment, the drift region is an N-type drift region, and the lateral insulated gate bipolar transistor further includes: a P-type buried region located in the drift region between the P-well and the N-well, and located on both sides of the second segment; a top N-type doped region located in the drift region between the P-well and the N-well, and located above the P-type buried region, the top N-type doped region being located on both sides of the second segment, and the doping concentration of the top N-type doped region being greater than the doping concentration of the drift region.

[0014] In one embodiment, the lateral insulated gate bipolar transistor is a silicon-on-insulator lateral insulated gate bipolar transistor, including a substrate and an insulating buried layer on the substrate, wherein the drift region is located on the insulating buried layer.

[0015] In one embodiment, the substrate is a silicon substrate, and the insulating buried layer is made of silicon oxide.

[0016] In one embodiment, the lateral insulated gate bipolar transistor is an anode-short-circuited lateral insulated gate bipolar transistor.

[0017] In one embodiment, the bottom of the P-well extends into the insulating buried layer.

[0018] In one embodiment, the bottom of the isolation groove structure extends to the insulating buried layer.

[0019] A method for manufacturing a lateral insulated gate bipolar transistor (lateral gate bipolar transistor) includes: obtaining a wafer with a drift region formed thereon; forming a P-well and an N-well; forming a segmented isolation trench structure; the isolation trench structure extending along the length of the conductive channel of the lateral gate bipolar transistor, the isolation trench structure forming an opening in the drift region for communication between the drift regions on both sides; forming a gate above the P-well and the N-well; forming an emitter region, a collector region, and a first N-type doped region; the emitter region being formed in the P-well, the collector region being formed in the N-well, the collector region and the first N-type doped region being formed on one side and the other side of the isolation trench structure, respectively, the doping concentration of the first N-type doped region being greater than the doping concentration of the N-well; and short-circuiting the first N-type doped region to the collector region.

[0020] The LIGBT manufactured using the aforementioned lateral insulated gate bipolar transistor (IGBT) fabrication method exhibits the following characteristics: When the device is turned off, a large number of electrons in the drift region flow through the drift region at the opening of the isolation trench structure to the first N-type doped region, while holes flow to the P-wells on both sides of the isolation trench structure, significantly shortening the LIGBT's tailing time. During conductance modulation, due to the isolation trench structure, the drift region located on the first N-type doped region side is unaffected by conductance modulation, resulting in a larger resistance and suppressing voltage foldback. Furthermore, in unipolar mode, the voltage difference between the N-well and the collector region on the first N-type doped region side is greater, meaning the emitter junction turns on earlier under the same anode voltage. In the unipolar-to-bipolar mode, the isolation trench structure effectively suppresses voltage foldback.

[0021] In one embodiment, prior to the step of forming the segmented isolation trench structure, the step further includes forming a P-type buried region and a top N-type doped region in the drift region; the P-type buried region and the top N-type doped region are formed in the drift region between the P-well and the N-well. Attached Figure Description

[0022] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0023] Figure 1 This is a top view of a lateral insulated gate bipolar transistor (LIGBT) in one embodiment of this application, showing the LIGBT body and auxiliary semiconductor structure arranged side by side.

[0024] Figure 2 This is a cross-sectional schematic diagram of the LIGBT body of a lateral insulated gate bipolar transistor in one embodiment of this application.

[0025] Figure 3 This is a cross-sectional schematic diagram of the auxiliary semiconductor structure of a lateral insulated gate bipolar transistor in one embodiment of this application.

[0026] Figure 4 This is a top view of a lateral insulated gate bipolar transistor (LIGBT) body and an LDMOS arranged side by side in one embodiment of this application.

[0027] Figure 5 This is a flowchart of a method for manufacturing a lateral insulated gate bipolar transistor according to one embodiment of this application. Detailed Implementation

[0028] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0034] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0035] If an N+ anode short-circuit structure is introduced only near the emitter of a LIGBT, the drift region resistance will suddenly decrease due to conductance modulation when the device is turned on, and voltage foldback is likely to occur when the device switches from unipolar to bipolar mode.

[0036] This application proposes a novel hybrid-mode lateral insulated-gate bipolar transistor (LGBT) in which an auxiliary semiconductor structure is introduced alongside the LGBT body. An isolation trench structure 30 is segmented between the LGBT body and the auxiliary semiconductor structure, with the opening of the isolation trench structure 30 located in the drift region 110. (See also...) Figure 1 . Figure 2 This is a cross-sectional schematic diagram of the LIGBT body of a transverse insulated gate bipolar transistor in one embodiment of this application (the cross-sectional line does not intersect with the isolation trench structure 30). Figure 3This is a cross-sectional schematic diagram of the auxiliary semiconductor structure of a lateral insulated gate bipolar transistor (LIGBT) in one embodiment of this application (the cross-sectional line does not intersect with the isolation trench structure 30). The LIGBT includes an emitter region 136, a P-well 116, a collector region 133, an N-well 114, a drift region 110, and an isolation trench structure 30. Figure 2 and Figure 3 (Not shown), a first N-type doped region 132, and a gate 138. An emitter region 136 is located in a P-well 116, and a collector region 133 is located in an N-well 114. At least a portion of the drift region 110 is located between the N-well 114 and the P-well 116. An isolation trench structure 30 is segmented and extends along the length of the conductive channel of the transverse insulated gate bipolar transistor. The isolation trench structure 30 has an opening in the drift region 110 for communication between the two drift regions 110 on both sides; that is, the drift regions 110 on both sides of the isolation trench structure 30 communicate with each other through this opening. P-wells 116 are distributed on both sides of the isolation trench structure 30, and N-wells 114 are distributed on both sides of the isolation trench structure 30. The collector region 133 is located on one side of the isolation trench structure 30, and the first N-type doped region 132 is located on the other side of the isolation trench structure 30. The doping concentration of the first N-type doped region 132 is greater than the doping concentration of the N-well 114, and the first N-type doped region 132 is short-circuited to the collector region 133.

[0037] In the aforementioned lateral insulated gate bipolar transistor (IGBT), when the device is turned off, a large number of electrons in the drift region 110 flow through the opening of the isolation trench structure 30 to the first N-type doped region 132, while holes flow to the P-wells 116 on both sides of the isolation trench structure 30, significantly shortening the tailing time of the LIGBT. During conductance modulation, due to the isolation trench structure 30, the drift region 110 located in the auxiliary semiconductor structure region is unaffected by conductance modulation, resulting in a larger resistance and suppressing voltage foldback. Furthermore, in unipolar mode, the voltage difference between the N-well 114 and the collector region 133 in the auxiliary semiconductor structure region is greater, meaning the emitter junction will turn on earlier under the same anode voltage. In the switch from unipolar to bipolar mode, voltage foldback can be suppressed by adjusting the opening length of the isolation trench structure 30. Since the LIGBT body and the auxiliary semiconductor structure share a portion of the structure, the manufacturing process is relatively simple.

[0038] exist Figure 1In the illustrated embodiment, the isolation trench structure 30 has two openings in the drift region. In other embodiments, the isolation trench structure 30 may have more or fewer openings in the drift region. In one embodiment of this application, the isolation trench structure 30 includes a first segment 32, a second segment 34, and a third segment 36. The second segment 34 is located in the drift region 110, P-wells 116 are distributed on both sides of the first segment 32, N-wells 144 are distributed on both sides of the third segment 36, a collector region 133 is located on one side of the third segment 36, and a first N-type doped region 132 is located on the other side of the third segment 36. In other embodiments, the isolation trench structure 30 may have fewer than three segments or more than three segments.

[0039] In one embodiment of this application, the LIGBT body further includes a second N-type doped region 134 located in the P-well 116 and on both sides of the first segment 32, the second N-type doped region 134 being located between the emitter region 136 and the gate 138.

[0040] In one embodiment of this application, the emitter region 136 and the collector region 133 are P-type regions, and the doping concentration of the emitter region 136 is greater than the doping concentration of the P-well 116. In one embodiment of this application, the drift region 110 is an N-type drift region.

[0041] In one embodiment of this application, the launch area 136 is distributed on both sides of the first segment 32.

[0042] In one embodiment of this application, the isolation trench structure 30 includes an insulating medium filled in the trench, which may be an oxide, such as silicon dioxide.

[0043] In one embodiment of this application, the auxiliary semiconductor structure is an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor), see reference. Figure 4 The first N-type doped region 132 serves as the drain region of the LDMOS, and the second N-type doped region 134 serves as the source region of the LDMOS. The gate 138 serves as both the gate of the LIGBT and the gate of the LDMOS. The drain region of the LDMOS is short-circuited to the collector region 133, serving as the anode of the LIGBT. The emitter regions 136 on both sides of the isolation trench structure 30 are short-circuited and also short-circuited to the second N-type doped regions 134 on both sides of the isolation trench structure 30. The electrode connected to the emitter region 136 serves as the cathode of the LIGBT.

[0044] exist Figure 2 and Figure 3 In the embodiment shown, the first N-type doped region 132 and the second N-type doped region 134 are N+ regions, and the emitter region 136 and the collector region 133 are P+ regions.

[0045] In one embodiment of this application, the lateral insulated-gate bipolar transistor further includes a P-type buried region 112 and a top N-type doped region 124. The P-type buried region 112 is located in the drift region 110 between the P-well 116 and the N-well 114, and is situated on both sides of the second segment 34. The top N-type doped region 124 is located in the drift region 110 between the P-well 116 and the N-well 114, and is situated above the P-type buried region 112. The top N-type doped region 124 is situated on both sides of the second segment 34, and the doping concentration of the top N-type doped region 124 is greater than the doping concentration of the drift region 110. The P-type buried region 112 and the top N-type doped region 124 located in the LIGBT body form a superjunction.

[0046] In one embodiment of this application, the lateral insulated gate bipolar transistor (LIGBT) is a silicon-on-insulator (SOI) LIGBT, comprising a substrate 10 and an insulating buried layer 20 on the substrate 10, with a drift region 110 located on the insulating buried layer 20. Further, the LIGBT can be an SOI anode-short-circuited LIGBT. Figure 2 and Figure 3 In the illustrated embodiment, substrate 10 is a P-type silicon substrate, and the material of the buried insulating layer 20 is silicon oxide, such as silicon dioxide. In one embodiment of this application, the bottom of the isolation trench structure 30 extends to the buried insulating layer 20. In one embodiment of this application, the bottom of the P-well 116 extends to the buried insulating layer 20.

[0047] In one embodiment of this application, the lateral insulated gate bipolar transistor further includes a field oxide layer 150 located between the second N-type doped region 134 and the collector region 133, and the gate 138 extends from the edge of the first N-type doped region 134 onto the field oxide layer 150.

[0048] In one embodiment of this application, the gate 138 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 138.

[0049] This application provides a method for manufacturing a lateral insulated gate bipolar transistor, which can be used to manufacture the lateral insulated gate bipolar transistor described in any of the foregoing embodiments. Figure 5 This is a flowchart of a method for manufacturing a lateral insulated gate bipolar transistor according to an embodiment of this application, including the following steps:

[0050] S510, acquire the wafer with the drift region formed.

[0051] In one embodiment of this application, the drift region 110 is an N-type region.

[0052] In one embodiment of this application, step S510 first obtains an SOI wafer, which includes a substrate 10, an insulating buried layer 20 on the substrate 10, and a top semiconductor layer on the insulating buried layer 20. Then, ion implantation (implanting N-type ions) is performed on the top semiconductor layer, and after push-well formation, a drift region 110 is formed on the insulating buried layer 20.

[0053] S520 forms P-wells and N-wells.

[0054] P-well 116 and N-well 114 were formed in the top semiconductor layer by photolithography and ion implantation, respectively.

[0055] S530 forms a segmented isolation groove structure.

[0056] In one embodiment of this application, prior to step S530, a step of forming a P-type buried region 112 and a top N-type doped region 124 in the drift region 110 is further included. The P-type buried region 112 and the top N-type doped region 124 in the LIGBT body and auxiliary semiconductor structure can be formed using the same implantation barrier layer and by high-energy ion implantation, i.e., the P-type buried region 112 and the top N-type doped region 124 in the LIGBT body and auxiliary semiconductor structure can be formed using a single photomask. The P-type buried region 112 and the top N-type doped region 124 are located in the drift region 110 between the P-well 116 and the N-well 114.

[0057] The isolation trench structure 30 extends along the length of the conductive channel of the transverse insulated gate bipolar transistor, and the isolation trench structure 30 forms an opening in the drift region 110 for communication between the two drift regions 110.

[0058] In one embodiment of this application, multiple trenches are formed by photolithography and etching, and then an insulating medium is filled into the trenches to obtain a segmented isolation trench structure 30. In another embodiment of this application, an oxide layer can be deposited in the trenches by SACVD (sub-atmospheric chemical vapor deposition) to form the isolation trench structure 30.

[0059] S540 forms a gate above the P-well and N-well.

[0060] In one embodiment of this application, after filling the trench with an insulating medium, the step further includes forming a field oxide layer 150 on the drift region 110. The gate 138 formed in step S540 extends onto the field oxide layer 150.

[0061] S550 forms the emitter region, collector region, and first N-type doped region.

[0062] The emitter region 136, the collector region 133, and the first N-type doped region 132 are formed using photolithography and ion implantation processes. The emitter region 136 is formed in the P-well 116, the collector region 133 is formed in the N-well 114, the collector region 133 is formed on one side of the isolation trench structure 30, and the first N-type doped region 132 is formed on the other side of the isolation trench structure 30. The doping concentration of the first N-type doped region 132 is greater than the doping concentration of the N-well 114. In one embodiment of this application, the emitter region 136 is formed on both sides of the isolation trench structure 30.

[0063] In one embodiment of this application, the emitter region 136 and the collector region 133 are P-type regions, and the doping concentration of the emitter region 136 is greater than the doping concentration of the P-well 116.

[0064] In one embodiment of this application, step S550 further includes forming a second N-type doped region 134 in the P-well 116, wherein the second N-type doped region 134 is located between the emitter region 136 and the gate 138. In one embodiment of this application, the second N-type doped region 134 is formed on both sides of the isolation trench structure 30.

[0065] S560 short-circuit the first N-type doped region to the collector region.

[0066] In one embodiment of this application, an interlayer dielectric (ILD) layer is formed on the front side of the wafer, and a first N-type doped region 132 is short-circuited to a collector region 133 by forming contact holes and metal interconnects that penetrate the interlayer dielectric layer. In another embodiment of this application, the step of short-circuiting the emitter regions 136 on both sides of the isolation trench structure 30 and short-circuiting them to the second N-type doped regions 134 on both sides of the isolation trench structure 30 is also included.

[0067] The LIGBT manufactured using the aforementioned lateral insulated gate bipolar transistor (IGBT) fabrication method exhibits the following characteristics: when the device is turned off, a large number of electrons in the drift region 110 flow through the opening of the isolation trench structure 30 to the first N-type doped region 132, while holes flow to the P-wells 116 on both sides of the isolation trench structure 30, significantly shortening the LIGBT's tailing time. During conduction modulation, due to the isolation trench structure 30, the drift region 110 located in the auxiliary semiconductor structure region is unaffected by conduction modulation, resulting in a larger resistance in the drift region 110, which suppresses voltage foldback. Furthermore, in unipolar mode, the voltage difference between the N-well 114 and the collector region 133 in the auxiliary semiconductor structure region is greater, meaning the emitter junction will turn on earlier under the same anode voltage. In the unipolar-to-bipolar mode, voltage foldback can be suppressed by adjusting the opening length of the isolation trench structure 30. Additionally, since the LIGBT body and the auxiliary semiconductor structure share a portion of the structure, the manufacturing process is relatively simple.

[0068] The manufacturing method of the lateral insulated gate bipolar transistor in this application is based on the same inventive concept as the lateral insulated gate bipolar transistor. For details not specifically described in the manufacturing method of the lateral insulated gate bipolar transistor, please refer to the above introduction of the lateral insulated gate bipolar transistor.

[0069] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0070] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0071] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A lateral insulated gate bipolar transistor, characterized in that, include: Launch area; P-well, wherein the emission region is located within the P-well; Collection area; N-well, wherein the current collecting region is located in the N-well; The drift region, at least a portion of which is located between the N-well and the P-well; An isolation trench structure is provided in segments and extends along the length of the conductive channel of the transverse insulated gate bipolar transistor. The isolation trench structure has an opening in the drift region for communication between the drift regions on both sides. The P-wells are distributed on both sides of the isolation trench structure, the N-wells are distributed on both sides of the isolation trench structure, and the collector region is located on one side of the isolation trench structure. The first N-type doped region is located on the other side of the isolation trench structure. The doping concentration of the first N-type doped region is greater than that of the N-well. The first N-type doped region is short-circuited to the collector region. The gate is located above the region between the emitter region and the collector region.

2. The lateral insulated gate bipolar transistor according to claim 1, characterized in that, The emitter region and collector region are P-type regions, and the doping concentration of the emitter region is greater than that of the P-well; the emitter region is distributed on both sides of the isolation trench structure; the isolation trench structure includes an insulating medium filled in the trench.

3. The lateral insulated gate bipolar transistor according to claim 2, characterized in that, It also includes a second N-type doped region located in the P-well and on both sides of the isolation trench structure, the second N-type doped region being located between the emitter region and the gate; the emitter regions on both sides of the isolation trench structure are short-circuited and short-circuited with the second N-type doped regions on both sides of the isolation trench structure.

4. The lateral insulated gate bipolar transistor according to claim 3, characterized in that, The first N-type doped region serves as the drain region of the LDMOS, the second N-type doped region serves as the source region of the LDMOS, and the gate also serves as the gate of the LDMOS. The isolation trench structure includes a first segment, a second segment, and a third segment. The second segment is located in the drift region. The P-wells are distributed on both sides of the first segment, the emitter regions are distributed on both sides of the first segment, the second N-type doped region is distributed on both sides of the first segment, the N-wells are distributed on both sides of the third segment, the collector region is located on one side of the third segment, and the first N-type doped region is located on the other side of the third segment.

5. The lateral insulated gate bipolar transistor according to claim 3, characterized in that, It also includes a field oxide layer located between the second N-type doped region and the collector region, wherein the gate extends from the edge of the first N-type doped region to the field oxide layer.

6. The lateral insulated gate bipolar transistor according to claim 1, characterized in that, The drift region is an N-type drift region, and the lateral insulated gate bipolar transistor further includes: The P-type burial area is located in the drift region between the P-well and the N-well, and is located on both sides of the isolation trench structure; The top N-type doped region is located in the drift region between the P-well and the N-well, and above the P-type buried region. The top N-type doped region is located on both sides of the isolation trench structure, and the doping concentration of the top N-type doped region is greater than the doping concentration of the drift region.

7. The lateral insulated gate bipolar transistor according to claim 1, characterized in that, The lateral insulated gate bipolar transistor is a silicon-on-insulator lateral insulated gate bipolar transistor, comprising a substrate and an insulating buried layer on the substrate, wherein the drift region is located on the insulating buried layer.

8. The lateral insulated gate bipolar transistor according to claim 7, characterized in that, The lateral insulated gate bipolar transistor is an anode-short-circuited lateral insulated gate bipolar transistor; and / or The bottom of the P-well extends to the insulating buried layer; and / or The bottom of the isolation groove structure extends to the insulating buried layer.

9. A method for manufacturing a lateral insulated gate bipolar transistor, comprising: Obtain a wafer with a drift region formed; Formation of P-wells and N-wells; A segmented isolation trench structure is formed; The isolation trench structure extends along the length of the conductive channel of the transverse insulated gate bipolar transistor, and the isolation trench structure forms an opening in the drift region for communication between the drift regions on both sides. A gate is formed above the space between the P-well and the N-well; An emitter region, a collector region, and a first N-type doped region are formed; the emitter region is formed in the P-well, the collector region is formed in the N-well, the collector region is formed on one side of the isolation trench structure, and the first N-type doped region is formed on the other side of the isolation trench structure, wherein the doping concentration of the first N-type doped region is greater than the doping concentration of the N-well; The first N-type doped region is short-circuited to the collector region.

10. The method for manufacturing a lateral insulated gate bipolar transistor according to claim 9, characterized in that, Before the step of forming the segmented isolation trench structure, the method further includes the step of forming a P-type buried region and a top N-type doped region in the drift region; the P-type buried region and the top N-type doped region are formed in the drift region between the P-well and the N-well.

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