Annular planar gate segmented IGBT chip and preparation method thereof

Abstract

This application provides a ring-shaped planar gate segmented IGBT chip and its fabrication method, relating to the field of power semiconductor device technology, including N... + The transmit segment is a block unit, each N + The transmit segment block unit includes four N-type cells that are symmetrically distributed. + The emission is divided into blocks; any adjacent N + A current balancing channel is provided between the emitter blocks. The current balancing channel is the exposed area of ​​the P-base region, and all current balancing channels converge at the center of the emitter block unit. The outer contour of the polysilicon gate coincides with the outer contour of the chip, and the inner side of the gate oxide layer of the polysilicon gate is attached with N-type oxide. + The outer edge of the emitter segment unit. This application uses N + The transmitter segmentation block unit will replace the traditional monolithic N + The emission area is divided into four completely symmetrical emission blocks along the plane. A cross-shaped current-carrying equalization channel with the same width is reserved between the four emission blocks. The transverse channel and the longitudinal channel intersect perpendicularly at the center of the chip to form a uniform path for the transverse diffusion of charge carriers.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device technology, and more specifically, to a ring-shaped planar gate segmented IGBT chip and its fabrication method. Background Technology

[0002] Currently, low-voltage, low-power (below 600V / 5A) IGBT chips mainly adopt planar gate or trench gate structures. Among them, planar gate IGBTs have become the first choice for basic applications due to their mature technology and low cost. However, the emitter and gate layout of traditional planar gate IGBTs has the following significant drawbacks: Unreasonable emitter structure: Most existing technologies use an integral strip or square emitter region. After the carriers (electrons) are injected into the P-base region from the emitter region, the lateral diffusion path length is inconsistent. The diffusion path is long and the carrier density is low in the area near the chip edge or gate lead, while the diffusion path is short and the carriers are excessively concentrated in the center of the emitter region. This results in uneven current distribution inside the chip, excessive local current density, and prominent heat concentration. Uneven gate control: Traditional planar gates are mostly single-sided or double-sided layouts, which result in inconsistent carrier injection control in different regions of the emitter region, further exacerbating the uneven electric field distribution and easily causing local hot spots and breakdown risks. Concentrated electric field at the center: Due to the accumulation of charge carriers and the superposition of gate electric fields in the central region of the chip, the electric field strength is significantly higher than that in other regions. Under long-term operation, thermal fatigue is likely to occur, reducing the breakdown voltage stability and lifespan of the chip. The contradiction between process cost and performance: Although trench gate IGBTs can improve current carrying uniformity, they require a new deep etching process, which significantly increases manufacturing costs and reduces yield, making them unsuitable for cost-sensitive requirements in low-voltage and low-power scenarios.

[0003] The aforementioned defects make it difficult for traditional basic IGBT chips to achieve optimal performance in key areas such as power conversion efficiency, reliability, and lifespan, thus limiting their large-scale application in consumer electronics, small-scale industrial control, and other scenarios. Summary of the Invention

[0004] To address the aforementioned problems, this application employs a ring-shaped planar gate segmented IGBT chip, comprising stacked P... + Substrate, N - Drift region, P-base region, N + Emitter region, gate oxide layer and polysilicon gate, Including N + The transmit segment is a block unit, each N + The transmit segment block unit includes four N-type cells that are symmetrically distributed. + The emission is divided into blocks; any adjacent N +A current equalization channel is set between the transmit area blocks. The current equalization channel is the exposed area of ​​the P-base region. All current equalization channels converge at the center of the transmit area block unit. The polysilicon gate has a ring-shaped planar structure, with its outer contour coinciding with the outer contour of the chip. The inner, upper, and lower sides of the polysilicon gate are covered by an inner gate oxide layer, an upper gate oxide layer, and a lower gate oxide layer, respectively. An N-type gate oxide layer is attached to the inner side of the inner gate oxide layer. + The outer edge of the emitter segment unit.

[0005] Optionally, the stacking order is set from bottom to top as P. + Substrate, N - Drift region, P-base region, N + The emitter region, gate oxide layer, and polysilicon gate are disposed above the P-base region. + A collector metal layer is disposed beneath the substrate, N + An emitter metal layer is disposed above the emitter region and the upper gate oxide layer.

[0006] Optionally, the collector metal layer is a Ti-Ni-Au based collector metal, and the emitter metal is an Al based emitter metal.

[0007] Optionally, P + The substrate is boron-doped with a doping concentration of 1×10⁻⁶. 19 ~ 3×10 19 cm -3 N - The drift region is phosphorus-doped with a doping concentration of 8 × 10⁻⁶. 13 ~ 2×10 14 cm -3 The P-based region is boron-doped with a doping concentration of 8 × 10⁻⁶. 16 ~ 2×10 17 cm -3 N + The emitter region is phosphorus-doped with a doping concentration of 5 × 10⁻⁶. 19 ~ 2×10 20 cm -3 The phosphorus doping concentration of the polysilicon gate is 1×10⁻⁶. 20 ~ 3×10 20 cm -3 .

[0008] Optionally, P + Substrate and N - The thickness ratio of the drift region is 1.8~2.2:1, and the thickness of the P-based region is N. - 1 / 9 to 1 / 11 of the thickness of the drift region; N +The thickness of the emitter region is 1 / 4 to 1 / 6 of the thickness of the P-base region, the gate oxide layer is made of SiO2, and the polysilicon gate thickness is 4.5 to 5.5 times the thickness of the gate oxide layer.

[0009] Optionally, the ring-shaped polysilicon gate has a uniform frame width, and the spacing between the inner frame and the outer edge of the chip is consistent, within the same N... + Within the transmitting segment unit, the spacing between adjacent segments is consistent with the width of the current equalization channel.

[0010] Optionally, when the chip memory has more than one N + When the emitter blocks are arranged in a centrally symmetrical and uniform manner around the chip center, the ring structure of the polysilicon gate surrounds all N-cells. + Transmitter segmentation unit.

[0011] Optionally, N - Drift region and P + N is also placed between the substrates + Buffer, N + The buffer layer has a thickness of 4–6 μm and a phosphorus doping concentration of 8 × 10⁻⁶ μm. 17 ~ 2×10 18 cm -3 .

[0012] Optionally, the chip has a rounded square cross-section with a corner radius of 1% to 5% of the side length. + The cross-section of the emission section is a rounded square structure with a corner radius of 1% to 5% of the side length.

[0013] This application also provides a method for fabricating a ring-shaped planar gate segmented IGBT chip. Suitable for fabricating any of the aforementioned ring-shaped planar gate segmented IGBT chips, comprising the following steps: Substrate preparation: Select a high-flatness P substrate. + Boron-doped silicon substrate with a total thickness variation ≤5μm, warpage ≤20μm, and surface roughness ≤0.5nm. The substrate undergoes standard RCA cleaning and chemical mechanical polishing. Epitaxial growth: in P + N epitaxial growth on substrate - In the drift zone, the growth temperature is controlled at 1050℃~1150℃, and the growth rate is 3μm / h~10μm / h. P-based region preparation: The P-based region range is defined by photolithography, boron ions are implanted, and then annealed and activated at 1000℃~1100℃ to form the P-based region; Fabrication of current-carrying equalization channel: The range of the current-carrying equalization channel is defined by photolithography, and the oxide layer on the surface of the P-based region of the channel region is removed by dry etching to expose the P-based region body and form the current-carrying equalization channel. N + Emitter region fabrication: A segmented patterned mask was replaced, and the extent of each emitter region was defined using photolithography. Phosphorus ions were implanted, and the region was annealed and activated at 900℃~1000℃ to form segmented N₂ regions. + Launch area; Gate fabrication: SiO2 gate oxide layer is thermally oxidized and grown in an oxygen atmosphere at 850℃~950℃; after depositing polysilicon and phosphorus doping, a ring-shaped polysilicon gate structure is formed by photolithography or dry etching. Metallization and passivation: An Al-based emitter metal layer and a Ti / Ni / Au-based collector metal layer were prepared, and a SiNx passivation layer was deposited using PECVD to complete the chip fabrication.

[0014] The beneficial effects of the annular planar gate segmented IGBT chip and its fabrication method provided in this application are as follows: (1) Retain the traditional core stack-up structure of IGBT chips (P + Substrate, N - Drift region, P-base region, N + The emitter region, gate oxide layer, and polysilicon gate remain unchanged, without altering the interlayer connectivity, material type, or doping process, thus reducing the difficulty of process adaptation. Only the planar layout of the emitter region, channel, and gate is optimized; the chip's layered structure, doping process, and gate fabrication flow remain the same. Existing IGBT chip production lines require no modification; only the photomask needs to be replaced for mass production.

[0015] (2) Through N + The transmitter segmentation unit will replace the traditional monolithic N + The launch area is divided into four completely symmetrical launch blocks along the planar direction, and the four blocks surround N. + The emitter blocks are evenly arranged in the center, and a cross-shaped current-carrying equalization channel with the same width is reserved between the four emitter blocks. The channel material is the exposed part of the P-base region. The lateral channel and the vertical channel intersect perpendicularly at the center of the chip to form a uniform path for the lateral diffusion of charge carriers.

[0016] (3) The polysilicon gate adopts a ring planar structure. The outer frame is completely aligned with the outer contour of the chip. The inner frame is closely attached to the outer edge of the four emitter blocks through the inner gate oxide layer, ensuring that when the gate voltage is applied, the four blocks receive the control signal synchronously and the carrier injection timing is consistent.

[0017] (4) Only the P-base region exposure point is retained at the chip center (the intersection of the horizontal and vertical channels), and no N-base region is set. +The emitter region or polysilicon gate coverage reduces the risk of electric field concentration in the central area and optimizes the overall electric field distribution. The segmented emitter region and cross-shaped equalization channel allow carriers to be injected synchronously from four segments, with a lateral diffusion path length deviation of ≤5% and an internal chip current density distribution deviation of ≤10%. This alleviates localized heat concentration and reduces the maximum operating temperature difference from 15℃ to less than 5℃. Improved carrier injection uniformity reduces on-state voltage drop fluctuation from ±0.15V to ±0.05V, increases chip power conversion efficiency by 3%~5%, and reduces switching losses to below 5mJ (10kHz operating condition). Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0019] Figure 1 This is a schematic diagram of the planar structure of the ring-shaped planar gate segmented IGBT chip provided in the embodiments of this application; Figure 2 This is a longitudinal cross-sectional view (N) of the annular planar gate segmented IGBT chip provided in the embodiments of this application. + (The junction of the emitter region, gate oxide layer, and polysilicon gate). Figure 3 yes Figure 2 Enlarged view of point A.

[0020] Explanation of reference numerals in the attached figures: 101 - Chip outline; 102 - Current balancing channel; 201 - Emitter metal; 202 - Gate oxide layer; 203 - N + Emitter region; 204 - Polysilicon gate; 205 - P-base region; 206 - N- - Drift zone; 207-P + Substrate; 208 - collector metal. Detailed Implementation

[0021] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0022] Example 1 like Figures 1-3 As shown, this application provides a ring-shaped planar gate segmented IGBT chip, including stacked P... + Substrate 207, N - Drift region 206, P-base region 205, N +Emitter 203, gate oxide layer 202, and polysilicon gate 204, including N + The launch area is divided into 203 blocks, each containing N blocks. + The 203th block of the launch area includes four N blocks that are symmetrically distributed. + The launch area is divided into 203 blocks; any adjacent N + A current equalization channel 102 is provided between the segments of the launch area 203. The current equalization channel 102 is the exposed area of ​​the P-base area 205. All current equalization channels 102 converge at the center of the launch area segment unit. The polysilicon gate 204 has a ring-shaped planar structure, with its outer contour coinciding with the outer contour of the chip. The inner, upper, and lower sides of the polysilicon gate 204 are covered with an inner gate oxide layer, an upper gate oxide layer, and a lower gate oxide layer, respectively. An N-type gate oxide layer is attached to the inner side of the inner gate oxide layer. + The outer edge of the 203 segment unit of the launch area.

[0023] Because in the core layer structure of the chip, P + Substrate 207 and N - Drift region 206 and P-base region 205, N + The size ratios of the emitter region 203, the gate oxide layer 202, and the polysilicon gate 204 are quite different. In order to represent the P-base region 205 and N-base region 204, the following measures are taken. + The relative positions of emitter region 203, gate oxide layer 202, and polysilicon gate 204 are specified in the appendix to the specification. Figure 2 In the middle, P + Substrate 207 and N - Drift region 206 is not drawn to scale; only the P base region 205 and N are shown. + The emitter region 203, gate oxide layer 202, and polysilicon gate 204 are drawn using the data scale of this embodiment.

[0024] The IGBT chip is a slightly rounded square. In this embodiment, the planar dimensions are 10mm × 10mm, and the corner radius R = 0.4mm. The layered structure from bottom to top is as follows: P + Substrate 207: 200 μm thick, boron doped, doping concentration 1 × 10⁻⁶ 19 cm -3 As a collector, it is responsible for collecting hole carriers; N - Drift region 206: 100 μm thick, phosphorus-doped, doping concentration 1 × 10⁻⁶ 14 cm -3 It withstands reverse high voltage, providing a transmission channel for charge carriers; P-based region 205: 10 μm thick, boron doped, doping concentration 1 × 10⁻⁶ 17 cm-3 Adjust the current carrier sub-path, including the exposed portion of the cross-shaped current carrier equalization channel.

[0025] N + Emitter region 203: 2 μm thick, phosphorus doped, doping concentration 5 × 10⁻⁶ 19 cm -3 It adopts a four-quadrant block structure and is responsible for injecting electron carriers; Gate oxide layer 202: 0.1μm thick, made of SiO2, isolates the polysilicon gate 204 and the P-base region 205 to prevent leakage; Polysilicon gate 204: 0.5 μm thickness, phosphorus doping concentration 1 × 10⁻⁶ 20 cm -3 It has a ring structure that wraps around the outside of the four emission zones.

[0026] Preferred, P + Substrate and N - The thickness ratio of the drift region is 1.8~2.2:1, and the thickness of the P-based region is N. - 1 / 9 to 1 / 11 of the thickness of the drift region; N + The thickness of the emitter region is 1 / 4 to 1 / 6 of the thickness of the P-base region, and the thickness of the polysilicon gate is 4.5 to 5.5 times the thickness of the gate oxide layer.

[0027] Based on the above proportional relationships, the size range is further optimized as follows: P + The substrate thickness is 180~220μm, N - The thickness of the drift region is 90~110 μm, the thickness of the P-based region is 9~12 μm, and the thickness of the N-based region is... + The thickness of the emitter region is 1.8~2.5μm, the thickness of the gate oxide layer is 0.09~0.11μm, and the thickness of the polysilicon gate is 0.45~0.55μm.

[0028] Regarding planar structures, the N provided in this application + The 203-block unit of the launch area constructs a four-quadrant launch area block, N + Launch area 203 has a total coverage area of ​​approximately 60mm. 2 (Consistent with the traditional monolithic design), it is divided into 4 identical square blocks, each block measuring 3.88mm × 3.88mm with a corner radius R = 0.19mm; the 4 blocks are evenly distributed around the center of the chip, and the spacing between adjacent blocks is consistent with the width of the cross channel; Cross-shaped current-carrying equalization channel: The channel width is 0.5mm, the material is the exposed part of the P-base region 205, the horizontal channel extends along y=4.75~5.25mm, the vertical channel extends along x=4.75~5.25mm, and the two intersect perpendicularly at the center of the chip (x=5mm, y=5mm). The channel runs through the entire emitter area and fits the edges of the 4 blocks without gaps; The ring-shaped polysilicon gate 204 has an outer frame that completely overlaps with the outer contour 101 of the chip (x=0~10mm, y=0~10mm), an inner frame with coordinates x=0.87~9.13mm and y=0.87~9.13mm, a frame width of 0.87mm, and a corner radius R=0.4mm. It closely fits the outer edges of the four emitter blocks to ensure that the gate has consistent control over each block. Central P-base region 205 exposure point: such as Figure 1 As shown, the central position and the surrounding cross-shaped current-carrying equalization channel 102 form an integrated connected area.

[0029] In this design, the central location retains the complete body of the P-base region 205, without covering the N-base region. + The emitter region 203 or polysilicon gate 204 belongs to the pure P-type channel conduction region with high conduction efficiency. This structure is essentially an extension and convergence of the current equalization channel 102 in the central region, and its doping type, concentration and interface characteristics are completely consistent with the surrounding current equalization channel 102.

[0030] When a forward drive voltage is applied to the gate, a conductive channel is induced to form on the surface of the gate oxide layer 202, with 4 N-channels. + Under the synchronous control of the ring gate, the emitter region 203 is divided into blocks, uniformly injecting electrons (charge carriers) into the P-base region 205. As the electrons diffuse laterally in the P-base region 205, they are dispersed through the cross-shaped current-carrier equalization channels between adjacent blocks, preventing carrier aggregation in a single region. Subsequently, the electrons pass through the P-base region 205 and enter the N-base region. - Drift zone 206, longitudinally transported to P along the drift zone + Substrate 207 recombines with holes to form a conducting current; due to the symmetrical distribution of the four blocks and the uniform diffusion path provided by the balanced channel, the current density distribution inside the chip is uniform, the heat concentration phenomenon is significantly improved, and the central exposed point reduces the risk of electric field superposition, further improving the reliability of operation.

[0031] Example 2 This embodiment provides a method for fabricating a ring-shaped planar gate modular IGBT chip, which employs an IGBT chip photolithography-doping process. The specific steps are as follows: Substrate preparation: Select a high-flatness P substrate. +Boron-doped silicon substrates are required to have a total thickness variation (TTV) ≤ 5 μm, a warpage (Bow / Warp) ≤ 20 μm, and a surface roughness (Ra) ≤ 0.5 nm. The substrates undergo standard RCA cleaning and chemical mechanical polishing (CMP) treatment. Epitaxial growth: in P + N epitaxial growth on substrate 207 - Drift zone 206, growth temperature controlled at 1100℃, growth rate 5μm / h; P-based region 205 implantation: The P-based region 205 was defined by photolithography, and boron ions were implanted (dose 1×10⁻⁶). 13 cm -2 ), and then annealed at 1050℃ to activate it, forming the P-based region 205; Cross-shaped channel etching: The cross-shaped channel range is defined by photolithography, and the oxide layer on the surface of the P-base region 205 in the channel area is removed by dry etching to expose the P-base region 205 body and form the current-carrying equalization channel 102. N + Fabrication of emitter region 203: Replace the segmented patterned mask, define the four emitter region segments using photolithography, and implant phosphorus ions (dose 5 × 10⁻⁶). 15 cm -2 Annealing at 950℃ activates the N2O2 to form a segmented N2O2 structure. + Launch area 203; Gate oxide layer 202 growth: A 0.1 μm thick SiO2 oxide layer is grown by thermal oxidation at a temperature of 900℃ in an oxygen atmosphere; Polysilicon gate 204 fabrication: 0.5 μm thick polysilicon is deposited, and a ring gate structure is formed by photolithography and etching; Metallization and passivation: Al-based emitter metal 201 (2 μm thick) and Ti / Ni / Au-based collector metal 208 (5 μm thick) were prepared, and SiNx passivation layer was deposited by PECVD to complete chip fabrication.

[0032] The entire process is fully compatible with traditional IGBT chips, except for N... + The photolithography steps for emitter region 203 and gate are performed by replacing the mask, without the need for additional process steps or equipment.

[0033] Example 3 N - Drift zone 206 and P + N is also disposed between the substrates 207 + Buffer, N + The buffer layer is 5 μm thick and has a phosphorus doping concentration of 1 × 10⁻⁶. 18 cm -3 .

[0034] To adapt to high-voltage scenarios above 1200V, this embodiment uses N... - Drift zone 206 and P + A 5μm thick layer of N2 was added between substrates 207. + The buffer is optimized for withstand voltage and switching characteristics, while the rest of the structure remains unchanged.

[0035] Example 4 When the chip memory has more than one N + When the emitter region 203 is divided into blocks, all emitter region blocks are arranged in a centrally symmetrical and uniform manner around the chip center, and the ring structure of the polysilicon gate 204 surrounds all N-type emitter blocks. + Launch area 203 block unit.

[0036] This embodiment provides a current-spreading variant. In order to improve the current carrying capacity, the number of emitter blocks is increased to 6 or 8, while keeping the ring gate structure unchanged. Only the block size and channel width are adjusted to ensure the uniformity of the total coverage area and current carrying path.

[0037] This application addresses the problems of uneven carrier injection in the emitter region, concentrated local heat generation, excessively high central electric field strength, and high trench gate process cost in existing basic IGBT chips. It provides a ring-shaped planar gate block-type IGBT chip with simple structure, low process difficulty, and uniform current distribution. It does not require complex doping or additional layer structures. It can achieve the requirements of current uniformity, reliability and low cost simply by optimizing the planar layout.

[0038] The ring-shaped planar gate modular IGBT chip and its fabrication method provided in this application retain the traditional core stack-up structure of IGBT chips (P + Substrate 207, N - Drift region 206, P-base region 205, N + The emitter region 203, gate oxide layer 202, and polysilicon gate 204 do not change the interlayer connection relationship, material type, or doping process, thus reducing the difficulty of process adaptation and making it compatible with existing production lines.

[0039] This application will transform the traditional monolithic N + The emitter region 203 is divided into four completely symmetrical "square emitter blocks" along the planar direction. The four blocks are evenly arranged around the center of the chip (adjacent blocks are at a 90° angle). The total coverage area of ​​the square emitter blocks is consistent with that of a traditional monolithic emitter region, thus ensuring that the current carrying capacity does not decrease. A cross-shaped current-carrying equalization channel 102 with the same width is reserved between the four emitter blocks. The channel material is the exposed part of the P-base region 205. The lateral channel and the vertical channel intersect perpendicularly at the center of the chip, forming a uniform path for the lateral diffusion of charge carriers. The channel width is strictly matched with the size of the emitter blocks to avoid deviation of the diffusion path.

[0040] The polysilicon gate 204 adopts a ring-shaped planar structure, with its outer frame completely overlapping the outer contour 101 of the chip. The inner frame is close to the outer edge of the four emitter blocks, ensuring that the four blocks synchronously receive control signals and that the carrier injection timing is consistent when the gate voltage is applied. The chip center (the intersection of the cross channels) retains the P-base region 205 for exposure, and no N-base region is set there. + The emitter area 203 or polysilicon gate 204 is covered to reduce the risk of electric field concentration in the central area and optimize the overall electric field distribution.

[0041] The segmented emitter area and cross-shaped equalization channel allow carriers to be injected synchronously from 4 segments, with a lateral diffusion path length deviation of ≤5%, a current density distribution deviation of ≤10% inside the chip, and the local heat concentration phenomenon is alleviated, reducing the maximum operating temperature difference from 15℃ to less than 5℃. Based on the above technical design, this application optimizes the planar layout of the emitter region, channel and gate without changing the chip layer structure, doping process and gate preparation process. Therefore, during production, there is no need to modify the existing IGBT chip production line. Only the photomask needs to be replaced for mass production. The process cost remains basically unchanged and the yield is increased to over 95%.

[0042] It alleviates the phenomenon of concentrated heat generation, reduces the risk of concentrated central electric field, reduces the risk of chip thermal fatigue by 40%, improves the breakdown voltage stability under 600V reverse withstand voltage by more than 15%, extends the service life by 20%, and controls the leakage current to below 1μA.

[0043] The uniformity of charge carrier injection is improved, the on-state voltage drop fluctuation is reduced from ±0.15V to ±0.05V, the chip power conversion efficiency is improved by 3%~5%, and the switching loss is reduced to below 5mJ (10kHz operating condition), making it suitable for general power scenarios with medium and low voltage below 1200V. In addition, the number (6 or 8) or size of the emitter blocks can be adjusted to flexibly adapt to different current requirements from 3A to 10A. The ring gate structure does not require synchronous adjustment and has strong process compatibility.

[0044] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A ring-shaped planar gate segmented IGBT chip, comprising stacked P... + Substrate, N - Drift region, P-base region, N + The emitter region, gate oxide layer, and polysilicon gate are characterized by: Including N + The transmission segmentation block unit, each of the N + The transmit segment block unit includes four N-type cells that are symmetrically distributed. + The transmission segment is divided into blocks; any adjacent N + A current equalization channel is provided between the transmit area blocks. The current equalization channel is the exposed area of ​​the P-base region. All the current equalization channels converge at the center of the transmit area block unit. The polysilicon gate is a ring-shaped planar structure, with its outer contour coinciding with the outer contour of the chip. An inner gate oxide layer, an upper gate oxide layer, and a lower gate oxide layer are respectively covering the inner, upper, and lower sides of the polysilicon gate. The N-type gate oxide layer is attached to the inner side of the inner gate oxide layer. + The outer edge of the emitter segment unit.

2. The annular planar gate segmented IGBT chip according to claim 1, characterized in that: The stacking arrangement is configured in a bottom-to-top stacking order of P. + Substrate, N - Drift region, P-base region, the N + The emitter region, gate oxide layer, and polysilicon gate are disposed above the P-base region, wherein the P-base region... + A collector metal layer is disposed beneath the substrate, wherein the N + An emitter metal layer is disposed above the emitter region and the upper gate oxide layer.

3. The annular planar gate segmented IGBT chip according to claim 2, characterized in that: The current collector metal layer is a Ti-Ni-Au based current collector metal, and the emitter metal is an Al based emitter metal.

4. The annular planar gate segmented IGBT chip according to claim 1, characterized in that: The P + The substrate is boron-doped with a doping concentration of 1×10⁻⁶. 19 ~ 3×10 19 cm -3 The N - The drift region is phosphorus-doped with a doping concentration of 8 × 10⁻⁶. 13 ~ 2×10 14 cm -3 ; The P-based region is boron-doped with a doping concentration of 8 × 10⁻⁶. 16 ~ 2×10 17 cm -3 The N + The emitter region is phosphorus-doped with a doping concentration of 5 × 10⁻⁶. 19 ~ 2×10 20 cm -3 The phosphorus doping concentration of the polysilicon gate is 1×10⁻⁶. 20 ~ 3×10 20 cm -3 .

5. The annular planar gate segmented IGBT chip according to claim 4, characterized in that: The P + Substrate and N - The thickness ratio of the drift region is 1.8~2.2:1, and the thickness of the P-based region is N. - 1 / 9 to 1 / 11 of the thickness of the drift region; N + The thickness of the emitter region is 1 / 4 to 1 / 6 of the thickness of the P-base region, the gate oxide layer is made of SiO2, and the thickness of the polysilicon gate is 4.5 to 5.5 times the thickness of the gate oxide layer.

6. The annular planar gate segmented IGBT chip according to claim 1, characterized in that: The ring-shaped polysilicon gate has a uniform frame width, and the spacing between the inner frame and the outer edge of the chip is consistent. Within the same N... + Within the transmitting segment unit, the spacing between adjacent segments is consistent with the width of the current equalization channel.

7. The annular planar gate segmented IGBT chip according to claim 1, characterized in that: When the chip memory has more than one N + When the emitter blocks are arranged in a centrally symmetrical and uniform manner around the chip center, the ring structure of the polysilicon gate surrounds all N-type emitter blocks. + Transmitter segmentation unit.

8. The annular planar gate segmented IGBT chip according to claim 1, characterized in that: The N - Drift region and P + N is also placed between the substrates + Buffer, the N + The buffer layer has a thickness of 4–6 μm and a phosphorus doping concentration of 8 × 10⁻⁶ μm. 17 ~ 2×10 18 cm -3 .

9. The annular planar gate segmented IGBT chip according to claim 1, characterized in that: The chip has a rounded square cross-section with a corner radius of 1% to 5% of the side length. The N... + The cross-section of the emission section is a rounded square structure with a corner radius of 1% to 5% of the side length.

10. A method for fabricating a ring-shaped planar gate segmented IGBT chip, characterized in that: The method for fabricating a ring-shaped planar gate segmented IGBT chip as described in any one of claims 1-9 includes the following steps: Substrate preparation: Select a high-flatness P substrate. + Boron-doped silicon substrates with total thickness variation ≤5μm, warpage ≤20μm, and surface roughness ≤0.5nm are subjected to standard RCA cleaning and chemical mechanical polishing. Epitaxial growth: in P + N epitaxial growth on substrate - In the drift zone, the growth temperature is controlled at 1050℃~1150℃, and the growth rate is 3μm / h~10μm / h. P-based region preparation: The P-based region range is defined by photolithography, boron ions are implanted, and then annealed and activated at 1000℃~1100℃ to form the P-based region; Fabrication of current-carrying equalization channel: The range of the current-carrying equalization channel is defined by photolithography, and the oxide layer on the surface of the P-based region of the channel region is removed by dry etching to expose the P-based region body and form the current-carrying equalization channel. N + Emitter fabrication: A segmented patterned mask was replaced, and the extent of each emitter region was defined using photolithography. Phosphorus ions were implanted, and the region was annealed and activated at 900℃~1000℃ to form segmented N₂ regions. + Launch area; Gate fabrication: SiO2 gate oxide layer is thermally oxidized and grown in an oxygen atmosphere at 850℃~950℃; after depositing polysilicon and phosphorus doping, a ring-shaped polysilicon gate structure is formed by photolithography or dry etching. Metallization and passivation: An Al-based emitter metal layer and a Ti / Ni / Au-based collector metal layer were prepared, and a SiNx passivation layer was deposited using PECVD to complete the chip fabrication.

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