Epitaxial structure of vertical transistor and preparation method and application thereof

Abstract

The application discloses an epitaxial structure of a vertical transistor and a preparation method and application thereof, and belongs to the technical field of semiconductor material growth. The application proposes a new method of combining an AlN / GaN composite barrier layer scheme with in-situ etching of an organic halide to prepare a high-performance CAVET epitaxial structure. The AlN / low-temperature GaN composite barrier layer design adopted by the application fully utilizes the high bond energy advantage of AlN, reduces the diffusion coefficient of Mg atoms in the barrier layer, and can reduce the thickness of the barrier layer. Meanwhile, the high critical breakdown field strength of AlN can further improve the voltage resistance of the device. The method for constructing the epitaxial structure of the CAVET proposed by the application can not only effectively improve the mobility and density of the two-dimensional electron gas, but also can realize a high-quality secondary epitaxial interface with low impurity content and low damage, and effectively improve the forward characteristics and reverse characteristics of the device.

Description

Technical Field

[0001] This invention specifically relates to an epitaxial structure of a vertical transistor, its fabrication method, and its application, belonging to the field of semiconductor material growth technology. Background Technology

[0002] Group III nitride semiconductor materials have broad application prospects in power electronics, microwave radio frequency and optoelectronics due to their direct wide bandgap, strong piezoelectric effect, high saturated electron drift velocity and easy fabrication of heterojunction structures. They can be widely used in radar, mobile communication, electric vehicles, sterilization and disinfection and medical fields. The market size is huge and growing rapidly.

[0003] Currently, lateral structure devices, represented by high electron mobility transistors (HEMTs), are the main research direction for gallium nitride (GaN) power electronic devices. However, HEMT devices face problems such as low power density, difficult thermal management, and lack of avalanche capability. In contrast, advanced vertical structure power electronic devices are expected to overcome these problems and further unleash the material potential of GaN. The most representative vertical structure device is the current-hole vertical transistor (CAVET). Its structure combines the structures of HEMTs and junction field-effect transistors (JFETs), utilizing the advantages of low on-resistance brought by high electron concentration and high mobility two-dimensional electron gas, while using the vertical transport of current to improve power density, reduce thermal management difficulty, and significantly improve device reliability. However, due to the current lack of efficient P-type selected doping technology for GaN-based materials, the fabrication of CAVET devices currently faces great difficulties.

[0004] According to relevant literature, there are currently two main technical solutions for fabricating CAVET devices: one is that the electron blocking layer is achieved by Mg ion implantation, and then the active region composed of AlGaN / GaN heterostructure is achieved by secondary epitaxy, which is the so-called "ion implantation-secondary epitaxy" hybrid solution; the other is that the electron blocking layer is achieved by primary epitaxy + etching of the opening region, and the 2DEG active region (hereinafter referred to as "active region") composed of AlGaN / GaN heterostructure is also achieved by secondary epitaxy, which is the so-called "etching-secondary epitaxy" solution.

[0005] For CAVET epitaxial structures fabricated using a hybrid "ion implantation-secondary epitaxy" approach, the performance falls short of expectations due to the immaturity of Mg ion implantation technology. For CAVET epitaxial structures fabricated using the secondary epitaxy approach, current main problems include the degradation of two-dimensional electron gas characteristics caused by the diffusion of Mg impurities from the electron blocking layer into the active region, and high impurity concentration and etching damage at the secondary epitaxy interface. To address the Mg diffusion problem, current solutions involve placing a diffusion barrier layer between the electron blocking layer and the active region to reduce the impact of Mg impurities on the two-dimensional electron gas performance. Regarding the secondary epitaxy interface problem, current solutions involve wet processing to reduce the impurity content and etching damage at the interface. However, due to the imperfections in the barrier layer structure and the inherent limitations of wet processing, the performance of current CAVET devices remains below expectations.

[0006] For Mg diffusion barrier layers, the current mainstream approach is a single-layer GaN insertion layer structure, such as [Shibata, D. et al. in 2016 IEEE International Electron Devices Meeting (IEDM). 10.11.11-10.11.14.] and [Chowdhury, S. et al. Crystals 13, 709 (2023).]. The drawback of this structure is that GaN has a low bond energy, resulting in a high diffusion coefficient for Mg atoms. Therefore, to achieve a good Mg diffusion barrier effect, the barrier layer needs to be thickened, which reduces gate control capability. In addition, the InGaN barrier layer technology proposed in CN116607210A can also be used to reduce the diffusion of Mg impurities into the channel layer. However, due to the low critical breakdown field strength of InGaN itself and the leakage problem caused by In atom enrichment in dislocations, CAVET devices fabricated using this approach face the risk of reduced breakdown voltage.

[0007] For secondary epitaxial interface treatment technology, the current mainstream approach is to remove interface contamination and etching damage through wet processing, such as [Noshin et al., Semiconductor Science and Technology, 37, 075018.], [Tajima et al., Journal of Crystal Growth, 2019, 509, 129-132.], [He, J. et al., Applied Physics Express, 2019, 12, 055507.], etc. However, after wet processing, the sample surface will inevitably suffer secondary contamination from impurities in the air, making efficient removal impossible. For etching damage, the biggest problem with wet processing is the difficulty in completely removing the etching damage layer. In CAVET fabrication, the ICP etching depth often exceeds 500 nm, resulting in etching damage layers on the order of hundreds of nanometers. Because GaN has high bond energy, wet cleaning at room temperature can only remove etching damage layers on the nanometer scale, making efficient repair of etching damage difficult. Besides wet etching, in-situ H2 etching within the MOCVD chamber has also been used to repair etching damage, as seen in [Zhong, Y. et al., ACS Applied Materials & Interfaces, 2019, 11, 21982-21987]. However, similar to wet etching, limited by the low decomposition rate, in-situ H2 etching struggles to achieve efficient repair of etching damage. CN116457946A also claims to use in-situ H2 etching for interface impurity treatment, but according to our experimental results, in-situ H2 etching alone is ineffective in removing interface Si impurities and cannot achieve efficient removal. Since interface Si impurities significantly impact the performance of CAVET devices, the performance improvement of in-situ H2 etching for CAVET is limited. Summary of the Invention

[0008] This invention mainly innovates the structure of the diffusion barrier layer and the method of secondary epitaxial interface processing, and provides an epitaxial structure of a vertical transistor, its fabrication method and application, thereby overcoming the shortcomings of the prior art.

[0009] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0010] The first aspect of this invention provides a method for fabricating an epitaxial structure of a vertical transistor, comprising:

[0011] A growth template is provided, the growth template comprising an n-type semiconductor layer, a drift region, a p-type semiconductor layer and a Mg barrier layer stacked sequentially along its own longitudinal direction, the Mg barrier layer comprising at least one first barrier layer and at least one second barrier layer stacked along the longitudinal direction of the growth template, the first barrier layer being an Al-containing III-V group nitride layer, the second barrier layer being a Ga-containing III-V group nitride layer, and the topmost layer of the Mg barrier layer being the second barrier layer;

[0012] The growth template is patterned and etched to form a groove structure, wherein the groove opening is located in the Mg barrier layer and the groove bottom is located in the drift region;

[0013] The etching interface of the groove structure formed by etching is etched in situ to decompose the surface material near the etching interface in a step flow mode.

[0014] A secondary epitaxial growth of a channel layer is performed in the groove structure, and a heterojunction is grown on the channel layer and a cap layer is grown on the heterojunction.

[0015] A second aspect of the present invention provides an epitaxial structure for a vertical transistor, wherein the epitaxial structure for the vertical transistor is obtained by a method for fabricating the epitaxial structure for the vertical transistor.

[0016] A third aspect of the present invention provides a vertical transistor, the vertical transistor including an epitaxial structure of the vertical transistor.

[0017] Furthermore, the vertical transistor includes a current aperture vertical electron transistor.

[0018] A fourth aspect of the present invention provides a method for improving the performance of a vertical transistor, comprising: fabricating the epitaxial structure of the vertical transistor using a method for fabricating the epitaxial structure of the vertical transistor.

[0019] Compared with the prior art, the advantages of the present invention include:

[0020] This invention employs a first barrier layer and a second barrier layer stacked to form a Mg barrier layer. Compared with a conventional single-layer GaN barrier layer, this can better reduce the diffusion of Mg atoms from the electron barrier layer to the channel layer, thereby reducing the Mg impurity concentration in the channel layer, increasing the concentration and mobility of the two-dimensional electron gas in the channel layer, reducing sheet resistance, and thus reducing the on-resistance of the CAVET device.

[0021] This invention utilizes in-situ etching technology to simultaneously remove impurities from the secondary epitaxial interface and repair damage caused by dry etching. Because the in-situ etching and the secondary epitaxy of the channel layer are performed continuously, secondary contamination of impurities can be avoided, achieving extremely high impurity removal efficiency.

[0022] The in-situ etching technology used in this invention can remove the etch-damaged layer layer by layer, efficiently repair the etch damage caused by dry etching while ensuring a smooth interface, prepare a high-quality secondary epitaxial interface, and improve the off-state breakdown voltage of CAVET devices.

[0023] In this invention, the thickness of the Mg barrier layer and the in-situ etching depth can be designed collaboratively. The thickness of the first barrier layer cannot be too thick, nor can it appear on top of the Mg barrier layer. The thickness of the second barrier layer cannot be too thin, otherwise the barrier effect on Mg diffusion will be insufficient. Correspondingly, the upper limit of the thickness of the second barrier layer can be higher, because it is also a sacrificial layer in the secondary epitaxial interface processing process, and a part of it will be etched away. Ultimately, the thickness of the second barrier layer is determined by the growth thickness and the etched portion during the interface processing. The thickness of the second barrier layer will also affect the final threshold voltage and on-resistance of the device. This invention collaboratively designs the thickness of the Mg barrier layer and the in-situ etching depth to jointly regulate the threshold voltage and saturation current of the device, enriching the design and manufacturing dimensions of the device.

[0024] This invention utilizes in-situ etching technology before secondary epitaxy, employing a mixed gas of hydrogen, ammonia, and tert-butyl chloride to etch GaN. This enables efficient removal of impurities at the GaN secondary epitaxy interface and high-quality repair of dry etching damage, significantly improving device performance. Attached Figure Description

[0025] Figure 1 This is a flowchart illustrating the fabrication process of an epitaxial structure for a CAVET (Current Aperture Vertical Electron Transistor) device, as provided in a typical embodiment of the present invention.

[0026] Figure 2a The Mg impurity concentration distribution curve in the epitaxial structure of the depletion-type CAVET in Comparative Example 1;

[0027] Figure 2b This is the Mg impurity concentration distribution curve in the epitaxial structure of the depleted CAVET in Example 1;

[0028] Figure 3a The capacitance-voltage curve and sheet resistance of the epitaxial structure of the depletion-type CAVET in Comparative Example 1 are shown.

[0029] Figure 3b The capacitance-voltage curve and sheet resistance of the epitaxial structure of the depletion-type CAVET in Example 1;

[0030] Figure 4 This refers to the surface morphology of the groove structure after in-situ etching in S13 in Example 2;

[0031] Figure 5aThe silicon impurity concentration distribution in the epitaxial structure of the enhanced CAVET obtained in Comparative Example 2;

[0032] Figure 5b The silicon impurity concentration distribution in the epitaxial structure of the enhanced CAVET obtained in Example 2;

[0033] Figure 6 This is the breakdown voltage curve of the epitaxial structure of the enhanced CAVET in Example 3;

[0034] Figure 7 This is the silicon impurity concentration distribution curve in the epitaxial structure of the enhanced CAVET obtained in Comparative Example 3. Detailed Implementation

[0035] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0036] This invention employs an "etch-secondary epitaxy" scheme to realize the epitaxial structure of CAVET (see details). Figure 1 ).

[0037] To address the above problems, this invention proposes a novel method combining an AlN / GaN composite barrier layer scheme with in-situ organic halide etching to fabricate high-performance CAVET epitaxial structures. The AlN / low-temperature GaN composite barrier layer design employed in this invention fully utilizes the high bond energy of AlN to reduce the diffusion coefficient of Mg atoms in the barrier layer, thereby reducing the barrier layer thickness. Simultaneously, the high critical breakdown field strength of AlN can further improve the device's breakdown voltage.

[0038] This invention utilizes a composite barrier layer, formed by a first barrier layer such as AlN of a specified thickness and a second barrier layer such as low-temperature GaN of a specified thickness, as the Mg barrier layer. Compared to a conventional single-layer GaN barrier layer, this composite layer effectively reduces the diffusion of Mg atoms from the electron barrier layer into the channel layer, thereby lowering the Mg impurity concentration in the channel layer, increasing the concentration and mobility of the two-dimensional electron gas (2DEG) in the channel layer, reducing sheet resistance, and ultimately lowering the on-resistance of the caveat. However, if a thick AlN barrier layer is used, on the one hand, the lattice mismatch strain it introduces may lead to cracks, causing device failure; on the other hand, a thick AlN layer can shield the electron barrier layer from the depletion of the 2DEG, resulting in a negative shift in the threshold voltage and making it difficult to fabricate enhancement-mode devices. Therefore, considering both the blocking effect of Mg impurities and the device's threshold voltage, the AlN / GaN composite barrier layer is the optimal choice. Regarding the thickness of both layers, the thickness of the first barrier layer (AlN, etc.) should not be too thick, nor should it appear at the top of the composite barrier layer; the thickness of the second barrier layer (GaN, etc.) should not be too thin, otherwise the blocking effect on Mg diffusion will be insufficient. Correspondingly, the upper limit of the thickness of the second barrier layer, such as GaN, can be higher, because it is also a sacrificial layer in the secondary epitaxial interface processing, and a portion of it will be etched away. Ultimately, the thickness of the second barrier layer, such as GaN, is determined by both the growth thickness and the portion etched during the interface processing. The thickness of the second barrier layer, such as GaN, also affects the final threshold voltage and on-resistance of the device. Therefore, the thickness of the composite barrier layer and the in-situ etching depth can be designed in a coordinated manner to control the device threshold voltage and saturation current.

[0039] The organic halide in-situ etching technology used in this invention can achieve high-rate, step-flow mode decomposition of GaN, while also achieving efficient removal of impurities at the secondary epitaxial interface and efficient repair of etching damage, thus preparing a high-quality secondary epitaxial interface and improving CAVET performance.

[0040] The first aspect of this invention provides a method for fabricating an epitaxial structure of a vertical transistor, comprising:

[0041] A growth template is provided, the growth template comprising an n-type semiconductor layer, a drift region, a p-type semiconductor layer and a Mg barrier layer stacked sequentially along its own longitudinal direction, the Mg barrier layer comprising at least one first barrier layer and at least one second barrier layer stacked along the longitudinal direction of the growth template, the first barrier layer being an Al-containing III-V group nitride layer, the second barrier layer being a Ga-containing III-V group nitride layer, and the topmost layer of the Mg barrier layer being the second barrier layer;

[0042] The growth template is patterned and etched to form a groove structure, wherein the groove opening is located in the Mg barrier layer and the groove bottom is located in the drift region;

[0043] The etching interface of the groove structure formed by etching is etched in situ to decompose the surface material near the etching interface in a step flow mode.

[0044] A secondary epitaxial growth of a channel layer is performed in the groove structure, and a heterojunction is grown on the channel layer and a cap layer is grown on the heterojunction.

[0045] Furthermore, the thickness of the first barrier layer is less than the thickness of the second barrier layer.

[0046] Furthermore, the thickness t2 of the first barrier layer is 0.2nm to 20nm, and the thickness t3 of the second barrier layer is 10nm to 1000nm.

[0047] Furthermore, the first barrier layer and the second barrier layer are stacked alternately.

[0048] Furthermore, the material of the first barrier layer includes AlN, AlGaN, AlInN, or AlInGaN, but is not limited thereto, and the material of the second barrier layer includes GaN or InGaN, but is not limited thereto.

[0049] In a more specific implementation, the second barrier layer is made of GaN, and the growth temperature of GaN is 500℃~800℃.

[0050] In another more specific implementation, the first barrier layer is made of AlInN, where the In content is less than 5% and the growth temperature is less than 800°C.

[0051] In another more specific embodiment, the first barrier layer is made of AlGaN, and the Al content in AlGaN is greater than 80%.

[0052] In another more specific embodiment, the first barrier layer is made of AlInGaN, where the Al content is greater than 80% and the growth temperature is less than 800°C.

[0053] Furthermore, the in-situ etching agent used in the in-situ etching includes one or more of hydrogen, halogenated organic compounds, and ammonia.

[0054] Furthermore, the halogenated organic compound includes, but is not limited to, at least one of tert-butyl chloride and tert-butyl fluorine.

[0055] Furthermore, the etching rate of the in-situ etching is greater than 5 nm / min and less than 150 nm / min.

[0056] Furthermore, the etching temperature of the in-situ etching is 800℃~1050℃, the etching pressure is 50mbar~800mbar, and the etching depth is less than the thickness of the second barrier layer located at the top layer.

[0057] Furthermore, the n-type semiconductor layer, the drift region, and the p-type semiconductor layer are all made of III-V group compounds.

[0058] Furthermore, the materials of the n-type semiconductor layer, the drift region, and the p-type semiconductor layer include at least one of GaN, AlGaN, InGaN, and AlN.

[0059] In a more specific embodiment, the method for fabricating the epitaxial structure of the vertical transistor includes: growing an n-type semiconductor layer, a drift region, a p-type semiconductor layer, and a Mg barrier layer sequentially stacked on a substrate to obtain the growth template; or, first growing a nucleation layer and a buffer layer sequentially stacked on a substrate, and then growing an n-type semiconductor layer, a drift region, a p-type semiconductor layer, and a Mg barrier layer sequentially stacked on the buffer layer to obtain the growth template.

[0060] The materials of the n-type semiconductor layer, the drift region, and the p-type semiconductor layer include at least one of GaN, AlGaN, InGaN, and AlN.

[0061] A second aspect of the present invention provides an epitaxial structure for a vertical transistor, wherein the epitaxial structure for the vertical transistor is obtained by a method for fabricating the epitaxial structure for the vertical transistor.

[0062] A third aspect of the present invention provides a vertical transistor, the vertical transistor including an epitaxial structure of the vertical transistor.

[0063] Furthermore, the vertical transistor includes a current aperture vertical electron transistor.

[0064] A fourth aspect of the present invention provides a method for improving the performance of a vertical transistor, comprising: fabricating the epitaxial structure of the vertical transistor using a method for fabricating the epitaxial structure of the vertical transistor.

[0065] The following will further explain the technical solution, its implementation process, and principles in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the semiconductor epitaxial equipment and processes, such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE), as well as the dry etching equipment and processes involved in the embodiments of this invention, are all known in the art. The growth processes and equipment for each structural layer of the growth template in the embodiments of this invention are all known in the art and are not considered improvements to the present invention; therefore, they will not be specifically described here.

[0066] In a more typical implementation scheme, please refer to Figure 1 A method for fabricating the epitaxial structure of a CAVET (Current Aperture Vertical Electron Transistor) device, specifically including the following steps:

[0067] 1) First, a nucleation layer and a buffer layer 2 are grown on substrate 1. Then, an n-type semiconductor layer 3 is grown on the buffer layer. Alternatively, the n-type semiconductor layer 3 is grown directly on the substrate. The material of the n-type semiconductor layer 3 is a III-V compound, the thickness of the n-type semiconductor layer 3 is 100 nm to 10000 nm, and the electron concentration is 1 × 10⁻⁶. 17 cm -3 ~1×10 20 cm -3 .

[0068] Specifically, substrate 1 can be a sapphire substrate, a GaN self-supporting substrate, a Si substrate, a SiC substrate, or an AlN substrate, etc. For different substrates, the structures of the nucleation layer and the buffer layer may differ. For example, embodiments of the present invention can realize a buffer-free CAVET epitaxial structure on a sapphire substrate, significantly reducing epitaxial wafer warpage and potentially applicable to the mass production of devices. Exemplarily, the material of nucleation layer 1 can be GaN or AlN, etc. Exemplarily, the n-type semiconductor layer 3 can be an n-type GaN layer, etc.

[0069] 2) A drift region 4 is grown on the n-type semiconductor layer 3. The drift region is made of a III-V compound, with a thickness of 1 μm to 1000 μm and an electron concentration of 1 × 10⁻⁶. 15 cm -3 ~1×10 17 cm -3 .

[0070] For example, the material of the drift region 4 can be GaN, AlGaN, InGaN, or AlN, etc.

[0071] 3) A p-type semiconductor layer 5 is formed on the drift region 4. The p-type semiconductor layer 5 is made of a III-V compound, and its thickness is t1, where t1 = 50 nm to 5000 nm. The Mg impurity concentration is 1 × 10⁻⁶.18 cm ～3 ~1×10 20 cm ～3 ;

[0072] For example, the material of the p-type semiconductor layer 5 can be GaN, AlGaN, InGaN, or AlN, etc.

[0073] 4) An alternating first barrier layer 6 and second barrier layer 7 are grown on the p-type semiconductor layer 5, with the second barrier layer 7 as the top layer. The first barrier layer 6 is an Al-containing III-V nitride layer with a thickness of t2, where t2 = 0.2 nm to 20 nm. The second barrier layer 7 is a Ga-containing III-V nitride layer with a thickness of t3, where t3 = 10 nm to 1000 nm, forming a Mg barrier layer, thereby completing the growth of the growth template.

[0074] Specifically, the material of the first barrier layer 6 can be AlN, AlGaN, AlInN or AlInGaN, etc., and the material of the second barrier layer 7 can be GaN, InGaN, etc. Specifically, the GaN barrier layer is a low-temperature GaN barrier layer with a growth temperature of 500℃~800℃.

[0075] For example, the Mg barrier layer can be an AlN / GaN composite barrier layer, an AlN / InGaN composite barrier layer, an AlInN / GaN composite barrier layer, a GaN / AlN / GaN composite barrier layer, an AlGaN / GaN composite barrier layer, an AlInGaN / GaN composite barrier layer, a GaN / AlGaN / GaN composite barrier layer, or a GaN / AlInGaN / GaN composite barrier layer, etc.

[0076] It should be noted that the total thickness of the Mg barrier layer is fixed. That is, when the Mg barrier layer is composed of multiple barrier layers, its total thickness is equal to the thickness of the Mg barrier layer composed of one first barrier layer 6 and one second barrier layer 7. For example, the thickness of the GaN / AlInGaN / GaN composite barrier layer is equal to the thickness of the AlInGaN / GaN composite barrier layer. Specifically, the thickness of the two GaN layers in the GaN / AlInGaN / GaN composite barrier layer is equal to the thickness of the single GaN layer in the AlInGaN / GaN composite barrier layer.

[0077] It should be noted that low-temperature GaN refers to a temperature range below 800℃, while the growth temperature of conventional GaN in MOCVD is generally above 1000℃. The purpose of low-temperature GaN is to prevent the diffusion of Mg during the growth of the barrier layer, reduce the Mg concentration inside the barrier layer, and ultimately reduce the Mg concentration in the channel layer, thereby reducing the on-resistance. If conventional GaN growth conditions are used, the thickness needs to be increased several times to reduce the Mg concentration to the same level, which will also cause a negative shift in the threshold voltage of the device, making it difficult to form an enhancement mode.

[0078] 5) A mask layer is deposited on the surface of the growth template, and the pattern in the photomask is transferred to the mask layer using photolithography, etching and other processes. A groove structure is formed on the growth template using dry etching methods such as ICP etching. The groove opening is located in the Mg barrier layer 7 and the bottom of the groove is located in the drift region 4. The depth of the groove structure is (t1+t2+t3)~(t1+t2+t3+500nm).

[0079] Specifically, the mask layer can be made of SiO2. x or SiN x The pattern in the photomask can be a polygon, such as a rectangle or a hexagon. The sides of the pattern in the photomask are at 60 or 90 degrees to each other, and are also parallel or perpendicular to the <10-10> crystal orientation of group III nitrides.

[0080] Specifically, after etching to form the groove structure, the patterned growth template can be placed in a tetramethylammonium hydroxide solution at 80°C and heated in a water bath for 1 hour to improve the steepness of the sidewalls of the groove structure. In addition, an acidic solution can be used to clean the patterned growth template to remove impurities. The acidic solution includes a mixture of concentrated sulfuric acid and hydrogen peroxide, dilute hydrochloric acid, or hydrofluoric acid.

[0081] 6) Vacuum pack the patterned growth template and transfer it to the growth chamber of the semiconductor growth equipment. Raise the temperature in the growth chamber to 800℃~1050℃ and adjust the pressure to 50~800mbar. Use in-situ etchant to etch the etching interface of the groove structure (i.e., the inner wall of the groove structure and the surface area of ​​the non-groove structure) in situ. The etching rate is greater than 5nm / min and less than 150nm / min. Ensure that the surface material near the etching interface is decomposed in a step flow mode. The depth of in-situ etching is less than t3.

[0082] Specifically, the in-situ etching agent used includes one or more of hydrogen, halogenated organic compounds, and ammonia, and the halogenated organic compounds can be tert-butyl chloride or tert-butyl fluorine, etc.

[0083] 7) A channel layer 8 is grown within the groove structure of the growth template and on the top surface of the growth template. The channel layer 8 is made of a III-V compound and has a thickness of 50 nm to 1000 nm. Specifically, the channel layer 8 can be a GaN channel layer, etc.

[0084] 8) A heterojunction 9 is grown on the channel layer 8. The heterojunction 9 is made of a III-V compound and has a thickness of 5 nm to 100 nm. Specifically, the heterojunction 9 can be AlN / AlGaN, etc.

[0085] 9) A cap layer 10 is grown on the heterojunction 9. The thickness of the cap layer 10 is 5nm to 100nm. At this point, the epitaxial structure growth of CAVET is completed.

[0086] Specifically, the cap layer 10 can be a p-type GaN cap layer or a GaN cap layer, etc., and the Mg impurity concentration of the p-type GaN cap layer is 5 × 10⁻⁶. 18 ~1×10 20 cm ～3 .

[0087] It should be noted that in the embodiments of the present invention, the n-type semiconductor layer, drift region, p-type semiconductor layer, Mg barrier layer, channel heterojunction, and cap layer can be grown using semiconductor epitaxial equipment and corresponding epitaxial growth processes known in the art, such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE).

[0088] The following will provide further explanation of the technical solution, its implementation process, and its principles, using specific implementation cases as examples.

[0089] Example 1: Growth of a depletion-type CAVET epitaxial structure on a sapphire substrate.

[0090] S1: A GaN nucleation layer with a thickness of 40 nm is grown on a sapphire substrate;

[0091] S2: An n-type GaN layer with a thickness of 2500 nm and an electron concentration of 3 × 10⁻⁶ is grown on the GaN nucleation layer. 18 cm -3 ;

[0092] S3: A GaN drift region is grown on an n-type GaN layer with a thickness of 2 μm and an electron concentration of 1 × 10⁻⁶. 16 cm -3 ;

[0093] S4: A p-type GaN layer with a thickness of 500 nm is grown in the GaN drift region, with a Mg impurity concentration of 3 × 10⁻⁶. 19 cm -3 ;

[0094] S5: An AlN barrier layer with a thickness of 1 nm is grown on the p-type GaN layer;

[0095] S6: A low-temperature GaN barrier layer with a thickness of 100 nm is grown on the AlN barrier layer at a growth temperature of 800 °C. This completes the growth of the template.

[0096] S7: Cool down and remove the growth template;

[0097] S8: SiOx and nickel are sequentially deposited on the surface of the growth template to form a composite mask layer, and a pattern is formed in the mask layer using photolithography and etching processes;

[0098] S9: Using ICP etching process, the pattern in the mask layer is transferred to the growth template to form a patterned growth template with an etching depth of 800nm;

[0099] S10: The patterned growth template is immersed in a 25% hot tetramethylammonium hydroxide solution at 70°C for 1 hour. The sidewall angle of the groove structure of the patterned growth template after treatment is 90°.

[0100] S11: Clean the patterned growth template sequentially with a mixed solution of concentrated sulfuric acid / hydrogen peroxide (volume ratio 3:1), dilute hydrochloric acid (volume concentration 20%), and hydrofluoric acid solution to remove surface contaminants;

[0101] S12: The vacuum-packed and cleaned patterned growth template is transferred to the growth chamber of the MOCVD equipment without being exposed to the atmosphere;

[0102] S13: A mixture of hydrogen, ammonia and tert-butyl chloride gas is introduced into the growth chamber. The pressure in the growth chamber is adjusted to 100 mbar and the temperature is adjusted to 1000℃. In-situ etching is performed, with the etching rate controlled at 20 nm / min and the etching depth at 60 nm. GaN is decomposed in a step flow mode.

[0103] S14: After in-situ etching, a GaN channel layer with a thickness of 150nm is grown in the groove structure of the growth template and on the surface.

[0104] S15: An AlN / AlGaN heterojunction is grown on the GaN channel layer. The AlN thickness in the AlN / AlGaN heterojunction is 1 nm, and the AlGaN thickness is 15 nm.

[0105] S16: A GaN cap layer with a thickness of 200 nm is grown on an AlN / AlGaN heterojunction to obtain an epitaxial structure of a depletion-type CAVET.

[0106] Comparative Example 1

[0107] Comparative Example 1 is basically the same as Example 1, and the similarities will not be repeated here. The differences between the two are as follows:

[0108] Comparative Example 1 did not grow an AlN barrier layer, but used only a low-temperature GaN barrier layer as a Mg barrier layer.

[0109] The epitaxial structures of the depletion-type CAVET in Example 1 and Comparative Example 1 were tested respectively. The Mg impurity concentration distribution curve in the epitaxial structure of the depletion-type CAVET in Comparative Example 1 is shown in Figure 1. Figure 2a As shown, the Mg impurity concentration distribution curve in the epitaxial structure of the depleted CAVET in Example 1 is as follows: Figure 2b As shown, the capacitance-voltage curve and sheet resistance of the epitaxial structure of the depletion-type CAVET in Comparative Example 1 are as follows: Figure 3a As shown, the capacitance-voltage curve and sheet resistance of the epitaxial structure of the depletion-type CAVET in Example 1 are as follows: Figure 3b As shown, it can be seen that, compared with the structure using a single GaN blocking layer, Embodiment 1 of the present invention successfully reduced the sheet resistance of the two-dimensional electron gas by 77% to 353 Ω / sq.

[0110] Example 2: Epitaxial structure of enhanced CAVET grown on a sapphire substrate.

[0111] S1: A GaN nucleation layer with a thickness of 40 nm is grown on a sapphire substrate;

[0112] S2: Growth of an n-type GaN layer with a thickness of 2500 nm and an electron concentration of 3 × 10⁻⁶. 18 cm -3 ;

[0113] S3: A GaN drift region is grown on an n-type GaN layer with a thickness of 2 μm and an electron concentration of 1 × 10⁻⁶. 16 cm -3 ;

[0114] S4: A p-type GaN layer with a thickness of 500 nm is grown on the GaN drift region, with a Mg impurity concentration of 3 × 10⁻⁶. 19 cm -3 ;

[0115] S5: An AlN barrier layer with a thickness of 1 nm is grown on the p-type GaN layer;

[0116] S6: A low-temperature GaN barrier layer with a thickness of 100 nm is grown on the AlN barrier layer at a growth temperature of 800 °C. This completes the template growth.

[0117] S7: Cool down and remove the growth template;

[0118] S8: SiOx and nickel are sequentially deposited on the surface of the growth template to form a composite mask layer, and a pattern is formed in the mask layer using photolithography and etching processes;

[0119] S9: Using ICP etching process, the pattern in the mask layer is transferred to the growth template to form a patterned growth template with an etching depth of 800nm;

[0120] S10: The patterned growth template is immersed in a 25% hot tetramethylammonium hydroxide solution at 70°C for 1 hour. The sidewall angle of the groove structure of the patterned growth template after treatment is 90°.

[0121] S11: Clean the patterned growth template sequentially with a mixed solution of concentrated sulfuric acid and hydrogen peroxide (volume ratio 3:1), dilute hydrochloric acid (volume concentration 20%), and hydrofluoric acid solution to remove surface contaminants;

[0122] S12: The vacuum-packed and cleaned patterned growth template is transferred to the growth chamber of the MOCVD equipment without being exposed to the atmosphere;

[0123] S13: A mixture of hydrogen, ammonia and tert-butyl chloride gas is introduced into the growth chamber. The pressure in the growth chamber is adjusted to 100 mbar and the temperature is adjusted to 1000℃. In-situ etching is performed, with the etching rate controlled at 30 nm / min and the etching depth at 60 nm. GaN is decomposed in a step flow mode.

[0124] S14: After in-situ etching, a GaN channel layer with a thickness of 150nm is grown in the groove structure of the growth template and on the surface.

[0125] S15: An AlN / AlGaN heterojunction is grown on the GaN channel layer. The AlN thickness in the AlN / AlGaN heterojunction is 1 nm, and the AlGaN thickness is 15 nm.

[0126] S16: A p-GaN cap layer was grown on an AlN / AlGaN heterojunction at a temperature gradually increased to 900℃ under a nitrogen / ammonia mixed atmosphere. The thickness of the p-GaN cap layer was 150 nm, and the Mg concentration was 2 × 10⁻⁶. 19 cm -3 This allows for the acquisition of an enhanced CAVET epitaxial structure.

[0127] Comparative Example 2

[0128] Comparative Example 2 is basically the same as Example 2, except that the in-situ etching step in S13 is omitted in Comparative Example 2.

[0129] The surface morphology of the groove structure after in-situ etching in S13 in Example 2 is as follows: Figure 4 As shown, Figure 4This indicates that the in-situ etching technique used in Example 2 decomposes GaN in a step-flow mode. The silicon impurity concentration distribution in the epitaxial structure of the enhanced CAVET obtained in Comparative Example 2 is as follows: Figure 5a As shown, the silicon impurity concentration distribution in the epitaxial structure of the enhanced CAVET obtained in Example 2 is as follows: Figure 5b As shown, by Figure 5b It can be seen that the in-situ etching process significantly reduces the concentration of Si impurity atoms at the secondary epitaxial interface, which can significantly improve the device's withstand voltage.

[0130] Example 3: Epitaxial structure of enhanced CAVET grown on GaN self-supporting substrate.

[0131] S1: An n-type GaN layer with a thickness of 500 nm and an electron concentration of 5 × 10⁻⁶ is grown on a GaN self-supporting substrate. 18 cm -3 ;

[0132] S2: A GaN drift region is grown on an n-type GaN layer with a thickness of 16 μm and an electron concentration of 1 × 10⁻⁶. 16 cm -3 The carbon impurity concentration is less than 1×10 16 cm -3 ;

[0133] S3: A p-type GaN layer with a thickness of 500 nm is grown on the GaN drift region, with a Mg impurity concentration of 3 × 10⁻⁶. 19 cm -3 ;

[0134] S4: An AlN barrier layer with a thickness of 1 nm is grown on the p-type GaN layer;

[0135] S5: A low-temperature GaN barrier layer with a thickness of 100 nm is grown on the AlN barrier layer at a growth temperature of 800 °C. This completes the growth of the template.

[0136] S6: Cool down and remove the growth template;

[0137] S7: SiOx and nickel are sequentially deposited on the growth template to form a composite mask layer, and a pattern is formed in the mask layer using photolithography and etching processes;

[0138] S8: Using ICP etching process, the pattern in the mask layer is transferred to the growth template to form a patterned growth template with an etching depth of 800nm;

[0139] S9: The patterned growth template is immersed in a 25% hot tetramethylammonium hydroxide solution at 70°C for 1 hour. The sidewall angle of the groove structure of the patterned growth template after treatment is 90°.

[0140] S10: Clean the patterned growth template sequentially with a mixed solution of concentrated sulfuric acid and hydrogen peroxide (volume ratio 3:1), dilute hydrochloric acid (volume concentration 20%), and hydrofluoric acid solution to remove surface contaminants;

[0141] S11: The vacuum-packed and cleaned graphic growth template is transferred to the growth chamber of the MOCVD equipment without being exposed to the atmosphere;

[0142] S12: A mixture of hydrogen, ammonia and tert-butyl chloride gas is introduced into the growth chamber. The pressure in the growth chamber is adjusted to 100 mbar and the temperature is adjusted to 1000℃. In-situ etching is performed, with the etching rate controlled at 30 nm / min and the etching depth at 60 nm. GaN is decomposed in a step flow mode.

[0143] S13: After in-situ etching, GaN channel layers with a thickness of 150nm are directly grown in the groove structure of the growth template and on the surface through secondary epitaxial growth.

[0144] S14: An AlN / AlGaN heterojunction is grown on the GaN channel layer. The AlN thickness in the AlN / AlGaN heterojunction is 1 nm, and the AlGaN thickness is 15 nm.

[0145] S15: Pharma-GaN was grown on an AlN / AlGaN heterojunction at a temperature gradually increased to 900℃ under a nitrogen / ammonia mixed atmosphere. The p-GaN thickness was 150 nm, and the Mg concentration was 2 × 10⁻⁶. 19 cm -3 At this point, the complete epitaxial structure growth of the self-supporting substrate CAVET is complete.

[0146] The breakdown voltage curve of the epitaxial structure of the enhanced CAVET in Example 3 is as follows: Figure 6 As shown, by Figure 6 It can be learned that the breakdown voltage of the epitaxial structure of the enhanced CAVET in Example 3 can reach over 1200V.

[0147] Example 4: Enhanced CAVET structure prepared on GaN self-supporting substrate using in-situ thermal decomposition treatment.

[0148] S1: An n-type GaN layer with a thickness of 500 nm and an electron concentration of 5 × 10⁻⁶ is grown on a GaN self-supporting substrate. 18 cm -3 ;

[0149] S2: A GaN drift region is grown on an n-type GaN layer with a thickness of 16 μm and an electron concentration of 1 × 10⁻⁶. 16 cm -3 The carbon impurity concentration is less than 1×10 16 cm -3 ;

[0150] S3: A p-type GaN layer with a thickness of 500 nm is grown on the GaN drift region, with a Mg impurity concentration of 3 × 10⁻⁶. 19 cm -3 ;

[0151] S4: An AlN barrier layer with a thickness of 1 nm is grown on the p-type GaN layer;

[0152] S5: A low-temperature GaN barrier layer with a thickness of 100 nm is grown on the AlN barrier layer at a growth temperature of 800 °C. This completes the growth of the template.

[0153] S6: Cool down and remove the growth template;

[0154] S7: SiOx and nickel are sequentially deposited on the growth template to form a composite mask layer, and a pattern is formed in the mask layer using photolithography and etching processes;

[0155] S8: Using ICP etching process, the pattern in the mask layer is transferred to the growth template to form a patterned growth template with an etching depth of 800nm;

[0156] S9: The patterned growth template is immersed in a 25% hot tetramethylammonium hydroxide solution at 70°C for 1 hour. The sidewall angle of the groove structure of the patterned growth template after treatment is 90°.

[0157] Sl0: Clean the patterned growth template sequentially with a mixed solution of concentrated sulfuric acid and hydrogen peroxide (volume ratio 3:1), dilute hydrochloric acid (volume concentration 20%), and hydrofluoric acid solution to remove surface contaminants;

[0158] S11: The vacuum-packed and cleaned patterned growth template is transferred to the growth chamber of the MOCVD equipment without being exposed to the atmosphere;

[0159] S12: A mixture of hydrogen and ammonia gas is introduced into the growth chamber. The pressure in the growth chamber is adjusted to 100 mbar and the temperature is adjusted to 950℃. In-situ etching is performed, with the etching rate controlled at 30 nm / min and the etching depth at 10 nm. GaN is decomposed in a step flow mode.

[0160] S13: After in-situ etching, GaN channel layers with a thickness of 150nm are directly grown in the groove structure of the growth template and on the surface through secondary epitaxial growth.

[0161] S14: An AlN / AlGaN heterojunction is grown on the GaN channel layer. The AlN thickness in the AlN / AlGaN heterojunction is 1 nm, and the AlGaN thickness is 15 nm.

[0162] S15: p-GaN growth was performed on an AlN / AlGaN heterojunction at a variable temperature of 900℃ under a nitrogen / ammonia mixed atmosphere. The p-GaN thickness was 150 nm, and the Mg concentration was 2 × 10⁻⁶. 19 cm -3 At this point, the complete epitaxial structure growth of the self-supporting substrate CAVET is complete.

[0163] Comparative Example 3

[0164] Comparative Example 3 is basically the same as Example 1, except that S13 in Comparative Example 3 is a conventional wet etching process.

[0165] The silicon impurity concentration distribution in the epitaxial structure of the enhanced CAVET obtained in Comparative Example 3 is as follows: Figure 7 As shown, with Figure 5b The comparison shows that wet etching is not effective in removing the concentration of Si impurity atoms at the secondary epitaxial interface, which is detrimental to the voltage withstand capability of the device.

[0166] Example 5

[0167] Example 5 is basically the same as Example 1, except that in Example 5, step S6 is: growing a low-temperature InGaN barrier layer with a thickness of 100 nm on the AlN barrier layer at a growth temperature of 700 °C, with an In composition of 1%. This completes the growth of the template.

[0168] Example 6

[0169] Example 6 is basically the same as Example 1, except that: in Example 5, S5: an InAlN barrier layer with a thickness of 1 nm and an In composition of 2% is grown on a p-type GaN layer;

[0170] Example 7

[0171] Example 7 is basically the same as Example 1, except that S5-S6 in Example 5 is adjusted as follows:

[0172] S5: A low-temperature GaN barrier layer with a thickness of 10 nm is grown on a p-type GaN layer at a growth temperature of 800℃.

[0173] S6: Grow an AlN barrier layer with a thickness of 1 nm;

[0174] S7: A low-temperature GaN barrier layer with a thickness of 90 nm is grown on the AlN barrier layer at a growth temperature of 800℃. This completes the growth of the template.

[0175] Compared to the device in Example 1, the CAVET device prepared based on this example is expected to have the same breakdown voltage.

[0176] It should be noted that, with reference to Example 1, the etching rate of in-situ etching was controlled to 6 nm / min, 10 nm / min, 15 nm / min, 22 nm / min, 33 nm / min, 40 nm / min, 55 nm / min, 64 nm / min, 70 nm / min, 95 nm / min, 100 nm / min, 120 nm / min, and 146 nm / min, respectively, and a series of devices were obtained. The performance of this series of devices is basically the same as that of Example 1.

[0177] This invention uses AlN and low-temperature GaN to form a composite barrier layer. Compared with conventional single-layer GaN barrier layers, it can better reduce the diffusion of Mg atoms from the electron barrier layer to the channel layer, thereby reducing the Mg impurity concentration in the channel layer, increasing the concentration and mobility of two-dimensional electron gas in the channel layer, reducing sheet resistance, and thus reducing the on-resistance of CAVET devices.

[0178] This invention utilizes in-situ etching technology to simultaneously remove impurities from the secondary epitaxial interface and repair dry etching damage. Because the in-situ etching and secondary epitaxy of the channel layer are performed continuously, secondary contamination by impurities is avoided, achieving extremely high impurity removal efficiency. Furthermore, the in-situ etching technology employed in this invention enables layer-by-layer removal of etch-damaged layers, efficiently repairing etching damage caused by dry etching while ensuring a smooth interface. This results in a high-quality secondary epitaxial interface and improves the off-state breakdown voltage of CAVET devices.

[0179] The thickness of the composite barrier layer and the in-situ etching depth in this invention can be designed in synergy to jointly control the threshold voltage and saturation current of the device, thus enriching the design and manufacturing dimensions of the device.

[0180] The CAVET device in this invention can adopt a bufferless design, which can significantly reduce epitaxial layer warpage and increase device process compatibility while keeping the active region thickness unchanged.

[0181] The method for constructing CAVET epitaxial structures proposed in this invention can not only effectively improve the mobility and density of two-dimensional electron gas, but also achieve high-quality secondary epitaxial interfaces with low impurity content and low damage, effectively improving the forward and reverse characteristics of the device.

[0182] This invention utilizes in-situ etching technology before secondary epitaxy, employing a mixed gas of hydrogen, ammonia, and tert-butyl chloride to etch GaN. This enables efficient removal of impurities at the GaN secondary epitaxy interface and high-quality repair of dry etching damage, significantly improving device performance.

[0183] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for fabricating an epitaxial structure of a vertical transistor, characterized in that, include: A growth template is provided, the growth template comprising an n-type semiconductor layer, a drift region, a p-type semiconductor layer and a Mg barrier layer stacked sequentially along its own longitudinal direction, the Mg barrier layer comprising at least one first barrier layer and at least one second barrier layer stacked along the longitudinal direction of the growth template, the first barrier layer being an Al-containing III-V group nitride layer, the second barrier layer being a Ga-containing III-V group nitride layer, and the topmost layer of the Mg barrier layer being the second barrier layer; The growth template is patterned and etched to form a groove structure, wherein the groove opening is located in the Mg barrier layer and the groove bottom is located in the drift region; The etching interface of the groove structure formed by etching is etched in situ to decompose the surface material near the etching interface in a step flow mode. A secondary epitaxial growth of a channel layer is performed in the groove structure, and a heterojunction is grown on the channel layer and a cap layer is grown on the heterojunction.

2. The method for fabricating the epitaxial structure of the vertical transistor according to claim 1, characterized in that: The thickness of the first barrier layer is less than the thickness of the second barrier layer; Preferably, the thickness t2 of the first barrier layer is 0.2 nm to 20 nm, and the thickness t3 of the second barrier layer is 10 nm to 1000 nm; Preferably, the first barrier layer and the second barrier layer are stacked alternately.

3. The method for fabricating the epitaxial structure of the vertical transistor according to claim 1, characterized in that: The material of the first barrier layer includes AlN, AlGaN, AlInN or AlInGaN, and the material of the second barrier layer includes GaN or InGaN; Preferably, the material of the second barrier layer is GaN, and the growth temperature of GaN is 500℃~800℃; Preferably, the first barrier layer is made of AlInN, the In content in AlInN is less than 5%, and the growth temperature is less than 800°C; Preferably, the first barrier layer is made of AlGaN, and the Al content in AlGaN is greater than 80%. Preferably, the first barrier layer is made of AlInGaN, with an Al content greater than 80% and a growth temperature less than 800°C.

4. The method for fabricating the epitaxial structure of the vertical transistor according to claim 1, characterized in that: The in-situ etching agent used includes one or more of hydrogen, halogenated organic compounds, and ammonia. Preferably, the halogenated organic compound includes at least one of tert-butyl chloride and tert-butyl fluorine; Preferably, the etching rate of the in-situ etching is greater than 5 nm / min and less than 150 nm / min.

5. The method for fabricating the epitaxial structure of a vertical transistor according to claim 1 or 4, characterized in that: The in-situ etching temperature is 800℃~1050℃, the etching pressure is 50mbar~800mbar, and the etching depth is less than the thickness of the second barrier layer located on the top layer.

6. The method for fabricating the epitaxial structure of the vertical transistor according to claim 1, characterized in that: The n-type semiconductor layer, the drift region, and the p-type semiconductor layer are all made of III-V compound materials; Preferably, the materials of the n-type semiconductor layer, the drift region, and the p-type semiconductor layer include at least one of GaN, AlGaN, InGaN, and AlN.

7. The method for fabricating the epitaxial structure of the vertical transistor according to claim 1, characterized in that, include: The growth template is obtained by growing an n-type semiconductor layer, a drift region, a p-type semiconductor layer and a Mg barrier layer sequentially stacked on a substrate; or, the growth template is obtained by first growing a nucleation layer and a buffer layer sequentially stacked on a substrate, and then growing an n-type semiconductor layer, a drift region, a p-type semiconductor layer and a Mg barrier layer sequentially stacked on the buffer layer. Preferably, the materials of the n-type semiconductor layer, the drift region, and the p-type semiconductor layer include at least one of GaN, AlGaN, InGaN, and AlN.

8. An epitaxial structure for a vertical transistor, characterized in that: The epitaxial structure of the vertical transistor is obtained by the method for preparing the epitaxial structure of the vertical transistor according to any one of claims 1-7.

9. A vertical transistor, characterized in that: The vertical transistor includes the epitaxial structure of the vertical transistor of claim 8; Preferably, the vertical transistor includes a current aperture vertical electronic transistor.

10. A method for improving the performance of a vertical transistor, characterized in that, include: The epitaxial structure of the vertical transistor is fabricated using the method for fabricating the epitaxial structure of the vertical transistor according to any one of claims 1-7.

Images