Semiconductor device and method of manufacturing the same

Abstract

The present application provides a semiconductor device and a preparation method thereof, the preparation method comprising the following steps: providing a semiconductor structure comprising first and second regions and first and second gate structures, the first and second gate structures being located on the upper surfaces of the first and second regions respectively; sequentially implanting first and second particles into the upper surface layer of the first region on the opposite sides of the first gate conductive layer in the first gate structure, and implanting third particles into the upper surface layer of the second region on the opposite sides of the second gate conductive layer in the second gate structure, so as to form first source-drain regions in the first region and second source-drain regions in the second region; and forming electrodes electrically connected with the first source-drain regions, the second source-drain regions, the first gate conductive layer, the first gate and the second gate conductive layer respectively. In the process of manufacturing narrow channel devices in the second region, the present application omits the step of amorphous treatment on the region to be implanted with the third particles, thereby inhibiting the reverse narrow channel effect of the small-size narrow channel devices and improving the reliability of the devices.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a semiconductor device and its preparation method. Background Technology

[0002] With the rapid development of semiconductor manufacturing processes, the geometric dimensions of transistors on chips are constantly shrinking to meet the requirements of high integration and complex circuit functions, while also reducing device manufacturing costs. However, as device size decreases, the electrical parameters of the device become increasingly sensitive to its geometry, and the reverse narrow channel effect (RNWE) has a growing impact on device performance. This results in a rapid drop in the device's threshold voltage, increased leakage current, increased power consumption, and decreased reliability as the channel width decreases.

[0003] Therefore, there is an urgent need to find a method for fabricating semiconductor devices that can suppress the anti-narrow channel effect in small-sized devices. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and its fabrication method to solve the problem that the performance of small-sized transistors in the prior art is greatly affected by the reverse narrow channel effect.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0006] A semiconductor structure is provided, comprising a first region, a second region, a first gate structure, and a second gate structure, wherein the first gate structure and the second gate structure are respectively located on the upper surfaces of the first region and the second region, which are spaced apart.

[0007] First particles and second particles are sequentially injected into the upper surface layer of the first region on both sides of the first gate conductive layer in the first gate structure, and third particles are injected into the upper surface layer of the second region on both sides of the second gate conductive layer in the second gate structure, so as to form a first source / drain region in the first region with the opposite conductivity type to the first region and a second source / drain region in the second region with the opposite conductivity type to the second region.

[0008] A first electrode and a second electrode are formed that are electrically connected to the first source and drain regions on opposite sides of the first gate conductive layer, a third electrode and a fourth electrode are formed that are electrically connected to the second source and drain regions on opposite sides of the second gate conductive layer, a first gate electrode is formed that is electrically connected to the first gate conductive layer, and a second gate electrode is formed that is electrically connected to the second gate conductive layer.

[0009] Optionally, the first gate structure further includes a first gate dielectric layer and a first sidewall layer, wherein the first gate dielectric layer is located on the upper surface of the first region, the first gate conductive layer is located on the upper surface of the first gate dielectric layer, and the first sidewall layer covers the sidewall of the first gate conductive layer. The second gate structure further includes a second gate dielectric layer and a second sidewall layer, wherein the second gate dielectric layer is located on the upper surface of the second region, the second gate conductive layer is located on the upper surface of the second gate dielectric layer, and the second sidewall layer covers the sidewall of the second gate conductive layer.

[0010] Optionally, the first particle includes germanium ions and carbon ions; the second particle includes one of trivalent ions and pentavalent ions; and the third particle includes one of trivalent ions and pentavalent ions.

[0011] Optionally, the second particle is the same as the third particle.

[0012] Optionally, the upper surface layer of the first region is further provided with a first shallow doped region located on opposite sides of the first gate conductive layer, and the first source / drain region is located on the upper surface layer of the first shallow doped region. The upper surface layer of the second region is further provided with a second shallow doped region located on opposite sides of the second gate conductive layer, and the second source / drain region is located on the upper surface layer of the second shallow doped region.

[0013] Optionally, the device fabricated based on the first region is a wide-channel device, and the device fabricated based on the second region is a narrow-channel device.

[0014] Optionally, after ion implantation of the upper surface of the first region on both sides of the first gate conductive layer and the upper surface of the second region on both sides of the second gate conductive layer, before forming the first source / drain region and the second source / drain region, a simultaneous annealing step is further included.

[0015] Optionally, the semiconductor structure further includes an isolation structure, which includes a first isolation structure surrounding the first region and a second isolation structure surrounding the second region.

[0016] Optionally, after forming the first source / drain region and the second source / drain region, and before forming the first electrode, the second electrode, the third electrode, the fourth electrode, the first gate, and the second gate, the method further includes forming an interlayer dielectric layer covering the exposed upper surface of the semiconductor structure. The first electrode and the second electrode respectively penetrate the interlayer dielectric layer and are electrically connected to the first source / drain regions on opposite sides of the first gate conductive layer. The third electrode and the fourth electrode respectively penetrate the interlayer dielectric layer and are electrically connected to the second source / drain regions on opposite sides of the second gate conductive layer. The first gate penetrates the interlayer dielectric layer directly above the first gate conductive layer and is electrically connected to the first gate conductive layer. The second gate penetrates the interlayer dielectric layer directly above the second gate conductive layer and is electrically connected to the second gate conductive layer.

[0017] The present invention also provides a semiconductor device, which is fabricated using the semiconductor device fabrication method described above.

[0018] As described above, in the process of fabricating a narrow-channel device in the second region of the semiconductor device and the method thereof of the present invention, before forming the second source-drain region of the narrow-channel device, the step of performing amorphization treatment on the implantation region of the third particle to form the second source-drain region is skipped. This reduces the lateral diffusion of ions at the boundary between the second source-drain region of the narrow-channel device and the second isolation structure, effectively suppresses the influence of the anti-narrow-channel effect on the performance of small-sized narrow-channel devices, improves the stability and reliability of small-sized devices, and has a simple process that is compatible with CMOS processes, thus having high industrial application value. Attached Figure Description

[0019] Figure 1 The diagram shown is a process flow chart of the method for fabricating the semiconductor device of the present invention.

[0020] Figure 2 The diagram shown is a cross-sectional view of the semiconductor structure used in the fabrication method of the semiconductor device of the present invention.

[0021] Figure 3 The diagram shows a cross-sectional structure of the semiconductor device fabrication method of the present invention after the formation of the amorphous region.

[0022] Figure 4 The diagram shown is a cross-sectional view of the semiconductor device fabrication method of the present invention after forming the first source / drain region and the second source / drain region.

[0023] Figure 5 The diagram shown is a cross-sectional view of the semiconductor device fabrication method of the present invention after the formation of each electrode.

[0024] Figure 6 Displayed as Figure 5The distribution diagram of the various structures on the top surface of the second region of the device.

[0025] Figure 7 Displayed as Figure 5 Chinese components and Figure 5 The threshold voltage of the device after normal injection of the first particle into the second region of the medium structure varies with the width W of the second source-drain region.

[0026] Figure 8 Displayed as Figure 5 Chinese components and Figure 5 Scatter plot of drain current and threshold voltage distribution of the device after normal injection of the first particle in the second region of the medium structure.

[0027] Explanation of icon numbers

[0028] 1. Semiconductor Structure

[0029] 11 First District

[0030] 12 Second District

[0031] 13 First shallow doped region

[0032] 14 Second shallow doped region

[0033] 15 First source leak area

[0034] 16 Second source leak area

[0035] 17 Amorphous region

[0036] 18. Isolation Structure

[0037] 2 First gate structure

[0038] 21 First gate dielectric layer

[0039] 22 First gate conductive layer

[0040] 23 First side wall layer

[0041] 24 Second gate structure

[0042] 25 Second gate dielectric layer

[0043] 26 Second gate conductive layer

[0044] 27 Second side wall layer

[0045] 3 Interlayer dielectric layer

[0046] 4 First Pole

[0047] 41 Second Pole

[0048] 42 Third Pole

[0049] 43 The Fourth Pole Detailed Implementation

[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0052] Example 1

[0053] This embodiment provides a method for fabricating a semiconductor device, such as... Figure 1 The diagram shown is a process flow chart of the method for fabricating the semiconductor device, including the following steps:

[0054] S1: A semiconductor structure including a first region, a second region, a first gate structure and a second gate structure is provided, wherein the first gate structure and the second gate structure are respectively located on the upper surfaces of the first region and the second region that are spaced apart;

[0055] S2: First particles and second particles are sequentially injected into the upper surface of the first region on both sides of the first gate conductive layer in the first gate structure, and third particles are injected into the upper surface of the second region on both sides of the second gate conductive layer in the second gate structure, so as to form a first source / drain region in the first region with the opposite conductivity type to the first region and a second source / drain region in the second region with the opposite conductivity type to the second region.

[0056] S3: Form a first electrode and a second electrode that are electrically connected to the first source and drain regions on opposite sides of the first gate conductive layer, a third electrode and a fourth electrode that are electrically connected to the second source and drain regions on opposite sides of the second gate conductive layer, a first gate electrode that is electrically connected to the first gate conductive layer, and a second gate electrode that is electrically connected to the second gate conductive layer.

[0057] Please see Figures 2 to 4Steps S1 and S2 are executed as follows: A semiconductor structure 1 including a first region 11, a second region 12, a first gate structure 2, and a second gate structure 24 is provided, wherein the first gate structure 2 and the second gate structure 24 are respectively located on the upper surfaces of the first region 11 and the second region 12, which are spaced apart; a first particle and a second particle are sequentially injected into the upper surface layer of the first region 11 on both sides of the first gate conductive layer 22 in the first gate structure 2, and a third particle is injected into the upper surface layer of the second region 12 on both sides of the second gate conductive layer 26 in the second gate structure 24, so as to form a first source / drain region 15 in the first region 11 with a conductivity type opposite to that of the first region 11 and a second source / drain region 16 in the second region 12 with a conductivity type opposite to that of the second region 12.

[0058] It should be noted that the conductivity type of the first region 11 and the second region 12 is related to the function of the semiconductor device to be fabricated. Typically, the conductivity type of the first region 11 can be either N-type or P-type, and the conductivity type of the second region 12 can also be either N-type or P-type. In this embodiment, the conductivity type of both the first region 11 and the second region 12 is P-type.

[0059] Specifically, such as Figure 2 The diagram shows a cross-sectional view of semiconductor structure 1. While ensuring device performance, the size, shape, and thickness of the first region 11 can be selected according to actual conditions; the size, shape, and thickness of the second region 12 can be selected according to actual conditions; and the distance between the first region 11 and the second region 12 can be selected according to actual conditions.

[0060] Specifically, the material of the first region 11 in semiconductor structure 1 includes silicon, silicon germanium, silicon carbide, gallium nitride, diamond, or other suitable semiconductor materials; the material of the second region 12 in semiconductor structure 1 includes silicon, silicon germanium, silicon carbide, gallium nitride, diamond, or other suitable semiconductor materials. Preferably, the first region 11 and the second region 12 are regions within a silicon layer.

[0061] As an example, the first gate structure 2 further includes a first gate dielectric layer 21 and a first sidewall layer 23. The first gate dielectric layer 21 is located on the upper surface of the first region 11, the first gate conductive layer 22 is located on the upper surface of the first gate dielectric layer 21, and the first sidewall layer 23 covers the sidewall of the first gate conductive layer 22. The second gate structure 24 further includes a second gate dielectric layer 25 and a second sidewall layer 27. The second gate dielectric layer 25 is located on the upper surface of the second region 12, the second gate conductive layer 26 is located on the upper surface of the second gate dielectric layer 25, and the second sidewall layer 27 covers the sidewall of the second gate conductive layer 26.

[0062] Specifically, while ensuring device performance, the thickness of the first gate dielectric layer 21 can be selected according to actual conditions; the shape of the first gate conductive layer 22 and its position on the upper surface of the first gate dielectric layer 21 can be selected according to actual conditions; the thickness of the first sidewall layer 23 can be selected according to actual conditions; the thickness of the second gate dielectric layer 25 can be selected according to actual conditions; the shape of the second gate conductive layer 26 and its position on the upper surface of the second gate dielectric layer 25 can be selected according to actual conditions; and the thickness of the second sidewall layer 27 can be selected according to actual conditions. Here, the thickness of the first sidewall layer 23 (second sidewall layer 27) refers to the distance between the sidewall adjacent to the first gate conductive layer 22 (second gate conductive layer 26) and the sidewall away from the first gate conductive layer 22 (second gate conductive layer 26).

[0063] It should be noted that, typically, the first gate dielectric layer 21 covers the upper surface of the first region 11, and the second gate dielectric layer 25 covers the upper surface of the second region 12.

[0064] As an example, the first particle includes germanium ions, carbon ions, or other suitable ions; the second particle includes one of trivalent ions and pentavalent ions; and the third particle includes one of trivalent ions and pentavalent ions. Preferably, germanium ions are used as the first particle.

[0065] Specifically, such as Figure 3 and Figure 4 The figures shown are cross-sectional schematic diagrams of the amorphous region 17 and the first source / drain region 15 and the second source / drain region 16, respectively. By injecting first particles into the upper surface of the first region 11 on both sides of the first gate conductive layer 22, the amorphous region 17 is pre-formed in the region to be injected by the second particles, thus hindering the channeling effect during the second particle injection. Point defects such as interstitial atoms can also be generated in the region to be injected by the second particles. Due to the presence of point defects, transient enhanced diffusion (TED) occurs, which further diffuses into the amorphous region 17 after the second particle injection, increasing... The lateral diffusion effect of implanted ions in the first source / drain region 15 is enhanced, making the distribution of the subsequently implanted second particles more uniform and facilitating rapid device turn-on. By implanting the first particles into the amorphous region 17 after implanting the first particles into the upper surface of the first region 11 on both sides of the first gate conductive layer 22, the upper surface of the first region 11 is formed with a first source / drain region 15 having a conductivity type opposite to that of the first region 11. By implanting the third particles into the upper surface of the second region 12 on both sides of the second gate conductive layer 26, the upper surface of the second region 12 is formed with a second source / drain region 16 having a conductivity type opposite to that of the second region 12.

[0066] Specifically, while ensuring device performance, the size, shape, and thickness of the first source / drain region 15 can be selected according to actual conditions; the size, shape, and thickness of the second source / drain region 16 can also be selected according to actual conditions. Here, thickness refers to the distance between the upper and lower surfaces of the first source / drain region 15 (second source / drain region 16).

[0067] It should be noted that the first source / drain region 15 and the second source / drain region 16 are usually heavily doped regions to facilitate good ohmic contact with the electrodes fabricated subsequently.

[0068] As an example, the second particle is the same as the third particle, that is, the doping type of the first source / drain region 15 is the same as the doped ion of the second source / drain region 16, the conductivity type of the first source / drain region 15 and the second source / drain region 16 is the same, and the conductivity type of the first region 11 and the second region 12 is the same. In this embodiment, both the second particle and the third particle are phosphorus ions.

[0069] It should be noted that when the second and third particles are the same, the first region 11 and the second region 12 can be injected simultaneously, or the first region 11 and the second region 12 can be injected separately.

[0070] As an example, the upper surface of the first region 11 is further provided with a first shallow doped region 13 located on opposite sides of the first gate conductive layer 22, and a first source / drain region 15 located on the upper surface of the first shallow doped region 13. The upper surface of the second region 12 is further provided with a second shallow doped region 14 located on opposite sides of the second gate conductive layer 26, and a second source / drain region 16 located on the upper surface of the second shallow doped region 14.

[0071] It should be noted that the first shallow doped region 13 and the second shallow doped region 14 are usually fabricated by shallow drain doping (LDD) process, and the sidewalls of the two first shallow doped regions 13 on opposite sides of the first gate conductive layer 22 extend to the bottom of the first gate conductive layer 22, and the sidewalls of the two second shallow doped regions 14 on opposite sides of the second gate conductive layer 26 extend to the bottom of the second gate conductive layer 26.

[0072] Specifically, when the upper surface of the first region 11 is provided with a first shallow doped region 13 and the upper surface of the second region 12 is provided with a second shallow doped region 14, the first source / drain region 15 can also penetrate the first shallow doped region 13 and the second source / drain region 16 can also penetrate the second shallow doped region 14.

[0073] Specifically, while ensuring device performance, the shape, size, and thickness of the first shallow doped region 13 can be selected according to actual conditions; the distance between the sidewall of the first shallow doped region 13 located directly below the first gate conductive layer 22 and the sidewall of the first gate conductive layer 22 adjacent to the sidewall can be selected according to actual conditions; the shape, size, and thickness of the second shallow doped region 14 can be selected according to actual conditions; the distance between the sidewall of the second shallow doped region 14 located directly below the second gate conductive layer 26 and the sidewall of the second gate conductive layer 26 adjacent to the sidewall can be selected according to actual conditions.

[0074] Specifically, while ensuring device performance, the distance between the two first shallow doped regions 13 on both sides of the first gate conductive layer 22 can be selected according to the actual situation; the distance between the two second shallow doped regions 14 on both sides of the second gate conductive layer 26 can be selected according to the actual situation.

[0075] As an example, the device fabricated based on the first region 11 is a wide-channel device, and the device fabricated based on the second region 12 is a narrow-channel device. That is, the width of the conductive channel directly below the first gate conductive layer 22 in the first region 11 is much larger than the width of the depletion layer between the first source and drain regions 15 on both sides of the first gate conductive layer 22, and the width of the conductive channel directly below the second gate conductive layer 26 in the second region 12 is similar to the width of the depletion layer between the second source and drain regions 16 on both sides of the second gate conductive layer 26.

[0076] It should be noted that the width of the depletion layer directly below the first gate conductive layer 22 is usually related to the doping concentration of the first region 11 directly below the first gate conductive layer 22. The higher the doping concentration, the narrower the width of the depletion layer directly below the first gate conductive layer 22. Similarly, the width of the depletion layer directly below the second gate conductive layer 26 is related to the doping concentration of the second region 12 directly below the second gate conductive layer 26. The higher the doping concentration, the narrower the width of the depletion layer directly below the second gate conductive layer 26.

[0077] As an example, after ion implantation is performed on the upper surface of the first region 11 on both sides of the first gate conductive layer 22 and the upper surface of the second region 12 on both sides of the second gate conductive layer 26, before the formation of the first source / drain region 15 and the second source / drain region 16, a synchronous annealing step is also included.

[0078] Specifically, through synchronous annealing, the second and third particles are diffused, so that the distribution of each particle in the region where the second particle is injected in the first region 11 and the region where the third particle is injected in the second region 12 is more uniform. At the same time, the damage to the first region 11 caused by the injection of the second particle and the damage to the second region 12 caused by the injection of the third particle are repaired, and the doped impurity ions are activated.

[0079] Specifically, while ensuring device performance, the annealing temperature and annealing time of the semiconductor structure 1 after the second and third particles are injected can be selected according to the actual situation.

[0080] As an example, the semiconductor structure 1 also includes an isolation structure 18, which includes a first isolation structure surrounding the first region 11 and a second isolation structure surrounding the second region 12.

[0081] Specifically, the first isolation structure is used to isolate the first region 11 from its external region to prevent devices fabricated in the external region of the first region 11 in the semiconductor structure 1 from affecting the operation of devices fabricated in the first region 11; the second isolation structure is used to isolate the second region 12 from its external region to prevent devices fabricated in the external region of the second region 12 in the semiconductor structure 1 from affecting the operation of devices fabricated in the second region 12.

[0082] Specifically, the first isolation structure includes a first isolation trench surrounding the first region 11 and a first isolation layer filling the first isolation trench, and the second isolation structure includes a second isolation structure surrounding the second region 12 and a second isolation layer filling the second isolation trench.

[0083] Specifically, while ensuring device performance, the opening size, shape, and depth of the first isolation trench can be selected according to actual conditions; the opening size, shape, and depth of the second isolation trench can be selected according to actual conditions; the distance between the first isolation structure and the second isolation structure can be selected according to actual conditions. Here, depth refers to the distance from the bottom surface of the first isolation trench (second isolation trench) to the opening of the first isolation trench (second isolation trench). In this embodiment, the first isolation structure on the side of the first region 11 closest to the second region 12 and the second isolation structure on the side of the second region 12 closest to the first region 11 share the same isolation trench and the same isolation layer.

[0084] Specifically, the material of the first isolation layer includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the second isolation layer includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0085] Please see Figures 5 to 8 Step S3 is executed: forming a first electrode 4 and a second electrode 41 that are electrically connected to the first source-drain regions 15 on both sides of the first gate conductive layer 22, a third electrode 42 and a fourth electrode 43 that are electrically connected to the second source-drain regions 16 on both sides of the second gate conductive layer 26, a first gate that is electrically connected to the first gate conductive layer 22, and a second gate that is electrically connected to the second gate conductive layer 26.

[0086] As an example, such as Figure 5 and Figure 6The figures shown are schematic diagrams of the cross-sectional structures after the formation of each electrode. Figure 5 The top surface of the second region 12 of the device includes a structural distribution diagram. After the formation of the first source / drain region 15 and the second source / drain region 16, and before the formation of the first electrode 4, the second electrode 41, the third electrode 42, the fourth electrode 43, the first gate, and the second gate, the step of forming an interlayer dielectric layer 3 covering the exposed upper surface of the semiconductor structure 1 is also included. The first electrode 4 and the second electrode 41 penetrate the interlayer dielectric layer 3 and are electrically connected to the first source / drain regions 15 on opposite sides of the first gate conductive layer 22, respectively. The third electrode 42 and the fourth electrode 43 penetrate the interlayer dielectric layer 3 and are electrically connected to the second source / drain regions 16 on opposite sides of the second gate conductive layer 26, respectively. The first gate penetrates the interlayer dielectric layer 3 directly above the first gate conductive layer 22 and is electrically connected to the first gate conductive layer 22. The second gate penetrates the interlayer dielectric layer 3 directly above the second gate conductive layer 26 and is electrically connected to the second gate conductive layer 26.

[0087] Specifically, the methods for forming the interlayer dielectric layer 3 include chemical vapor deposition, physical vapor deposition, atomic vapor deposition, or other suitable methods.

[0088] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 3 can be selected according to the actual situation.

[0089] Specifically, the interlayer dielectric layer 3 also has a first contact hole, a second contact hole, and a third contact hole. The first contact hole penetrates the interlayer dielectric layer 3 directly above the first source / drain regions 15 on both sides of the first gate conductive layer 22 and exposes the first source / drain regions 15 on its bottom surface. The second contact hole penetrates the interlayer dielectric layer 3 directly above the second source / drain regions 16 on both sides of the second gate conductive layer 26 and exposes the second source / drain regions 16 on its bottom surface. The third contact hole penetrates the interlayer dielectric layer 3 directly above the first gate conductive layer 22 and the second gate conductive layer 26, and exposes the first gate conductive layer 22 and the second gate conductive layer 26 on its bottom surface.

[0090] Specifically, the first electrode 4 and the second electrode 41 respectively fill the first contact holes on opposite sides of the first gate conductive layer 22 to achieve electrical connection between the first source / drain regions 15 at the bottom of the first contact holes. The third electrode 42 and the fourth electrode 43 respectively fill the second contact holes on opposite sides of the second gate conductive layer 26 to achieve electrical connection between the second source / drain regions 16 at the bottom of the second contact holes. The bottom surface of the first gate fills to expose the third contact hole of the first gate conductive layer 22 to achieve electrical connection with the first gate conductive layer 22. The bottom surface of the second gate fills to expose the third contact hole of the second gate conductive layer 26 to achieve electrical connection with the second gate conductive layer 26.

[0091] Specifically, the methods for forming the first contact hole include dry etching, wet etching, or other suitable methods; the methods for forming the second contact hole include dry etching, wet etching, or other suitable methods; and the methods for forming the third contact hole include dry etching, wet etching, or other suitable methods.

[0092] It should be noted that the first contact holes on opposite sides of the first gate conductive layer 22 can be formed simultaneously or in stages; the second contact holes on opposite sides of the second gate conductive layer 26 can be formed simultaneously or in stages; the third contact hole directly above the first gate conductive layer 22 and the third contact hole directly above the second gate conductive layer 26 can be formed simultaneously or in stages.

[0093] Specifically, while ensuring device performance, the opening size and shape of the first contact hole can be selected according to the actual situation; the opening size and shape of the second contact hole can be selected according to the actual situation; and the opening size and shape of the third contact hole can be selected according to the actual situation.

[0094] Specifically, the methods for forming the first electrode 4 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the methods for forming the second electrode 41 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; and the methods for forming the third electrode 42 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. Methods; methods for forming the fourth electrode 43 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; methods for forming the first gate include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; methods for forming the second gate include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0095] Specifically, such as Figure 7 and Figure 8 As shown, they are respectively Figure 5 Chinese components and Figure 5 The threshold voltage of the device after normal injection of the first particle into the second region 12 of the middle structure varies with the width W of the second source-drain region 16. Figure 5 Chinese components and Figure 5A scatter plot of the drain current and threshold voltage distribution of the device after normal injection of the first particle in the second region 12 of the middle structure. The channel length L of the device is 1 μm in all cases, except... Figure 5 Except for the narrow-channel devices in the figure, which were not amorphized, the relevant parameters in the same region are the same. As can be seen from the figure, after the first particle implantation before doping ion implantation is omitted in the source and drain regions of the narrow-channel device, the threshold voltage of the device increases slightly, but the performance is not significantly affected. The electrical parameters of the wide-channel device are not significantly changed, and the anti-narrow-channel effect of the narrow-channel device is reduced.

[0096] Specifically, in the process of fabricating narrow-channel devices, the step of forming an amorphous region 17 in the region to be implanted by the third particle adjacent to the second isolation structure in the second region 12 is skipped, and the third particle is implanted directly. This can reduce the lateral diffusion of ions at the boundary between the second source / drain region 16 and the second isolation structure, thereby effectively suppressing the anti-narrow-channel effect, improving the stability and reliability of small-size devices, with lower cost, simple process and compatibility with CMOS process.

[0097] The semiconductor device fabrication method of this embodiment skips the step of amorphization treatment of the third particle to be implanted region adjacent to the second isolation structure in the second region 12 during the fabrication of the narrow channel device, and directly implants the third particle. This reduces the lateral diffusion of ions at the boundary between the second source / drain region 16 of the narrow channel device and the second isolation structure, effectively suppresses the anti-narrow channel effect of small-size devices, improves the stability and reliability of small-size devices, and has a simple process that is compatible with CMOS processes.

[0098] Example 2

[0099] This embodiment also provides a semiconductor device, such as Figure 5 and Figure 6 The figures shown are a cross-sectional view of the semiconductor device and a diagram showing the distribution of various structures on the top surface of a portion of the semiconductor device. The semiconductor device is fabricated using the semiconductor device fabrication method described above.

[0100] Specifically, the semiconductor device includes a semiconductor structure 1, a first source / drain region 15, a second source / drain region 16, a first electrode 4, a second electrode 41, a third electrode 42, and a fourth electrode 43. The semiconductor structure 1 includes a first region 11, a second region 12, a first gate structure 2, and a second gate structure 24. The first gate structure 2 and the second gate structure 24 are located on the upper surfaces of the first region 11 and the second region 12, which are spaced apart. The first source / drain region 15 is located on the upper surface of the first region 11 on opposite sides of the first gate conductive layer 22 in the first gate structure 2. The second source / drain region 16 is located on the upper surface of the second region 12 on opposite sides of the second gate conductive layer 26 in the second gate structure 24. The first electrode 4 and the second electrode 41 are electrically connected to the first source / drain regions 15 on opposite sides of the first gate conductive layer 22, respectively. The third electrode 42 and the fourth electrode 43 are electrically connected to the second source / drain regions 16 on opposite sides of the second gate conductive layer 26, respectively. The first gate and the second gate are electrically connected to the first gate conductive layer 22 and the second gate conductive layer 26, respectively.

[0101] Specifically, while ensuring device performance, the doping concentration of region 11 in the first region can be selected according to the actual situation; the doping concentration of region 12 in the second region can be selected according to the actual situation.

[0102] Specifically, the semiconductor structure 1 also includes an isolation structure 18, which includes a first isolation structure surrounding the first region 11 and a second isolation structure surrounding the second region 12. The first isolation structure is embedded in the semiconductor structure 1 surrounding the first region 11, and the second isolation structure is embedded in the semiconductor structure 1 surrounding the second region 12. The first isolation structure includes a first isolation trench surrounding the first region 11 and a first isolation layer filling the first isolation trench. The second isolation structure includes a second isolation trench surrounding the second region 12 and a second isolation layer filling the second isolation trench.

[0103] Specifically, the semiconductor structure 1 also includes a first shallow doped region 13 and a second shallow doped region 14. The first shallow doped region 13 is located on the upper surface of the first region 11 on both sides of the first gate conductive layer 22, and the first source / drain region 15 is located on the upper surface of the first shallow doped region 13. The adjacent sidewalls of the two first shallow doped regions 13 on both sides of the first gate conductive layer 22 extend to the bottom of the first gate conductive layer 22. The second shallow doped region 14 is located on the upper surface of the second region 12 on both sides of the second gate conductive layer 26, and the second source / drain region 16 is located on the upper surface of the second shallow doped region 14. The adjacent sidewalls of the two second shallow doped regions 14 on both sides of the second gate conductive layer 26 extend to the bottom of the second gate conductive layer 26.

[0104] Specifically, while ensuring device performance, the doping concentration of the first shallow doped region 13 can be selected according to the actual situation; the doping concentration of the second shallow doped region 14 can be selected according to the actual situation; the doping concentration of the first source / drain region 15 can be selected according to the actual situation; and the doping concentration of the second source / drain region 16 can be selected according to the actual situation.

[0105] Specifically, the sidewall of the first source / drain region 15 adjacent to the first gate conductive layer 22 is spaced apart from the sidewall of the first shallow doped region 13 located directly below the first gate conductive layer 22 by a predetermined distance; the sidewall of the second source / drain region 16 adjacent to the second gate conductive layer 26 is spaced apart from the sidewall of the second shallow doped region 14 located directly below the second gate conductive layer 26 by a predetermined distance.

[0106] Specifically, the first gate structure 2 further includes a first gate dielectric layer 21 and a first sidewall layer 23. The first gate dielectric layer 21 is located on the upper surface of the first region 11, the first gate conductive layer 22 is located on the upper surface of the first gate dielectric layer 21, and the first sidewall layer 23 covers the sidewall of the first gate conductive layer 22. The second gate structure 24 further includes a second gate dielectric layer 25 and a second sidewall layer 27. The second gate dielectric layer 25 is located on the upper surface of the second region 12, the second gate conductive layer 26 is located on the upper surface of the second gate dielectric layer 25, and the second sidewall layer 27 covers the sidewall of the second gate conductive layer 26.

[0107] Specifically, the material of the first gate dielectric layer 21 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the first gate conductive layer 22 includes polysilicon or other suitable conductive materials; the material of the first sidewall layer 23 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, or other suitable dielectric materials; the material of the second gate dielectric layer 25 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the second gate conductive layer 26 includes polysilicon or other suitable conductive materials; and the material of the second sidewall layer 27 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, or other suitable dielectric materials.

[0108] Specifically, the semiconductor device also includes an interlayer dielectric layer 3, a first contact hole, a second contact hole, and a third contact hole. The interlayer dielectric layer 3 covers the exposed upper surface of the semiconductor structure 1. The first contact hole penetrates the interlayer dielectric layer 3 directly above the first source / drain regions 15 on opposite sides of the first gate conductive layer 22 and exposes the first source / drain regions 15 on its bottom surface. The second contact hole penetrates the interlayer dielectric layer 3 directly above the second source / drain regions 16 on opposite sides of the second gate conductive layer 26 and exposes the second source / drain regions 16 on its bottom surface. The third contact hole penetrates the interlayer dielectric layer 3 directly above the first gate conductive layer 22 and the second gate conductive layer 26 and exposes the first gate conductive layer 22 and the second gate conductive layer 26 on its bottom surface.

[0109] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, or other suitable dielectric materials.

[0110] Specifically, the first electrode 4 and the second electrode 41 fill the first contact holes on opposite sides of the first gate conductive layer 22 and are electrically connected to the first source / drain region 15 at the bottom, respectively. The third electrode 42 and the fourth electrode 43 fill the second contact holes on opposite sides of the second gate conductive layer 26 and are electrically connected to the second source / drain region 16 at the bottom, respectively. The first gate fills the third contact hole directly above the first gate conductive layer 22 and is electrically connected to the first gate conductive layer 22 at the bottom. The second gate fills the third contact hole directly above the second gate conductive layer 26 and is electrically connected to the second gate conductive layer 26 at the bottom.

[0111] Specifically, the material of the first electrode 4 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the material of the second electrode 41 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the material of the third electrode 42 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the material of the fourth electrode 43 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the material of the first gate includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; and the material of the second gate includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials.

[0112] Specifically, by using the semiconductor device fabrication method described in Example 1, the performance of the device is improved, the reverse narrow channel effect of narrow channel devices in semiconductor devices is reduced, and the stability and reliability of small-sized devices are improved.

[0113] The semiconductor device in this embodiment is fabricated using the semiconductor device fabrication method described in Embodiment 1, which reduces the reverse narrow channel effect of narrow channel devices in semiconductor devices and improves the stability and reliability of small-size devices.

[0114] In summary, the semiconductor device and its fabrication method of the present invention, by improving the semiconductor device fabrication process, eliminates the step of amorphizing the region to be implanted with the third particle adjacent to the second isolation structure in the second region during the fabrication of the narrow-channel device. Instead, the third particle is directly implanted, reducing the lateral diffusion of ions at the interface between the second source / drain region and the second isolation structure. This effectively suppresses the reverse narrow-channel effect in small-sized devices, improves the stability and reliability of small-sized devices, and the process is simple and compatible with CMOS technology. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor structure is provided, comprising a first region, a second region, a first gate structure, and a second gate structure, wherein the first gate structure and the second gate structure are respectively located on the upper surfaces of the first region and the second region, which are spaced apart. First particles and second particles are sequentially injected into the upper surface layer of the first region on both sides of the first gate conductive layer in the first gate structure, and third particles are injected into the upper surface layer of the second region on both sides of the second gate conductive layer in the second gate structure, so as to form a first source / drain region in the first region with the opposite conductivity type to the first region and a second source / drain region in the second region with the opposite conductivity type to the second region. A first electrode and a second electrode are formed that are electrically connected to the first source and drain regions on opposite sides of the first gate conductive layer, a third electrode and a fourth electrode are formed that are electrically connected to the second source and drain regions on opposite sides of the second gate conductive layer, a first gate electrode is formed that is electrically connected to the first gate conductive layer, and a second gate electrode is formed that is electrically connected to the second gate conductive layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that: The first gate structure further includes a first gate dielectric layer and a first sidewall layer. The first gate dielectric layer is located on the upper surface of the first region, the first gate conductive layer is located on the upper surface of the first gate dielectric layer, and the first sidewall layer covers the sidewall of the first gate conductive layer. The second gate structure further includes a second gate dielectric layer and a second sidewall layer. The second gate dielectric layer is located on the upper surface of the second region, the second gate conductive layer is located on the upper surface of the second gate dielectric layer, and the second sidewall layer covers the sidewall of the second gate conductive layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that: The first particle includes germanium ions and carbon ions; the second particle includes one of trivalent ions and pentavalent ions; the third particle includes one of trivalent ions and pentavalent ions.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that: The second particle is the same as the third particle.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that: The upper surface of the first region is further provided with a first shallow doped region located on opposite sides of the first gate conductive layer, and the first source / drain region is located on the upper surface of the first shallow doped region. The upper surface of the second region is further provided with a second shallow doped region located on opposite sides of the second gate conductive layer, and the second source / drain region is located on the upper surface of the second shallow doped region.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that: Devices fabricated based on the first region are wide-channel devices, while devices fabricated based on the second region are narrow-channel devices.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that: After ion implantation of the upper surface of the first region on both sides of the first gate conductive layer and the upper surface of the second region on both sides of the second gate conductive layer, before forming the first source / drain region and the second source / drain region, a synchronous annealing step is also included.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that: The semiconductor structure also includes an isolation structure, which includes a first isolation structure surrounding the first region and a second isolation structure surrounding the second region.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that: After forming the first source / drain region and the second source / drain region, and before forming the first electrode, the second electrode, the third electrode, the fourth electrode, the first gate, and the second gate, the method further includes forming an interlayer dielectric layer covering the exposed upper surface of the semiconductor structure. The first electrode and the second electrode respectively penetrate the interlayer dielectric layer and are electrically connected to the first source / drain regions on opposite sides of the first gate conductive layer. The third electrode and the fourth electrode respectively penetrate the interlayer dielectric layer and are electrically connected to the second source / drain regions on opposite sides of the second gate conductive layer. The first gate penetrates the interlayer dielectric layer directly above the first gate conductive layer and is electrically connected to the first gate conductive layer. The second gate penetrates the interlayer dielectric layer directly above the second gate conductive layer and is electrically connected to the second gate conductive layer.

10. A semiconductor device, characterized in that, The semiconductor device is fabricated using the semiconductor device fabrication method as described in any one of claims 1 to 9.

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