Semiconductor element and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a method for manufacturing the same. The method includes the following steps: forming a first recess in a substrate; forming a gate dielectric layer in the first recess; forming a gate structure on the gate dielectric layer; removing part of the gate structure and part of the substrate to form a second recess; forming a liner layer in the second recess; forming a field plate in the second recess; forming a protective layer on the gate structure; forming a source electrode on the substrate and connecting the field plate; and forming a drain electrode on the back of the substrate.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a silicon carbide metal oxide semiconductor field-effect transistor (SiC MOSFET) and a method for manufacturing the same. Background Technology

[0002] Power semiconductor devices include insulated gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). Silicon carbide MOSFETs have critical breakdown strength, can operate at higher temperatures, provide higher current density, and support higher switching frequencies.

[0003] While metal-oxide-semiconductor (MOSFETs) offer the aforementioned advantages, the thin gate oxide layer and low oxide quality make the gate oxide layer of silicon carbide (SiMo) MOSFETs relatively fragile during operation and electrostatic discharge (ESD) stress, due to voltage surges caused by gate bias. In existing technologies, additional devices can be added to semiconductor devices to protect the gate oxide layer from voltage overshoot and ESD stress. However, these additional devices require additional space to accommodate the structures, thus increasing the cell spacing of the semiconductor device. Since existing SiMo manufacturing methods still present many problems, providing a SiMo MOSFET and its manufacturing method to address the shortcomings of existing technologies and enhance practical industrial applications is a crucial issue. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first forming a first groove in a substrate, then forming a gate dielectric layer in the first groove, forming a gate structure on the gate dielectric layer, removing part of the gate structure and part of the substrate to form a second groove, forming a pad layer in the second groove, forming a field electrode in the second groove, forming a protective layer on the gate structure, forming a source electrode on the substrate and connecting it to the field electrode, and finally forming a drain electrode on the back side of the substrate.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a field electrode plate disposed in a substrate, a first gate structure disposed on one side of the field electrode plate, a second gate structure disposed on the other side of the field electrode plate, a source electrode disposed on the substrate and connected to the field electrode plate, and a drain electrode disposed on the back side of the substrate.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a field electrode plate disposed in a substrate, a first gate structure disposed on one side of the field electrode plate, a second gate structure disposed on the other side of the field electrode plate, a first gate dielectric layer disposed next to the first gate structure, a pad layer disposed between the field electrode plate and the first gate structure, a source electrode disposed on the substrate and connected to the field electrode plate, and a drain electrode disposed on the back side of the substrate, wherein the pad layer and the first gate dielectric layer have different thicknesses. Attached Figure Description

[0007] Figures 1 to 7 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0008] Figure 8 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0009] Figure 9 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention.

[0010] Symbol explanation:

[0011] 12: Base

[0012] 14: Drift Zone

[0013] 16:Matrix area

[0014] 18: Doped region

[0015] 20: Doped region

[0016] 22: Doped region

[0017] 24: First Groove

[0018] 26: Doped region

[0019] 28: Doped region

[0020] 30: Gate dielectric layer

[0021] 32: Gate structure

[0022] 34: Second groove

[0023] 36: Gate dielectric layer

[0024] 38: Gate dielectric layer

[0025] 40: Gate structure

[0026] 42: Gate structure

[0027] 44: Lining layer

[0028] 46: Field plate

[0029] 48: Protective layer

[0030] 50: Source electrode

[0031] 52: Drain electrode

[0032] 54: Third groove

[0033] 64 cushioning layer

[0034] 66: Field plate

[0035] 68 padding layers

[0036] 70: Field plate

[0037] 72: Lining layer

[0038] 74: Field plate Detailed Implementation

[0039] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0040] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0041] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context), as used herein, can be used to describe any feature, structure, or characteristic in a single sense, or to describe multiple combinations of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a single usage or to convey multiple usages, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0042] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosed content of this case should be interpreted in the broadest possible sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “above” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0043] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0044] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers (wafers).

[0045] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0046] Please refer to Figures 1 to 7 , Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1As shown, a substrate 12 made of semiconductor material is first provided. The substrate 12 preferably comprises a silicon carbide (SiC) substrate or, more specifically, an N+ silicon carbide substrate, but is not limited thereto. According to other embodiments of the present invention, the substrate 12 may also be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, or even a silicon-on-insulator (SOI) substrate; all these material choices are within the scope of the present invention. Then, a drift region 14 can be formed on the substrate 12 using epitaxial growth. The drift region 14 preferably comprises an N- drift region, but is not limited thereto.

[0047] like Figure 2 As shown, a body region 16 and a doped region 18 are then formed sequentially from bottom to top above the drift region, and doped regions 20 and 22 are formed on both sides of the subsequently formed gate structure (not shown) or gate dielectric layer. In this embodiment, the drift region 14 and the body region 16 preferably have different conductivity types, and the doped region 18 and the doped regions 20 and 22 preferably have different conductivity types. The drift region 14 preferably includes an N-drift region, the body region 16 includes a P-body region, the doped region 18 includes an N+ doped region, and the doped regions 20 and 22 each include a P+ doped region. Furthermore, the depth of the doped regions 20 and 22 is preferably greater than the depth of the doped region 18, or the bottom surface of the doped regions 20 and 22 is preferably slightly lower than the bottom surface of the doped region 18.

[0048] Subsequently, as Figure 3 As shown, a photolithography and etching process is performed to form a first groove 24 within the substrate 12. In this embodiment, the first groove 24 can be formed by first performing an etching process using a patterned mask, such as a patterned photoresist, to remove a portion of the substrate 12, including a portion of the doped region 18, a portion of the substrate region 16, and even a portion of the drift region 14, to form the first groove 24. The bottom surface of the first groove 24 may be slightly lower than the bottom surface of the substrate region 16, as in this embodiment, or it may be flush with or slightly higher than the bottom surface of the substrate region 16 but still lower than the top surface of the substrate region 16; all of these fall within the scope of this invention.

[0049] It should be noted that after removing part of the doped region 18 to form the first groove 24 in this stage, it is preferable to divide the remaining doped region 18 into doped regions 26 and 28 on both sides of the first groove 24, wherein the width of each doped region 26 and 28 can be approximately equal to the width of the adjacent doped regions 20 and 22. In addition, for the purpose of clearly illustrating the positions of the subsequent components, the drift region 14, the substrate region 16, and the doped regions 20, 22, 26, and 28 above the substrate 12 can all be collectively referred to as the substrate 12, and the first groove 24 is formed within the substrate 12.

[0050] Then as Figure 4As shown, a gate dielectric layer 30 and a gate material layer (not shown) are sequentially formed in the first groove 24 and on the surfaces of the substrate 12 on both sides of the first groove 24, filling the first groove 24. Then, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove part of the gate dielectric layer 30 and part of the gate material layer, leaving the top surfaces of the remaining gate dielectric layer 30 and part of the gate material layer approximately flush with the surfaces of the substrate 12 on both sides, forming a gate structure 32 in the first groove 24. A patterned gate dielectric layer 30 is disposed between the substrate 12 and the gate structure 32. In this embodiment, the gate dielectric layer 30 may contain silicon oxide, and the gate material layer or gate structure 32 may contain polysilicon or metal, but is not limited to these.

[0051] like Figure 5 As shown, another photolithography and etching process is then performed to form a second groove 34 within the substrate 12. In this embodiment, the second groove 34 can be formed by first performing an etching process using a patterned mask, such as a patterned photoresist, to remove a portion of the gate structure 32, a portion of the gate dielectric layer 30, and a portion of the substrate 12 directly below the gate structure 32 to form the second groove 34. Preferably, the bottom surface of the second groove 34 is lower than the bottom surface of the first groove 24, and the depth of the second groove 34, for example, the distance from the bottom surface to the top surface of the second groove 24, can be greater than one, two, three, or even more than three times the thickness of the first groove 24, all of which are within the scope of this invention.

[0052] It should also be noted that after removing part of the gate structure 32 and part of the gate dielectric layer 30 to form the second groove 34 in this stage, it is preferable to separate the remaining gate dielectric layer 30 and gate structure 32 into gate dielectric layers 36 and 38 and gate structures 40 and 42 on both sides of the second groove 34. The width of each gate structure 40 and 42 can be slightly larger than the width of each doped region 20, 22, 26 and 28 but smaller than the width of the second groove 34. The gate dielectric layer 30, which originally had a U-shaped cross section, is changed in this stage to gate dielectric layers 36 and 38 with an L-shaped cross section, which are respectively disposed between the substrate 12 and the gate structures 40 and 42.

[0053] Subsequently, as Figure 6As shown, a pad layer 44 and a field plate 46 are sequentially formed in the second groove 34 and on the surface of the substrate 12 on both sides of the second groove 34, filling the second groove 34. Then, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove part of the field plate 46 and part of the pad layer 44, so that the remaining field plate 46 and the top surface of the pad layer 44 are approximately flush with the surfaces of the substrate 12 on both sides. In this embodiment, the pad layer 44 preferably contains silicon oxide, while the field plate 46 may contain the same or different materials as the aforementioned gate structure 32, such as polysilicon or metal, but is not limited thereto. Furthermore, although the thickness of the pad layer 44 formed in this stage is slightly greater than the thickness of each gate dielectric layer 36, 38, it is not limited thereto. According to other embodiments of the present invention, the pad layer 44 and each gate dielectric layer 36, 38 may have the same thickness, and this variation is also within the scope of the present invention.

[0054] Then as Figure 7 As shown, a protective layer 48 is first formed on the gate structures 40 and 42, and then a source electrode 50 is formed to connect to the field plate 46. More specifically, in this stage, a protective layer 48 made of, for example, silicon oxide can be formed comprehensively on the substrate 12, covering the field plate 46, the gate structures 40 and 42, and the doped regions 20, 22, 26, and 28. Then, a photolithography and etching process is performed. For example, a patterned mask, such as a patterned photoresist, is used as a mask to etch away part of the protective layer 48, so that the remaining protective layer 48 covers the pad layer 44, the gate structures 40 and 42, the gate dielectric layers 36 and 38, and the doped regions 26 and 28, but preferably does not cover the doped regions 20 and 22 and most or even all of the field plates 46. The patterned protective layer 48 may have two inclined sidewalls or vertical sidewalls as shown in the figure, all of which are within the scope of this invention.

[0055] Next, a source electrode 50 is formed to fully cover the protective layer 48 and the doped regions 20 and 22 and connect to the field plate 46. In this embodiment, the source electrode 50 may contain conductive or metallic materials such as aluminum, titanium, or titanium nitride. Finally, the substrate 12 can be flipped and a deposition process is performed to form a conductive layer on the back side or bottom surface of the substrate 12 as a drain electrode 52. In this embodiment, the drain electrode 52 may contain the same or different materials as the source electrode 50; for example, the drain electrode 52 may contain conductive or metallic materials such as aluminum, titanium, or titanium nitride. This completes the fabrication of a semiconductor element or silicon carbide metal-oxide-semiconductor field-effect transistor of the present invention.

[0056] Please continue to refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 8 As shown, compared to Figure 7In this embodiment, only a single field plate 46 is formed within the substrate 12 between the gate structures 40 and 42. The present invention... Figure 5 When forming the second groove 34, the size of the original second groove 34 can be adjusted, such as increasing the overall width of the second groove 34 but decreasing the depth of the original second groove 34, and then compared with... Figure 6 The padding layer 44 and the field electrode 46 are filled into the second groove 34 and a planarization process is performed. Then, another photolithography and etching process is performed to remove part of the field electrode 46, part of the padding layer 44 and part of the substrate 12 directly below the padding layer 44 to form a third groove 54. Then, another padding layer 64 and another field electrode 66 are formed in the third groove 54 and a planarization process is performed to make the top surface of the remaining padding layer 64 and the top surface of the remaining field electrode 66 approximately flush with the surfaces of the substrate 12 on both sides.

[0057] It should be noted that when removing part of the pad layer 44 and part of the field plate 46 using photolithography and etching processes in this stage, it is preferable to separate the pad layer 44 and the field plate 46 into two parts, such as the pad layer 68 and the field plate 70 located on the left side of the subsequent field plate 66, and the pad layer 72 and the field plate 74 located on the right side of the field plate 66. The bottom surface of the middle field plate 66 is preferably lower than the bottom surfaces of the field plates 70 and 74 located on the left and right sides. The three field plates 66, 70, and 74 can have the same or different widths, and the width of each field plate 66, 70, and 74 can be slightly smaller than the width of each gate structure 40 and 42. In this embodiment, the composite field plate design can provide a new peak electric field and reduce the highest electric field value at the edge of the gate structure.

[0058] Please continue to refer to Figure 9 , Figure 9 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 9 As shown, compared to Figure 8 In this embodiment, the gate dielectric layers 36 and 38 and the pad layer 44 are all made of silicon oxide. In this embodiment, the gate dielectric layers 36 and 38 and / or the pad layer 44 may be made of a high-dielectric-constant dielectric layer. In other words, the gate dielectric layers 36 and 38 and the pad layer 44 in this embodiment may be made of the same or different materials and have different material combinations. For example, the gate dielectric layers 36 and 38 may be made of silicon oxide while the pad layer 44 may be made of a high-dielectric-constant dielectric layer; the gate dielectric layers 36 and 38 may be made of a high-dielectric-constant dielectric layer while the pad layer 44 may be made of silicon oxide; or the gate dielectric layers 36 and 38 and the pad layer 44 may all be made of the same or different high-dielectric-constant dielectric layers. These variations are all within the scope of this invention.

[0059] In this embodiment, the high dielectric constant dielectric layer may comprise a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide (SrTiO3). SrBi₂Ta₂O₉, SBT, lead zirconate titanate, PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1-x The group consisting of TiO3, BST, or combinations thereof.

[0060] Furthermore, the gate dielectric layers 36 and 38 and the pad layer 44 preferably have different thicknesses, wherein the thickness of the pad layer 44 is preferably greater than the thickness of each of the gate dielectric layers 36 and 38. For example, the thickness of the pad layer 44 is preferably greater than one, two, three, or even more than three times the thickness of the gate dielectric layer 36 or 38, all of which fall within the scope of this invention. In this embodiment, using a high dielectric constant material to form the gate dielectric layer and / or the pad layer can improve the on-resistance (R) of the device. ON By controlling the thickness of the pad layer to be greater than the thickness of the gate dielectric layer, the breakdown voltage (V) of the device can be modified. BD ).

[0061] In summary, this invention mainly discloses a method and related structure for fabricating a silicon carbide metal-oxide-semiconductor field-effect transistor (SiCMOSFET). The method primarily involves first forming a first groove 24 within a substrate, then forming a gate structure within the first groove, removing a portion of the gate structure and a portion of the substrate to form a second groove while simultaneously dividing the gate structure into two parts, and finally filling the second groove with a pad layer and a field electrode plate. According to a preferred embodiment of this invention, as follows... Figure 7 As shown, placing the buried gate structure on both sides of the buried field electrode can significantly reduce the peak electric field at the edge of the gate structure. Besides placing only a single field electrode within the substrate, according to the present invention… Figure 8 The embodiments can also be selected from Figure 6 After forming the field electrode, a third groove is formed to divide the field electrode into two parts, and then another field electrode is filled into the third groove, thereby forming a three-field electrode structure. Furthermore, according to the present invention... Figure 9 In some embodiments, the gate dielectric layers 36 and 38 next to the gate structure and / or the pad layer 44 around the field plate may be made of a high dielectric constant dielectric layer, and the gate dielectric layers 36 and 38 and the pad layer 44 may also have the same or different thicknesses depending on the manufacturing process or product requirements. These variations are all within the scope of this invention.

[0062] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: The first groove is formed within the substrate; A gate structure is formed within the first recess; Remove the gate structure and the substrate to form a second recess; and A field electrode is formed in the second groove.

2. The method of claim 1, further comprising: A matrix region is formed on the substrate; A first doped region is formed on the substrate region; Multiple second doped regions are formed on both sides of the first groove; This first groove is formed; A gate dielectric layer is formed in the first groove; The gate structure is formed on the gate dielectric layer; This second groove is formed; A liner layer is formed within the second groove; The field plate is formed on the liner layer; A protective layer is formed on the gate structure; A source electrode is formed on the substrate and connected to the field electrode plate; as well as A drain electrode is formed on the back side of the substrate.

3. The method of claim 2, wherein the substrate region and the plurality of second doped regions comprise the same conductivity type.

4. The method of claim 2, wherein the substrate region and the first doped region comprise different conductivity types.

5. The method of claim 2, wherein the first doped region and the plurality of second doped regions comprise different conductivity types.

6. The method of claim 2, wherein the depth of the plurality of second doped regions is greater than the depth of the first doped region.

7. The method of claim 2, wherein the depth of the first groove is greater than the depth of the base region.

8. A semiconductor element, characterized in that, Include: Field plates are disposed within the substrate; The first gate structure is disposed on one side of the field electrode; The second gate structure is located on the other side of the field electrode; The source electrode is disposed on the substrate and connected to the field electrode plate; as well as The drain electrode is located on the back side of the substrate.

9. The semiconductor element of claim 8, further comprising: A substrate region is disposed on both sides of the first gate structure and the second gate structure; The first doped region and the second doped region are disposed on one side of the first gate structure; The third and fourth doped regions are disposed on one side of the second gate structure; and A protective layer is disposed on the first gate structure and the second gate structure.

10. The semiconductor device of claim 9, wherein the first doped region and the second doped region comprise different conductivity types.

11. The semiconductor device of claim 9, wherein the third doped region and the fourth doped region comprise different conductivity types.

12. The semiconductor element of claim 9, further comprising: A first gate dielectric layer is disposed between the first gate structure and the substrate region; A second gate dielectric layer is disposed between the second gate structure and the substrate region; and A pad layer is disposed between the field plate and the first gate structure.

13. The semiconductor device of claim 12, wherein the pad layer comprises a U-shape.

14. The semiconductor device of claim 12, wherein the first gate dielectric layer comprises an L-shape.

15. A semiconductor element, characterized in that, Include: Field plates are disposed within the substrate; The first gate structure is disposed on one side of the field electrode; The second gate structure is located on the other side of the field electrode; A first gate dielectric layer is disposed next to the first gate structure; A pad layer is disposed between the field electrode and the first gate structure, wherein the pad layer and the first gate dielectric layer have different thicknesses; The source electrode is disposed on the substrate and connected to the field electrode plate; as well as The drain electrode is located on the back side of the substrate.

16. The semiconductor element of claim 15, further comprising: A substrate region is disposed on both sides of the first gate structure and the second gate structure; The first doped region and the second doped region are disposed on one side of the first gate structure; The third and fourth doped regions are disposed on one side of the second gate structure; and A protective layer is disposed on the first gate structure and the second gate structure.

17. The semiconductor device of claim 15, further comprising a second gate dielectric layer disposed adjacent to the second gate structure, wherein the first gate dielectric layer and the second gate dielectric layer comprise the same material.

18. The semiconductor device of claim 15, wherein the dielectric constant of the first gate dielectric layer is greater than the dielectric constant of the pad layer.

19. The semiconductor device of claim 15, wherein the first gate dielectric layer comprises a high dielectric constant dielectric layer.

20. The semiconductor device of claim 15, wherein the thickness of the first gate dielectric layer is less than the thickness of the pad layer.

Images