A method for reducing high-temperature leakage of a PD-SOI MOS device

Abstract

The application discloses a method for reducing high-temperature leakage of a PD-SOI MOS device, which adopts a double-layer filling structure in shallow trench isolation of the PD-SOI MOS device, fills high-stress material at the bottom of the shallow trench isolation, and fills stress-free or low-stress material at the top of the shallow trench isolation; the stress layer at the bottom of the shallow trench isolation applies lateral mechanical stress to a neutral region at the bottom of a well region, causes distortion of a band structure of silicon in the neutral region, increases a scattering rate of minority carriers, equivalently reduces a diffusion coefficient of the minority carriers, and thus inhibits diffusion leakage of the minority carriers to a boundary of a depletion region at high temperature; the top filling layer of the shallow trench isolation does not apply significant stress to a channel region, and maintains high mobility of the minority carriers in the channel region. The application does not introduce additional impurities and annealing processes, is compatible with a standard CMOS process, and does not affect on-state characteristics of the device. Therefore, the application is particularly suitable for reducing high-temperature leakage of the PD-SOI MOS device and improving application effects of the PD-SOI process in a high-temperature environment.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for reducing high-temperature leakage current in PD-SOI MOS devices. Background Technology

[0002] With the increasing demands for high-temperature operating capabilities of electronic systems in aerospace, oil drilling, automotive electronics, and other fields, the high-temperature characteristics of silicon-based MOS devices have become a research hotspot. Partially depleted SOI technology, relying on the isolation effect of the buried oxide layer (BOX) in the SOI wafer structure, significantly reduces the inherent well-substrate junction leakage current of bulk silicon MOS devices, and has become one of the mainstream substrate technologies for high-temperature applications.

[0003] However, under high temperature conditions (especially temperatures >150°C), a large number of minority carriers will still be generated in the neutral region near the buried oxide layer at the bottom of the PD-SOI MOS device. After these minority carriers reach the depletion region boundary through diffusion, they will be swept across the junction region by the built-in electric field of the depletion region, causing a sharp increase in the reverse bias leakage current of the PN junction of the MOS device.

[0004] Existing methods for suppressing high-temperature leakage current in PD-SOI MOS devices mainly include increasing the doping concentration in the well region to reduce the minority carrier concentration and using shallow junction processes to extend the diffusion path. However, increasing the doping concentration increases the junction capacitance, affecting the threshold voltage; the effectiveness of shallow junctions is limited by the minimum junction depth process. Therefore, the field of high-temperature semiconductor device technology urgently needs a method for reducing high-temperature leakage current in PD-SOI devices that is simple to process and does not affect the on-state characteristics of the channel region. Summary of the Invention

[0005] The purpose of this invention is to provide a method for reducing high-temperature leakage current in PD-SOI MOS devices, thereby solving the problems in the background art.

[0006] To address the aforementioned technical problems, this invention provides a method for reducing high-temperature leakage current in PD-SOI MOS devices, comprising: An SOI substrate is provided, wherein the SOI substrate comprises, from bottom to top, a back substrate, a buried oxide layer, and a top silicon layer; The top silicon layer is etched to form a shallow trench isolation structure. The shallow trench isolation structure surrounds the active region of the MOS device, and a thin pad oxide layer is grown on the sidewall of the shallow trench isolation structure. A bottom stress layer is deposited in the lower half of the shallow trench isolation structure. The bottom stress layer is in contact with the sidewall of the bottom neutral zone of the well area. The material of the bottom stress layer is a material with high mechanical stress. A top filler layer is deposited on the upper half of the shallow trench isolation structure, and the material of the top filler layer is a stress-free or low-stress medium. After planarization, a well region, a gate region, and source / drain regions are formed, all of which are located within the active region; Forming metal contacts and interconnections.

[0007] In one embodiment, the bottom stress layer is prepared by plasma-enhanced chemical vapor deposition or high-density plasma-enhanced chemical vapor deposition, and the stress magnitude and type are controlled by adjusting the deposition parameters.

[0008] In one embodiment, the stress type of the bottom stress layer is compressive stress or tensile stress.

[0009] In one embodiment, the bottom stress layer applies lateral stress to the bottom neutral region of the adjacent well region. This stress distorts the band structure of silicon within the neutral region, increases the scattering rate of minority carriers, effectively reduces the minority carrier diffusion coefficient, and suppresses the diffusion flux of minority carriers to the depletion region boundary at high temperatures.

[0010] In one embodiment, the top filling layer is made of silicon dioxide or low-stress silicon nitride, which does not apply significant stress to the channel region in order to maintain the high mobility of charge carriers in the channel region.

[0011] In one embodiment, the well region is a P-type well region or an N-type well region.

[0012] The present invention provides a method for reducing high-temperature leakage current in PD-SOI MOS devices, which has the following advantages: 1. No additional impurities are introduced. Completely controlled by mechanical stress, it avoids ion implantation damage and annealing processes, and is highly compatible with standard CMOS processes.

[0013] 2. Selective application region. Stress only acts on the neutral region at the bottom of the well region, without affecting the stress state of the channel region and without sacrificing the on-state characteristics of the device.

[0014] 3. Significantly effective at suppressing high-temperature leakage current. Stress-induced band distortion increases minority carrier scattering, effectively reducing the diffusion coefficient.

[0015] 4. High long-term reliability. The stress structure remains stable during device operation, with no degradation mechanism.

[0016] In summary, this invention can significantly reduce high-temperature leakage current of PD-SOI MOS devices, and is particularly suitable for high-temperature applications such as aerospace, oil drilling, and automotive electronics. Attached Figure Description

[0017] Figures 1-7 A schematic diagram of the steps involved in forming a double-layer filled STI PD-SOI MOS device.

[0018] Figure 8This is a schematic diagram of the reverse-biased leakage current of the PN junction in the off-state of a double-layer filled STI PD-SOI MOS device.

[0019] Figure 9 This is a method for fabricating PD-SOI MOS devices with double-layer filled STI. Detailed Implementation

[0020] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for reducing high-temperature leakage current in PD-SOI MOS devices according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0021] Research has revealed that when the neutral region at the bottom of the well region of a MOS device is subjected to a certain amount of mechanical stress, the band structure of the silicon material in this region will be distorted. This distortion increases the scattering rate of minority carriers in the neutral region, which is equivalent to reducing the diffusion coefficient of minority carriers. D This suppresses the diffusion flux of minority carriers to the depletion region boundary at high temperatures. According to the diffusion current formula, this method can significantly suppress reverse-biased leakage current in PN junctions.

[0022] Therefore, introducing a stress layer at the bottom of the STI is an effective way to reduce high-temperature leakage current in PD-SOI MOS devices. Furthermore, by controlling the stress layer's effective region to be in the neutral region at the bottom of the well, it will not affect the on-state performance of the PD-SOI MOS device. Example 1

[0023] This embodiment provides a method for fabricating PD-SOI NMOS devices using a double-layer filled STI structure. The high-temperature leakage current is reduced through STI stress modulation. The process is as follows: Figure 9 As shown, it includes the following steps: Provide SOI substrate like Figure 1 As shown, a PD-SOI substrate is provided, with silicon as the back substrate. From bottom to top, it includes: a back silicon substrate 1, a buried oxide layer 2, and a top silicon layer 4. The top silicon layer 4 has a P-type conductivity.

[0024] Step 2: Forming shallow trenches like Figure 2 As shown, the top silicon layer 4 is etched to form a shallow trench 3, and the trench sidewalls are oxidized to grow a thin pad silicon dioxide. The thickness of the thin pad silicon dioxide is too small to be shown in the figure.

[0025] Step 3: Fill the STI bottom stress layer like Figure 3As shown, high-stress silicon nitride is deposited in the trench using high-density chemical vapor deposition or plasma-enhanced chemical vapor deposition, with the deposition thickness filling to the target position of the bottom neutral region of the well region; the STI bottom stress layer 11 applies lateral stress to the bottom neutral region of the well region.

[0026] Step 4: Fill the top of the STI with regular filler layer like Figure 4 As shown, stress-free silica is deposited to fill the remaining trenches and form the STI top conventional filler layer 12; chemical mechanical polishing is then performed for planarization.

[0027] Step 5: Forming a P-type well region like Figure 5 As shown, P-type well injection is performed in the active region.

[0028] Step 6: Form the gate oxide layer and gate electrode. like Figure 6 As shown, a gate oxide layer 5 is grown on the surface of the top silicon layer. Polysilicon or a metal gate material 6 is deposited on the gate oxide layer 5. The gate pattern is formed by photolithography and etching.

[0029] Step 7: Form source / drain regions like Figure 7 As shown, drain region 7 and source region 8 are implanted using the gate as a mask. Depletion region 9 is formed between drain region 7 and P-type well region, and depletion region 10 is formed between source region 8 and P-type well region.

[0030] Step 8: Rapid thermal annealing Rapid thermal annealing is performed to activate the injected impurities.

[0031] Step 9: Forming metal contacts and interconnects The device is fabricated using standard back-end processes to form metal silicides, contact holes, and metal interconnect layers.

[0032] The PD-SOI NMOS device prepared by the above steps forms a high-stress layer at the bottom of the STI, which applies lateral stress to the sidewalls of the STI trench. Figure 8 The circles in the diagram represent minority carriers in the well region, and the arrows indicate the diffusion direction of these minority carriers. This stress is transferred to the neutral region at the bottom of the well (located below the depletion region and above the buried oxide layer), causing distortion in the conduction and valence bands of silicon in the neutral region. This increases the electron-phonon scattering rate and effectively reduces the electron scattering coefficient. D According to the diffusion current formula, the diffusion coefficient... D The reduction in density directly decreases the diffusion current, effectively suppressing reverse-biased leakage current in the PN junction of PD-SOI NMOS devices at high temperatures. Simultaneously, the top filler layer of the STI is stress-free, and the carrier mobility in the channel region remains unaffected. Example 2

[0033] The difference between this embodiment and Embodiment 1 is that the top silicon conductivity type of the PD-SOI is N-type, which is suitable for fabricating PD-SOI PMOS devices.

[0034] For PMOS devices, the well region is N-type, and the minority carriers are holes. Example 3

[0035] The difference between this embodiment and Embodiment 1 is that high-density chemical vapor deposition or plasma-enhanced chemical vapor deposition is used to deposit high-stress silicon carbide, high-stress silicon oxynitride, or high-stress polycrystalline silicon at the bottom of the STI trench. Example 4

[0036] The difference between this embodiment and Embodiment 1 is that low-stress silicon nitride is deposited on top of the STI to fill the remaining trenches.

[0037] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for reducing high-temperature leakage current in PD-SOI MOS devices, characterized in that, include: An SOI substrate is provided, wherein the SOI substrate comprises, from bottom to top, a back substrate, a buried oxide layer, and a top silicon layer; The top silicon layer is etched to form a shallow trench isolation structure. The shallow trench isolation structure surrounds the active region of the MOS device, and a thin pad oxide layer is grown on the sidewall of the shallow trench isolation structure. A bottom stress layer is deposited in the lower half of the shallow trench isolation structure. The bottom stress layer is in contact with the sidewall of the bottom neutral zone of the well area. The material of the bottom stress layer is a material with high mechanical stress. A top filler layer is deposited on the upper half of the shallow trench isolation structure, and the material of the top filler layer is a stress-free or low-stress medium. After planarization, a well region, a gate region, and source / drain regions are formed, all of which are located within the active region; Forming metal contacts and interconnections.

2. The method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 1, characterized in that, The bottom stress layer is constructed using plasma-enhanced chemical vapor deposition or high-density plasma-enhanced chemical vapor deposition, and the stress magnitude and type are controlled by adjusting the deposition parameters.

3. The method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 1, characterized in that, The stress type of the bottom stress layer is either compressive stress or tensile stress.

4. The method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 1, characterized in that, The bottom stress layer is made of silicon nitride, silicon carbide, silicon oxynitride, or polycrystalline silicon.

5. The method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 1, characterized in that, The bottom stress layer applies lateral stress to the neutral region at the bottom of the adjacent well region. This stress distorts the band structure of silicon in the neutral region, increases the scattering rate of minority carriers, effectively reduces the minority carrier diffusion coefficient, and suppresses the diffusion flux of minority carriers to the depletion region boundary at high temperatures.

6. The method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 1, characterized in that, The top filling layer is made of silicon dioxide or low-stress silicon nitride, which does not apply significant stress to the channel region, so as to maintain the high mobility of charge carriers in the channel region.

7. The method for reducing high-temperature leakage current in PD-SOI MOS devices as described in claim 1, characterized in that, The well region is either a P-type well region or an N-type well region.

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