Epitaxial wafer preparation method, epitaxial wafer, and gallium nitride radio frequency device

Abstract

The present application relates to a method for preparing an epitaxial wafer, the epitaxial wafer and a gallium nitride radio frequency device. The method for preparing the epitaxial wafer comprises the following steps: step 1, growing a C-doped layer of GaN doped with C on a substrate and passivating the C-doped layer; step 2, growing a high-resistance layer of GaN doped with Fe on the C-doped layer; step 3, growing a V-shaped pit layer of GaN doped with TMIn on the high-resistance layer and baking the V-shaped pit layer; and step 4, growing a GaN channel layer on the V-shaped pit layer. The epitaxial wafer is prepared by the method for preparing the epitaxial wafer. The gallium nitride radio frequency device comprises an epitaxial layer prepared by the epitaxial wafer. The present application can inhibit the upward diffusion of oxygen and silicon of the substrate and solve the diffusion tailing and residual memory effect of the Fe source, thereby improving the electrical performance.

Description

Technical Field

[0001] This invention relates to the field of power electronics / power electronics technology, specifically to an epitaxial wafer fabrication method and a corresponding epitaxial wafer, and also to gallium nitride radio frequency devices fabricated using the epitaxial wafer. Background Technology

[0002] In the fabrication of epitaxial wafers used in existing gallium nitride radio frequency (GaN RF) devices, a GaN buffer layer is grown on the substrate, and an Fe source is doped below the GaN channel layer to achieve a high-resistivity state.

[0003] However, Fe doping does not suppress the upward diffusion of oxygen and silicon from the substrate in the initial stage. Under thermally balanced MOCVD epitaxy conditions, Fe mainly occupies Ga sites (FeGa), acting as the dominant element; it does not directly occupy O (N site) or Si (Ga site) sites unless composite defects (Fe–O, Fe–Si) are formed or a trace amount of interstitial Fe appears during extreme non-equilibrium deposition. Fe atoms themselves do not form a continuous two-dimensional layer at the interface, and the migration energy of Fe in GaN is ≈6–8 eV (extremely high), so it does not form a diffusion barrier at the interface. Conversely, the diffusion paths of O and Si are through lattice vacancies or cracks, which point defects of Fe cannot fill.

[0004] Meanwhile, the doped Fe source exhibits severe upward diffusion tailing and residual memory effect, causing 2DEG layer contamination and leading to a decline in device performance. Furthermore, high-power RF devices experience higher current and junction temperatures during operation, which makes them more susceptible to Fe diffusion, resulting in reduced device reliability. Summary of the Invention

[0005] The purpose of this invention is to provide an epitaxial wafer fabrication method that can suppress the upward diffusion of oxygen and silicon in the substrate and solve the diffusion tailing and residual memory effect of the Fe source, thereby improving the electrical performance.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for preparing an epitaxial wafer includes the following steps: Step 1: Grow a C-doped GaN layer on the substrate and passivate the C-doped layer; Step 2: Grow a GaN-doped Fe high-resistivity layer on the C-doped layer; Step 3: Grow a GaN-doped TMIn V-shaped pit layer on the high-resistivity layer and bake the V-shaped pit layer; Step 4: Grow a GaN channel layer on the V-shaped pit layer.

[0007] Furthermore, in step 1, growing the C-doped layer includes growing a GaN-doped C nucleation layer on the substrate and baking the nucleation layer, and growing a GaN-doped C body layer on the nucleation layer.

[0008] Furthermore, in step 1, the temperature for growing the nucleation layer is set to 550℃~600℃, the temperature for baking the nucleation layer is set to 950℃~1100℃, and the temperature for growing the body layer is set to 1000℃~1100℃.

[0009] In one embodiment, in step 1, the H2 injection rate is increased and the temperature is set to 750°C~900°C to passivate the C-doped layer.

[0010] Preferably, the thickness of the C-doped layer grown in step 1 is less than 150 nm.

[0011] Furthermore, in step 2, the high-resistivity layer is grown in three stages; in the first stage, the temperature is set to 950℃~1025℃, in the second stage, the temperature is set to 1070℃~1150℃, and in the third stage, the temperature is set to 1050℃~1100℃.

[0012] Preferably, the thickness of the high-resistivity layer grown in step 2 is 1000~1500 nm.

[0013] In one specific implementation, during step 3, H2 is stopped being introduced when the V-shaped pit layer is grown, and the temperature is set to 750℃~850℃.

[0014] Preferably, the thickness of the V-shaped pit layer grown in step 3 is 50~150nm.

[0015] More preferably, in step 3, H2 is introduced when baking the V-shaped pit layer, and the temperature is set to 1050℃~1100℃, and the baking time is 3~5 minutes.

[0016] In the embodiments of this application, the thickness of the GaN channel layer grown in step 4 is 200~600nm.

[0017] Furthermore, the epitaxial wafer preparation method further includes the following steps: Step 5: Grow a barrier layer on the GaN channel layer; Step 6: Grow a P-type GaN layer or a Si3N4 layer on the barrier layer.

[0018] The present invention also provides an epitaxial wafer prepared by the above-described epitaxial wafer preparation method, which can suppress the upward diffusion of oxygen and silicon in the substrate and solve the diffusion tailing and residual memory effect of the Fe source.

[0019] The present invention also provides a gallium nitride radio frequency device, including an epitaxial layer prepared from the above-mentioned epitaxial wafer, which improves the electrical performance and has the advantages of stable threshold voltage and stable and effective operation at high temperatures.

[0020] Due to the application of the above technical solutions, the present invention has the following advantages compared with the prior art: the present invention can suppress the upward diffusion of oxygen and silicon in the substrate and solve the diffusion tailing and residual memory effect of the Fe source, thereby improving the electrical performance. Attached Figure Description

[0021] Appendix Figure 1 This is a schematic flowchart of the epitaxial wafer preparation method of the present invention.

[0022] Appendix Figure 2 This is a schematic diagram of the epitaxial wafer structure of the present invention.

[0023] In the above figures: 1. Substrate; 2. Nucleation layer; 3. Body layer; 4. Passivation layer; 5. High resistivity layer; 6. V-shaped pit layer; 7. Baking layer; 8. Channel layer; 9. Barrier layer; 10. P-type GaN layer / Si3N4 layer. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] Example 1: As shown in the attached document Figure 1 and attached Figure 2 As shown, a method for preparing an epitaxial wafer includes the following steps: Step 0: Prepare substrate 1, which is made of sapphire, Si, or SiC. Remove dust, foreign matter, and other particles from the surface of substrate 1 at approximately 1100°C in an H2 atmosphere.

[0027] Step 1: Grow a C-doped GaN layer on substrate 1 and passivate the C-doped layer.

[0028] Specifically, the C-doped layer consists of two parts: a GaN-doped C nucleation layer 2 and a GaN-doped C bulk layer 3. First, the GaN-doped C nucleation layer 2 is grown on the substrate 1 and baked. Then, the GaN-doped C bulk layer 3 is grown on the nucleation layer 2.

[0029] The temperature for growing nucleation layer 2 is set to 550℃~600℃. Nucleation layer 2 acts as a buffer layer to balance the lattice mismatch (polycrystalline) between the GaN lattice and the substrate. The temperature for baking nucleation layer 2 is set to 950℃~1100℃. The amorphous buffer layer grown at low temperature, i.e., nucleation layer 2, is baked at high temperature to form a high-quality crystal nucleus (recrystallization layer), which forms an island-like growth around the nucleation layer. The temperature for growing bulk layer 3 is set to 1000℃~1100℃, and the temperature for growing bulk layer 3 is higher than the temperature for baking nucleation layer 2. After growing the above two C-doped layers, the temperature is lowered to 750℃~900℃ and the H2 introduction rate is increased (the H2 introduction rate increases by approximately 25%) to passivate the C-doped layers, thus forming a passivation layer 4 on the surface of bulk layer 3. The thickness of the grown C-doped layer is less than 150nm.

[0030] The C-doped layer of GaN described above constitutes the initial layer (<150nm) for GaN growth, suppressing oxygen and silicon precipitation from the substrate through carbon doping. Although carbon does not directly occupy oxygen sites (i.e., O sites), since oxygen already occupies N sites, the two can compete for N sites or form CO recombination. Similarly, carbon does not directly occupy silicon sites (Si sites are also Ga sites), but CGa and SiGa can form adjacent C-Si acceptor-donor pairs, achieving mutual compensation. CN (C replacing N) produces a p-type effect (but the depth is too shallow, making it easily passivated by hydrogen).

[0031] Step 2: Grow a GaN-doped Fe high-resistivity layer 5 on the C-doped layer, with an Fe concentration of 1e18 to 1e19.

[0032] The growth of the Fe-doped GaN high-resistivity layer 5 is divided into three stages: the first stage, a medium-temperature growth stage, is carried out at a temperature of 950℃~1025℃; the second stage, a high-temperature growth stage, is carried out at a temperature of 1070℃~1150℃; and the third stage, a medium-high temperature growth stage, is carried out at a temperature of 1050℃~1100℃. Typically, the temperature for the third stage is lower than that for the second stage. The thickness of the grown high-resistivity layer 5 is 1000~1500 nm.

[0033] The effects of Fe doping are as follows: ① Deep-Level and Semi-Insulation: Deep-level compensation can transform intrinsic or lightly doped conductive layers into high-resistance / semi-insulating layers, making the material semi-insulating / high-resistance. Fe forms deeply dominant layers (~0.5–0.9 eV) in III-V, II-VI, and III-N semiconductors, effectively capturing intrinsic carriers. This is a key requirement for leakage current suppression in RF power amplifiers, microwave integrated circuits, and high-power microwave / RF devices. ② In oxygen-rich (O2) MOCVD, oxygen spontaneously occupies N sites and provides electrons, while the simultaneous incorporation of Fesub>Ga compensates for these electrons, leading to a significant decrease in carrier concentration (from 102). 18 cm -3 →<10 16 cm -3 ); ③ Lattice matching and structural stability; Fe's atomic radius (≈0.126nm) is similar to that of common III-V and III-N elements, resulting in minimal lattice distortion after doping and easy maintenance of epitaxial quality. High-quality single-crystal epitaxial films (GaN, AlGaN) achieve high resistivity by strongly compensating for intrinsic or exogenous shallow donors (Si, O, H, etc.) through deep-acceptor interaction.

[0034] Step 3: Grow a GaN-doped TMIn V-pit layer 6 (InGaN-Vpit layer) on the high-resistivity layer 5, and bake the V-pit layer 6.

[0035] After growing the GaN-doped Fe high-resistivity layer 5, the H2 supply is stopped, the temperature is lowered to 750℃~850℃, and a V-shaped pit layer (Vpits layer) 6 with a thickness of 50~150nm is grown. The V-shaped pit layer (Vpits layer) 6 has intentionally grown defects.

[0036] Vpits are the projections of dislocation ends onto the epitaxial surface. They are concave arrays formed by crystal defects (especially screw dislocations and nested dislocations) "interrupting" planar growth during lateral growth. At the same time, the low-temperature V-shaped pit layer (Vpits layer) can also improve growth warping.

[0037] When GaN is at low temperature, low Ga source flux, and high nitrogen source (NH3) concentration, the first GaN nuclei form a two-dimensional layer. Subsequently, due to the mismatch between strain and surface energy, the low temperature causes a significant decrease in the migration distance of Ga atoms. The atoms are "captured" at lattice defects or surface roughness, and rapidly transform into three-dimensional islands, causing the formation of spikes locally.

[0038] Low-temperature burrs naturally provide a geometric platform for dislocation capture / truncation, thereby reducing the overall dislocation density and indirectly reducing the long-range elastic stress caused by dislocations. Due to the high longitudinal stiffness and low lateral stiffness of the burrs, they can "tilt" or "bend" on their own during overall cooling and contraction, dispersing stress concentration.

[0039] After growing a 50-150 nm GaN-doped TMI V-pit layer (Vpits layer) 6, H2 is introduced and the temperature is raised to 1050℃-1100℃. The V-pit layer (Vpits layer) 6 is baked for 3-5 minutes, forming a baked layer 7 on its surface. Because the crystal quality of the low-temperature grown InGaN V-pit layer (Vpits layer) 6 is poor, baking in a heated H2 environment utilizes the in-situ etching effect of H2, which facilitates the rapid decomposition and escape characteristics of TMI at high temperatures. This allows the residual Fe source and the GaN spikes grown at low temperatures to be rapidly desorbed and carried away from the reaction chamber, resolving the memory residue tailing phenomenon formed between the Fe source layer and the channel layer, and creating a cross-section between the Fe-doped layer and the channel layer.

[0040] Step 4: Grow GaN channel layer 8 on V-pit layer 6.

[0041] After the Fe-doped source residual layer is properly treated, a high-quality GaN channel layer 8 is regrown. The thickness of the grown GaN channel layer 8 is 200~600nm, preferably 250~500nm.

[0042] Step 5: Grow an AlGaN barrier layer 9, i.e. a two-dimensional electron gas layer, on the GaN channel layer 8.

[0043] Step 6: Grow a P-type GaN layer or a Si3N4 layer 10 on the barrier layer 9.

[0044] Example 2: An epitaxial wafer prepared by the epitaxial wafer preparation method in Example 1. The diffusion of oxygen and silicon in its bottom layer is suppressed, the residual memory effect and diffusion tail of the Fe-doped layer are resolved, the threshold voltage is stable, and the device is stable and effective during high-temperature use.

[0045] Example 3: A gallium nitride radio frequency device for high-power, high-frequency applications, comprising an epitaxial layer prepared from the epitaxial wafer in Example 2, which improves electrical performance and has the advantages of stable threshold voltage and stable and effective operation at high temperatures.

[0046] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for preparing an epitaxial wafer, characterized in that: The method for preparing the epitaxial wafer includes the following steps: Step 1: Grow a C-doped GaN layer on the substrate and passivate the C-doped layer; Step 2: Grow a GaN-doped Fe high-resistivity layer on the C-doped layer; Step 3: Grow a GaN-doped TMIn V-shaped pit layer on the high-resistivity layer and bake the V-shaped pit layer; Step 4: Grow a GaN channel layer on the V-shaped pit layer.

2. The method for preparing an epitaxial wafer according to claim 1, characterized in that: In step 1, growing the C-doped layer includes growing a GaN-doped C nucleation layer on the substrate and baking the nucleation layer, and growing a GaN-doped C body layer on the nucleation layer.

3. The method for preparing an epitaxial wafer according to claim 1, characterized in that: In step 1, the temperature for growing the nucleation layer is set to 550℃~600℃, the temperature for baking the nucleation layer is set to 950℃~1100℃, and the temperature for growing the body layer is set to 1000℃~1100℃.

4. The method for preparing an epitaxial wafer according to claim 1, characterized in that: In step 1, the H2 injection rate is increased and the temperature is set to 750℃~900℃ to passivate the C-doped layer.

5. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The thickness of the C-doped layer grown in step 1 is less than 150 nm.

6. The method for preparing an epitaxial wafer according to claim 1, characterized in that: In step 2, the high-resistivity layer is grown in three stages: in the first stage, the temperature is set to 950℃~1025℃; in the second stage, the temperature is set to 1070℃~1150℃; and in the third stage, the temperature is set to 1050℃~1100℃.

7. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The thickness of the high-resistivity layer grown in step 2 is 1000~1500nm.

8. The method for preparing an epitaxial wafer according to claim 1, characterized in that: In step 3, H2 is stopped during the growth of the V-shaped pit layer, and the temperature is set to 750℃~850℃.

9. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The thickness of the V-shaped pit layer grown in step 3 is 50~150nm.

10. The method for preparing an epitaxial wafer according to claim 1, characterized in that: In step 3, H2 is introduced when baking the V-shaped pit layer, and the temperature is set to 1050℃~1100℃, and the baking time is 3~5 minutes.

11. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The thickness of the GaN channel layer grown in step 4 is 200~600nm.

12. The method for preparing an epitaxial wafer according to any one of claims 1 to 11, characterized in that: The epitaxial wafer preparation method further includes the following steps: Step 5: Grow a barrier layer on the GaN channel layer; Step 6: Grow a P-type GaN layer or a Si3N4 layer on the barrier layer.

13. An epitaxial wafer, characterized in that: The epitaxial wafer is prepared using the epitaxial wafer preparation method as described in claim 12.

14. A gallium nitride radio frequency device, characterized in that: The gallium nitride radio frequency device includes an epitaxial layer prepared from the epitaxial wafer of claim 13.

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