Method of forming a semiconductor device

Abstract

The application provides a semiconductor device forming method, which comprises the following steps: forming a bottom gate electrode; forming a first protective layer, which covers the bottom gate electrode and extends to cover the inner wall of a groove and the top surface and side surface of an ohmic contact layer; forming a patterned second photoresist layer on the first protective layer, which exposes part of the first protective layer above the bottom gate electrode; taking the patterned second photoresist layer as a mask to etch the exposed first protective layer to expose the top surface of the bottom gate electrode; forming a top gate electrode on the bottom gate electrode and electrically connecting the bottom gate electrode; and stripping the patterned second photoresist layer. Since the bottom gate electrode and the top gate electrode are formed in two steps, the morphology of the bottom gate electrode is relatively regular and is not easy to peel off, the process window is improved, and the bottom gate electrode and the groove are protected by forming the first protective layer, so that the groove is prevented from being damaged in subsequent processes and the Schottky contact between the bottom gate electrode and the channel layer is prevented from being damaged.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for forming a semiconductor device. Background Technology

[0002] Gallium arsenide (GaAs) is a mature compound semiconductor material with high breakdown voltage, widely used in ultra-high-speed and ultra-high-frequency devices. GaAs-based high electron mobility transistors (PHEMTs) feature high frequency, high power gain, and low noise, making them widely used in fiber optic, microwave, and satellite communications, as well as integrated circuits. However, PHEMT devices have increasingly higher operating frequencies, which means the linewidth of the gate pin lithography needs to be reduced accordingly. Therefore, narrow linewidths lead to a series of process problems, such as uncontrollable gate dipole (CD) or gate breakage. Traditional GaAssp HEMTs use a single-stage gate metal evaporation method, where the gate metal is evaporated directly after trenching. This often results in the gate being peeled off along with the photoresist after metal stripping. Summary of the Invention

[0003] The purpose of this invention is to provide a method for forming a semiconductor device to avoid gate peeling and improve the process window.

[0004] To achieve the above objectives, the present invention provides a method for forming a semiconductor device, comprising:

[0005] A substrate is provided on which a channel layer, an epitaxial structure layer and at least two ohmic contact layers are sequentially formed. A groove is provided in the epitaxial structure layer between two adjacent ohmic contact layers. The groove exposes a portion of the channel layer. A bottom gate is formed in the groove. The bottom gate is electrically connected to the channel layer, and the two sides of the bottom gate are spaced apart from the sidewalls of the groove.

[0006] A first protective layer is formed, which covers the bottom gate and extends to cover the inner wall of the groove and the top and side surfaces of the ohmic contact layer;

[0007] A patterned second photoresist layer is formed on the first protective layer, the patterned second photoresist layer exposing a portion of the first protective layer above the bottom gate;

[0008] Using the patterned second photoresist layer as a mask, the exposed first protective layer is etched to expose the top surface of the bottom gate.

[0009] A top gate is formed and the patterned second photoresist layer is stripped off. The top gate is located on the bottom gate and electrically connected to the bottom gate.

[0010] Optionally, in the method for forming the semiconductor device, the method for forming the bottom gate includes:

[0011] A channel layer, an epitaxial structure layer, and at least two ohmic contact layers are sequentially formed on the substrate;

[0012] A patterned first photoresist layer is formed, which covers the ohmic contact layer and exposes the epitaxial structure layer between two adjacent ohmic contact layers;

[0013] Using the patterned first photoresist layer as a mask, the exposed epitaxial structure layer is etched to form the groove;

[0014] A bottom gate material layer is formed by a vacuum evaporation process, the bottom gate material layer being located in the groove and on the patterned first photoresist layer;

[0015] The patterned first photoresist layer and the bottom gate material layer above it are stripped off, while the bottom gate material layer in the groove is retained to form the bottom gate.

[0016] Optionally, in the method for forming the semiconductor device, the patterned first photoresist layer has a first opening and a second opening that are connected, the second opening being located above the first opening, the width of the first opening being greater than the width of the second opening, and the sidewall inclination angle of the first opening being 90° to 110°.

[0017] Optionally, in the method for forming the semiconductor device, the thickness of the first protective layer is 0.05 μm to 0.1 μm.

[0018] Optionally, in the method for forming the semiconductor device, the method for forming the top gate includes:

[0019] A patterned third photoresist layer is formed, the patterned third photoresist layer being located on the patterned second photoresist layer, and the patterned third photoresist layer exposing the bottom gate.

[0020] A top gate material layer is formed, which covers a patterned third photoresist layer and the exposed bottom gate;

[0021] The patterned second photoresist layer and the patterned third photoresist layer are stripped, as well as the top gate material layer above the patterned third photoresist layer is stripped, while the top gate material layer above the bottom gate is retained to form the top gate.

[0022] Optionally, in the method for forming the semiconductor device, the patterned third photoresist layer has a connected third opening and a fourth opening, the fourth opening being located above the third opening, and the third opening and the fourth opening exposing the bottom gate, wherein the width of the third opening is greater than the width of the fourth opening, and the sidewall tilt angle of the third opening is 90°~110°.

[0023] Optionally, in the method for forming the semiconductor device, after stripping the patterned second photoresist layer and the patterned third photoresist layer, the method further includes:

[0024] A second protective layer is formed, which covers the top and side surfaces of the top gate and the first protective layer.

[0025] Optionally, in the method for forming the semiconductor device, both the first protective layer and the second protective layer are made of silicon nitride.

[0026] Optionally, in the method for forming the semiconductor device, the bottom gate is made of Pt, Ti, or Au.

[0027] Optionally, in the method for forming the semiconductor device, the top gate is formed by a vacuum evaporation process, and the material of the top gate is Au or Ti.

[0028] In the semiconductor device formation method provided by this invention, a bottom gate is first formed, followed by the formation of a first protective layer. The first protective layer covers the bottom gate and extends to cover the top and side surfaces of the ohmic contact layer. A patterned second photoresist layer is formed on the first protective layer, exposing a portion of the first protective layer above the bottom gate. Using the patterned second photoresist layer as a mask, the exposed first protective layer is etched to expose the top surface of the bottom gate. A top gate is formed, located on the bottom gate and electrically connected to it. Then, the patterned second photoresist layer is peeled off. Because the bottom gate and top gate are formed in two steps, the bottom gate has a more regular morphology and is therefore less prone to peeling off, improving the process window. Furthermore, by forming the first protective layer to protect the bottom gate and the trench, subsequent processes can avoid damaging the trench and the Schottky contact between the bottom gate and the channel layer. Gate peeling is also avoided during the peeling off of the patterned second photoresist layer. In addition, the top gate and bottom gate are electrically connected, and the adhesion between the top gate and bottom gate is higher than that between the bottom gate and the channel layer, improving gate strength. Attached Figure Description

[0029] Figure 1 This is a schematic flowchart of a method for forming a semiconductor device provided in an embodiment of the present invention.

[0030] Figures 2 to 11 This is a schematic diagram of the structure formed in the semiconductor device formation method provided in the embodiments of the present invention.

[0031] The reference numerals in the attached figures are explained as follows:

[0032] 100 - Substrate; 101 - Channel layer; 102 - Epitaxial structure layer; 102a - Groove; 110 - Ohmic contact layer; 120 - Patterned first photoresist layer; 121 - First opening; 122 - Second opening; 130 - Bottom gate material layer; 131 - Bottom gate; 140 - First protective layer; 150 - Patterned second photoresist layer; 151 - Fifth opening; 160 - Patterned third photoresist layer; 161 - Third opening; 162 - Fourth opening; 170 - Top gate material layer; 171 - Top gate; 180 - Second protective layer. Detailed Implementation

[0033] The method for forming a semiconductor device according to the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different proportions may be used in different drawings to illustrate different aspects.

[0034] Figure 1 This is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the method for forming a semiconductor device provided in this embodiment includes:

[0035] Step S1: Provide a substrate on which a channel layer, an epitaxial structure layer and at least two ohmic contact layers are sequentially formed. The epitaxial structure layer between two adjacent ohmic contact layers has a groove, the groove exposing a portion of the channel layer. A bottom gate is formed in the groove, the bottom gate is electrically connected to the channel layer, and the two sides of the bottom gate are spaced apart from the sidewalls of the groove.

[0036] Step S2: Form a first protective layer, which covers the bottom gate and extends to cover the inner wall of the groove and the top and side surfaces of the ohmic contact layer;

[0037] Step S3: A patterned second photoresist layer is formed on the first protective layer, the patterned second photoresist layer exposing a portion of the first protective layer above the bottom gate;

[0038] Step S4: Using the patterned second photoresist layer as a mask, etch the exposed first protective layer to expose the top surface of the bottom gate.

[0039] Step S5: Form a top gate and strip the patterned second photoresist layer, the top gate being located on the bottom gate and electrically connected to the bottom gate.

[0040] Figures 2 to 11 This is a schematic diagram of the structure formed in the semiconductor device formation method provided in the embodiments of the present invention. The following will refer to the accompanying drawings. Figures 2 to 11 The method for forming the semiconductor device provided in the embodiments will be described in more detail.

[0041] In step S1, as Figure 2 As shown, a substrate 100 is provided, on which a channel layer 101, an epitaxial structure layer 102 and at least two ohmic contact layers 110 are sequentially formed. A groove 102a is provided in the epitaxial structure layer 102 between two adjacent ohmic contact layers 110. The groove 102a exposes a portion of the channel layer 101. A bottom gate is formed in the groove 102a. The bottom gate is electrically connected to the channel layer 101, and the two sides of the bottom gate are spaced apart from the sidewalls of the groove 102a.

[0042] In this embodiment, the substrate 100 can be made of silicon (Si), gallium nitride (GaN), sapphire, or gallium arsenide (GaAs).

[0043] Specifically, the method for forming the bottom gate includes: as follows Figure 2 As shown, firstly, a channel layer 101, an epitaxial structure layer 102, and at least two ohmic contact layers 110 are sequentially formed on the substrate 100. The channel layer 101 is located on the substrate 100 and can be made of gallium arsenide. The epitaxial structure layer 102 can be made of gallium nitride. The ohmic contact layers 110 are located on the epitaxial structure layer 102, with adjacent ohmic contact layers 110 spaced apart. Two adjacent ohmic contact layers 110 can be used to form a source and a drain.

[0044] Then, as Figure 2As shown, a patterned first photoresist layer 120 is formed, which covers the ohmic contact layer 110 and exposes the epitaxial structure layer 102 between two adjacent ohmic contact layers 110. Specifically, the patterned first photoresist layer 120 has a communicating first opening 121 and a second opening 122, with the second opening 122 located above the first opening 121. The first opening 121 and the second opening 122 expose the epitaxial structure layer 102 between two adjacent ohmic contact layers 110. The width of the first opening 121 is greater than the width of the second opening 122, and the sidewall inclination angle α1 of the first opening 121 is 90°~110°, for example, 100°. The cross-sectional shape of the second opening 122 in the vertical direction of the substrate 100 is trapezoidal, and the sidewall of the first opening 121 is perpendicular to the surface of the substrate.

[0045] In this embodiment, the patterned first photoresist layer 120 is a negative photoresist layer, the thickness of the patterned first photoresist layer 120 can be 0.8μm~1.6μm, and the CD (minimum linewidth or feature size) of the patterned first photoresist layer 120 can be 0.1μm~0.2μm.

[0046] Next, as Figure 3 As shown, using the patterned first photoresist layer 120 as a mask, the exposed epitaxial structure layer 102 is etched to form the groove 102a. The groove 102a penetrates the epitaxial structure layer 102 to expose a portion of the channel layer 101. The groove 102a is located within the epitaxial structure layer 102 between ohmic contact layers, and the sidewalls of the groove 102a are spaced apart from the sidewalls of the ohmic contact layer 110.

[0047] Next, as Figure 4 As shown, a bottom gate material layer 130 is formed by a vacuum evaporation process. The bottom gate material layer 130 is located in the groove 102a and on the patterned first photoresist layer 120. The thickness of the bottom gate material layer 130 can be 0.4μm to 0.8μm.

[0048] After that, as Figure 5As shown, the patterned first photoresist layer 120 and the bottom gate material layer 130 above it can be peeled off using a peeling process. When peeling off the patterned first photoresist layer 120, the bottom gate material layer 130 on the surface of the patterned first photoresist layer 120 is also peeled off and removed, while the bottom gate material layer 130 within the groove 102a is retained to form the bottom gate (or gate pin) 131. The bottom gate 131 has a rectangular cross-sectional shape vertically to the substrate 100. The bottom gate is formed by a vacuum evaporation process and is relatively thin and regularly shaped, making it difficult to peel off and improving the process window. The material of the bottom gate is Pt, Ti, or Au.

[0049] Next, proceed to step S2, as follows: Figure 6 As shown, a first protective layer 140 is formed, which covers the bottom gate 131 and extends to cover the inner wall (side wall and bottom of the groove 102a) and the top and side surfaces of the ohmic contact layer 110. That is, the first protective layer 140 covers the top surface and side wall of the bottom gate 131 and extends to cover the bottom and side wall of the groove 102a, and the first protective layer 140 also extends to cover the top surface and side wall of the ohmic contact layer 110.

[0050] In this embodiment, the first protective layer 140 is made of silicon nitride (SiN) and is formed by plasma-enhanced chemical vapor deposition (PECVD). The thickness of the first protective layer 140 is 0.05 μm to 0.1 μm. By forming the first protective layer 140 to protect the bottom gate and the trench 102a, subsequent processes can be prevented from damaging the trench 102a and the Schottky contact between the bottom gate 131 and the channel layer 101. Furthermore, the problem of gate peeling can be avoided during the subsequent stripping of the patterned second photoresist layer 150.

[0051] Next, step S2 is performed to form a patterned second photoresist layer 150 on the first protective layer 140, the patterned second photoresist layer 150 exposing a portion of the first protective layer 140 above the bottom gate 131.

[0052] In this embodiment, the patterned second photoresist layer 150 is a positive photoresist layer, and the thickness of the patterned second photoresist layer 150 is 0.8μm to 1.6μm, and the CD is 0.1μm to 0.2μm.

[0053] Furthermore, after forming the patterned second photoresist layer 150, the morphology of the patterned second photoresist layer 150 can be optimized by a pattern shrinking process, so that the sidewalls of the patterned second photoresist layer 150 are arc-shaped sidewalls.

[0054] Next, proceed to step S4, as follows: Figure 7 As shown, using the patterned second photoresist layer 150 as a mask, the exposed first protective layer 140 is etched to expose the top surface of the bottom gate 131. The exposed first protective layer 140 can be etched using a dry etching process to form a via in the first protective layer 140, the via being located above the bottom gate 131.

[0055] In this embodiment, the patterned second photoresist layer 150 has a fifth opening 151, which exposes the top surface of the bottom gate 131.

[0056] Next, as Figure 10 As shown, step S5 is performed to form a top gate 171 and peel off the patterned second photoresist layer 150. The top gate 171 is located on the bottom gate 131 and electrically connected to the bottom gate 131. Due to the presence of the first protective layer 140, the bottom gate 131 can be protected, and the problem of gate (bottom gate) peeling off can be avoided during the peeling off of the patterned second photoresist layer 150.

[0057] Furthermore, since the top gate 171 and the bottom gate 131 are electrically connected, the adhesion between the top gate 171 and the bottom gate 131 is higher than the adhesion between the bottom gate 131 and the channel layer 101, which improves the gate strength and thus improves the stability of the gate.

[0058] Specifically, the method for forming the top gate 171 includes: firstly, as... Figure 8 As shown, a patterned third photoresist layer 160 is formed on the patterned second photoresist layer 150, and the patterned third photoresist layer 160 exposes the top surface of the bottom gate 131.

[0059] In this embodiment, the patterned third photoresist layer 160 can be a negative photoresist layer, and the thickness of the patterned third photoresist layer 160 can be 0.8μm~1.6μm, and the CD is 0.5μm~10μm.

[0060] like Figure 8As shown, the patterned third photoresist layer 160 has a connected third opening 161 and a fourth opening 162, the fourth opening 162 being located above the third opening 161, the third opening 161 exposing the top surface of the bottom gate, wherein the third opening 161 is aligned with and connected to a fifth opening 151 in the patterned second photoresist layer 150.

[0061] In this embodiment, the width of the third opening 161 is greater than the width of the fourth opening 162, and the sidewall inclination angle α2 of the third opening 161 is 90°~110°, for example, it can be 100°. The cross-sectional shape of the third opening 161 in the vertical direction of the substrate 100 can be trapezoidal.

[0062] Then, as Figure 9 As shown, a top gate material layer 170 is formed, which covers a patterned third photoresist layer 160 and an exposed bottom gate 131. The top gate material layer 170 can be formed by a vacuum evaporation process, and its thickness is 1.6 μm to 2.4 μm.

[0063] Next, as Figure 10 As shown, the patterned second photoresist layer 150 and the patterned third photoresist layer 160 are stripped, as is the top gate material layer 170 above the patterned third photoresist layer 160, while the top gate material layer 170 above the bottom gate is retained to form the top gate (or gate cap) 171. The patterned second photoresist layer 150 and the patterned third photoresist layer 160 can be stripped using a stripping process.

[0064] Furthermore, the presence of the first protective layer prevents the bottom gate from being pulled during the stripping of the patterned second photoresist layer 150 and the patterned third photoresist layer 160, thereby avoiding the problem of gate breakage.

[0065] In this embodiment, the top gate 171 is made of Au or Ti. Furthermore, the material of the top gate 171 can be different from that of the bottom gate.

[0066] After that, as Figure 11 As shown, a second protective layer 180 is formed, which covers the top and side surfaces of the top gate 171 and the first protective layer 140. The second protective layer 180 is made of silicon nitride and is formed using plasma-enhanced chemical vapor deposition (PECVD). The thickness of the second protective layer 180 is 0.05 μm to 0.1 μm.

[0067] Furthermore, the semiconductor device provided in this embodiment can be a gallium arsenide-based high electron mobility transistor (GaAs-based PHEMT).

[0068] In summary, in the semiconductor device formation method provided by this invention, a bottom gate is first formed, followed by a first protective layer. The first protective layer covers the bottom gate and extends to cover the inner wall of the trench and the top and side surfaces of the ohmic contact layer. A patterned second photoresist layer is formed on the first protective layer, exposing a portion of the first protective layer above the bottom gate. Using the patterned second photoresist layer as a mask, the exposed first protective layer is etched to expose the top surface of the bottom gate. A top gate is formed, located on the bottom gate and electrically connected to it. Then, the patterned second photoresist layer is peeled off. Because the bottom gate and top gate are formed in two steps, the bottom gate has a more regular morphology and is less prone to peeling off, thus improving the process window. Furthermore, by forming the first protective layer to protect the bottom gate and the trench, subsequent processes can avoid damaging the trench and the Schottky contact between the bottom gate and the channel layer. Gate peeling off can also be avoided during the peeling off of the patterned second photoresist layer. In addition, the top gate and the bottom gate are electrically connected, and the adhesion between the top gate and the bottom gate is higher than the adhesion between the bottom gate and the channel layer, which improves the gate strength.

[0069] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0070] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided on which a channel layer, an epitaxial structure layer and at least two ohmic contact layers are sequentially formed. A groove is provided in the epitaxial structure layer between two adjacent ohmic contact layers. The groove exposes a portion of the channel layer. A bottom gate is formed in the groove. The bottom gate is electrically connected to the channel layer, and the two sides of the bottom gate are spaced apart from the sidewalls of the groove. A first protective layer is formed, which covers the bottom gate and extends to cover the inner wall of the groove and the top and side surfaces of the ohmic contact layer; A patterned second photoresist layer is formed on the first protective layer, the patterned second photoresist layer exposing a portion of the first protective layer above the bottom gate; Using the patterned second photoresist layer as a mask, the exposed first protective layer is etched to expose the top surface of the bottom gate. A top gate is formed and the patterned second photoresist layer is stripped off. The top gate is located on the bottom gate and electrically connected to the bottom gate.

2. The method for forming a semiconductor device as described in claim 1, characterized in that, The method for forming the bottom gate includes: A channel layer, an epitaxial structure layer, and at least two ohmic contact layers are sequentially formed on the substrate; A patterned first photoresist layer is formed, which covers the ohmic contact layer and exposes the epitaxial structure layer between two adjacent ohmic contact layers; Using the patterned first photoresist layer as a mask, the exposed epitaxial structure layer is etched to form the groove; A bottom gate material layer is formed by a vacuum evaporation process, the bottom gate material layer being located in the groove and on the patterned first photoresist layer; The patterned first photoresist layer and the bottom gate material layer above it are stripped off, while the bottom gate material layer in the groove is retained to form the bottom gate.

3. The method for forming a semiconductor device as described in claim 2, characterized in that, The patterned first photoresist layer has a first opening and a second opening that are connected. The second opening is located above the first opening. The width of the first opening is greater than the width of the second opening, and the sidewall inclination angle of the first opening is 90°~110°.

4. The method for forming a semiconductor device as described in claim 1, characterized in that, The thickness of the first protective layer is 0.05 μm to 0.1 μm.

5. The method for forming a semiconductor device as described in claim 1, characterized in that, The method of forming the top gate includes: A patterned third photoresist layer is formed, the patterned third photoresist layer being located on the patterned second photoresist layer, and the patterned third photoresist layer exposing the bottom gate. A top gate material layer is formed, which covers a patterned third photoresist layer and the exposed bottom gate; The patterned second photoresist layer and the patterned third photoresist layer are stripped, as well as the top gate material layer above the patterned third photoresist layer is stripped, while the top gate material layer above the bottom gate is retained to form the top gate.

6. The method for forming a semiconductor device as described in claim 5, characterized in that, The patterned third photoresist layer has a connected third opening and a fourth opening, the fourth opening being located above the third opening, and the third opening and the fourth opening exposing the bottom gate, wherein the width of the third opening is greater than the width of the fourth opening, and the sidewall tilt angle of the third opening is 90°~110°.

7. The method for forming a semiconductor device as described in claim 1, characterized in that, After stripping the patterned second photoresist layer and the patterned third photoresist layer, the process further includes: A second protective layer is formed, which covers the top and side surfaces of the top gate and the first protective layer.

8. The method for forming a semiconductor device as described in claim 7, characterized in that, Both the first protective layer and the second protective layer are made of silicon nitride.

9. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The bottom gate is made of Pt, Ti, or Au.

10. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The top gate is formed by a vacuum evaporation process, and the material of the top gate is Au or Ti.

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