A method for reducing reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures
Patent Information
- Application Number
- CN202611138034.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-29
- Publication Date
- 2026-10-16
AI Technical Summary
虽然引入高密度复合中心，缩短了少数载流子的有效扩散长度，降低了少子寿命τ，对PN结反偏漏电存在一定负面效应，但由于泄漏电流与本征载流子浓度的平方ni2成正比，局域有效本征载流子浓度下降远强于少子寿命降低带来的负面影响，有望实现对PN结反偏漏电的大幅度抑制
[0018] This invention provides a method for reducing the reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures. By introducing a recombination center layer in the neutral region at the bottom of the well region, the local effective intrinsic carrier concentration is reduced, which can significantly reduce the leakage current of SOI MOS devices above 150°C. The recombination center layer is at a certain distance from the channel (inversion layer), which does not change the threshold voltage, on-state current, or subthreshold swing of the SOI MOS device. The recombination center layer is in the neutral region, not in the depletion region, and does not generate a barrier current. The recombination center layer is electrically neutral, which does not change the width of the depletion region, the junction capacitance remains unchanged, and the switching speed is not affected. Only one ion implantation step is added, which is fully compatible with standard SOI CMOS processes. It can significantly extend the high-temperature operating range of SOI MOS devices and meet the needs of high-temperature applications such as automotive electronics, oil drilling, and aerospace.
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Figure CN122934849A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of high-temperature semiconductor technology, and in particular to a method for reducing the reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures. Background Technology
[0002] Commercial silicon-based integrated circuit MOS devices can only operate within a narrow temperature range of -40 to 125°C. However, the operating temperature requirements of silicon-based MOS devices in fields such as automotive electronics, oil and gas exploration, and aerospace often exceed this range. High-temperature semiconductor technology has become an important development direction for microelectronics technology, aiming to improve the high-temperature performance of microelectronic devices and increase their operating temperature to meet the needs of high-temperature applications.
[0003] The main characteristics of silicon-based MOS devices at high temperatures are a sharp increase in leakage current and a decrease in threshold voltage. As temperature rises, the intrinsic carrier concentration increases exponentially, leading to a significant increase in the reverse-biased current of the PN junction. This, in turn, increases static power consumption, reduces circuit reliability, and in severe cases, can even cause device failure. When the temperature exceeds 150°C, the main component of the leakage current is the reverse-biased diffusion current of the PN junction, which is related to the PN junction area. A The square root of the minority carrier diffusion length D 0.5 The square of the intrinsic carrier concentration n i 2 Proportional to the square root of the lifespan of people with fewer births τ 0.5 well region doping concentration N sub Inversely proportional. Intuitively, increasing the substrate doping concentration... N sub Or reduce the PN junction area A This can reduce the reverse bias diffusion current of the PN junction, thereby improving the high-temperature characteristics of silicon-based MOS devices.
[0004] Compared to bulk silicon, SOI material's unique buried oxide layer achieves electrical isolation between the top silicon layer and the substrate. SOI MOS devices eliminate the large-area well-substrate PN junction found in bulk silicon CMOS, significantly reducing the PN junction area, greatly decreasing the reverse bias leakage current of the PN junction, and significantly improving high-temperature stability. Therefore, SOI has become the preferred substrate material for high-temperature semiconductor technology.
[0005] However, even in SOI MOS devices, a PN junction still exists between the source / drain region and the well region, resulting in a non-negligible PN junction area. AAs the temperature continues to rise, the intrinsic carrier concentration increases, and the reverse-biased leakage current problem of the PN junction still exists. Therefore, how to further reduce the reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures has become an important research direction in high-temperature semiconductor technology.
[0006] Research revealed that when a certain concentration of recombination centers exists in the neutral region at the depletion region boundary of the drain PN junction, its effective minority carrier concentration is pinned to a low level. From a band structure perspective, high-density deep-level defects increase the local effective bandgap and reduce the local effective intrinsic carrier concentration. Although the introduction of high-density recombination centers shortens the effective diffusion length of minority carriers and reduces the minority carrier lifetime τ, thus having a certain negative effect on the reverse-biased leakage current of the PN junction, the leakage current is still significantly affected by the square of the intrinsic carrier concentration. n i 2 The decrease in local effective intrinsic carrier concentration is directly proportional to the reduction in minority carrier lifetime, which is far more detrimental than the negative impact of the decrease in local effective intrinsic carrier concentration. This is expected to significantly suppress reverse-biased leakage current in PN junctions. Furthermore, as long as the recombination center is located below the top silicon layer and away from the channel (inversion layer), it will not affect the on-state performance of SOI MOS devices. As long as the recombination center is located in the neutral region (not in the high-field depletion region), no barrier current will be generated, thus preventing leakage current. Summary of the Invention
[0007] The purpose of this invention is to provide a method for reducing the reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures, so as to solve the problems in the background art.
[0008] To address the aforementioned technical problems, this invention provides a method for reducing the reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures, comprising: An SOI substrate is provided, wherein the SOI substrate comprises, from bottom to top, a back substrate, a buried oxide layer, and a top silicon layer; A well region is formed within the top silicon layer; A composite central layer is formed between the bottom of the trap region and the buried oxygen layer; After forming the composite central layer, the method further includes: performing rapid thermal annealing to activate the implanted impurities and simultaneously activate the composite activity of the composite central layer; wherein, The composite central layer has a high density of electrically active defects or deep-level impurities, which is used to reduce the local effective intrinsic carrier concentration in the bottom region of the well region, so as to suppress the reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures.
[0009] In one embodiment, the composite center layer is located on the neutral region side of the edge of the space charge region of the drain PN junction and is at a distance from the channel interface of the ultimately formed SOI MOS device.
[0010] In one embodiment, the composite central layer is formed by ion implantation, wherein the implanted ions are one or more combinations of helium, hydrogen, carbon, silicon, germanium, platinum, or gold.
[0011] In one embodiment, the ion implantation energy is selected such that the implantation peak is located in the lower half of the top silicon layer.
[0012] In one embodiment, the composite center layer is an electrically neutral layer, and its net doping concentration is not higher than that of the well region, thus not changing the net doping concentration distribution inside the well region.
[0013] In one embodiment, the step of forming the composite central layer is located after the formation of the well region and before the formation of the gate oxide layer.
[0014] In one embodiment, the composite center layer step is performed after the gate is formed and before the source / drain regions are formed, and the gate is used as a mask so that the composite center layer is formed only at the bottom of the well region below the source region and below the drain region.
[0015] In one embodiment, the SOI MOS device is a partially depleted type; when it is an NMOS device, the well region is a P-type well region; when it is a PMOS device, the well region is an N-type well region.
[0016] In one embodiment, the composite center layer is formed by multiple ion implantations of different energies, forming a composite center distribution band with width in the lower half of the top silicon layer.
[0017] In one embodiment, the annealing process of the composite central layer is laser annealing or microwave annealing.
[0018] This invention provides a method for reducing the reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures. By introducing a recombination center layer in the neutral region at the bottom of the well region, the local effective intrinsic carrier concentration is reduced, which can significantly reduce the leakage current of SOI MOS devices above 150°C. The recombination center layer is at a certain distance from the channel (inversion layer), which does not change the threshold voltage, on-state current, or subthreshold swing of the SOI MOS device. The recombination center layer is in the neutral region, not in the depletion region, and does not generate a barrier current. The recombination center layer is electrically neutral, which does not change the width of the depletion region, the junction capacitance remains unchanged, and the switching speed is not affected. Only one ion implantation step is added, which is fully compatible with standard SOI CMOS processes. It can significantly extend the high-temperature operating range of SOI MOS devices and meet the needs of high-temperature applications such as automotive electronics, oil drilling, and aerospace. Attached Figure Description
[0019] Figures 1-6A schematic diagram of the steps in a device fabrication method for forming a recombination center layer at the bottom of the well region of an SOI NMOS device.
[0020] Figure 7 This is a schematic diagram of the reverse-biased leakage current of the off-state PN junction after a recombination center layer is formed at the bottom of the well region of an SOI NMOS device.
[0021] Figure 8 This is a schematic cross-sectional view of an SOI MOS device after the gate is formed and a recombination center layer is added.
[0022] Figure 9 yes Figure 8 The diagram shows the reverse-biased leakage current of the PN junction in the off-state of the SOI MOS device.
[0023] Figure 10 This is a schematic cross-sectional view of a traditional SOI MOS device.
[0024] Figure 11 yes Figure 10 The diagram shows the reverse-biased leakage current of the PN junction in the off-state of the SOI MOS device.
[0025] Figure 12 This is a schematic cross-sectional view of a traditional SOI MOS device.
[0026] Figure 13 yes Figure 12 The diagram shows the reverse-biased leakage current of the PN junction in the off-state of the SOI MOS device.
[0027] Figure 14 yes Figure 12 The diagram shows the reverse-biased leakage current of the off-state PN junction after adding a recombination center layer to the SOI MOS device.
[0028] Figure 15 This is a schematic diagram of the fabrication process for an SOI NMOS device in which a composite central layer is formed at the bottom of the well region.
[0029] Figure 16 This is a schematic diagram of the fabrication process for an SOI NMOS device in which a composite central layer is formed at the bottom of the well region. Detailed Implementation
[0030] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for reducing reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures, as proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Example 1
[0031] This embodiment 1 provides a method for reducing the reverse bias leakage current of the PN junction in SOI MOS devices at high temperatures. Specifically, it is a device fabrication method that uses helium (He) ion implantation to form a recombination center layer at the bottom of the P-type well region of the SOI NMOS device. The process is as follows: Figure 15 As shown, it includes the following steps: Step 1: Provide an SOI substrate; like Figure 1 As shown, an SOI substrate is provided, which includes, from bottom to top: a back substrate 1, a buried oxide layer 2, and a top silicon layer 4. The top silicon layer 4 has a P-type conductivity.
[0032] Step 2: Form shallow trenches for isolation; like Figure 2 As shown, shallow trenches 3 are formed in the top silicon layer 4 using a standard shallow trench isolation process, filled with silicon dioxide, and then chemically mechanically polished.
[0033] Step 3: Form a P-type well region; like Figure 3 As shown, P-type well injection is performed in the active region.
[0034] Step 4: Form the composite central layer; like Figure 4 As shown, a composite center layer 11 is formed in the neutral region between the bottom of the P-type well region and the buried oxide layer 2. Specifically, helium ion implantation is performed, with the implantation energy adjusted according to the thickness of the top silicon layer 4, so that the implantation peak is located within the neutral region of the lower half of the top silicon layer 4. This composite center layer 11 is located on one side of the neutral region at the edge of the drain PN junction space charge region and is at a certain distance from the final SOI MOS device channel interface.
[0035] Step 5: Form the gate oxide layer and the gate electrode; like Figure 5 As shown, a gate oxide layer 5 is grown on the surface of the top silicon layer 4. Polysilicon or a metal gate material is deposited on the gate oxide layer 5 to form the gate 6. The gate pattern is formed by photolithography and etching.
[0036] Step 6: Form the source / drain region; like Figure 6 As shown, drain region 7 and source region 8 are implanted using the gate as a mask. Depletion region 9 is formed between drain region 7 and P-type well region, and depletion region 10 is formed between source region 8 and P-type well region.
[0037] Step 7: Rapid thermal annealing; Rapid thermal annealing is performed, which is used to activate the injected impurities and simultaneously activate the composite activity of the composite central layer 11.
[0038] Step 8: Form metal contacts and interconnects; The device fabrication is completed by using standard back-end processes to form metal silicides, contact vias, and metal interconnect layers. (Not illustrated here.)
[0039] The SOI MOS device fabricated through the above steps forms a high-density helium-injected recombination center layer in the neutral region between the bottom of the P-type well region and the buried oxide layer. This recombination center layer significantly reduces the local effective intrinsic carrier concentration in this region, effectively suppressing reverse-biased leakage current of the PN junction in the SOI MOS device at high temperatures, such as... Figure 7 As shown in the figure. Circles in the figure represent minority carriers in the well region; arrows indicate the diffusion direction of minority carriers in the well region. Example 2
[0040] The difference between Example 2 and Example 1 is that the composite central layer is formed by carbon (C) ion implantation or silicon (Si) self-implantation.
[0041] Lattice damage defects formed by carbon ion implantation or silicon self-implantation can serve as effective recombination centers. Compared with helium (He) ion implantation, recombination centers formed by carbon (C) ion implantation have better thermal stability and are less likely to be eliminated by annealing in subsequent high-temperature processes. Example 3
[0042] The difference between Example 3 and Example 1 is that the composite central layer is formed by implantation of heavy metal ions such as platinum (Pt) or gold (Au).
[0043] Due to their large mass, heavy metal ions require higher implantation energy to achieve the same implantation depth. Heavy metal ions form deep impurity levels in silicon, located near the center of the band gap, which have high capture cross-sections for both electrons and holes, resulting in higher recombination efficiency. Example 4
[0044] The difference between Example 4 and Example 1 is that the SOI MOS device is a PMOS device.
[0045] For PMOS devices, the well region is an N-type well region, and the recombination center layer is located in the neutral region between the bottom of the N-type well region and the buried oxide layer. The recombination center layer formed at the bottom of the N-type well region can reduce the lifetime of minority carriers (holes) and suppress the reverse bias diffusion current of the PN junction in SOIPMOS devices. Example 5
[0046] The difference between Example 5 and Example 1 is that the composite central layer is formed by multiple ion implantations with different energies.
[0047] Multiple implantations can form a composite center distribution band of a certain width in the neutral region of the lower half of the top silicon layer, rather than a single peak layer, making the composite effect more uniform and stable. Example 6
[0048] The difference between this embodiment 6 and embodiment 1 is that the formation step of the composite central layer 12 is located after the gate formation and before the source / drain injection.
[0049] like Figure 8 As shown, after the gate is formed, helium (He) ion implantation is performed using the gate as a mask to form the composite central layer 11. At this time, the source and drain regions have not yet been formed, and the implanted region is the well region below the source and drain regions. The channel region directly below the gate is shielded by the gate and is not affected by the implantation. The advantage of this method is that the channel region is completely unaffected by implantation, achieving zero impact on the on-state characteristics.
[0050] Its complete process is as follows Figure 16 As shown.
[0051] like Figure 9 As shown, Figure 8 A schematic diagram of the reverse-biased leakage current of the PN junction in the off-state of an SOI MOS device. Example 7
[0052] The difference between Example 7 and Example 1 is that the annealing process of the composite central layer uses laser annealing or microwave annealing.
[0053] Traditional rapid thermal annealing can cause diffusion of the composite centers, leading to deviations of the composite center layer from the designated area. Laser annealing or microwave annealing allows for better control over the location and concentration distribution of the composite center layer.
[0054] Figure 10 A schematic cross-sectional view of a traditional SOI MOS device is shown, in which the source and drain regions do not contact the buried oxide layer.
[0055] Figure 11 for Figure 10 The diagram shows the reverse-biased leakage current of the PN junction in the off-state of the SOI MOS device.
[0056] Will Figure 11 and Figure 7 or Figure 9 By comparison, it can be seen that Figure 7 and Figure 9 The composite central layer effectively suppresses reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures.
[0057] Figure 12 A schematic cross-sectional view of another conventional SOI MOS device is shown, in which the depth of the source and drain regions contacts the buried oxide layer.
[0058] Figure 13 for Figure 12 The diagram shows the reverse-biased leakage current of the PN junction in the off-state of the SOI MOS device.
[0059] Figure 14 Then it is Figure 12 The diagram shows the reverse-biased leakage current of the off-state PN junction after adding a recombination center layer to the SOI MOS device.
[0060] Will Figure 14 and Figure 13 By comparison, it can be seen that Figure 14 The composite central layer effectively suppresses reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures.
[0061] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for reducing the reverse-biased leakage current of the PN junction in an SOI MOS device at high temperatures, characterized in that, include: An SOI substrate is provided, wherein the SOI substrate comprises, from bottom to top, a back substrate, a buried oxide layer, and a top silicon layer; A well region is formed within the top silicon layer; A composite central layer is formed between the bottom of the trap region and the buried oxygen layer; After forming the composite central layer, the method further includes: performing rapid thermal annealing to activate the implanted impurities and simultaneously activate the composite activity of the composite central layer; wherein, The composite central layer has a high density of electrically active defects or deep-level impurities, which is used to reduce the local effective intrinsic carrier concentration in the bottom region of the well region, so as to suppress the reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures.
2. The method for reducing reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures as described in claim 1, characterized in that, The composite center layer is located on the neutral region side of the edge of the space charge region of the drain PN junction, and is at a distance from the channel interface of the final SOI MOS device.
3. The method for reducing reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures as described in claim 1, characterized in that, The composite central layer is formed by ion implantation, and the implanted ions are one or more combinations of helium, hydrogen, carbon, silicon, germanium, platinum or gold.
4. The method for reducing reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures as described in claim 3, characterized in that, The ion implantation energy is selected such that the implantation peak is located in the lower half of the top silicon layer.
5. The method for reducing reverse-biased leakage current of the PN junction in SOI MOS devices at high temperatures as described in claim 1, characterized in that, The composite center layer is an electrically neutral layer, and its net doping concentration is not higher than that of the well region, thus not changing the net doping concentration distribution inside the well region.
6. The method for reducing reverse-biased leakage current of the PN junction in an SOI MOS device at high temperature as described in claim 1, characterized in that, The step of forming the composite central layer occurs after the formation of the well region and before the formation of the gate oxide layer.
7. The method for reducing reverse-biased leakage current of the PN junction in an SOI MOS device at high temperature as described in claim 1, characterized in that, The process of forming the composite center layer is performed after the formation of the gate and before the formation of the source and drain regions, and the gate is used as a mask so that the composite center layer is formed only at the bottom of the well region below the source region and below the drain region.
8. The method for reducing reverse-biased leakage current of the PN junction in an SOI MOS device at high temperature as described in claim 1, characterized in that, The SOI MOS device is a partially depleted type. When it is an NMOS device, the well region is a P-type well region; when it is a PMOS device, the well region is an N-type well region.
9. The method for reducing reverse-biased leakage current of the PN junction in an SOI MOS device at high temperature as described in claim 1, characterized in that, The composite center layer is formed by multiple ion implantations of different energies, forming a composite center distribution band with width in the lower half of the top silicon layer.
10. The method for reducing reverse-biased leakage current of the PN junction in an SOI MOS device at high temperature as described in claim 1, characterized in that, The annealing process for the composite central layer is laser annealing or microwave annealing.