A trench gate silicon carbide MOSFET based on strain-regulated oxidation and a preparation method thereof

Abstract

The application discloses a trench gate silicon carbide MOSFET based on strain regulation oxidation and a preparation method thereof. By adopting Ar⁺ / Xe⁺ inert ion implantation process at the bottom of the trench, a compressive strain lattice layer with a depth of 10-50 nm and a strain degree of 0.5%-2% is constructed, the Si-C chemical bond is stretched by lattice distortion, and the bond energy is reduced, so that the oxidation rate at the bottom of the trench can be locally accelerated without doping modification, and the differential thickness structure of the gate oxide at the bottom of the trench of 80-100 nm and the gate oxide at the sidewall of 50-60 nm is realized. The application completely avoids the interface defect and threshold drift problems caused by the traditional doping oxygen increasing process, effectively alleviates the electric field concentration effect at the bottom of the trench, greatly improves the voltage resistance capability and high-temperature reliability of the device, reduces the gate leakage capacitance and the switching loss, takes into account the conduction characteristic and high-frequency performance of the device, is highly compatible with the existing SiC device production line, is excellent in mass production, and is suitable for the field of high-voltage high-frequency power electronic equipment.

Description

Technical Field

[0001] This invention relates to a trench-gate silicon carbide MOSFET and its fabrication method, specifically to a trench-gate silicon carbide MOSFET based on strain-controlled oxidation and its fabrication method, belonging to the field of semiconductor technology. Background Technology

[0002] Trench-gate silicon carbide (SiC) MOSFETs have become core components of high-voltage, high-frequency power devices due to their lower on-resistance, faster switching speed, and higher temperature and voltage withstand performance. The gate oxide layer is the core dielectric structure of SiC MOSFETs, and its thickness uniformity and interface quality directly determine the device's voltage withstand capability, switching characteristics, threshold stability, and long-term reliability.

[0003] To address the issues of concentrated electric field at the bottom of trench gate devices and easy gate oxide breakdown, existing technologies mainly adjust the oxidation rate through doping modification or trench amorphization. For example, patent CN122269742A discloses a trench gate SiC MOSFET that forms a dense N-type doped layer below the bottom of the gate trench, using heavy doping to accelerate the SiC oxidation rate and make the bottom gate oxide thickness significantly thicker than the sidewalls. In addition, some patents use ion implantation to amorphize the silicon carbide at the bottom of the trench to improve the oxidation rate, but their goal is to reduce the thickness difference between the bottom and sidewall gate oxide layers.

[0004] In summary, existing technologies suffer from the drawback of relying on N-type doping to alter chemical activity, which may introduce interface defects. There are also some amorphization schemes, but their goal is to reduce the thickness difference rather than increase it. Therefore, the industry lacks a gate oxide thickening method that does not involve doping elements and does not change the electrical properties of SiC. Summary of the Invention

[0005] In view of the technical defects of the existing technology, the purpose of this invention is to provide a trench gate silicon carbide MOSFET based on strain-controlled oxidation and its fabrication method. The oxidation rate is locally accelerated by implanting inert ions into the bottom of the trench to form a lattice strain layer, so that the bottom gate oxide is significantly thicker than the sidewall, and no doping elements are introduced.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] This invention first provides a method for fabricating a trench-gate silicon carbide MOSFET based on strain-controlled oxidation, comprising the following steps:

[0008] (1) An N- drift layer is epitaxially grown on an N+ type 4H-SiC substrate;

[0009] (2) Using ICP etching process, trenches are formed on the surface of N-drift layer;

[0010] (3) Photoresist is used to mask the sidewalls and top of the trench, leaving only the bottom area of ​​the trench exposed;

[0011] (4) Inert ion implantation is performed on the exposed bottom of the trench to form a lattice strain layer, and pressure strain is generated below the bottom surface of the trench to form a lattice strain layer.

[0012] (5) Remove the photoresist from the surface of the trench and perform RCA cleaning to remove surface impurities and residues;

[0013] (6) High-temperature thermal oxidation is carried out, the Si-C bonds in the strain region are stretched and the bond energy is reduced, and oxygen molecules are more likely to react with the stretched Si-C bonds, which locally accelerates the oxidation rate and makes the gate thickness at the bottom of the trench significantly greater than that of the sidewall.

[0014] (7) Post-processing: The polysilicon gate filling, source metal implantation, drain metal implantation and metallization are completed sequentially (according to standard traditional process) to prepare the finished product, namely the trench gate silicon carbide MOSFET based on strain-controlled oxidation.

[0015] In the above technical solution, in step (1), the N-drift layer has a thickness of 10 μm and a doping concentration of 1 × 10¹. 6 cm⁻³.

[0016] In the above technical solution, in step (2), the trench depth is 1.5 to 2 μm and the width is 0.8 to 1.2 μm.

[0017] In the above technical solution, in step (4), the inert ion is Ar⁺ or Xe⁺, and the injection dose is 1×10¹. 4 ~5×10¹ 4 cm⁻², implantation energy 100~300keV; after implantation of inert ions, compressive strain is generated in the range of 10~50nm below the bottom surface of the trench to form a lattice strain layer with a strain degree of 0.5%~2%.

[0018] In the above technical solution, in step (6), the high-temperature oxidation has an oxidation temperature of 1100-1200℃ and an oxidation time of 30-90min. Oxygen is introduced during oxidation, and the oxygen flow rate is 1-10L / min (preferably 5L / min).

[0019] The second objective of this invention is to provide a trench gate silicon carbide MOSFET based on strain-controlled oxidation, which is prepared by the above-described method and includes an N+ type 4H-SiC substrate, an N- drift layer epitaxially grown on the substrate, a trench etched on the surface of the N- drift layer, a gate oxide layer grown on the inner wall of the trench, a lattice strain layer formed below the bottom surface of the trench, a polysilicon gate region filled in the trench, and a source metal region and a drain metal region disposed outside the trench in the N- drift layer.

[0020] In the above technical solution, the lattice strain layer is formed after inert ions are injected into the bottom of the trench to generate compressive stress, and the lattice strain layer is located in the depth range of 10 to 50 nm below the bottom surface of the trench.

[0021] In the above technical solution, the N-drift layer has a thickness of 10 μm; the trench has a depth of 1.5–2 μm and a width of 0.8–1.2 μm.

[0022] In the above technical solution, the gate oxide layer includes a bottom gate located at the bottom of the trench and a sidewall gate located on the sidewall of the trench. The thickness of the bottom gate is 80-100 nm, and the thickness of the sidewall gate oxide layer is 50-60 nm.

[0023] The principle of this invention is as follows: a lattice strain layer is formed at the bottom of the trench by high-energy inert ion implantation. Compressive strain is generated in the depth range of 10 to 50 nm below the bottom surface of the trench, and a lattice strain layer is formed. The Si-C bonds in the strain region are stretched, the bond energy is reduced, and oxygen molecules are more likely to react with the stretched Si-C bonds, which locally accelerates the oxidation rate and makes the bottom gate oxygen thickness significantly greater than that of the sidewall gate.

[0024] The beneficial effects of the present invention are: (1) Inert ion implantation does not change the electrical properties of SiC and has no doping defects; (2) Local oxidation rate is accelerated and the oxidation rate in the strain region is increased by 30% to 50%; (3) The bottom gate oxide thickness (80 to 100 nm) is significantly greater than that of the sidewall gate (50 to 60 nm). The thicker bottom gate oxide enhances the withstand voltage capability and reduces Qgd to improve the switching speed. Attached Figure Description

[0025] Figure 1 This is a process flow diagram of the preparation method of the present invention;

[0026] Figure 2 This is a schematic diagram of the overall structure of the trench-gate silicon carbide MOSFET based on strain-controlled oxidation according to the present invention; (the circular dashed lines correspond to...) Figure 3 (Parts that need to be enlarged)

[0027] Figure 3 for Figure 2 Enlarged view of the bottom grid and lattice strain layer inside the middle circle;

[0028] Wherein: 1 is an N+ type 4H-SiC substrate, 2 is an N- drift layer, 3 is a bottom gate, 4 is a sidewall gate, 5 is a lattice strain layer, 6 is a polysilicon gate region, 7 is a source metal region, and 8 is a drain metal region. Detailed Implementation

[0029] The following describes in detail the specific embodiments of the technical solution of the present invention, but the present invention is not limited to the following description:

[0030] This invention first provides a method for fabricating a trench-gate silicon carbide MOSFET based on strain-controlled oxidation, the flowchart of which is shown below. Figure 1 As shown, it includes the following steps:

[0031] (1) An N- drift layer is epitaxially grown on an N+ type 4H-SiC substrate;

[0032] (2) Using ICP etching process, trenches are formed on the surface of N-drift layer;

[0033] (3) Photoresist is used to mask the sidewalls and top of the trench, leaving only the bottom area of ​​the trench exposed;

[0034] (4) Inert ion implantation is performed on the exposed bottom of the trench to form a lattice strain layer, and pressure strain is generated below the bottom surface of the trench to form a lattice strain layer.

[0035] (5) Remove the photoresist from the surface of the trench and perform RCA cleaning to remove surface impurities and residues;

[0036] (6) High-temperature thermal oxidation is carried out, the Si-C bonds in the strain region are stretched and the bond energy is reduced, and oxygen molecules are more likely to react with the stretched Si-C bonds, which locally accelerates the oxidation rate and makes the gate thickness at the bottom of the trench significantly greater than that of the sidewall.

[0037] (7) Post-processing: The polysilicon gate filling, source metal implantation, drain metal implantation and metallization are completed sequentially (according to standard traditional process) to prepare the finished product, namely the trench gate silicon carbide MOSFET based on strain-controlled oxidation.

[0038] This invention also provides a strain-controlled oxidation-based trench gate silicon carbide MOSFET prepared by the above-described method, the overall structure of which is shown in the figure below. Figure 2 As shown, it includes an N+ type 4H-SiC substrate 1, an N- drift layer 2 epitaxially grown on the substrate, and trenches etched on the surface of the N- drift layer;

[0039] The inner wall of the trench is covered with a gate oxide layer, which includes a bottom gate 3 located at the bottom of the trench (e.g., Figure 3 (as shown) and the sidewall grid 4 located on the sidewall of the trench;

[0040] A lattice strain layer 5, formed by compressive stress generated through inert ion implantation, is disposed below the bottom surface of the trench (e.g., Figure 3 (as shown)

[0041] The trench contains a polysilicon gate region 6, and the surface of the N-drift layer contains a source metal region 7 and a drain metal region 8, located on the left and right sides outside the trench, respectively.

[0042] In a preferred embodiment of the present invention, the lattice strain layer is formed by injecting inert ions into the bottom of the trench to generate compressive stress, and the lattice strain layer is located at a depth of 10 to 50 nm below the bottom surface of the trench.

[0043] In a preferred embodiment of the present invention, the N-drift layer has a thickness of 10 μm; the trench has a depth of 1.5–2 μm and a width of 0.8–1.2 μm.

[0044] In a preferred embodiment of the present invention, the gate oxide layer includes a bottom gate located at the bottom of the trench and a sidewall gate located on the sidewall of the trench, wherein the thickness of the bottom gate is 80-100 nm and the thickness of the sidewall gate oxide layer is 50-60 nm.

[0045] The present invention will be further described in detail below with reference to specific embodiments.

[0046] Example 1: A method for fabricating a trench-gate silicon carbide MOSFET based on strain-controlled oxidation

[0047] The preparation method in this embodiment specifically includes the following steps:

[0048] (1) An N- drift layer with a thickness of 10 μm and a doping concentration of 1×10¹ is epitaxially grown on an N+ type 4H-SiC substrate for a trench gate silicon carbide MOSFET. 6 cm⁻³;

[0049] (2) The trenches are formed by etching using ICP etching technology. The trenches are 1.8 μm deep and 1.0 μm wide.

[0050] (3) Photoresist is used to mask the sidewalls and top of the trench, leaving only the bottom area of ​​the trench exposed;

[0051] (4) Inert ion implantation was performed on the exposed bottom of the trench. The implanted ions were Ar⁺ ions, and the implantation dose was 2×10¹. 4 cm⁻², with an injection energy of 150keV, compressive strain is formed in a region of 10-50nm below the bottom surface of the trench, thereby forming a lattice strain layer with a strain degree of about 1%.

[0052] (5) Remove the photoresist from the surface of the trench and perform RCA cleaning to remove surface impurities and residues;

[0053] (6) Perform high-temperature thermal oxidation at 1150℃ for 60 min;

[0054] (7) Post-processing: The polysilicon gate filling, source metal implantation, drain metal implantation and metallization are completed in sequence to prepare the finished product, namely the trench gate silicon carbide MOSFET based on strain-controlled oxidation.

[0055] The trench gate silicon carbide MOSFET obtained in this embodiment has a bottom gate oxide thickness of 90 nm and a sidewall gate oxide thickness of 55 nm. The oxidation rate in the strain region is about 40% higher than that in the non-strain region.

[0056] Example 2: A trench-gate silicon carbide MOSFET based on strain-controlled oxidation

[0057] The strain-controlled oxidation-based trench gate silicon carbide MOSFET described in this embodiment is obtained by the preparation method of Example 1:

[0058] It includes an N+ type 4H-SiC substrate, an N-drift layer epitaxially grown on the substrate, and trenches etched on the surface of the N-drift layer; the N-drift layer has a thickness of 10 μm; the trenches have a depth of 1.7 μm and a width of 1 μm.

[0059] The inner wall of the trench is covered with a gate oxide layer, which includes a bottom gate 3 located at the bottom of the trench and a sidewall gate 4 located on the sidewall of the trench; the thickness of the bottom gate is 90 nm and the thickness of the sidewall gate oxide layer is 55 nm.

[0060] A lattice strain layer 5, formed by compressive stress generated by inert ion implantation, is disposed below the bottom surface of the trench, and is located at a depth of 10 to 50 nm below the bottom surface of the trench.

[0061] The trench contains a polysilicon gate region 6, and the surface of the N-drift layer contains a source metal region 7 and a drain metal region 8, located on the left and right sides outside the trench, respectively.

[0062] The above examples are merely illustrative of the technical concept and features of the present invention and should not be construed as limiting the scope of protection of the present invention. All equivalent transformations or modifications made in accordance with the essence of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a trench-gate silicon carbide MOSFET based on strain-controlled oxidation, characterized in that, Includes the following steps: (1) An N- drift layer is epitaxially grown on an N+ type 4H-SiC substrate; (2) Using ICP etching process, trenches are formed on the surface of N-drift layer; (3) Photoresist is used to mask the sidewalls and top of the trench, leaving only the bottom area of ​​the trench exposed; (4) Inert ion implantation is performed on the exposed bottom of the trench to form a lattice strain layer, and pressure strain is generated below the bottom surface of the trench to form a lattice strain layer. (5) Remove the photoresist from the surface of the trench and perform RCA cleaning to remove surface impurities and residues; (6) High-temperature thermal oxidation is carried out, the Si-C bonds in the strain region are stretched and the bond energy is reduced, and oxygen molecules are more likely to react with the stretched Si-C bonds, which locally accelerates the oxidation rate and makes the gate thickness at the bottom of the trench significantly greater than that of the sidewall. (7) Post-processing: The polysilicon gate filling, source metal implantation, drain metal implantation and metallization are completed in sequence to prepare the finished product, namely the trench gate silicon carbide MOSFET based on strain-controlled oxidation.

2. The preparation method according to claim 1, characterized in that, In step (1), the N-drift layer has a thickness of 10 μm and a doping concentration of 1 × 10¹. 6 cm⁻³.

3. The preparation method according to claim 1, characterized in that, In step (2), the trench has a depth of 1.5 to 2 μm and a width of 0.8 to 1.2 μm.

4. The preparation method according to claim 1, characterized in that, In step (4), the inert ion is Ar⁺ or Xe⁺, and the injection dose is 1×10¹. 4 ~5×10¹ 4 cm⁻², injected energy 100~300keV.

5. The preparation method according to claim 1, characterized in that, In step (4), after the inert ions are implanted, compressive strain is generated in the range of 10~50nm below the bottom surface of the trench to form a lattice strain layer with a strain degree of 0.5%~2%.

6. The preparation method according to claim 1, characterized in that, In step (6), the high-temperature oxidation is carried out at an oxidation temperature of 1100-1200℃ for 30-90 minutes, and oxygen is introduced during oxidation at a flow rate of 1-10 L / min.

7. A trench-gate silicon carbide MOSFET based on strain-controlled oxidation, prepared by the method according to any one of claims 1-6, characterized in that: It includes an N+ type 4H-SiC substrate (1), an N- drift layer epitaxially grown on the substrate (2), a trench formed on the surface of the N- drift layer by etching, a gate oxide layer grown on the inner wall of the trench, a lattice strain layer formed below the bottom surface of the trench (5), a polysilicon gate region filled in the trench (6), a source metal region (7) and a drain metal region (8) disposed outside the trench in the N- drift layer.

8. The trench-gate silicon carbide MOSFET according to claim 7, characterized in that, The lattice strain layer is formed by injecting inert ions into the bottom of the trench to generate compressive stress, and the lattice strain layer is located at a depth of 10 to 50 nm below the bottom surface of the trench.

9. The trench-gate silicon carbide MOSFET according to claim 7, characterized in that, The N-drift layer has a thickness of 10 μm; the trench has a depth of 1.5–2 μm and a width of 0.8–1.2 μm.

10. The trench-gate silicon carbide MOSFET according to claim 7, characterized in that, The gate oxide layer includes a bottom gate (3) located at the bottom of the trench and a sidewall gate (4) located on the sidewall of the trench. The thickness of the bottom gate is 80-100 nm and the thickness of the sidewall gate oxide is 50-60 nm.

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