Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate, a channel layer and a barrier layer which are sequentially stacked; a P-type layer located at a gate region on a side of the barrier layer away from the substrate; an insertion layer located on a side of the P-type layer away from the substrate; and a cap layer located on a side of the insertion layer away from the substrate. A surface of the cap layer on the side away from the substrate comprises a plurality of pits. The pits can change the crystal face of the contact interface between the cap layer and the gate, thereby effectively increasing the Schottky barrier height, reducing the gate leakage current, and improving the device quality and reliability. The material of the insertion layer is different from that of the cap layer, so as to adjust the barrier height and the interface state density, improve the Schottky contact characteristics, and enhance the gate control ability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] Compared to first- and second-generation semiconductor materials, third-generation semiconductor materials, especially GaN (gallium nitride)-based materials, have advantages such as large bandgap, high breakdown field strength, high electron mobility, and strong radiation resistance. GaN-based HEMT (High Electron Mobility Transistor) devices have great development potential in high-frequency, high-power fields such as wireless communication base stations, radar, and automotive electronics.

[0003] Typically, GaN-based HEMT devices are depletion-mode field-effect transistors. However, in practical applications, considering factors such as cost and fault protection, enhancement-mode HEMT devices are often required. Traditional GaN-based HEMT devices can achieve enhancement mode using a P-type gate, but the P-type gate process still suffers from current leakage and other issues. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor structure and a method for fabricating the same, to reduce the gate leakage current of a P-gate HEMT device and improve the quality of the P-gate HEMT device.

[0005] According to one aspect of this application, an embodiment of this application provides a semiconductor structure comprising: a substrate, a channel layer, and a barrier layer sequentially stacked; a P-type layer located in a gate region of the barrier layer on the side away from the substrate; an insertion layer located on the side of the P-type layer away from the substrate; and a cap layer located on the side of the insertion layer away from the substrate; wherein the surface of the cap layer on the side away from the substrate includes a plurality of pits.

[0006] According to another aspect of this application, one embodiment of this application provides a method for fabricating a semiconductor structure. The method for fabricating the semiconductor structure includes: S1, sequentially epitaxially fabricating a channel layer and a barrier layer on a substrate; S2, sequentially epitaxially fabricating a P-type layer, an insertion layer, and a cap layer in a gate region on the side of the barrier layer away from the substrate, wherein the surface of the cap layer on the side away from the substrate includes a plurality of pits.

[0007] This application provides a semiconductor structure comprising: a substrate, a channel layer, and a barrier layer stacked sequentially; a P-type layer located in the gate region of the barrier layer away from the substrate; an insertion layer located on the side of the P-type layer away from the substrate; and a cap layer located on the side of the insertion layer away from the substrate. The surface of the cap layer away from the substrate includes multiple pits, which cause a crystal plane transformation at the interface between the cap layer and the gate, thereby effectively increasing the Schottky barrier height, reducing gate leakage current, and improving device quality and reliability. The material of the insertion layer differs from that of the cap layer, adjusting the barrier height and interface state density to improve Schottky contact characteristics and enhance gate control capability. Attached Figure Description

[0008] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application. Figure 2 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application; Figure 3 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application; Figure 4 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application; Figure 5 The image shown is a top view of a cap layer of a semiconductor structure provided in an embodiment of this application; Figure 6 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application; Figure 7 As shown Figure 6 A top view of the provided semiconductor structure cap layer; Figure 8 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application; Figure 9 As shown Figure 8 A top view of the provided semiconductor structure cap layer; Figure 10 The figure shown is a three-dimensional structural diagram of the cap layer of a semiconductor structure provided in an embodiment of this application; Figure 11 The image shown is a top view of the cap layer of another semiconductor structure provided in an embodiment of this application; Figures 12 to 19 The diagram shown is an intermediate structure diagram of a semiconductor structure provided in an embodiment of this disclosure during the fabrication process; Figure 20 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application. Detailed Implementation

[0009] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0010] To reduce the gate leakage current of P-gate HEMT devices and improve the quality of P-gate HEMT devices, this application provides a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, a channel layer, and a barrier layer stacked sequentially; a P-type layer located in the gate region of the barrier layer away from the substrate; an insertion layer located on the side of the P-type layer away from the substrate; and a cap layer located on the side of the insertion layer away from the substrate. The surface of the cap layer away from the substrate includes multiple pits.

[0011] The following is combined Figures 1 to 20 Further examples illustrate the semiconductor structures and fabrication methods mentioned in this application.

[0012] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application. Figure 1 As shown, the semiconductor structure includes: a substrate 10, a channel layer 20, and a barrier layer 30 stacked sequentially; a P-type layer 40 located in the gate region of the barrier layer 30 away from the substrate 10; an insertion layer 70 located on the P-type layer 40 away from the substrate 10; and a cap layer 50 located on the insertion layer 70 away from the substrate 10. The surface of the cap layer 50 away from the substrate 10 includes multiple pits 51. Specifically, when the crystal plane of the interface between the cap layer 50 and the gate is a C-plane, the C-plane has a lower Schottky barrier height compared to other non-C-planes. The pits 51 provided in the cap layer 50 can transform the crystal plane of the interface between the cap layer 50 and the gate, effectively increasing the Schottky barrier height, reducing gate leakage current, and improving device quality and reliability. Furthermore, the material of the insertion layer 70 is different from the material of the cap layer 50, adjusting the barrier height and interface state density to improve Schottky contact characteristics and enhance gate control capability.

[0013] In this embodiment, the substrate 10 may be sapphire, silicon carbide, silicon, GaN, or diamond. The materials of the channel layer 20 and the barrier layer 30 may include group III nitrides, and a two-dimensional electron gas (2DEG) may be formed at the interface between the channel layer 20 and the barrier layer 30.

[0014] In one alternative, the channel layer 20 is a GaN layer, and the barrier layer 30 is an AlGaN layer. In other alternatives, the material combination of the channel layer 20 and the barrier layer 30 can be GaN / AlN, GaN / InN, GaN / InAlGaN, GaN / InAlN, or InN / InAlN. The material of the p-type layer 40 includes p-type doped GaN-based materials.

[0015] In one embodiment, such as Figure 1 As shown, the semiconductor structure also includes: a source electrode 61 and a drain electrode 62 located on the side of the barrier layer 30 away from the substrate 10, and a gate electrode 63 located on the side of the cap layer 50 away from the substrate 10 and between the source electrode 61 and the drain electrode 62, wherein the metal material of the gate electrode 63 completely fills the pit 51.

[0016] In one embodiment, the material of the cap layer 50 includes InGaN, AlInGaN, unintentionally doped GaN, or n-type doped GaN. Optionally, when the material of the cap layer 50 is InGaN or AlInGaN, V-shaped pits are generated during the epitaxial growth of the InGaN or AlInGaN material, so the pit 51 is a V-shaped pit formed by epitaxial growth, and the inner wall crystal plane of the pit 51 includes the (1-101) crystal plane; when the material of the cap layer 50 is unintentionally doped GaN or n-type doped GaN, the pit 51 can be a pyramidal pit or frustum pit formed by etching, and the inner wall crystal plane of the pit 51 includes the (1-101) crystal plane or the (11-22) crystal plane. Specifically, the principle of generating the pit 51 is described in the embodiment of the fabrication method, and will not be repeated here.

[0017] Because the C-plane typically has a high surface state density, it generates a strong Fermi level pinning effect, which limits the Schottky barrier height to a certain range when the metal contacts the semiconductor. Furthermore, the C-plane has a specific polarization direction and intensity, and its polarization effect affects the electric field distribution and charge accumulation at the interface when in contact with the metal gate electrode, weakening the Schottky barrier height. The metal material of the gate electrode 63 completely fills the recess 51, transforming the contact interface between the cap layer 50 and the gate electrode 63 from the C-plane to the (1-101) or (11-22) crystal plane. On the one hand, the (1-101) or (11-22) crystal planes, as non-C-planes, have relatively low surface state densities and weaker Fermi level pinning effects. When the metal gate electrode contacts these crystal planes, factors such as the work function of the metal and the electron affinity of the semiconductor can play a more significant role, making the Schottky barrier height closer to the ideal state determined by the inherent properties of the metal and semiconductor materials. The determined value allows for a higher barrier height. On the other hand, the polarization properties of the (1-101) or (11-22) crystal planes differ from those of the C plane. Their polarization direction and intensity are more conducive to forming an enhanced built-in electric field at the interface. When the metal comes into contact with these crystal planes, an electric field distribution that is more conducive to increasing the barrier height is generated. This makes it necessary for electrons to overcome greater strength to reach the metal side from the semiconductor side, thereby effectively increasing the Schottky barrier height, reducing gate leakage current, and improving gate control capability, thus improving device quality and reliability.

[0018] In one embodiment, the material of the insertion layer 70 includes AlN or AlGaN. Optionally, the bandgap width of the insertion layer 70 is greater than the bandgap width of the cap layer 50. Specifically, the introduction of the insertion layer 70 can form a higher potential barrier, effectively limiting the diffusion of electrons or holes below the gate, reducing leakage current and improving threshold voltage stability. Optionally, when the insertion layer 70 contains Al, the insertion layer 70 can serve as an etch stop layer for etching pits, preventing the etching process from affecting the underlying P-type layer 40.

[0019] In one embodiment, Figure 2 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 2 As shown, the pit 51 penetrates the cap layer 50 and partially penetrates the insertion layer 70.

[0020] Optionally, Figure 3 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 3 As shown, the pit 51 penetrates the cap layer 50, and no pit is formed on the surface of the insertion layer 70 away from the substrate 10. At this time, the cross-sectional shape of the pit 51 in the direction perpendicular to the plane of the substrate 10 is trapezoidal, which can prevent the gate electrode 63 located in the pit 51 from forming a metal tip, avoid breakdown problems caused by local electric field enhancement, and improve the device's withstand voltage capability; it also prevents the metal tip from changing the band bending characteristics of the barrier layer, improves the gate's control capability of 2DEG, and reduces the off-state leakage current.

[0021] Optionally, Figure 4 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 4 As shown, the pit 51 extends through the cap layer 50. The cross-sectional shape of the pit 51 in the direction perpendicular to the plane of the substrate 10 is trapezoidal, which can avoid the problem caused by the gate electrode 63 in the pit 51 forming a metal tip.

[0022] In one embodiment, Figure 5 The image shown is a top view schematic diagram of a semiconductor structure provided in an embodiment of this application, as follows: Figure 5 As shown, the projected area of ​​the pit 51 on the plane of the substrate 10 accounts for more than 70% of the projected area of ​​the cap layer 50 on the plane of the substrate 10. Increasing the density and size of the pit 51, i.e., reducing the area of ​​the C-plane in the cap layer 50 that contacts the gate metal, can increase the Schottky barrier height, reduce the gate leakage current, and improve device quality and reliability. It can be understood that when the crystal plane of the pit is determined, the greater the pit depth, the larger its orthogonal projected area on the substrate.

[0023] It should be noted that, as Figure 5 As shown, the three-dimensional structure of the pit 51 is a hexagonal pyramid shape.

[0024] Optionally, Figure 6 The diagram shown is a schematic representation of another semiconductor structure provided in one embodiment of this application. Figure 7 As shown Figure 6 The provided top view diagram of the semiconductor structure cap layer, such as Figure 6 and Figure 7 As shown, the depth of the multiple pits 51 gradually increases from the center to the edge. The center refers to the region of the cap layer 50 far from the sidewalls, and the edge refers to the region of the cap layer 50 near the sidewalls. Current leakage is more likely to occur at the sidewalls of the gate region of the semiconductor structure; therefore, the pits 51 at the edges are designed to be deeper to reduce the possibility of sidewall leakage. Specifically, as... Figure 7 As shown, compared with the center of the cap layer 50, the edge region of the cap layer 50 is provided with a deeper pit 51 with a larger projected area on the substrate 10. This further reduces the C-surface area of ​​the cap layer 50 in contact with the gate metal at the edge region, reduces the possibility of gate sidewall leakage current, and improves device quality and reliability.

[0025] Optionally, the depth of the pit in the edge region of the cap layer near the drain is greater than the depth of the pit in the edge region of the cap layer near the source. This can reduce the C-surface area of ​​the cap layer on the drain side that is in contact with the gate metal, thereby reducing current leakage on the drain side caused by the increase in reverse current.

[0026] In one embodiment, Figure 8 The diagram shown is a schematic representation of another semiconductor structure provided in one embodiment of this application. Figure 9 As shown Figure 8 The provided top view diagram of the semiconductor structure cap layer, such as Figure 8 and Figure 9 As shown, the projection density of multiple pits 51 on the plane of the substrate 10 gradually increases from the center to the edge. Current leakage is more likely to occur at the sidewalls of the gate region of the semiconductor structure; therefore, the density of pits 51 at the edges is designed to be higher to reduce the possibility of sidewall leakage. It should be noted that... Figure 9 The projected areas of the pits 51 on the plane of the substrate 10 are the same. Alternatively, in a semiconductor structure, the projected areas of multiple pits 51 on the plane of the substrate 10 are not the same, as long as the projected area of ​​the pits 51 in the edge region of the cap layer 50 is larger.

[0027] Optionally, Figure 10 The diagram shown is a three-dimensional structural schematic of the cap layer of a semiconductor structure according to an embodiment of this application. Figure 10 As shown, the pits 51 are hexagonal in shape and are randomly distributed on the upper surface of the substrate 10. The depths of the multiple pits 51 are different and the opening areas on the surface of the substrate 10 are different.

[0028] Optionally, Figure 11 The image shown is a top view of the cap layer of another semiconductor structure provided in an embodiment of this application. Figure 11 and Figure 5 The difference is that the side of the pit 51 closest to the substrate 10 is a plane, and the plane is hexagonal in shape. The pit 51 is a hexagonal frustum, and the cross section of the pit 51 in the direction perpendicular to the plane of the substrate 10 is trapezoidal.

[0029] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is also provided. Figures 12 to 19 The diagram shown is an intermediate structure diagram of a semiconductor structure provided in an embodiment of this disclosure during the fabrication process. The fabrication method includes: S1, such as Figure 12 As shown, a channel layer 20 and a barrier layer 30 are sequentially epitaxially fabricated on a substrate 10. Specifically, the materials of the channel layer 20 and the barrier layer 30 may include group III nitride materials, and a two-dimensional electron gas may be formed at the interface between the channel layer 20 and the barrier layer 30; the material combination of the substrate 10, the channel layer 20 and the barrier layer 30 is as described in the aforementioned embodiments.

[0030] S2. A P-type layer 40, an insertion layer 70, and a cap layer 50 are sequentially epitaxially fabricated in the gate region on the side of the barrier layer 30 away from the substrate 10, wherein the surface of the cap layer 50 on the side away from the substrate 10 includes a plurality of pits 51.

[0031] The semiconductor structure prepared by the above method can reduce the area of ​​the C-plane crystal plane at the interface between the cap layer and the gate, increase the Schottky barrier height, reduce the gate leakage current, and improve the device quality and reliability. Secondly, the material of the insertion layer is different from that of the cap layer, which adjusts the barrier height and interface state density, improves the Schottky contact characteristics, and enhances the gate control capability.

[0032] In one embodiment, the material of the cap layer 50 includes InGaN, AlInGaN, unintentionally doped GaN, or n-type doped GaN. When the material of the cap layer 50 is InGaN or AlInGaN, V-shaped pits will be generated during the epitaxial growth of the InGaN or AlInGaN material. Therefore, the pit 51 is a V-shaped pit defect formed by epitaxial growth. At this time, the inner wall crystal plane of the pit 51 includes the (1-101) crystal plane. When the material of the cap layer 50 is unintentionally doped GaN or n-type doped GaN, the pit 51 can be a pyramidal pit or frustum pit formed by etching. At this time, the inner wall crystal plane of the pit 51 includes the (1-101) crystal plane or the (11-22) crystal plane.

[0033] In one embodiment, the material of the insert layer 70 includes AlN or AlGaN. Optionally, the bandgap width of the insert layer 70 is greater than the bandgap width of the cap layer 50.

[0034] In one embodiment, taking unintentionally doped GaN or n-type doped GaN as an example, a P-type layer 40, an insertion layer 70, and a cap layer 50 are sequentially epitaxially fabricated in the gate region of the barrier layer 30 away from the substrate 10, including: Figure 13 As shown, a P-type layer 40, an insertion layer 70, and a cap layer 50 are grown across the entire surface; as... Figure 14 As shown, the P-type layer 40, the insertion layer 70, and the cap layer 50, excluding the gate region 60a, are then etched away.

[0035] Optionally, a P-type layer 40, an insertion layer 70, and a cap layer 50 are sequentially epitaxially fabricated in the gate region on the side of the barrier layer 30 away from the substrate 10, including: Figure 15 As shown, after growing a 40-layer P-type layer across the entire surface; as Figure 16 As shown, the P-type layer 40 outside the gate region 60a is etched away; as Figure 14 As shown, an insertion layer 70 and a cap layer 50 are selectively epitaxially formed on the P-type layer 40 of the gate region 60a. It should be noted that during selective epitaxy, a mask layer needs to be deposited in the area outside the gate region 60a to avoid epitaxially forming the insertion layer 70 and the cap layer 50 in the area outside the gate region 60a, thereby reducing the number of etching steps for the insertion layer 70 and the cap layer 50 and simplifying the process.

[0036] like Figure 17 As shown, after forming the cap layer 50, the material of the cap layer 50 is unintentionally doped GaN or n-type doped GaN. The surface of the material can be treated with SiH4. SiH4 can selectively etch around dislocations to form pyramidal or frustum-shaped pits 51. The SiH4 treatment can be performed on the entire surface of the cap layer 50, followed by etching to remove the non-gate region of the cap layer 50, or it can be performed locally on the surface of the cap layer 50 in the gate region after etching to remove the non-gate region of the cap layer 50.

[0037] In one embodiment, taking InGaN or AlInGaN as an example, the P-type layer 40, the insertion layer 70, and the cap layer 50 are sequentially epitaxially fabricated in the gate region on the side of the barrier layer 30 away from the substrate 10, including: Figure 18 As shown, a P-type layer 40, an insertion layer 70, and a cap layer 50 are grown across the entire surface. During the epitaxial growth of InGaN or AlInGaN material (cap layer 50), when the material thickness exceeds a critical thickness, the material surface releases stress by generating V-shaped pits, thus forming V-shaped depressions 51; as shown... Figure 17 As shown, the P-type layer 40, the insertion layer 70, and the cap layer 50, excluding the gate region 60a, are then etched away.

[0038] In one embodiment, the pit 51 penetrates the cap layer 50 and a portion of the insert layer 70, and is etched to make the pit 51 penetrate the portion of the insert layer 70.

[0039] In one embodiment, the manufacturing method further includes: S3, such as Figure 1 As shown, a source electrode 61 and a drain electrode 62 are disposed on the side of the barrier layer 30 away from the substrate 10, and a gate electrode 63 is disposed on the side of the cap layer 50 away from the substrate 10 and between the source electrode 61 and the drain electrode 62, wherein the metal material of the gate electrode 63 completely fills the pit 51.

[0040] In one embodiment, Figure 20 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 20 As shown, the pit 51 penetrates the cap layer 50, the insertion layer 70, and part of the P-type layer 40. The gate electrode 63 fills the pit 51 and is in direct contact with the P-type layer 40. This three-dimensional structure expands the lateral and longitudinal control range of the gate on the channel, further enhances the depletion effect of 2DEG, reduces leakage current, and ensures off-state stability.

[0041] This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate, a channel layer, and a barrier layer stacked sequentially; a P-type layer, located in the gate region of the barrier layer on the side away from the substrate; an insertion layer, located on the side of the P-type layer away from the substrate; and a cap layer, located on the side of the insertion layer away from the substrate. The surface of the cap layer on the side away from the substrate includes multiple pits, which can cause a crystal plane transformation at the interface between the cap layer and the gate, thereby effectively increasing the Schottky barrier height, reducing gate leakage current, and improving device quality and reliability. The material of the insertion layer is different from that of the cap layer, adjusting the barrier height and interface state density to improve Schottky contact characteristics and enhance gate control capability.

[0042] It should be understood that the term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment". Specific features, structures, materials, or characteristics described in this specification may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

Claims

1. A semiconductor structure, characterized in that, include: A substrate (10), a channel layer (20), and a barrier layer (30) are stacked sequentially. The P-type layer (40) is located in the gate region of the barrier layer (30) on the side away from the substrate (10); An insertion layer (70) is located on the side of the P-type layer (40) away from the substrate (10); A cap layer (50) is located on the side of the insertion layer (70) away from the substrate (10); The surface of the cap layer (50) on the side away from the substrate (10) includes a plurality of pits (51).

2. The semiconductor structure according to claim 1, characterized in that, The material of the insertion layer (70) includes AlN or AlGaN.

3. The semiconductor structure according to claim 1, characterized in that, The material of the cap layer (50) includes InGaN, AlInGaN, unintentionally doped GaN, or n-type doped GaN.

4. The semiconductor structure according to claim 1, characterized in that, The pit (51) includes a V-shaped pit formed by epitaxial growth or a pyramidal pit or frustum formed by etching.

5. The semiconductor structure according to claim 4, characterized in that, The inner wall crystal planes of the pit (51) include (1-101) crystal planes or (11-22) crystal planes.

6. The semiconductor structure according to claim 4, characterized in that, The recess (51) penetrates the cap layer (50) and a portion of the insert layer (70).

7. The semiconductor structure according to claim 1, characterized in that, The projected area of ​​the pit (51) on the plane where the substrate (10) is located is greater than 70% of the projected area of ​​the cap layer (50) on the plane where the substrate (10) is located.

8. The semiconductor structure according to claim 1, characterized in that, The depth of the multiple pits (51) gradually increases from the center to the edge.

9. The semiconductor structure according to claim 1, characterized in that, The projection density of the multiple pits (51) on the plane of the substrate (10) gradually increases from the center to the edge.

10. The semiconductor structure according to claim 1, characterized in that, Also includes: The source electrode (61) and drain electrode (62) are located on the side of the barrier layer (30) away from the substrate (10), and the gate electrode (63) is located on the side of the cap layer (50) away from the substrate (10) and between the source electrode (61) and the drain electrode (62). The metal material of the gate electrode (63) completely fills the pit (51).

11. A method for fabricating a semiconductor structure, characterized in that, include: S1. A channel layer (20) and a barrier layer (30) are epitaxially fabricated sequentially on a substrate (10). S2. A P-type layer (40), an insertion layer (70) and a cap layer (50) are sequentially epitaxially formed on the gate region of the barrier layer (30) away from the substrate (10), wherein the surface of the cap layer (50) away from the substrate (10) includes a plurality of pits (51).

12. The manufacturing method according to claim 11, characterized in that, The process of sequentially epitaxially fabricating a P-type layer (40), an insertion layer (70), and a cap layer (50) in the gate region on the side of the barrier layer (30) away from the substrate (10) includes: The P-type layer (40), the insertion layer (70), and the cap layer (50) are grown over the entire surface, and then the P-type layer (40), the insertion layer (70), and the cap layer (50) outside the gate region are etched away; or, After growing the P-type layer (40) over the entire surface, the P-type layer (40) outside the gate region is etched away, and the insertion layer (70) and the cap layer (50) are epitaxially formed on the P-type layer (40) in the gate region.

13. The manufacturing method according to claim 11, characterized in that, The pit (51) is a V-shaped pit defect formed during the epitaxial growth of the cap layer (50) or a pyramidal pit or frustum pit formed by etching the cap layer (50).

14. The manufacturing method according to claim 13, characterized in that, The inner wall crystal planes of the V-shaped pit include (1-101) crystal planes, and the inner wall crystal planes of the pyramidal pit or frustum pit include (1-101) crystal planes or (11-22) crystal planes.

15. The manufacturing method according to claim 13, characterized in that, The recess (51) penetrates the cap layer (50) and a portion of the insert layer (70).

16. The manufacturing method according to claim 11, characterized in that, The manufacturing method further includes: S3. A source electrode (61) and a drain electrode (62) are provided on the side of the barrier layer (30) away from the substrate (10), and a gate electrode (63) is provided on the side of the cap layer (50) away from the substrate (10) and between the source electrode (61) and the drain electrode (62), wherein the metal material of the gate electrode (63) completely fills the pit (51).

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