A semiconductor structure and a method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate, a channel layer and a barrier layer which are sequentially stacked; a P-type layer located in a gate region of the barrier layer away from the substrate; and a cap layer located in the P-type layer away from the substrate; wherein a surface of the cap layer away from the substrate comprises a plurality of pits. The pits provided on the cap layer can change the crystal surface of the contact interface between the cap layer and the gate, effectively increase the Schottky barrier height, reduce the gate leakage current, and improve the quality and reliability of the device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and specifically to a semiconductor structure and its manufacturing method. Background Technology

[0002] Compared to first- and second-generation semiconductor materials, third-generation semiconductor materials, especially GaN (gallium nitride)-based materials, have advantages such as large bandgap, high breakdown field strength, high electron mobility, and strong radiation resistance. GaN-based HEMT (High Electron Mobility Transistor) devices have great development potential in high-frequency, high-power fields such as wireless communication base stations, radar, and automotive electronics.

[0003] Typically, GaN-based HEMT devices are depletion-mode field-effect transistors. However, in practical applications, considering factors such as cost and fault protection, enhancement-mode HEMT devices are often required. Traditional GaN-based HEMT devices can achieve enhancement mode using a P-type gate, but the P-type gate process still suffers from current leakage and other issues. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same, to reduce the gate leakage current of a P-gate HEMT device and improve the quality of the P-gate HEMT device.

[0005] According to one aspect of this disclosure, an embodiment of this disclosure provides a semiconductor structure, the semiconductor structure comprising: A substrate, a channel layer, and a barrier layer are stacked sequentially. A P-type layer is located in the gate region on the side of the barrier layer away from the substrate; A cap layer is located on the side of the P-type layer away from the substrate; The surface of the cap layer away from the substrate includes a plurality of pits, and the inner wall crystal planes of the pits include (1-101) crystal planes or (11-22) crystal planes.

[0006] As an optional embodiment, the pit includes a V-shaped pit formed by epitaxial growth or a pyramidal pit or frustum formed by etching.

[0007] As an optional embodiment, it further includes an insertion layer located between the P-type layer and the cap layer.

[0008] As an optional embodiment, the material of the cap layer includes InGaN, AlInGaN, unintentionally doped GaN, or n-type doped GaN.

[0009] As an optional embodiment, the projected area of ​​the pit on the plane where the substrate is located accounts for more than 70% of the projected area of ​​the cap layer on the plane where the substrate is located.

[0010] As an optional embodiment, the depth of at least one of the pits is different from the depth of the other pits.

[0011] As an optional embodiment, the depth of the plurality of pits gradually increases from the center to the edge.

[0012] As an optional embodiment, the projection density of the plurality of pits on the plane of the substrate gradually increases from the center to the edge.

[0013] As an optional embodiment, it further includes: a source electrode and a drain electrode located on the side of the barrier layer away from the substrate, and a gate electrode located on the side of the cap layer away from the substrate and between the source electrode and the drain electrode.

[0014] As an optional embodiment, the metal material of the gate electrode completely fills the pit.

[0015] According to another aspect of this disclosure, one embodiment provides a method for manufacturing a semiconductor structure, the method comprising: S1. A substrate, a channel layer, and a barrier layer are sequentially stacked. S2. A P-type layer and a cap layer are sequentially stacked in the gate region on the side of the barrier layer away from the substrate. The surface of the cap layer on the side away from the substrate includes multiple pits, and the inner wall crystal plane of the pits includes a (1-101) crystal plane or a (11-22) crystal plane.

[0016] As an optional embodiment, the step of sequentially stacking a P-type layer and a cap layer in the gate region includes: growing the P-type layer and the cap layer over the entire surface, and then etching away the P-type layer and the cap layer outside the gate region.

[0017] As an optional embodiment, the step of sequentially stacking a P-type layer and a cap layer in the gate region includes: growing the P-type layer over the entire surface and then etching away the P-type layer outside the gate region, and epitaxially forming the cap layer on a selected area of ​​the P-type layer in the gate region.

[0018] As an optional embodiment, the pit is a V-shaped pit defect formed during the epitaxial growth of the cap layer, and the inner wall crystal plane of the V-shaped pit includes (1-101) crystal planes; or, the cap layer is etched to form a pyramidal pit or frustum pit, and the inner wall crystal plane of the pyramidal pit or frustum pit includes (1-101) crystal planes or (11-22) crystal planes.

[0019] As an optional embodiment, the method for manufacturing the semiconductor structure further includes: S3. A source electrode and a drain electrode are disposed on the side of the barrier layer away from the substrate, and a gate electrode is disposed on the side of the cap layer away from the substrate and between the source electrode and the drain electrode.

[0020] As an optional embodiment, the metal material of the gate electrode completely fills the pit.

[0021] This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes: a substrate, a channel layer, and a barrier layer sequentially stacked; a P-type layer, a gate region located on the side of the barrier layer away from the substrate; and a cap layer located on the side of the P-type layer away from the substrate. The surface of the cap layer on the side away from the substrate includes multiple pits. The pits in the cap layer can cause a crystal plane transition at the interface between the cap layer and the gate, thereby effectively increasing the Schottky barrier height, reducing gate leakage current, and improving device quality and reliability. Attached Figure Description

[0022] Figure 1 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0023] Figure 2a The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0024] Figure 2b As shown Figure 2a Top view of the provided semiconductor structure cap layer Figure 3a The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0025] Figure 3b As shown Figure 3a A top view of the provided semiconductor structure cap layer.

[0026] Figure 4 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0027] Figure 5 The diagram shown is a flowchart of a semiconductor structure manufacturing method according to an embodiment of this disclosure.

[0028] Figures 6 to 11 The diagram shown is an intermediate structure diagram of a semiconductor structure provided in an embodiment of this disclosure during the manufacturing process.

[0029] Figure 12 The figure shown is a three-dimensional structural diagram of the cap layer of a semiconductor structure provided in an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0031] To reduce the gate leakage current and improve the quality of P-gate HEMT devices, this disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes: a substrate, a channel layer, and a barrier layer sequentially stacked; a P-type layer, located in the gate region on the side of the barrier layer away from the substrate; and a cap layer, located on the side of the P-type layer away from the substrate. The surface of the cap layer on the side away from the substrate includes multiple pits. The pits in the cap layer allow for a crystal plane transition at the interface between the cap layer and the gate, effectively increasing the Schottky barrier height, reducing the gate leakage current, and improving device quality and reliability.

[0032] The following is combined with Figures 1 to 11 A further example illustrates a semiconductor structure and its manufacturing method mentioned in this disclosure.

[0033] Figure 1 The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. Figure 1 As shown, the semiconductor structure includes: a substrate 10, a channel layer 20, and a barrier layer 30 stacked sequentially; a P-type layer 40 located in the gate region of the barrier layer 30 away from the substrate 10; and a cap layer 50 located on the side of the P-type layer 40 away from the substrate 10. The surface of the cap layer 50 away from the substrate 10 includes multiple pits 51, and the inner wall crystal planes of the pits 51 include (1-101) or (11-22) crystal planes. When the crystal plane of the interface between the cap layer 50 and the gate is a C-plane, the C-plane has a lower Schottky barrier height compared to other non-C-planes (e.g., (1-101) and (11-22) crystal planes). The pits 51 provided in the cap layer 50 in this disclosure can transform the crystal plane of the interface between the cap layer 50 and the gate, effectively increasing the Schottky barrier height, reducing gate leakage current, and improving device quality and reliability.

[0034] In this embodiment, as Figure 1As shown, the semiconductor structure further includes: a source electrode 61 and a drain electrode 62 located on the side of the barrier layer 30 away from the substrate 10, and a gate electrode 63 located on the side of the cap layer 50 away from the substrate 10 and between the source electrode 61 and the drain electrode 62. The metal material of the gate electrode 63 completely fills the pit 51. On the one hand, it transforms the contact interface between the cap layer 50 and the gate electrode 63 from the C-plane to the (1-101) or (11-22) crystal plane. The C-plane usually has a high surface state density, which will produce a strong Fermi level pinning effect. This makes it difficult to increase the Schottky barrier height when the metal contacts the semiconductor. In addition, the C-plane has a specific polarization direction and polarization intensity. When it contacts the metal gate electrode, its polarization effect will affect the electric field distribution and charge accumulation at the interface. This effect will weaken the Schottky barrier height. On the other hand, the (1-101) or (11-22) crystal planes, as non-C-planes, have a relatively low surface state density and a weaker Fermi level pinning effect. When the metal gate electrode contacts this… When these crystal planes come into contact, factors such as the work function of the metal and the electron affinity of the semiconductor can play a more significant role, making the Schottky barrier height closer to the value determined by the inherent properties of the metal and semiconductor materials under ideal conditions, thereby achieving a higher barrier height. At the same time, the polarization properties of the (1-101) or (11-22) crystal planes are different from those of the C plane, and their polarization direction and polarization intensity are more conducive to forming an enhanced built-in electric field at the interface. When the metal comes into contact with these crystal planes, an electric field distribution that is more conducive to increasing the barrier height will be generated, making electrons need to overcome a higher energy to reach the metal side from the semiconductor side, thereby effectively increasing the Schottky barrier height, reducing the gate leakage current, and improving the device quality and reliability. On the other hand, it can improve the gate control capability.

[0035] In this embodiment, the substrate 10 may be sapphire, silicon carbide, silicon, GaN, or diamond. The materials of the channel layer 20 and the barrier layer 30 may include group III nitrides, and a two-dimensional electron gas may be formed at the interface between the channel layer 20 and the barrier layer 30.

[0036] In one alternative, the channel layer 20 is a GaN layer, and the barrier layer 30 is an AlGaN layer. In other alternatives, the material combination of the channel layer 20 and the barrier layer 30 can be GaN / AlN, GaN / InN, GaN / InAlGaN, GaN / InAlN, or InN / InAlN. The material of the p-type layer 40 includes p-type doped GaN-based materials.

[0037] In this embodiment, the material of the cap layer 50 includes InGaN, AlInGaN, unintentionally doped GaN, or n-type doped GaN. When the material of the cap layer 50 is InGaN or AlInGaN, V-shaped pits are generated during the epitaxial growth of the InGaN or AlInGaN material. Therefore, the pit 51 is a V-shaped pit formed by epitaxial growth, and the inner wall crystal plane of the pit 51 includes the (1-101) crystal plane. When the material of the cap layer 50 is unintentionally doped GaN or n-type doped GaN, the pit 51 can be a pyramidal pit or frustum pit formed by etching. In this case, the inner wall crystal plane of the pit 51 includes the (1-101) crystal plane or the (11-22) crystal plane. Specifically, the principle of generating the pit 51 is described in the embodiment of the manufacturing method, and will not be repeated here. The recess 51 provided in the cap layer 50 can transform the contact interface between the cap layer 50 and the gate electrode 63 from the C-plane to the (1-101) crystal plane or the (11-22) crystal plane, thereby effectively increasing the Schottky barrier height, reducing the gate leakage current, and improving the device quality and reliability.

[0038] In some embodiments, the projected area of ​​the pit 51 on the plane of the substrate 10 is greater than 70% of the projected area of ​​the cap layer 50 on the plane of the substrate 10. Increasing the density and size of the pit 51, i.e. reducing the area of ​​the C-plane in the cap layer 50 that contacts the gate metal, can increase the Schottky barrier height, reduce the gate leakage current, and improve device quality and reliability.

[0039] In some embodiments, Figure 2a The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. Figure 2b As shown Figure 2a The provided top view diagram of the semiconductor structure cap layer, such as Figure 2a and Figure 2b As shown, the depth of at least one pit 51 differs from the depths of the other pits 51. It is understood that, when the crystal plane of the pit is determined, the greater the pit depth, the larger the area of ​​its orthogonal projection on the substrate.

[0040] Optional, such as Figure 2a and Figure 2b As shown, the depth of the multiple pits 51 gradually increases from the center to the edge. The center refers to the region of the cap layer 50 far from the sidewalls, and the edge refers to the region of the cap layer 50 near the sidewalls. Current leakage is more likely to occur at the sidewalls of the gate region of the semiconductor structure; therefore, the pits 51 at the edges are designed to be deeper to reduce the possibility of sidewall leakage. Optionally, such as... Figure 2bAs shown, the area of ​​the multiple pits 51 projected onto the substrate 10 gradually increases from the center to the edge. Compared to the center of the cap layer 50, the edge region of the cap layer 50 can further reduce the C-surface area of ​​the cap layer 50 in contact with the gate metal, thereby reducing gate sidewall leakage current and improving device quality and reliability. Generally, the direction from the center to the edge is parallel to the direction from the source to the drain. Optionally, the depth of the pits in the edge region of the cap layer near the drain is greater than the depth of the pits in the edge region of the cap layer near the source. This can reduce the C-surface area of ​​the cap layer 50 located on the drain side and in contact with the gate metal, thereby reducing current leakage on the drain side caused by increased reverse current.

[0041] In some embodiments, FIG3 shows a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 3b As shown Figure 3a A top view of the provided semiconductor structure cap layer. (See diagram below.) Figure 3a and Figure 3b As shown, the projection density of multiple pits 51 on the plane of the substrate 10 gradually increases from the center to the edge. Current leakage and other problems are more likely to occur at the sidewalls of the gate region of the semiconductor structure. Therefore, the density of pits 51 at the edge is designed to be greater to reduce the possibility of sidewall leakage.

[0042] It should be noted that, as Figure 2b and Figure 3b As shown, the top view of the pit 51 is hexagonal, and the three-dimensional structure of the pit 51 is a hexagonal pyramid.

[0043] Optionally, the pit 51 is provided through the cap layer 50, and within the thickness range of the film layer where the cap layer 50 is located, the three-dimensional structure of the pit 51 is a hexagonal truncated pyramid.

[0044] In one embodiment, Figure 4 The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. Figure 4 As shown, the semiconductor structure also includes an insertion layer 70 located between the P-type layer 40 and the cap layer 50. Optionally, the bandgap of the insertion layer 70 is greater than the bandgap of the cap layer 50. Specifically, the introduction of the insertion layer 70 can form a higher potential barrier, effectively limiting the diffusion of electrons or holes below the gate, reducing leakage current and improving threshold voltage stability. Optionally, when the insertion layer 70 contains Al, the insertion layer 70 can serve as an etch stop layer for forming pits, preventing the etching process from affecting the underlying P-type layer 40.

[0045] According to another aspect of this disclosure, a method for manufacturing a semiconductor structure is provided. Figure 5 The diagram shown is a flowchart of a semiconductor structure manufacturing method according to an embodiment of this disclosure. Figures 6 to 11The diagram shown is an intermediate structure diagram of a semiconductor structure provided in an embodiment of this disclosure during the manufacturing process. Figure 5 As shown, a method for manufacturing a semiconductor structure according to an embodiment of this disclosure includes the following steps: Step S1: The substrate, channel layer and barrier layer are stacked sequentially.

[0046] Specifically, such as Figure 6 As shown, a substrate 10, a channel layer 20, and a barrier layer 30 are sequentially stacked. The substrate 10 can be sapphire, silicon carbide, silicon, GaN, or diamond. The materials of the channel layer 20 and the barrier layer 30 can include group III nitride materials, and a two-dimensional electron gas can be formed at the interface between the channel layer 20 and the barrier layer 30. In one optional embodiment, the channel layer 20 is a GaN layer, and the barrier layer 30 is an AlGaN layer. In other optional embodiments, the material combination of the channel layer 20 and the barrier layer 30 can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN.

[0047] Step S2: A P-type layer and a cap layer are sequentially stacked in the gate region on the side of the barrier layer away from the substrate, wherein the surface of the cap layer on the side away from the substrate includes multiple pits.

[0048] Specifically, such as Figure 7As shown, a P-type layer 40 and a cap layer 50 are sequentially stacked in the gate region of the barrier layer 30 away from the substrate 10. The surface of the cap layer 50 away from the substrate 10 includes multiple pits 51. The material of the P-type layer 40 includes a P-type doped GaN-based material. The material of the cap layer 50 includes InGaN, AlInGaN, unintentionally doped GaN, or n-type doped GaN. When the material of the cap layer 50 is InGaN or AlInGaN, V-shaped pits will be generated during the epitaxial growth of InGaN or AlInGaN. Therefore, the pits 51 are V-shaped pit defects formed by epitaxial growth. In this case, the inner wall crystal plane of the pit 51 includes the (1-101) crystal plane. When the material of the cap layer 50 is unintentionally doped GaN or n-type doped GaN, the pits 51 can be etched pyramidal pits or frustum pits. In this case, the inner wall crystal plane of the pit 51 includes the (1-101) crystal plane or the (11-22) crystal plane. Specifically, when the cap layer 50 is made of InGaN or AlInGaN, during the epitaxial growth of InGaN or AlInGaN, when the material thickness exceeds the critical thickness, the material surface will release stress by generating V-shaped pits, thus forming V-shaped pits 51. Optionally, the cap layer 50 may include Si / Mg co-doping. Specifically, when the cap layer 50 is made of unintentionally doped GaN or n-type doped GaN, the material surface can be treated with SiH4. SiH4 can selectively etch around dislocations to form pyramidal or frustum-shaped pits 51. The SiH4 treatment can be performed on the entire surface of the cap layer 50, followed by etching to remove the non-gate region of the cap layer 50, or it can be performed locally on the surface of the cap layer 50 in the gate region after etching to remove the non-gate region of the cap layer 50.

[0049] In some embodiments, sequentially stacking a P-type layer 40 and a cap layer 50 in the gate region includes: as follows Figure 8 As shown, a P-type layer 40 and a cap layer 50 are grown across the entire surface, as follows: Figure 9 As shown, the P-type layer 40 and the cap layer 50 outside the gate region are etched away.

[0050] In some embodiments, sequentially stacking a P-type layer 40 and a cap layer 50 in the gate region includes: as follows Figure 10 As shown, a P-type layer 40 is grown across the entire surface, as... Figure 11 As shown, the P-type layer 40 outside the gate region is etched away, and a cap layer 50 is epitaxially formed on a selected area of ​​the P-type layer 40 in the gate region, forming a cap layer 50 as shown. Figure 9 The semiconductor structure shown.

[0051] Step S3: A source electrode and a drain electrode are disposed on the side of the barrier layer away from the substrate, and a gate electrode is disposed on the side of the cap layer away from the substrate and between the source electrode and the drain electrode.

[0052] Specifically, a source electrode 61 and a drain electrode 62 are disposed on the side of the barrier layer 30 away from the substrate 10, and a gate electrode 63 is disposed on the side of the cap layer 50 away from the substrate 10 and between the source electrode 61 and the drain electrode 62, forming a structure as shown in the diagram. Figure 1 The semiconductor structure shown. The metal material of the gate electrode 63 completely fills the pit 51. On the one hand, it transforms the contact interface between the cap layer 50 and the gate electrode 63 from the C-plane to the (1-101) crystal plane or the (11-22) crystal plane, thereby effectively increasing the Schottky barrier height, reducing the gate leakage current, and improving the device quality and reliability. On the other hand, it can improve the gate control capability.

[0053] In some embodiments, the projected area of ​​the pit 51 on the plane of the substrate 10 is greater than 70% of the projected area of ​​the cap layer 50 on the plane of the substrate 10. Increasing the density and size of the pit 51, i.e. reducing the area of ​​the C-plane in contact with the gate metal, can increase the Schottky barrier height, reduce the gate leakage current, and improve device quality and reliability.

[0054] In some embodiments, the depth of at least one recess 51 differs from the depths of the other recesses 51. Optionally, as shown in FIG2, the depth of the plurality of recesses 51 gradually increases from the center to the edge. Current leakage and other problems are more likely to occur at the sidewalls of the gate region of the semiconductor structure, so the recesses 51 at the edges are designed to be deeper to reduce the possibility of sidewall leakage.

[0055] In some embodiments, as shown in FIG3, the projection density of the plurality of pits 51 on the plane of the substrate 10 gradually increases from the center to the edge. Current leakage and other problems are more likely to occur at the sidewalls of the gate region of the semiconductor structure. Therefore, the density of pits 51 at the edge is designed to be greater to reduce the possibility of sidewall leakage.

[0056] Optionally, Figure 12 The diagram shown is a three-dimensional structural schematic of the cap layer of a semiconductor structure according to an embodiment of this application. Figure 12 As shown, the pits 51 are hexagonal in shape and are randomly distributed on the upper surface of the substrate 10. The depths of the multiple pits 51 are different and the opening areas on the surface of the substrate 10 are different.

[0057] This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes: a substrate, a channel layer, and a barrier layer sequentially stacked; a P-type layer, located in the gate region on the side of the barrier layer away from the substrate; and a cap layer, located on the side of the P-type layer away from the substrate. The surface of the cap layer on the side away from the substrate includes multiple pits. The pits in the cap layer can cause a crystal plane transition at the interface between the cap layer and the gate, effectively increasing the Schottky barrier height, reducing gate leakage current, and improving device quality and reliability.

[0058] It should be understood that the term "comprising" and its variations as used in this disclosure are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0059] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications or equivalent substitutions made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate (10), a channel layer (20), and a barrier layer (30) are stacked sequentially. The P-type layer (40) is located in the gate region of the barrier layer (30) on the side away from the substrate (10); A cap layer (50) is located on the side of the P-type layer (40) away from the substrate (10); The cap layer (50) has a plurality of pits (51) on the side away from the substrate (10), and the inner wall crystal plane of the pit (51) includes a (1-101) crystal plane or a (11-22) crystal plane.

2. The semiconductor structure according to claim 1, characterized in that, The pit (51) includes a V-shaped pit formed by epitaxial growth or a pyramidal pit or frustum formed by etching.

3. The semiconductor structure according to claim 1, characterized in that, Also includes: An insert layer (70) is located between the P-type layer (40) and the cap layer (50).

4. The semiconductor structure according to claim 1, characterized in that, The material of the cap layer (50) includes InGaN, AlInGaN, unintentionally doped GaN, or n-type doped GaN.

5. The semiconductor structure according to claim 1, characterized in that, The projected area of ​​the pit (51) on the plane where the substrate (10) is located is greater than 70% of the projected area of ​​the cap layer (50) on the plane where the substrate (10) is located.

6. The semiconductor structure according to claim 1, characterized in that, The depth of at least one of the pits (51) is different from the depth of the other pits (51).

7. The semiconductor structure according to claim 6, characterized in that, The depth of the multiple pits (51) gradually increases from the center to the edge.

8. The semiconductor structure according to claim 1, characterized in that, The projection density of the multiple pits (51) on the plane of the substrate (10) gradually increases from the center to the edge.

9. The semiconductor structure according to claim 1, characterized in that, Also includes: The source electrode (61) and drain electrode (62) are located on the side of the barrier layer (30) away from the substrate (10), and the gate electrode (63) is located on the side of the cap layer (50) away from the substrate (10) and between the source electrode (61) and the drain electrode (62).

10. The semiconductor structure according to claim 9, characterized in that, The metal material of the gate electrode (63) completely fills the pit (51).

11. A method for manufacturing a semiconductor structure, characterized in that, include: S1. A substrate (10), a channel layer (20), and a barrier layer (30) are sequentially stacked. S2. A P-type layer (40) and a cap layer (50) are sequentially stacked in the gate region on the side of the barrier layer (30) away from the substrate (10). The surface of the cap layer (50) away from the substrate (10) includes a plurality of pits (51). The inner wall crystal plane of the pit (51) includes a (1-101) crystal plane or a (11-22) crystal plane.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The step of sequentially stacking a P-type layer (40) and a cap layer (50) in the gate region includes: growing a P-type layer (40) and a cap layer (50) over the entire surface, and then etching away the P-type layer (40) and the cap layer (50) outside the gate region.

13. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The step of sequentially stacking a P-type layer (40) and a cap layer (50) in the gate region includes: growing the P-type layer (40) over the entire surface and then etching away the P-type layer (40) outside the gate region, and selectively epitaxially forming the cap layer (50) on the P-type layer (40) in the gate region.

14. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The pit (51) is a V-shaped pit defect formed during the epitaxial growth of the cap layer (50), and the inner wall crystal plane of the V-shaped pit includes (1-101) crystal planes; or, The cap layer (50) is etched to form a pyramidal pit or frustum pit, wherein the inner wall crystal planes of the pyramidal pit or frustum pit include (1-101) crystal planes or (11-22) crystal planes.

15. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The method for manufacturing the semiconductor structure further includes: S3. A source electrode (61) and a drain electrode (62) are provided on the side of the barrier layer (30) away from the substrate (10), and a gate electrode (63) is provided on the side of the cap layer (50) away from the substrate (10) and between the source electrode (61) and the drain electrode (62).

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, The metal material of the gate electrode (63) completely fills the pit (51).

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