A single event nitride gallium device accelerating charge collection and a preparation method thereof

Abstract

This invention discloses a gallium nitride (GaN) device with accelerated charge collection and single-particle suppression, comprising, from bottom to top, a substrate, a buffer layer, a channel layer, a barrier layer, and a passivation layer. A source and a drain are respectively disposed on the left and right sides of the passivation layer, extending downwards from the upper surface of the passivation layer to the lower surface of the barrier layer. The lower surface of the source is in contact with the upper surface of the channel layer. A lateral pn junction buried layer is embedded on the upper surface of the channel layer near the drain, with its upper surface in contact with the lower surface of the drain. A p-GaN cap layer is embedded inside the passivation layer between the source and drain, with its lower surface in contact with the barrier layer. The p-GaN cap layer is separated from the source and drain by the passivation layer on both sides. A gate is disposed on the upper surface of the p-GaN cap layer. The lateral pn junction buried layer introduced in this invention provides an accelerated path for carrier transport, modulates the electric field strength near the drain, reduces the impact ionization rate, and prevents single-particle burn-out due to thermal runaway.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a gallium nitride device for accelerating charge collection and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) HEMT devices, due to their wide bandgap, high breakdown electric field, and high electron mobility, have become core components in high-frequency, high-power applications and aerospace power systems. To meet the demands of power electronic systems for normally-off devices, P-GaN gate enhancement-mode HEMT structures are widely used. However, in radiation environments such as space, these devices are inevitably bombarded by high-energy cosmic rays (heavy ions or high-energy particles). When heavy ions penetrate a HEMT device under high-voltage bias, they generate high-density electron-hole pairs along its trajectory. Under a strong electric field, these charge carriers can trigger avalanche multiplication, leading to catastrophic single-event burn-up (SEB) and seriously threatening the system safety of spacecraft.

[0003] The most common radiation-hardened GaN HEMT structure currently employs field plate technology, such as an n-type doped field plate structure introduced on the drain side. This structure includes, from bottom to top, a substrate, a buffer layer, a channel layer, a barrier layer, and a P-GaN cap layer, source, and drain that are in contact with the upper surface of the barrier layer. A slowly doped n-type semiconductor is designed on the passivation layer between the drain and the cap layer, with its right side in contact with the drain and its left side not in contact with the cap layer. This can suppress the high electric field at the drain caused by single-event effects and improve the device's resistance to single-event burn-out.

[0004] However, because the n-type drain field plate of this radiation-resistant GaN HEMT structure is located on the device surface, it can only modulate a shallow electric field, while the internal electric field in the GaN channel layer and buffer layer remains very high. Its resistance to single-event burn-off is limited, and it still cannot meet the requirements for long-term stable application in high-energy particle radiation environments. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a gallium nitride device for accelerating charge collection and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a gallium nitride device for accelerating charge collection and resisting single-particle emissions, comprising, from bottom to top, a substrate, a buffer layer, a channel layer, a barrier layer, and a passivation layer, wherein, A source and a drain are respectively disposed on the left and right sides of the passivation layer. The source and the drain extend downward from the upper surface of the passivation layer to the lower surface of the barrier layer. The lower surface of the source is in contact with the upper surface of the channel layer. A transverse pn junction buried layer is embedded on the upper surface of the channel layer near the drain electrode, and the upper surface of the transverse pn junction buried layer is in contact with the lower surface of the drain electrode. A p-GaN cap layer is embedded inside the passivation layer between the source and the drain. The lower surface of the p-GaN cap layer is in contact with the barrier layer. The two sides of the p-GaN cap layer are separated from the source and the drain by the passivation layer. A gate is disposed on the upper surface of the p-GaN cap layer.

[0006] In one embodiment of the present invention, the lateral pn junction buried layer includes a p region and an n region disposed in the lateral direction and in contact with each other, the p region and the n region forming a pn junction, and the lower surface of the drain electrode in contact with the upper surface of the n region.

[0007] In one embodiment of the present invention, the lateral pn junction buried layer includes one or more pn junctions disposed in the lateral direction.

[0008] In one embodiment of the present invention, the first side of the lateral pn junction buried layer is located below the drain electrode, and the second side does not overlap with the vertical projection of the p-GaN cap layer; the thickness of the lateral pn junction buried layer is 10~200nm.

[0009] In one embodiment of the present invention, the doping concentration of the p-region and n-region in the lateral pn junction buried layer is 1e15~1e20cm. - ³, the p-region and the n-region are uniformly doped.

[0010] In one embodiment of the present invention, the doping concentrations of the p-region and n-region in the lateral pn junction buried layer gradually increase from the side closer to the source to the side closer to the drain.

[0011] In one embodiment of the present invention, the p region and the n region have the same thickness, and the p region and the n region have different widths.

[0012] In one embodiment of the present invention, the upper end of the gate includes a field plate structure extending toward the drain.

[0013] In one embodiment of the present invention, the source and the drain are ohmic contact electrodes, and the gate is a Schottky contact electrode.

[0014] Another aspect of the present invention provides a method for fabricating a gallium nitride (GaN) device with accelerated charge collection, for fabricating the GaN device, the method comprising: S1: A buffer layer and a channel layer are grown sequentially on the upper surface of the substrate; S2: A transverse pn junction buried layer is prepared on the upper surface of the channel layer near the drain region; S3: A barrier layer and a p-GaN cap layer are sequentially grown on the upper surface of the channel layer; S4: Etch the p-GaN cap layer in the non-gate region and deposit a passivation layer on the upper surface of the barrier layer not covered by the p-GaN cap layer; S5: Remove the passivation layer from the gate region, source region, and drain region; S6: Deposit source metal and drain metal in the source region and the drain region respectively, and perform rapid thermal annealing to form source and drain, wherein the source and drain are both ohmic contact electrodes; S7: Deposit gate metal in the gate region on the upper surface of the p-GaN cap layer to form a gate with a field plate structure, wherein the gate is a Schottky contact electrode.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention introduces a lateral pn junction buried layer inside the channel layer below the drain, which can directly act on the peak electric field region under the off-state of the device. This lateral pn junction buried layer forms a built-in electric field under high-voltage bias, which can participate in the regulation of the internal electric field distribution of the device, effectively absorbing voltage drops and alleviating the originally highly concentrated local electric field near the drain, thereby significantly reducing the peak drain electric field and smoothing the internal potential distribution. Compared with traditional structures that rely solely on surface field plates for regulation, this invention provides more direct and sensitive regulation of the bulk electric field, suppressing impact ionization and avalanche multiplication effects caused by high field strength, and significantly improving the single-particle burn-out threshold of the device under radiation conditions.

[0016] 2. To address the large number of electron-hole pairs generated by the incidence of heavy ions or high-energy particles, this invention utilizes the built-in electric field effect of the pn junction to construct a highly efficient carrier separation and transport channel. Specifically, the buried layer of this lateral pn junction can rapidly collect and export holes generated by secondary collisional ionization near the buffer layer and drain, while accelerating electron transport to the drain, effectively preventing the retention and accumulation of high-concentration charges in the drain region. This active control of the carrier collection path blocks the local electric field enhancement mechanism caused by space charge accumulation, reduces transient current peaks, and prevents device failure caused by this.

[0017] 3. Because the lateral pn junction buried layer enables rapid extraction of additional charge and effectively reduces the transient current after single-particle incident, the Joule heat concentration phenomenon caused by localized high current is alleviated. Compared with traditional device structures, this invention can reduce the local temperature during device operation, slow down the temperature rise rate, thereby avoiding thermal runaway and significantly improving the long-term reliability and stability of the device under irradiation, high temperature, and high power conditions.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a gallium nitride device for accelerating charge collection and resisting single-particle collisions, provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another gallium nitride device for accelerating charge collection and resisting single-particle dumping provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another gallium nitride device for accelerating charge collection and resisting single-particle dumping provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating a method for fabricating a gallium nitride device with accelerated charge collection and resistance to single-particle interference, provided in an embodiment of the present invention. Figure 5 This is a transient drain current response curve of a device containing a lateral pn junction buried layer provided in an embodiment of the present invention; Figure 6 This is a drain transient current response curve of a typical device model that does not include a lateral pn junction buried layer.

[0020] Explanation of reference numerals in the attached figures: 1-Substrate; 2-Buffer layer; 3-Channel layer; 4-Barrier layer; 5-Passivation layer; 6-Source; 7-Drain; 8-p-GaN cap layer; 9-Gate; 10-Lateral pn junction buried layer. Detailed Implementation

[0021] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a gallium nitride device for accelerating charge collection and its preparation method according to the present invention.

[0022] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0023] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0024] Example 1 Please see Figure 1 , Figure 1 This is a schematic diagram of a gallium nitride (GaN) device for accelerating charge collection according to an embodiment of the present invention. The GaN device includes, from bottom to top, a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a passivation layer 5. A source 6 and a drain 7 are respectively disposed on the left and right sides of the passivation layer 5, extending downwards from the upper surface of the passivation layer 5 to the lower surface of the barrier layer 4. The lower surface of the source 6 contacts the upper surface of the channel layer 3. A lateral pn junction buried layer 10 is embedded on the upper surface of the channel layer 3 near the drain 7, and its upper surface contacts the lower surface of the drain 7. A p-GaN cap layer 8 is embedded inside the passivation layer 5 between the source 6 and the drain 7. The lower surface of the p-GaN cap layer 8 contacts the barrier layer 4, and its two sides are separated from the source 6 and drain 7 by the passivation layer 5. A gate 9 is disposed on the upper surface of the p-GaN cap layer 8.

[0025] In this embodiment, the substrate 1 can be made of one of Si, SiC, sapphire, or GaN. The buffer layer 2 can be made of one or more of GaN, AlN, AlGaN, InGaN, and InAlN, with a thickness of 1-10 μm. The barrier layer 4 can be made of one of GaN, AlN, AlGaN, InGaN, and InAlN, with a thickness of 5-100 nm. The passivation layer 5 can be made of SiN. x One of Al2O3, AlN, SiO2, HfO2, ScO2, TiO2, and ZrO2.

[0026] Preferably, in this embodiment, the buffer layer 2 is a GaN buffer layer, the channel layer 3 is a GaN channel layer, the barrier layer 4 is an AlGaN barrier layer, and the passivation layer 5 is a Si3N4 passivation layer.

[0027] Furthermore, the lateral pn junction buried layer 10 includes p regions and n regions arranged in a lateral direction and in contact with each other, and the p regions and n regions form a pn junction; the lateral pn junction buried layer 10 includes one or more pn junctions arranged in a lateral direction.

[0028] In one specific embodiment, the lateral pn junction buried layer 10 includes a p region and an n region arranged laterally and in contact with each other, such as Figure 1 In another specific embodiment, the lateral pn junction buried layer 10 includes a plurality of pn junctions arranged in a lateral direction, such as... Figure 2 As shown, structures such as pnpn and pnpnpn are formed.

[0029] The lower surface of the drain electrode 7 is in contact with the upper surface of the n-region. That is, the n-region is located on the lower surface of the drain electrode 7 and the width of the n-region in the lateral direction is greater than or equal to the width of the drain electrode 7, so that the drain electrode 7 is not in contact with the p-region.

[0030] If the current lateral pn junction buried layer 10 includes multiple pn junctions, then the lower surface of the drain 7 contacts the first p-region at the outermost edge. The first side of the lateral pn junction buried layer 10 is located below the drain 7, and the second side does not overlap with the vertical projection of the p-GaN cap layer 8; the thickness of the lateral pn junction buried layer 10 is 10~200nm. As shown in the figure, the left edge of the lateral pn junction buried layer 10 is flush with the left edge of the drain 7, and the right edge extends towards the source, but does not exceed the rightmost edge of the vertical projection of the p-GaN cap layer 8.

[0031] In one specific embodiment, the doping concentration of the p-region and n-region in the lateral pn junction buried layer 10 is 1e15~1e20cm⁻¹. - ³, the p-region and n-region are uniformly doped. That is, the doping concentration is equal throughout the p-region and n-region. In this embodiment, the lateral pn junction buried layer 10 can be a homojunction structure or a heterojunction structure.

[0032] In another specific embodiment, the doping concentrations of the p-regions and n-regions in the lateral pn junction buried layer 10 gradually increase from the side closer to the source to the side closer to the drain. Specifically, for each n-region, the doping concentration gradually increases from the side closer to the source to the side closer to the drain, with an overall doping concentration of 1e15~1e20 cm⁻¹. - The doping concentration varies within the range of ³; similarly, for each p-region, the doping concentration gradually increases from the side closer to the source to the side closer to the drain, with the overall doping concentration ranging from 1e15 to 1e20 cm⁻¹. - Variations within the range of ³.

[0033] Furthermore, the p-region and n-region have the same thickness. In one specific embodiment, the thickness of the p-region and n-region is less than the thickness of the channel layer 3. In another specific embodiment, the thickness of the p-region and n-region can be greater than or equal to the thickness of the channel layer 3, thereby contacting the upper surface of the buffer layer 2, such as... Figure 3 As shown, the p-region and the n-region can have the same or different widths.

[0034] See also Figure 1 The upper end of the gate 9 includes a field plate structure extending towards the drain 7. The gate 9 can be one of a Schottky contact P-GaN gate, an ohmic contact P-GaN gate, a recessed gate, a MIS gate, or other complex gate structures with gate characteristics. The gate 9 may also not include a field plate structure. Similarly, the source 6 and drain 7 may or may not include field plate structures. Preferably, the source 6 and drain 7 are ohmic contact electrodes, and the gate 9 is a Schottky contact electrode.

[0035] In this embodiment, the introduced lateral pn junction buried layer 10 can provide an accelerated path for carrier transport, modulate the electric field strength near the drain, reduce the collisional ionization rate, and prevent thermal runaway from causing single-event burnout of the device.

[0036] The working principle of the gallium nitride device for accelerating charge collection and resisting single-particle events provided by this invention is described in detail below: In the on state, that is, when a voltage higher than the threshold voltage is applied to the gate. V th When the forward voltage is applied, the depletion effect of the p-GaN cap layer on the barrier layer weakens, and a high-concentration two-dimensional electron gas (2DEG) channel reforms at the AlGaN / GaN heterojunction interface. At this point, electrons are injected from the ohmic contact source and transported laterally through the 2DEG channel to the ohmic contact drain, resulting in a low-resistance conduction state. During this process, the lateral PN junction buried layer below the drain is in a zero-bias or slightly reverse-biased state, which does not significantly affect the 2DEG transport path, ensuring that the device has a low on-resistance.

[0037] In the high-voltage shutdown state, i.e. when the gate voltage is lower than the threshold voltage V th And a high voltage is applied to the drain. V DSAt this time, the depletion effect of the p-GaN cap layer on the barrier layer is enhanced, and the 2DEG channel at the heterojunction interface below the gate is depleted and cut off. In this state, the region where the device mainly bears voltage is located in the 2DEG channel between the gate edge and the drain, and the buffer layer region below it. The lateral pn junction buried layer 10 provided in this invention is reverse-biased in this state, and its built-in electric field modulates the potential distribution in the drain region, thus alleviating the electric field concentration phenomenon at the drain, reducing the local peak electric field, and thereby weakening the severe impact ionization effect caused by the high electric field.

[0038] Under irradiation conditions, heavy ions or high-energy particles, upon incident, generate a large number of electron-hole pairs within the device, especially near the buffer layer and channel, along their incident paths. Under the influence of a high drain electric field, electrons drift towards the drain, while holes move towards the gate and source. Without special control structures, because the hole mobility is significantly lower than the electron mobility, they are more likely to accumulate in the region near the gate or drain under these conditions, leading to a local potential rise and electric field enhancement, which can then trigger avalanche multiplication or even thermal runaway and burnout. In this invention, the lateral pn junction buried layer 10 utilizes its built-in electric field effect to construct an efficient carrier shunting path: the generated holes are rapidly separated and discharged by the PN junction, while electrons are swept towards the drain by the N region and collected by the electrodes. Secondary holes generated by collisional ionization in the drain region are also rapidly extracted under the influence of the built-in electric field of the pn junction, further reducing the accumulation of holes in the high-field region. This active control over the carrier collection path effectively avoids the accumulation of high-concentration space charge and breaks the positive feedback failure chain of electric field enhancement—carrier multiplication—Jörg heat increase.

[0039] In summary, this invention, by introducing a lateral pn junction buried layer in the channel layer below the drain, optimizes the electric field distribution under radiation and high-voltage turn-off conditions and rapidly extracts transient carriers while maintaining the normal conduction characteristics of the device. This reduces the probability of local hot spots from a physical mechanism perspective and significantly improves the high-voltage reliability and resistance to single-event burn-out of the device.

[0040] It should be noted that the lateral pn junction buried layer 10 of the present invention can be used in conjunction with the field plate structure and the optimized buffer layer structure. For example, the gate field plate or drain field plate can first expand and modulate the potential distribution at the electrode edge, thereby reducing the electric field peak near the electrode and suppressing the initiation conditions of collisional ionization and the carrier multiplication process; the lateral pn junction buried layer can further weaken the electric field peak and avoid charge accumulation by rapidly separating and extracting carriers through the built-in electric field; the optimized buffer layer structure is used to improve the transport environment of deep carriers, further reducing the probability of deep charge trapping and avoiding deep charge accumulation and potential distortion. The three can act on the device surface region, the bulk channel region and the deep region of the device on a spatial scale, respectively, and correspond to the initial stage of electric field formation, the charge transport stage under the action of the electric field and the deep charge accumulation stage on a temporal evolution scale, respectively, thereby forming a multi-scale synergistic control mechanism and effectively improving the device's resistance to single-event burn-out.

[0041] Example 2 Based on Example 1, this example provides a method for fabricating a gallium nitride device with accelerated charge collection resistance, such as... Figure 4 As shown, the preparation method includes: S1: A buffer layer 2 and a channel layer 3 are sequentially grown on the upper surface of substrate 1.

[0042] Si, SiC, sapphire, or GaN is selected as substrate 1. The substrate is cleaned to remove surface contaminants, followed by high-temperature annealing to optimize the surface lattice / chemical state and ensure high-quality growth of subsequent epitaxial layers.

[0043] A buffer layer 2 and a channel layer 3 are sequentially grown on the upper surface of substrate 1 using methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hybrid vapor phase epitaxy (HVPE). The buffer layer 2 is used to alleviate lattice mismatch / thermal expansion mismatch between the substrate and the epitaxial layer, improving the quality of the epitaxial layer, such as reducing dislocation density. The channel layer 3 serves as a transport channel for charge carriers (two-dimensional electron gas, 2DEG). In this embodiment, the buffer layer 2 is a GaN buffer layer, and the channel layer 3 is a GaN channel layer.

[0044] S2: A transverse pn junction buried layer 10 is prepared on the upper surface of the channel layer 3 near the drain region.

[0045] Specifically, the PN junction buried layer window is first defined in the preset drain region through photolithography (coating, exposure, and development).

[0046] A PN junction is formed through a two-step ion implantation process: Step 1: A first photolithographic mask structure is fabricated on the upper surface of the channel layer 3 to form the P-region and N-region windows of the lateral pn junction buried layer, defining the spatial distribution area for ion implantation. Step 2: Ion implantation is performed on the channel layer 3 through the first mask, implanting P-type impurities (such as Mg or other acceptor impurities) into the P-region windows to form a P-type buried layer. Step 3: After removing the first mask, a second photolithographic mask structure is fabricated, implanting N-type impurities (such as Si or other donor impurities) into the N-region windows to form an N-type buried layer. If the lateral pn junction buried layer 10 to be fabricated includes multiple pn junctions, all P-regions are implanted simultaneously, and all N-regions are implanted simultaneously. These P-regions and N-regions together constitute the lateral pn junction buried layer 10.

[0047] Subsequently, annealing is performed using a rapid thermal annealing (RTA) process to activate dopant atoms (allowing impurities to enter lattice sites) and repair lattice damage caused by ion implantation, thereby restoring the material's electrical properties. In one specific embodiment, the annealing conditions are: rapid thermal annealing in a protective gas at a temperature of 700-1000°C for 30-90 seconds. The protective gas includes nitrogen and argon.

[0048] In another specific embodiment, the lateral pn junction buried layer 10 can be partially removed by etching, and then selectively regrown in the etched trench using methods such as MOCVD, MBE or HVPE to form the lateral pn junction buried layer 10. The regrown semiconductor material can be one or two of GaN, AlGaN, InGaN, InAlN, Si, and SiC, thereby forming a heterojunction structure.

[0049] S3: A barrier layer 4 and a p-GaN cap layer 8 are sequentially grown on the upper surface of the channel layer 10.

[0050] A barrier layer 4 and a p-GaN cap layer 8 are sequentially grown on the upper surfaces of the channel layer 10 and the lateral pn junction buried layer 10 using methods such as MOCVD, MBE, or HVPE. In this embodiment, the barrier layer 4 is an AlGaN barrier layer, forming a heterojunction with the GaN channel layer 3. A high concentration of 2DEG (carrier source) is induced on the surface of the channel layer through band shift (AlGaN conduction band is lower than GaN). The p-GaN cap layer covers the surface of the barrier layer and is used as a sacrificial layer for subsequent gate processes, such as Schottky contacts or ohmic contacts.

[0051] S4: Etch the p-GaN cap layer 8 in the non-gate region and deposit a passivation layer 5 on the upper surface of the barrier layer not covered by the p-GaN cap layer 8.

[0052] Specifically, processes such as inductively coupled plasma (ICP) etching, plasma etching, reactive ion etching (RIE), or wet etching are used to etch the p-GaN cap layer in the non-gate region.

[0053] Subsequently, a passivation layer 5 was deposited on the upper surface of the barrier layer not covered by the p-GaN cap layer 8 using techniques such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD).

[0054] S5: Remove the passivation layer 5 from the gate region, source region, and drain region.

[0055] Specifically, photolithography and etching processes are used to remove the passivation layer 5 of the preset gate region, source region and drain region to expose the upper surface of the channel layer in the source region; expose the upper surface of the N region in the lateral pn junction buried layer 10 in the drain region; and expose the upper surface of the p-GaN cap layer 8 in the gate region.

[0056] S6: Source metal and drain metal are deposited in the source region and drain region respectively, and rapid thermal annealing is performed to form the source and drain.

[0057] Specifically, source and drain metals are deposited in the source and drain regions respectively using processes such as electron beam evaporation (MBE), magnetron sputtering, pulsed laser deposition (PLD), ALD, LPCVD, or PECVD, followed by rapid thermal annealing to form the source and drain electrodes, both of which are ohmic contact electrodes. Specifically, the annealing temperature is 750–900°C, and the annealing time is 30–90 seconds.

[0058] S7: Deposit gate metal in the gate region on the upper surface of the p-GaN cap layer to form a gate with a field plate structure.

[0059] Specifically, gate metal is deposited and a gate field plate is formed using processes such as MBE, sputtering, PLD, ALD, LPCVD or PECVD to form a Schottky contact.

[0060] The following simulation experiments further illustrate the performance of the gallium nitride device with accelerated charge collection and resistance to single-particle dumping provided in the embodiments of the present invention.

[0061] Simulation content: Using TCAD software, a ruggedized device model including a lateral pn junction buried layer and a typical device model without the lateral pn junction buried layer were established. Except for the lateral pn junction buried layer structure, all other structural parameters were identical between the two models. During the simulation, a doping concentration of 1e18cm was selected for both the p-region and n-region. -3Uniform doping was used. Lattice self-heating, mobility, carrier generation-recombination, collisional ionization, polarization, and heavy ion models were introduced in the simulation. A single particle with a LET of 0.7 pC / μm and a trajectory radius of 0.05 μm was incident perpendicularly from the gate edge near the drain and penetrated the entire device. The device was biased in the off state (Vgs=0).

[0062] Please see Figure 5 and Figure 6 , Figure 5 This is a transient drain current response curve of a device containing a lateral pn junction buried layer provided in an embodiment of the present invention; Figure 6 This is a drain transient current response curve for a typical device model without a lateral pn junction buried layer. From Figure 6 It can be seen that the typical device model without a lateral pn junction buried layer does not experience a current surge at a drain-source voltage of 360V, but the drain current surges at 370V, resulting in single-event burnout. Therefore, the single-event burnout threshold voltage is 360V. Figure 5 It can be seen that the ruggedized device of this invention did not experience a current surge at a drain-source voltage of 480V, but experienced a current surge at 490V, resulting in single-event burn-out; that is, the single-event burn-out threshold voltage is 480V. The ruggedized device proposed in this invention improves resistance to single-event burn-out, providing reliability assurance for high-voltage applications of devices under irradiation environments. The lateral pn junction buried layer of this invention can regulate the drain electric field distribution, suppressing single-event burn-out caused by local heat accumulation and carrier multiplication effect.

[0063] This invention introduces a lateral pn junction buried layer within the channel layer beneath the drain, directly affecting the peak electric field region in the device's off-state. This lateral pn junction buried layer forms a built-in electric field under high-voltage bias, participating in the regulation of the internal electric field distribution, effectively absorbing voltage drops, and alleviating the previously highly concentrated local electric field near the drain. This significantly reduces the drain electric field peak and smooths the internal potential distribution. Compared to traditional structures that rely solely on surface field plates for modulation, this invention provides more direct and sensitive control of the bulk electric field, suppressing impact ionization and avalanche multiplication effects induced by high field strength, and significantly improving the single-particle burn-out threshold of the device under radiation conditions.

[0064] To address the large number of electron-hole pairs generated by the incidence of heavy ions or high-energy particles, this invention utilizes the built-in electric field effect of the pn junction to construct a highly efficient carrier separation and transport channel. Specifically, the buried layer of this lateral pn junction can rapidly collect and export holes generated by secondary collisional ionization near the buffer layer and drain, while simultaneously accelerating electron transport to the drain, effectively preventing the retention and accumulation of high-concentration charges in the drain region. This active control of the carrier collection path blocks the local electric field enhancement mechanism caused by space charge accumulation, reduces transient current peaks, and prevents device failure caused by this.

[0065] Furthermore, the lateral pn junction buried layer enables rapid extraction of additional charge and effectively reduces the transient current after single-particle incident, thus mitigating the Joule heat concentration phenomenon caused by localized high current. Compared to traditional device structures, this invention can reduce the local temperature during device operation and slow down the temperature rise rate, thereby avoiding thermal runaway and significantly improving the long-term reliability and stability of the device under irradiation, high temperature, and high power conditions.

[0066] Furthermore, the lateral pn junction buried layer provided by this invention is achieved through ion implantation and rapid thermal annealing processes, which are fully compatible with existing GaN HEMT standard fabrication processes (such as MOCVD epitaxy, ICP etching, metal deposition, etc.). It does not require the introduction of complex special equipment or significant modifications to the original process flow, making it easy to achieve large-scale production and showing good prospects for industrial applications.

[0067] In the several embodiments provided by this invention, it should be understood that the apparatus and methods disclosed in this invention can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0068] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0069] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A gallium nitride device for accelerating charge collection and resisting single-particle events, characterized in that, From bottom to top, it includes a substrate (1), a buffer layer (2), a channel layer (3), a barrier layer (4), and a passivation layer (5), wherein, The passivation layer (5) has a source electrode (6) and a drain electrode (7) respectively on its left and right sides. The source electrode (6) and the drain electrode (7) extend downward from the upper surface of the passivation layer (5) to the lower surface of the barrier layer (4). The lower surface of the source electrode (6) is in contact with the upper surface of the channel layer (3). A transverse pn junction buried layer (10) is embedded on the upper surface of the channel layer (3) near the drain electrode (7), and the upper surface of the transverse pn junction buried layer (10) is in contact with the lower surface of the drain electrode (7). A p-GaN cap layer (8) is embedded inside the passivation layer (5) between the source (6) and the drain (7). The lower surface of the p-GaN cap layer (8) is in contact with the barrier layer (4). The two sides of the p-GaN cap layer (8) are separated from the source (6) and the drain (7) by the passivation layer (5). A gate (9) is disposed on the upper surface of the p-GaN cap layer (8).

2. The gallium nitride device for accelerating charge collection according to claim 1, characterized in that, The lateral pn junction buried layer (10) includes a p region and an n region arranged in the lateral direction and in contact with each other, the p region and the n region forming a pn junction, and the lower surface of the drain (7) in contact with the upper surface of the n region.

3. The gallium nitride device for accelerating charge collection according to claim 1, characterized in that, The lateral pn junction buried layer (10) includes one or more pn junctions arranged in the lateral direction.

4. The gallium nitride device for accelerating charge collection according to claim 1, characterized in that, The first side of the lateral pn junction buried layer (10) is located below the drain electrode (7), and the second side does not overlap with the vertical projection of the p-GaN cap layer (8); the thickness of the lateral pn junction buried layer (10) is 10~200nm.

5. The gallium nitride device for accelerating charge collection according to claim 2, characterized in that, The doping concentration of the p-region and n-region in the lateral pn junction buried layer (10) is 1e15~1e20 cm⁻¹. -3 The p-region and the n-region are uniformly doped.

6. The gallium nitride device for accelerating charge collection according to claim 2, characterized in that, In the transverse pn junction buried layer (10), the doping concentrations of the p and n regions gradually increase from the side closer to the source to the side closer to the drain.

7. The gallium nitride device for accelerating charge collection according to claim 2, characterized in that, The p region and the n region have the same thickness, and the p region and the n region have different widths.

8. The gallium nitride device for accelerating charge collection according to claim 1, characterized in that, The upper end of the gate (9) includes a field plate structure extending toward the drain (7).

9. The gallium nitride device for accelerating charge collection according to claim 1, characterized in that, The source (6) and the drain (7) are ohmic contact electrodes, and the gate (9) is a Schottky contact electrode.

10. A method for fabricating a gallium nitride device with accelerated charge collection resistance to single-particle interference, characterized in that, The method for preparing the gallium nitride anti-single-particle device according to any one of claims 1 to 9 comprises: S1: A buffer layer and a channel layer are grown sequentially on the upper surface of the substrate; S2: A transverse pn junction buried layer is prepared on the upper surface of the channel layer near the drain region; S3: A barrier layer and a p-GaN cap layer are sequentially grown on the upper surface of the channel layer; S4: Etch the p-GaN cap layer in the non-gate region and deposit a passivation layer on the upper surface of the barrier layer not covered by the p-GaN cap layer; S5: Remove the passivation layer from the gate region, source region, and drain region; S6: Deposit source metal and drain metal in the source region and the drain region respectively, and perform rapid thermal annealing to form source and drain, wherein the source and drain are both ohmic contact electrodes; S7: Deposit gate metal in the gate region on the upper surface of the p-GaN cap layer to form a gate with a field plate structure, wherein the gate is a Schottky contact electrode.

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