A high-heat-dissipation-enhanced GaN-based HEMT epitaxial wafer, device and preparation method thereof

Abstract

The application belongs to the technical field of semiconductor devices, and discloses a high-heat-dissipation-enhanced GaN-based HEMT epitaxial wafer, a device and a preparation method thereof. The epitaxial wafer comprises a diamond substrate, a nitrogen-containing graphene insertion layer, an AlN composite nucleation layer, an AlN dislocation filtering layer, a stress release layer, a semi-insulating GaN transition layer, a GaN channel layer, an AlN insertion layer, a first AlGaN barrier layer and a p-type gate epitaxial layer which are sequentially stacked. The p-type gate epitaxial layer comprises a second AlGaN transition layer, an In isoelectronic-doped GaN layer, an Mg heavily-doped p + GaN layer and an Mg lightly-doped p-GaN layer. The device is prepared from the epitaxial wafer through mesa isolation, p-type gate patterning, gate dielectric deposition, electrode formation and passivation treatment. The application is conducive to improving the nucleation and stress state of diamond-based GaN epitaxy, improving the heat dissipation capacity of the device and enhancing the depletion effect of the p-type gate on the two-dimensional electron gas under the gate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a high heat dissipation enhanced GaN-based HEMT epitaxial wafer, device, and its fabrication method. Background Technology

[0002] GaN materials possess wide bandgap, high critical breakdown electric field, high electron saturation drift velocity, and good high-temperature stability. High electron mobility transistors (HEMTs) based on AlGaN / GaN heterojunctions can form a high-concentration two-dimensional electron gas at the heterojunction interface, thus exhibiting high carrier mobility and low channel resistance, making them valuable for applications in high-frequency, high-voltage, and high-power electronic devices.

[0003] Traditional AlGaN / GaNHEMTs typically utilize polarization effects to form a two-dimensional electron gas at the heterojunction interface. Even with zero gate voltage, a conductive path may still exist in the channel, causing the device to behave normally on. Normally on power devices have limitations in terms of drive and fault protection; therefore, p-type gates, gate trenches, or other channel depletion structures are required to keep the device off at zero gate voltage. p-GaN gate-enhanced HEMTs can deplete the two-dimensional electron gas beneath the gate through the built-in potential generated by the p-type GaN, thus achieving normally off operation.

[0004] However, the doping, activation, and hole transport properties of Mg in GaN are easily affected by factors such as compensation effects, hydrogen passivation, doping distribution, and crystal defects. A single concentration of Mg doped layer cannot simultaneously achieve optimal hole concentration, crystal quality, gate depletion capability, and metal contact performance.

[0005] Furthermore, GaN-based HEMTs generate significant localized heat near the gate and in the channel region under high power density operating conditions. Increased junction temperature can lead to decreased carrier mobility, increased on-resistance, reduced output current, and decreased reliability. The thermal conductivity of commonly used substrates such as silicon, sapphire, and silicon carbide limits heat dissipation to varying degrees.

[0006] Diamond possesses high thermal conductivity, making it suitable as a heat dissipation substrate for high-power GaN devices. However, differences exist between diamond and group III nitrides in terms of lattice structure, thermal expansion properties, and surface nucleation characteristics, making it challenging to directly form high-quality AlN or GaN epitaxial layers on the diamond surface. Furthermore, while introducing an interface layer between diamond and nitrides may improve nucleation and stress conditions, the added interface can also generate thermal boundary resistance. Therefore, a coordinated design is needed for the interface material, nucleation method, stress relief structure, and subsequent epitaxial processes on the diamond surface.

[0007] Therefore, existing technologies still require a GaN-based HEMT epitaxial wafer and device structure that can balance heat dissipation on diamond substrates, nitride epitaxial quality, and enhanced gate depletion capability. Summary of the Invention

[0008] The purpose of this invention is to provide a high heat dissipation enhanced GaN-based HEMT epitaxial wafer, device, and fabrication method thereof, which improves the doping efficiency of Mg in the p-GaN gate, increases the hole concentration and mobility, thereby enhancing the depletion capability of the p-GaN gate for the channel of the enhanced GaN-based HEMT device.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: On one hand, the present invention provides a high heat dissipation enhanced GaN-based HEMT epitaxial wafer, comprising, from bottom to top, a diamond substrate, a nitrogen-containing graphene insertion layer, an AlN composite nucleation layer, an AlN dislocation filtering layer, a stress relief layer, a semi-insulating GaN transition layer, an undoped GaN channel layer, an AlN insertion layer, a first AlGaN barrier layer, and a p-type gate epitaxial layer.

[0010] Nitrogen-containing graphene intercalation layers were grown directly on diamond substrates using a Ga catalyst. The nitrogen in the intercalation layers was introduced into the graphene through the formation of nitrogen-containing gas during graphene growth. These intercalation layers were used to improve the nucleation and adhesion conditions of subsequent AlN materials on the graphene surface.

[0011] The AlN composite nucleation layer comprises a sputtered AlN seed layer and an MOCVD in-situ grown AlN nucleation layer arranged sequentially.

[0012] The AlN dislocation filtering layer comprises a 3DAlN layer and a 2DAlN layer on top of the 3DAlN layer. The 3DAlN layer is preferably grown using a nitrogen-containing precursor pulse supply method, and the 2DAlN layer is preferably formed using a continuous planar growth method.

[0013] Stress relief layer includes AlN / Al X Ga 1-X N superlattice layer and Al Y Ga 1-Y N-component graded layer, where x and y represent the corresponding Al molar composition in AlGaN material, and 0 < x < 1, 0 < y < 1.

[0014] The semi-insulating GaN transition layer comprises alternating layers of Fe-doped GaN and undoped GaN. One alternating doping cycle consists of one Fe-doped GaN layer and one undoped GaN layer.

[0015] Preferably, the alternating doping period is 10 to 30, and the thickness of the Fe-doped GaN layer in each period is 4 to 6 nm, while the thickness of the undoped GaN layer is 1 to 3 nm.

[0016] Preferably, the Fe doping source is ferrocene.

[0017] An undoped GaN channel layer, an AlN insertion layer, and a first AlGaN barrier layer together constitute an electron channel epitaxial structure. The chemical formula of the first AlGaN barrier layer can be represented as Al Z Ga 1-Z N, where 0 < z < 1.

[0018] Preferably, the thickness of the undoped GaN channel layer is 100–1000 nm; the thickness of the AlN insertion layer is 0.5–1.5 nm; the thickness of the first AlGaN barrier layer is 10–200 nm; and the Al molar composition Z is 10%–25%.

[0019] The p-type gate epitaxial layer, from bottom to top, includes a second AlGaN transition layer, an In isoelectronically doped GaN layer, and a first Mg heavily doped p-type gate epitaxial layer. + -GaN layer, Mg lightly doped p-GaN layer and optional second Mg heavily doped p-GaN layer + -GaN ohmic contact layer.

[0020] The chemical formula of the second AlGaN transition layer can be represented as Al m Ga 1-m N, where 0 < m < 1.

[0021] Preferably, the thickness of the second AlGaN transition layer is 5–200 nm, and the Al molar composition m is 25%–40%.

[0022] Preferably, the thickness of the In isoelectronic doped GaN layer is 1–200 nm, and the In doping amount is 0.5%–5%.

[0023] Preferably, the first Mg heavy doping p + The thickness of the GaN layer is 1–200 nm, and the Mg doping content is 0.1%–6%.

[0024] Preferably, the thickness of the lightly Mg-doped p-GaN layer is 1–200 nm, and the Mg doping amount is 0.1%–2%.

[0025] Preferably, the second Mg heavy doping p + - The Mg doping concentration of the GaN ohmic contact layer is higher than that of the Mg doping concentration of the Mg lightly doped p-GaN layer.

[0026] On the other hand, the present invention provides a GaN-based HEMT device with enhanced heat dissipation, formed by the above-mentioned epitaxial wafer, including a mesa active region, a p-type gate structure located in the gate region, a gate dielectric layer, a source, a drain, a gate, a passivation layer, and a metal pad.

[0027] The p-type gate structure is formed by patterning a p-type gate epitaxial layer in an epitaxial wafer, and retains at least a first Mg-doped p-type gate in the gate region. + -GaN layer and Mg lightly doped p-GaN layer.

[0028] Setting a second Mg heavy doping p + In the case of a GaN ohmic contact layer, a second Mg-doped p + - The GaN ohmic contact layer is retained at least in the gate metal contact region.

[0029] The gate dielectric layer at least covers the upper surface of the p-type gate structure and may further cover the sidewalls of the p-type gate structure and the exposed surface between the source and drain.

[0030] The gate dielectric layer includes HfZrO X , HfO2, ZrO2, Al2O3, SiO2, SiN X At least one of them, preferably HfZrO X High dielectric constant materials.

[0031] The thickness of the gate dielectric layer is preferably 10–200 nm.

[0032] The source and drain are respectively located in the source contact region and the drain contact region.

[0033] The metal stack used for the source and drain can be selected from one of Ni / Ti / Ni / Au, Ni / Au, Ti / Au, Ni / Ti / Cu / Au, and Ti / Al / Ti / Au.

[0034] The metal stack used for the gate can be selected from Ti / Au, W / Au, and Mo / Au.

[0035] The passivation layer includes SiN X It contains at least one of SiO2 and Al2O3, and the thickness is preferably 10 to 200 nm.

[0036] The metal pads can be Au / Sn metal pads.

[0037] Thirdly, the present invention provides a method for preparing epitaxial wafers, comprising the following steps.

[0038] Surface treatment is performed on the diamond substrate.

[0039] Metallic Ga catalysts are loaded onto the surface of a diamond substrate.

[0040] A diamond substrate loaded with a Ga catalyst was placed in a chemical vapor deposition apparatus, and carbon-containing and nitrogen-containing gases were introduced to grow a nitrogen-containing graphene intercalation layer under the action of the Ga catalyst.

[0041] A sputtered AlN seed layer and an in-situ MOCVD-grown AlN nucleation layer were formed on a nitrogen-containing graphene insertion layer.

[0042] An AlN dislocation filtering layer comprising 3DAlN and 2DAlN layers is formed on the AlN nucleation layer.

[0043] AlN / Al is formed on the AlN dislocation filter layer. X Ga 1-X N superlattice layer and AlYGa1-YN composition gradient layer.

[0044] Fe-doped GaN layers and undoped GaN layers are alternately grown on the stress-relief layer to form a semi-insulating GaN transition layer.

[0045] An undoped GaN channel layer, an AlN insertion layer, and a first AlGaN barrier layer are sequentially formed on a semi-insulating GaN transition layer.

[0046] A second AlGaN transition layer, an In isoelectronically doped GaN layer, and a first Mg heavily doped p-layer are sequentially formed on the first AlGaN barrier layer. + -GaN layer, Mg lightly doped p-GaN layer and optional second Mg heavily doped p-GaN layer + -GaN ohmic contact layer.

[0047] Acceptor activation treatment was performed on the Mg-doped GaN layer to obtain a GaN-based HEMT epitaxial wafer with high heat dissipation enhancement.

[0048] Fourthly, the present invention also provides a method for fabricating a HEMT device, comprising the following steps.

[0049] The epitaxial wafer is then surface-cleaned. Photolithography and etching are then performed on the epitaxial wafer to form the mesa active region and device isolation structure.

[0050] The p-type gate epitaxial layer is patterned to form a locally retained p-type gate structure in the gate region. Each epitaxial layer constituting the p-type gate epitaxial layer is retained in the gate region, and the p-type gate epitaxial layer is removed in the non-gate region to form the source region contact region and the drain region contact region.

[0051] The gate dielectric layer is patterned to form the source contact window, drain contact window, and gate contact region.

[0052] The source, drain, and gate are formed separately, and appropriate metal contact annealing is performed according to the selected metal system.

[0053] A passivation layer is formed on the surface of the device.

[0054] The passivation layer is patterned and metal pads are formed to obtain a GaN-based HEMT device with high heat dissipation enhancement.

[0055] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention uses diamond as the carrier substrate and heat dissipation substrate of the epitaxial wafer, which is beneficial to transfer the heat generated in the GaN channel region to the substrate.

[0056] 2. Inserting a nitrogen-containing graphene intercalation layer between the diamond and AlN epitaxial structures is beneficial for regulating the interfacial nucleation state between diamond and nitride materials. Removing the Ga catalyst after graphene growth can reduce the impact of residual Ga on subsequent high-temperature epitaxial processes and interfacial stability.

[0057] 3. The use of sputtered AlN seed layer, in-situ AlN nucleation layer, 3D / 2D AlN dislocation filter layer, AlN / AlGaN superlattice layer and compositionally graded AlGaN layer is beneficial to promote nitride material nucleation, epitaxial layer fusion and stress release.

[0058] 4. The method of alternating growth of Fe-doped GaN layers and undoped GaN layers is beneficial to adjusting the spatial distribution of Fe in the semi-insulating GaN transition layer and reducing the adverse effects of continuous high-concentration Fe doping on crystal quality.

[0059] 5. The p-type gate epitaxial structure, which combines In iso-doped GaN layers with Mg heavy doping and Mg light doping, is beneficial for adjusting the carrier performance, gate depletion capability, and metal contact performance of the p-type layer respectively.

[0060] 6. Retaining the p-type gate structure in the gate region can enhance the depletion effect on the two-dimensional electron gas below the gate, making the device suitable for achieving an enhanced operating state with zero gate bias turn-off. Attached Figure Description

[0061] Figure 1 This application provides a flowchart of a method for preparing the first region of the substrate; Figure 2 A schematic diagram of the epitaxial structure of the enhanced GaN-based HMET wafer for improved heat dissipation provided in this application; Figure 3 This is a flowchart illustrating the fabrication process of an enhanced HMET device based on an enhanced GaN-based HMET wafer with improved heat dissipation, provided as an example.

[0062] Figure 4 The simulation model diagrams and corresponding heat dissipation simulation results are shown for Al(Ga)N epitaxial layers grown on graphene / single-crystal diamond substrates (a), single-crystal silicon substrates (b), and single-crystal silicon carbide substrates (c).

[0063] Figure Labels 10. Substrate structure; 101. Diamond substrate; 102. Metallic Ga catalyst; 103. Nitrogen-containing graphene insertion layer; 104. Sputtered AlN seed layer; 105. In-situ grown AlN nucleation layer; 106. AlN dislocation filtering layer; 106-A, 3D AlN layer; 106-B, 2D AlN layer; 107. AlN / Al X Ga 1-X N superlattice layer; 108, Al Y Ga 1-Y N-component graded layer; 20. Semi-insulating GaN transition layer; 201. Fe-doped GaN layer; 202. Undoped GaN layer; 30. Channel epitaxial structure; 301. Undoped GaN channel layer; 302. AlN insertion layer; 303. First AlGaN barrier layer; 40. p-type gate epitaxial layer; 401. Second AlGaN transition layer; 402. In isoelectronic doped GaN layer; 403. First Mg heavily doped p-type gate epitaxial layer. + -GaN layer; 404, Mg lightly doped p-GaN layer; 405, second Mg heavily doped p-GaN layer + -GaN ohmic contact layer; 501, Gate dielectric layer; 502, Source; 503, Drain; 504, Gate; 505, Passivation layer; 506, Metal pad; 507, Isolation trench. Detailed Implementation

[0064] To enable those skilled in the art to better understand the present application, the technical solutions in specific embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by those skilled in the art.

[0065] Unless otherwise specified, "undoped" or "unintentionally doped" in this invention means that no corresponding conductive doping source was actively introduced during the epitaxial growth process, but does not exclude background impurities introduced by raw materials, equipment or growth environment.

[0066] In this invention, "heavily doped" and "lightly doped" refer to the relative doping relationship between different layers in the same p-type gate epitaxial structure. The effective Mg doping concentration in the heavily doped layer is higher than that in the lightly doped layer; the specific concentration range and testing methods are described in the corresponding embodiments.

[0067] The "nitrogen-containing graphene" of this invention refers to graphene materials that contain nitrogen elements that can be detected through material characterization in the graphene lattice, defect sites, or surface functional sites.

[0068] Example 1 This embodiment provides a method for fabricating a GaN-based HEMT epitaxial wafer with enhanced heat dissipation, comprising the following steps.

[0069] Diamond substrate pretreatment: A single-crystal diamond substrate 101 with a crystal orientation of (111), a size of 25 / 50 mm, and a thickness of 2 mm was selected.

[0070] The diamond substrate 101 was sequentially cleaned with a 1:1 molar ratio of ethanol / acetone mixed organic solvent and deionized water to remove surface organic contaminants, particles, and oxidation residues. After cleaning, it was dried at 200°C for 30 minutes in air.

[0071] Formation of Ga metal catalysts: A Ga oxide precursor layer is formed on the surface of a diamond substrate 101. In this embodiment, an atomic layer deposition process is used to form the Ga oxide precursor layer, and the precursor layer thickness is 2 nm. The diamond substrate with the Ga oxide precursor layer is placed in a reaction chamber and treated at 850 °C for 60 min at a flow rate of 450 sccm in an atmosphere with an H2 / inert gas ratio of 1:1, to reduce the Ga oxide and form a metallic Ga catalyst 102. The resulting metallic Ga catalyst 102 has an average particle size of ≤10 nm and a surface coverage of 99%.

[0072] Metallic Ga catalysts can also be obtained by direct deposition of metallic Ga, decomposition of organometallic precursors, or other methods that can form Ga catalytic sites on the diamond surface.

[0073] Growth of nitrogen-containing graphene intercalation layers: A diamond substrate 101 loaded with a metallic Ga catalyst 102 is placed inside a CVD reaction chamber.

[0074] The basic pressure of the reaction chamber is ≤5×10 -7 mbar, graphene growth pressure ≤5×10 -7 mbar, with a growth temperature of 1000℃.

[0075] Methane, NH3, and a carrier gas are introduced into the reaction chamber. The flow rate of the carbon-containing gas is 20 sccm, the flow rate of NH3 is 150 sccm, the carrier gas is H2, the flow rate of the carrier gas is 800 sccm, and the reaction time is 200 min.

[0076] Under the action of the Ga catalyst 102, the carbon-containing gas decomposes and forms a nitrogen-containing graphene intercalation layer 103 on the surface of the diamond substrate 101.

[0077] Formation of AlN composite nucleation layer: An AlN seed layer 104 was formed on a nitrogen-containing graphene intercalation layer 103 using magnetron sputtering. The sputtering target was 5N pure aluminum, and the sputtering gas was an N2 / Ar mixture (Ar:N2=1:3) at a working pressure of 1.5×10⁻⁶. -5 The sputtering parameters were: Pa, sputtering power: 5500 W, substrate temperature: 650 °C, sputtering time: 5 min. The resulting sputtered AlN seed layer 104 had a thickness of 30 nm.

[0078] The sample was then transferred to the MOCVD reaction chamber, where an in-situ AlN nucleation layer 105 was formed on the sputtered AlN seed layer 104.

[0079] The Al source was Al(CH3)3, the N source was NH3, and the carrier gas was H2. The growth temperature was 1200℃, the growth pressure was 67 mbar, the V / III ratio was 800, and the growth time was 10 min. The thickness of the resulting in-situ grown AlN nucleation layer 105 was 25 nm.

[0080] Formation of AlN dislocation filtering layer: A 3D AlN layer 106-A was formed on the in-situ grown AlN nucleation layer 105 using a pulsed NH3 supply method. One NH3 pulse cycle consisted of 6 seconds of NH3 introduction followed by 10 seconds of stopping or reducing the NH3 supply, and the number of pulse cycles was 25.

[0081] The 3D AlN layer 106-A was grown at a temperature of 1200℃, a growth pressure of 67mbar, and a thickness of 300nm.

[0082] Subsequently, the growth temperature, pressure, and V / III ratio were adjusted to transform AlN from island-like growth to planar merging growth, forming a 2D AlN layer 106-B on the 3D AlN layer 106-A.

[0083] The 2D AlN layer 106-B was grown at a temperature of 1200℃, a growth pressure of 67 mbar, a V / Ⅲ ratio of 20, and a thickness of 1000 nm.

[0084] The 3D AlN layer 106-A and the 2D AlN layer 106-B together form the AlN dislocation filtering layer 106. Formation of the stress relief layer: AlN / Al was formed on a 2D AlN layer 106-B. X Ga 1-X N superlattice layer 107. AlN / Al X Ga 1-X The N superlattice layer 107 comprises 100 periods, each period consisting of a 1 nm thick AlN sublayer and a 1 nm thick Al... X Ga 1-X N sublayer. Al X Ga 1-X The Al molar composition X in the N sublayer is 0.8.

[0085] Subsequently in AlN / Al X Ga 1-X Al is formed on the N superlattice layer 107 Y Ga 1-Y N-component graded layer 108. Al Y Ga 1-Y The thickness of the N-component graded layer 108 is 300 nm, and the Al molar composition Y gradually changes from 0.7 near the superlattice layer to 0.3 away from the superlattice layer.

[0086] Formation of the semi-insulating GaN transition layer: In Al Y Ga 1-Y Fe-doped GaN layers 201 and undoped GaN layers 202 are alternately grown on an N-component graded layer 108. The Fe doping source is ferrocene, the Ga source is Ga(CH3)3, and the N source is NH3.

[0087] One alternating doping cycle consists of a 4 nm thick Fe-doped GaN layer 201 and a 2 nm thick undoped GaN layer 202. There are 30 alternating doping cycles. The Fe concentration in the Fe-doped GaN layer 201 is 5 × 10⁻⁶. 18 cm -3 The total thickness of the semi-insulating GaN transition layer 20 is 180 nm.

[0088] Formation of channel extension structures: An undoped GaN channel layer 301 with a thickness of 800 nm is grown on the semi-insulating GaN transition layer 20. An AlN insertion layer 302 with a thickness of 1 nm is grown on the undoped GaN channel layer 301.

[0089] A first AlGaN barrier layer 303 is grown on the AlN insertion layer 302. The thickness of the first AlGaN barrier layer 303 is 10 nm, and the Al molar composition Z is 25%.

[0090] Formation of the p-type gate epitaxial layer: A second AlGaN transition layer 401 with a thickness of 5 nm and an Al molar composition m of 40% is formed on the first AlGaN barrier layer 303.

[0091] An In isoelectronically doped GaN layer 402 is formed on the second AlGaN transition layer 401.

[0092] The thickness of the In isoelectronic doped GaN layer 402 is 5 nm, and the In solid phase atom concentration is 1.5%.

[0093] Subsequently, the first Mg-doped p-type plants were grown sequentially. + -GaN layer 403, Mg lightly doped p-GaN layer 404 and second Mg heavily doped p-GaN layer 404 + -GaN ohmic contact layer 405.

[0094] First Mg heavily doped p + The GaN 403 layer is 20 nm thick, and the Mg concentration is 5 × 10⁻⁶. 19 cm -3 .

[0095] The thickness of the Mg-lightly doped p-GaN 404 layer is 20 nm, and the Mg concentration is 6.5 × 10⁻⁶. 18 cm -3 .

[0096] Second Mg heavy doping p + The GaN ohmic contact layer 405 has a thickness of 20 nm and a Mg concentration of 8 × 10⁻⁶. 19 cm -3 .

[0097] First Mg heavily doped p + -GaN layer 403 and second Mg heavily doped p + The Mg concentration in the GaN ohmic contact layer 405 is higher than that in the Mg-lightly doped p-GaN layer 404.

[0098] Mg acceptor activation: After epitaxial growth is completed, acceptor activation treatment is performed on the Mg-doped GaN layer.

[0099] The activation process was carried out in an N2 atmosphere at an activation temperature of 650℃ for 30 minutes. This yielded a GaN-based HEMT epitaxial wafer with enhanced heat dissipation.

[0100] Example 2 This embodiment provides a fabrication method for a GaN-based HEMT device with enhanced heat dissipation, comprising the following steps: Wafer cleaning: Take the epitaxial wafer obtained in Example 1 and clean it in a mixed cleaning solution of hydrochloric acid and hydrogen peroxide.

[0101] The hydrochloric acid concentration was 37%, the volume ratio of hydrochloric acid to hydrogen peroxide was 3:1, the cleaning temperature was 25℃, and the cleaning time was 20 minutes. After cleaning, the sample was rinsed with deionized water and dried with nitrogen gas.

[0102] Countertop isolation: Photoresist is coated on the surface of the epitaxial wafer, and a mesa isolation pattern is formed after exposure and development. ICP dry etching is used to form isolation trench 507 with an etching depth of 600 nm. The etching terminates at the undoped GaN channel layer 301.

[0103] Patterning of p-type gate structure: Photoresist is recoated to form a p-type gate structure pattern. ICP dry etching is used to remove the p-type gate epitaxial layer in the non-gate region, leaving the gate region consisting of a second AlGaN transition layer, an isoelectronically doped In GaN layer, and a first heavily doped Mg p-type gate structure. + -GaN layer, Mg lightly doped p-GaN layer and second Mg heavily doped p-GaN layer + - A p-type gate structure composed of a GaN ohmic contact layer.

[0104] The etching gas is a BCl3 / SF6 mixture (BCl3:SF6=7:3), the ICP power is 550W, the bias power is 70W, and the chamber pressure is 6.67Pa.

[0105] After etching, surface damage is repaired or wet treatment is performed by annealing at 800℃ in a mixed atmosphere of NH3 / N2.

[0106] Gate dielectric layer formation: A gate dielectric layer 501 is formed on the device surface using atomic layer deposition.

[0107] This embodiment uses HfZrO X As the gate dielectric material, the deposition temperature is 250℃, the atomic ratio of Hf to Zr is 1:1, and the thickness of the gate dielectric layer is 20nm.

[0108] The gate dielectric layer 501 covers at least the upper surface and sidewalls of the p-type gate structure.

[0109] Source and drain formation: The gate dielectric layer 501 is patterned to form source contact windows and drain contact windows.

[0110] The source electrode 502 and the drain electrode 503 are formed by metal evaporation or atomic layer deposition.

[0111] The source 502 and drain 503 are made of Ni / Au metal stack, with the thickness of each metal layer being 25 (Ni) nm and 50 (Au) nm, respectively.

[0112] After metal deposition, the metal is annealed at 550°C for 60 seconds in an Ar atmosphere to form source-drain ohmic contacts.

[0113] Gate formation: A gate metal contact window is formed above the p-type gate structure, and gate 504 is deposited.

[0114] The gate 504 uses a Ti / Au metal stack with thicknesses of 50 (Ti) and 100 (Au) nm for each metal layer.

[0115] The gate length is 1μm, the gate-source pitch is 0.7μm, and the gate-drain pitch is 20μm.

[0116] Passivation layer and pad formation: A passivation layer 505 is deposited on the device surface. The passivation layer 505 is made of SiO2, deposited by PECVD, and has a thickness of 80 nm.

[0117] The passivation layer 505 is photolithographically and etched to form pad openings. Au / Sn metal pads 506 are deposited in the pad opening region, with Au layer and Sn layer thicknesses of 200 nm and 400 nm, respectively.

[0118] This results in a GaN-based HEMT device with enhanced heat dissipation.

[0119] Example 3 This embodiment provides a heat dissipation simulation experiment for a GaN-based HEMT device with enhanced heat dissipation, and the specific analysis is as follows: Figure 4 This paper presents schematic diagrams of simulation models of Al(Ga)N epitaxial layers grown on different substrates, along with corresponding heat dissipation simulation results. This embodiment provides a heat dissipation simulation experiment of Al(Ga)N epitaxial layers grown on single-crystal silicon substrates and single-crystal silicon carbide substrates for comparison. The substrate size used in the simulation experiment is 80×40µm. 2 The thickness of the graphene layer is 30µm; the thickness of the graphene layer is 100nm; the AlN layer is a buffer layer with a thickness of 1µm; the GaN layer is a heat source with a thickness of 100nm and a heat dissipation rate of 0.6W; the reference thermal conductivity of each component and the interfacial thermal conductivity are shown in the figure.

[0120] in, Figure 4(a) Simulation models of Al(Ga)N epitaxial layers grown on graphene / diamond substrates and heat dissipation simulation results are shown. As shown in the figure, according to the simulation results, the highest temperature of the GaN layer grown on the graphene / diamond substrate and AlN buffer layer is 24.35℃ (GaN surface temperature), and the average temperature of the epitaxial layer and substrate is 22.08℃. In contrast, the surface temperature of the GaN layer grown on a single-crystal silicon substrate and AlN buffer layer is 59.20℃, and the average temperature of the epitaxial layer and substrate is 40.24℃. Figure 4 As shown in (b); the surface temperature of the GaN layer grown on the single-crystal silicon carbide substrate and AlN buffer layer is 33.69℃, and the average temperature of the epitaxial layer and substrate is 27.06℃. Figure 4 As shown in (c), the simulation results fully demonstrate that the graphene / diamond substrate provided by this patent is significantly superior to existing single-crystal silicon substrates and single-crystal silicon carbide substrates in terms of device heat dissipation.

[0121] Finally, it should be noted that the described embodiments are merely some, not all, of the embodiments of the present invention. Those skilled in the art will understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the claims and their equivalents; that is, all other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A GaN-based HEMT epitaxial wafer with enhanced heat dissipation, characterized in that, It includes a diamond substrate, a nitrogen-containing graphene insertion layer, an AlN composite nucleation layer, an AlN dislocation filtering layer, a stress relief layer, a semi-insulating GaN transition layer, a GaN channel layer, an AlN insertion layer, a first AlGaN barrier layer, and a p-type gate epitaxial layer, which are stacked sequentially from bottom to top. The p-type gate epitaxial layer, from bottom to top, includes a second AlGaN transition layer, an In isoelectronically doped GaN layer, and a Mg-heavily doped p-type gate epitaxial layer. + -GaN layer and Mg lightly doped p-GaN layer.

2. The high heat dissipation enhanced GaN-based HEMT epitaxial wafer according to claim 1, characterized in that, The AlN composite nucleation layer includes a sputtered AlN seed layer and an MOCVD in-situ grown AlN nucleation layer; the AlN dislocation filtering layer includes a 3D AlN layer and a 2D AlN layer disposed on the 3D AlN layer; the stress relief layer includes AlN / Al X Ga 1-X N superlattice layer and Al Y Ga 1-Y N-component graded layer.

3. The high heat dissipation enhanced GaN-based HEMT epitaxial wafer according to claim 1, characterized in that, The semi-insulating GaN transition layer comprises alternating Fe-doped GaN layers and undoped GaN layers, with an alternating growth cycle of 10 to 30. In each cycle, the thickness of the Fe-doped GaN layer is 4 to 6 nm, and the thickness of the undoped GaN layer is 1 to 3 nm.

4. The high heat dissipation enhanced GaN-based HEMT epitaxial wafer according to claim 1, characterized in that, The p-type gate epitaxial layer also includes a Mg-heavily doped p-type gate layer disposed on a lightly doped Mg p-GaN layer. + -GaN ohmic contact layer, Mg heavily doped p + -GaN layer and Mg heavily doped p + The Mg doping concentration of the GaN ohmic contact layer is higher than that of the Mg doping concentration of the lightly Mg-doped p-GaN layer.

5. A GaN-based HEMT device with enhanced heat dissipation, characterized in that, It includes a mesa active region formed by epitaxial wafer processing according to any one of claims 1 to 4, a p-type gate structure disposed in the gate region, a gate dielectric layer, a source, a drain and a gate; The gate dielectric layer at least covers the p-type gate structure, the gate is disposed above the p-type gate structure, the source and drain are disposed in the source contact region and the drain contact region, respectively, and a passivation layer and metal pads are also disposed on the device surface.

6. A method for fabricating a high heat dissipation enhanced GaN-based HEMT epitaxial wafer, characterized in that, include: A metallic Ga catalyst is placed on the surface of a diamond substrate, and nitrogen-containing graphene is catalytically grown in an atmosphere containing carbon and nitrogen gases to form a nitrogen-containing graphene intercalation layer. An AlN composite nucleation layer, an AlN dislocation filtering layer, and a stress relief layer are sequentially formed on a nitrogen-containing graphene insertion layer. A semi-insulating GaN transition layer, a GaN channel layer, an AlN insertion layer, and a first AlGaN barrier layer are sequentially epitaxially grown on the stress relief layer. as well as A second AlGaN transition layer, an In isoelectronically doped GaN layer, and a Mg heavily doped p-layer are sequentially epitaxially grown on the first AlGaN barrier layer. + An epitaxial wafer is obtained by adding a GaN layer and a lightly doped Mg p-GaN layer.

7. The preparation method according to claim 6, characterized in that, The Ga metal catalyst is formed by the gas-phase reduction of metal oxides. The carbon-containing gas includes at least one of short-chain alkanes, short-chain alkenes, and short-chain alkynes, and the nitrogen-containing gas includes NH3.

8. The preparation method according to claim 6, characterized in that, The formation of the AlN composite nucleation layer, AlN dislocation filtering layer, and stress relief layer includes: An AlN seed layer was formed on a nitrogen-containing graphene insertion layer using magnetron sputtering; MOCVD was used to form an in-situ grown AlN nucleation layer on an AlN seed layer; A 3DAlN layer was formed using an NH3 pulse growth method, and a 2DAlN layer was formed on top of the 3DAlN layer; and AlN / Al are formed sequentially X Ga 1-X N superlattice layer and Al Y Ga 1-Y N-component graded layer.

9. The preparation method according to claim 6, characterized in that, The semi-insulating GaN transition layer is formed by alternating growth of Fe-doped GaN layers and undoped GaN layers; the p-type gate epitaxial layer also includes a Mg-doped p-type gate epitaxial layer grown on a lightly Mg-doped p-GaN layer. + -GaN ohmic contact layer, and acceptor activation treatment is performed on each Mg-doped GaN layer.

10. A method for fabricating a high heat dissipation enhanced GaN-based HEMT device, characterized in that, include: Provide an epitaxial wafer according to any one of claims 1 to 4; Mesa isolation is applied to the epitaxial wafer; The p-type gate epitaxial layer is patterned to form a locally preserved p-type gate structure, source contact region, and drain contact region; A gate dielectric layer is formed that at least covers the p-type gate structure; The source, drain, and gate are formed respectively above the source contact region, the drain contact region, and the p-type gate structure; And to form a passivation layer and metal pads.

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