Semiconductor transistor device and method of manufacturing the same
Patent Information
- Application Number
- CN202610428087.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-04-03
- Filing Date
- 2026-04-02
- Publication Date
- 2026-10-16
Smart Images
Figure CN122934860A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to semiconductor transistor devices and methods for manufacturing semiconductor transistor devices. Background Technology
[0002] A semiconductor transistor device may include a semiconductor body on which an insulating layer and metallization may be disposed. Metallization may, for example, allow wiring of the device structure within the semiconductor body. The insulating layer may define one or more contact holes, where electrical contacts are formed, for example, between the metallization and the semiconductor body. Summary of the Invention
[0003] The embodiments of this application are intended to provide an advantageous semiconductor transistor device.
[0004] In one embodiment, a semiconductor transistor device includes a semiconductor body, an insulating layer on a first side of the semiconductor body, and metallization on the insulating layer. The metallization includes a barrier layer and an upper layer disposed on the barrier layer. Referring to the lateral width w of a contact hole intersecting the insulating layer, the barrier layer has a thickness t, wherein the thickness t is at least half the width w of the contact hole, t ≥ w / 2. This means that the barrier layer can be selected to have a minimum thickness that depends on the width of the contact hole, i.e., increases with increasing contact hole width.
[0005] Ensuring a minimum thickness for the barrier layer is advantageous, for example, for filling contact holes, allowing them to be completely filled by the barrier layer. This reduces the morphology on the upper side or surface of the barrier layer, which in turn reduces the risk of voids or pinholes forming in the subsequently deposited metallized overlayer. In other words, providing a thickness t ≥ w / 2 helps or ensures that the barrier layer grows together and fills the contact holes.
[0006] Further embodiments and features are provided in the claims and throughout this disclosure. While each feature is disclosed independently of a particular class of claims, this disclosure relates to apparatus and devices, but also to methods and uses. If, for example, an apparatus is described as being manufactured in a particular manner, this also discloses the corresponding manufacturing process, and vice versa. In general, embodiments of this application are intended to fill contact holes in an insulating layer with a barrier layer, the thickness of which is at least half the width of the contact hole.
[0007] An insulating layer can be disposed on a first side of the semiconductor body, which may also be referred to as the "front side". A contact hole intersects the insulating layer, forming a via. In other words, the contact hole can extend along the entire path between the upper surface of the insulating layer and its perpendicularly opposite lower surface. The vertical direction can extend substantially perpendicular to the lateral direction; for example, the semiconductor body's vertical extension is less than its lateral extension. Laterally, the area of the semiconductor body or die can be taken.
[0008] The width w of the contact hole can be obtained in the lateral direction, where the contact hole has its minimum lateral extension. This lateral direction can also be referred to as the "transverse direction". In the lateral direction perpendicular to the transverse direction, the contact hole can, for example, have an elongated extension, and this direction can be referred to as the "length direction". Consider a device structure formed in a semiconductor body and comprising multiple device units, which can, for example, have translational symmetry with respect to the transverse direction.
[0009] Specifically, the lateral width w can be taken at a vertical position between the lower and upper ends of the contact hole, for example, at half the height of the contact hole. In other words, the width w can be obtained at half the thickness of the insulation layer.
[0010] Generally, when referring to an arrangement of one layer or entity "on" another layer or entity, such as an insulating layer on a semiconductor body and / or a metallization on an insulating layer, this does not necessarily mean an arrangement directly adjacent to that layer or entity. In other words, an additional layer can be arranged between an insulating layer and the semiconductor body and / or between a metallization and an insulating layer. This additional layer can, for example, serve as an adhesion promoter and / or an etch stop layer. It can have a thickness of, for example, no more than 30 nanometers, 20 nanometers, 15 nanometers, or 6 nanometers, with a possible lower limit of, for example, 3 nanometers. To summarize, an arrangement "on" can mean a distance, such as a relatively small distance of no more than 100 nanometers, 50 nanometers, 30 nanometers, 20 nanometers, 15 nanometers, or 6 nanometers, or an arrangement "directly on".
[0011] The barrier layer may include one or more sublayers, each sublayer including at least one of, for example, Ti, W, or N. Conversely, the upper layer may include, for example, aluminum and / or copper, as discussed in further detail below. The thickness t of the barrier layer may be obtained in the vertical direction, for example, on the insulating layer, i.e., next to the contact hole. In other words, the thickness t may be obtained from the upper surface of the insulating layer to the upper surface of the barrier layer and / or to the lower surface of the upper metallization layer (e.g., to the lower surface of the aluminum and / or copper layer).
[0012] When the insulating layer has multiple contact holes, for each contact hole, for example, the standard t ≥ w / 2 can be satisfied. The contact holes can be arranged in a translationally symmetrical manner in the transverse direction, for example, having the same spacing in the semiconductor body, similar to device cells. Using one or more contact holes, the insulating layer can define the contact structure between the metallization and the semiconductor body, for example, serving as an interlayer dielectric. For example, the insulating layer can have a total thickness, with a lower limit of at least 0.1µm, 0.2µm, 0.3µm, or 0.4µm, and an upper limit, for example, at most 3µm, 2µm, or 1.5µm.
[0013] A semiconductor body may include a semiconductor substrate, for example, bonded to one or more epitaxial layers thereon. Embodiments of this application relate to semiconductor bodies made of silicon carbide (SiC). This can, for example, allow for relatively high voltages during the operation of the device or device structure.
[0014] A semiconductor transistor device may include, for example, a first load terminal and a second load terminal, the first load terminal being disposed on a first side of the semiconductor body, and the second load terminal being disposed on a vertically opposite second side of the semiconductor body. The transistor device may be a field-effect transistor (FET), the first load terminal being, for example, a source region, and the second load terminal being a drain region. Furthermore, a body region may be disposed within the semiconductor body, for example, below the source region formed on the first side of the semiconductor body and / or above the drain region formed on the second side of the semiconductor body. Optionally, the transistor device may include a drift region between the body and the drain region, for example, made of the same doping type but with a lower doping concentration than the drain region. Independent of these details, contacts may be disposed, for example, in the active region of the chip or die, such as above the device structure (laterally inward of the edge termination).
[0015] Typically, metallization at the bottom of a contact hole enables electrical contact with a substance embedded in the semiconductor body, such as an electrode made of a conductive material (e.g., polysilicon or metal). However, in one embodiment, metallization enables electrical contact with a region formed within the semiconductor body, such as a doped region. Referring to the transistor device discussed above, metallization can, for example, contact a first load terminal in the contact hole, such as a source region. Optionally or additionally, it can contact an undoped region, such as the device body or a diode region.
[0016] In one embodiment, when viewed from a vertical cross-section, the sidewalls of the contact hole form an angle δ of up to 10° with the vertical direction (which is perpendicular to the transverse orientation, see above). In other words, one or more sidewalls of the contact hole have a relatively steep orientation, which can, for example, reduce the variation between the contact opening width at the bottom and top of the contact hole. This reduction in the width of the contact hole can reduce or prevent a “mountain-shaped” morphology, i.e., achieve a relatively flat morphology that prevents the formation of voids or pinholes.
[0017] In detail, when viewed from a vertical cross-section, angle δ can be considered as the minimum angle between the vertical direction and the sidewall of the contact hole. For example, in the case of curved or convex sidewalls, angle δ can be obtained between the vertical direction and a straight line fitted into the sidewall of the contact hole (as seen in the vertical cross-section, a linear fit). However, in one embodiment, the sidewall forms a straight line when viewed from a vertical cross-section. Independent of these details, the cross-sectional plane can, for example, be parallel to the translational symmetry direction of the device cell and / or parallel to the transverse direction.
[0018] In one embodiment, the width of the contact hole is at least 0.1µm, with a further lower limit of, for example, at least 0.2µm, 0.3µm, 0.4µm, or 0.5µm. The upper limit of the contact hole width can be, for example, up to 10µm, 8µm, 6µm, or 4µm.
[0019] In one embodiment, the upper surface of the barrier layer has a roughness of at least 10 nm, with a further lower limit of, for example, at least 15 nm or 20 nm. In other words, a certain roughness can be permitted, and the upper surface may, for example, not be planarized, e.g., not planarized by chemical mechanical polishing (CMP). Specifically, the roughness can be measured, for example, as an arithmetic mean height (Sa). In cases where the device structure includes elongated trench structures (e.g., elongated gate trenches), the measurement can, for example, be performed parallel to the trench (so as not to capture any possible topography caused by the trench). Independent of these details, the upper limit of the roughness can, for example, be at most 300 nm.
[0020] In one embodiment, the barrier layer fills the contact hole over its entire height. As seen, for example, in a vertical section perpendicular to the sidewalls of the contact hole, the upper surface of the barrier layer is disposed, for example, at or above the upper end of the contact hole. This may be applied over the entire width. In other words, the upper surface of the barrier layer may be disposed above a surface plane containing the upper surface of the insulating layer. As seen in the vertical section, the surface plane may be a straight line perpendicular to the vertical direction, where the straight line is a tangent to the upper surface of the insulating layer.
[0021] In other words, the surface plane is not the actual surface of the insulating layer, but rather a mathematical plane fitted to the upper surface of the insulating layer. Therefore, the surface plane extends across the contact hole and can be used, for example, to describe or measure the fill height, e.g., at the middle of the contact hole (at a mid-lateral position between its sidewalls). In one embodiment, a portion of the barrier layer above the contact hole, e.g., at the central position in the middle, has a thickness of at least 20 nm. h Other lower limits are, for example, at least 50 nm, 80 nm, or 100 nm. For example, the upper limit can be at most 5µm, 4µm, 3µm, or 2µm.
[0022] In one embodiment, the thickness t of the barrier layer, for example taken near a contact hole in the insulating layer (see above), is at least 20 nm, with additional lower limits such as at least 50 nm, 100 nm, or 200 nm. For example, the upper limit could be at most 5 µm, 4 µm, 3 µm, or 2 µm.
[0023] In one embodiment, the barrier layer includes at least one tungsten-based layer. The tungsten-based layer may consist of tungsten, i.e., a W layer, or include W, such as a TiW layer. In other words, the barrier layer may include at least one of W or TiW. For example, the barrier layer may include at least one W layer, such as bonded to a TiW layer on top of a W layer. As discussed above, the barrier layer may be a single layer or a stack of multiple (sub)layers. Alternatively, or in addition to the tungsten-based layer, it may include a titanium-based layer, such as a Ti and / or TiN layer, and / or a tantalum-based layer, such as a Ta and / or TaN layer. One or more titanium-based layers and / or one or more tantalum-based layers may, for example, be disposed beneath one or more tungsten-based layers. Typically, the barrier layer may include a nitrogen-based layer.
[0024] In one embodiment, the metallized upper layer is or includes a sputtered deposited layer, such as a sputtered Cu or sputtered AlCu layer. The sputtered deposited layer may, for example, have a thickness of at least 0.5 µm, 1 µm, or 1.5 µm. However, alternative materials, such as Ni or NiV layers, are generally conceivable. Providing the upper layer as a sputtered deposited layer may be advantageous, for example, for yield. Conversely, the aspect ratios discussed above can reduce or prevent the formation of voids or pinholes, for example, when the upper layer is sputtered. Reducing void formation based on morphology considerations can also lower the deposition temperature (which may be economically advantageous and / or reduce the risk of cross-reactions).
[0025] In one embodiment, the upper layer is or includes an aluminum layer or a copper layer. The aluminum layer may be composed of, for example, aluminum or a combination of aluminum and copper, such as an Al layer or an AlCu layer. The copper layer may include or be composed of copper, such as a copper layer. The upper layer may, for example, have a total thickness of at least 2 µm and / or at most 30 µm. The upper layer may be a single layer, such as a sputter-deposited copper layer. Alternatively, the upper layer may be a stack comprising multiple layers, such as a sputter-deposited seed layer and one or more bath-deposited layers on top. In other words, the metallized upper layer may include one or more plating layers. In the case of a stack, the aforementioned thickness range applies to the entire stack. For example, the thickness of the upper layer may be obtained vertically from the upper surface of the barrier layer to the uppermost surface of the metallization.
[0026] One or more additional layers may be disposed on the top layer. In other words, the top layer is not necessarily the outermost metallized layer. The additional layers (one or more) may include, for example, one of nickel, phosphorus, and palladium, such as a NiP layer and a Pd layer thereon. Optionally, a gold layer may be disposed on top.
[0027] In one embodiment, the insulating layer comprises a phosphosilicate glass (PSG) or borosilicate glass (BPSG) layer with a boron content of up to 2.9% (wt.%). Further upper limits may include, for example, up to 2.6%, and possible lower limits for the boron content may include, for example, at least 1%. Providing a PSG or BPSG layer can be advantageous, for example, for recirculation behavior, such as preventing rounding at the upper edge and reducing morphology.
[0028] Alternatively or additionally, the insulating layer may comprise a phosphosilicate glass (PSG) or borosilicate glass (BPSG) layer with a phosphorus content of up to 5%, with additional upper limits such as up to 4% or 3%. For example, a possible lower limit could be 1%. Again, this relates to mass percentages, i.e., wt.%.
[0029] In one embodiment, a method for manufacturing a semiconductor transistor device includes: i. An insulating layer is formed on the first side of the semiconductor body; ii. Etch contact holes that intersect with the insulating layer and have a width w; iii. Metallization is formed on the insulating layer.
[0030] Metallization includes a barrier layer, as discussed above, which can be a single barrier layer or a stack. The thickness of the barrier layer, t, is ≥ w / 2. Further embodiments and details are also described above.
[0031] In one embodiment, in step ii, the contact hole is anisotropically etched, for example, over the entire depth of the contact hole. In other words, only anisotropic etching is applied to the contact hole, which can, for example, allow for relatively steep sidewalls (reduced morphology, see above).
[0032] In one embodiment, after etching the contact hole and before forming the barrier layer, a transition metal layer is deposited into the contact hole and reacts to form a silicide within the contact hole. For example, during an annealing step, the transition metal may react with the substrate material (e.g., silicon) at the bottom of the contact hole to form a transition metal silicide there. However, it does not react with oxides, for example, so the transition metal remains on the insulating layer. Unreacted transition metal, i.e., the remaining transition metal, can subsequently be removed. The transition metal can be or includes transition metals such as Ni, NiAl, NiSi, TiAl, etc.
[0033] This self-aligned silicide also allows for contact formation on the relatively steep sides of the contact holes [see above]. In contrast, a stripping process where transition metal is deposited onto a photoresist to remove it from the insulating layer would require contact with the photoresist for chemical stripping, which is achieved by a certain amount of under-etching at the sidewalls of the contact holes. Attached Figure Description
[0034] The semiconductor transistor device and its manufacturing method will be explained in further detail below with the aid of exemplary embodiments. The various features may also be related in different combinations.
[0035] Figure 1a , Figure 1b A cross-sectional view of a semiconductor transistor device is shown; Figure 2 The illustration shows a detailed view of the contact holes in an insulating layer filled with a barrier layer; Figure 3 Another detailed view of the contact hole is shown; Figure 4a Figure 4b Schematic diagrams are shown to illustrate different morphologies; Figure 5 The flowchart summarizes some of the manufacturing steps. Detailed Implementation
[0036] Figure 1a A semiconductor transistor device 10 is shown in a vertical cross-section, wherein the cross-sectional plane is parallel to the vertical direction 100 and the transverse direction 101. The device 10 includes a plurality of device units 10.1, 10.2, wherein in... Figure 1b A portion of the first device unit 10.1 is shown in more detail below. The following description refers to... Figure 1a and Figure 1b Device units 10.1 and 10.2 are formed in semiconductor body 20, which in the example shown is a silicon carbide (SiC) semiconductor body 21.
[0037] An insulating layer 30 is disposed on a first side 20.1 of the semiconductor body 20, wherein a metallization 40 is formed on the insulating layer 30. The metallization 40 includes a barrier layer 41 and an upper layer 42, such as a copper layer 142. These layers, which may each comprise a stack of layers, are not shown to scale in this schematic diagram. The metallization 40 achieves electrical contact with the semiconductor body 20 in a contact hole 35 intersecting the insulating layer 30. In the longitudinal direction 102, i.e., perpendicular to the plane of the drawing, the contact hole has an elongated extension.
[0038] Device 10 is a vertical device, comprising a first load terminal 11 on a first side 20.1 of a semiconductor body 20 and a second load terminal 12 on a second side 20.2. In the example shown, the first load terminal 11 is a source region 13, and the second load terminal 12 is a drain region 14. Below the source region 13, a body region 15 is disposed, in which a channel region 15.1 is formed, see [reference needed]. Figure 1b .
[0039] A gate region 16 is disposed adjacent to channel region 15.1. In the example shown, it is laterally disposed adjacent to channel region 15.1 in gate trench 17. Gate region 16 includes gate electrode 16.1 and gate dielectric 16.2, with gate electrode 16.1 capacitively coupled to channel region 15.1 via gate dielectric 16.2. A diode region 18, having the same doping type as body region 15, is formed on the opposite sidewall of gate trench 17. Below body region 15 and diode region 18, a drift region 19, having the same doping type as drain region 14, is disposed. In the example shown, source region 13, drift region 19, and drain region 14 are n-type doped, while body region 15 and diode region 18 are p-type doped.
[0040] Figure 2 The contact hole 35 and the barrier layer 41 are shown in more detail. The contact hole 35 is defined by sidewalls 35.1 and 35.2 in the insulating layer 30 relative to the transverse direction 101. Referring to the width w of the contact hole 35, the thickness t of the barrier layer 41 is at least half the width, t ≥ w / 2. Providing this aspect ratio allows the contact hole 35 to be completely filled by the barrier layer 41, which reduces the morphology at the upper surface 41.1 of the barrier layer 41. Referring to the surface plane 130 fitted to the upper surface 30.1 of the insulating layer 30, the portion of the barrier layer 41 above the contact hole 35 has a thickness t, for example, tens or hundreds of nanometers. h In other words, the barrier layer 41 completely fills the contact hole 35 and also extends over it.
[0041] The barrier layer 41 may be or include a tungsten-based layer 141. The barrier layer 41 may be a stack of multiple layers 41a-41c, as schematically indicated in the example shown.
[0042] Figure 3 Another detailed view of the contact hole 35 in the insulating layer 30 is shown, where the barrier layer is not depicted. The cross-sectional plane is perpendicular to the sidewalls 35.1, 35.2 and parallel to the vertical direction 100. The sidewalls 35.1, 35.2 each form an angle δ with the vertical direction 100. The angle δ can be at most 10°, for example, approximately 5° in the example shown. As discussed and illustrated above, it can also be zero, such that the sidewalls 35.1, 35.2 are parallel to the vertical direction 100. In the case of inclined sidewalls 35.1, 35.2, the width w is obtained at half the height of the contact hole 35.
[0043] The insulating layer 30 may be or include a PSG or BPSG layer 31, for example, as the top layer in the case where the insulating layers are stacked. This can, for example, reduce the rounding at the upper edges of the sidewalls 35.1, 35.2. Figure 4a , Figure 4b The illustration shows a circle with a variable circle ( Figure 4a) and not having rounded ( Figure 4b A schematic comparison between the sidewalls 35.1 and 35.2 of the contact hole 35. Providing relatively steep sidewalls 35.1 and 35.2 above the entire height of the contact hole 35 can reduce the topography in subsequent layer stacks, such as in the barrier layer 41. This can reduce or prevent the formation of voids in the upper layer 42, such as at a potentially critical location above the center of the contact hole 35.
[0044] Figure 5 The flowchart summarizes some manufacturing steps. Manufacturing a semiconductor transistor device may include forming an insulating layer 80 on the semiconductor body. Before forming metallization 83 on the insulating layer, contact holes 81 may be etched. Optionally, silicide may be performed after the contact holes are etched 81, for example by depositing a transition metal layer 82.1 into the contact holes and onto the insulating layer, causing the transition metal to react 82.2 to form a transition metal silicide, and removing 82.3 any unreacted transition metal.
Claims
1. A semiconductor transistor device (10), comprising: Semiconductor body (20); An insulating layer (30) on the first side (20.1) of the semiconductor body (20); Metallization layer (40) on insulating layer (30); The metallization layer (40) includes a barrier layer (41) and an upper layer (42) disposed on the barrier layer (41). The contact hole (35) intersects with the insulating layer (30), and the contact hole (35) has a width w. The barrier layer (41) has a thickness t, which is at least half the width w of the contact hole, and t ≥ w / 2.
2. The semiconductor transistor device (10) according to claim 1, wherein, When viewed in a vertical section perpendicular to the sidewall (35.1) of the contact hole (35), the sidewall (35.1) of the contact hole (35) forms an angle δ of up to 10° with the vertical direction (100).
3. The semiconductor transistor device (10) according to claim 1 or 2, wherein, The width (10) of the contact hole is at least 0.1µm and / or at most 10µm.
4. The semiconductor transistor device (10) according to any one of the preceding claims, wherein, The upper surface (41.1) of the barrier layer (41) has a roughness of at least 10 nm.
5. The semiconductor transistor device (10) according to any one of the preceding claims, wherein, When viewed in a vertical section perpendicular to the sidewall (35.1) of the contact hole (35), the barrier layer (41) fills the contact hole (35) over its entire height.
6. The semiconductor transistor device (10) according to claim 5, wherein a portion of the barrier layer (41) above the contact hole (35) has a thickness t of at least 20 nm obtained from a surface plane (130) comprising the upper surface (30.1) of the insulating layer (30). h .
7. The semiconductor transistor device (10) according to any one of the preceding claims, wherein, The thickness t of the barrier layer (41) is at least 20 nm and / or at most 5 µm.
8. The semiconductor transistor device (10) according to any one of the preceding claims, wherein, The barrier layer (41) includes a tungsten-based layer or a titanium-based layer (141).
9. The semiconductor transistor device (10) according to any one of the preceding claims, wherein, The upper layer (42) includes a sputtered deposition layer.
10. The semiconductor transistor device (10) according to any one of the preceding claims, wherein, The upper layer (42) includes an aluminum or copper layer (142).
11. The semiconductor transistor device (10) according to any one of the preceding claims, wherein, The insulating layer (30) comprises a phosphosilicate (PSG) or borophosphosilicate (BPSG) layer with a boron content of up to 2.9%.
12. The semiconductor transistor device (10) according to any one of the preceding claims, wherein, The insulating layer (30) includes a phosphosilicate (PSG) or borophosphosilicate (BPSG) layer (31) with a phosphorus content of up to 5%.
13. A method for manufacturing a semiconductor transistor device (10), particularly the semiconductor transistor device (10) according to any one of the preceding claims, comprising the following steps: i. An insulating layer (30) (80) is formed on the first side (10.1) of the semiconductor body (10); ii. Etch (81) a contact hole (35) that intersects with the insulating layer (30) and has a width w; iii. Form (82) metallization (40) on the insulating layer (30); The metallization layer (40) includes a barrier layer (41). Furthermore, the barrier layer (41) has a thickness t, which is at least half the width w of the contact hole, t ≥ w / 2.
14. The method of claim 13, wherein the contact hole (35) is anisotropically etched over its entire depth.
15. The method according to claim 13 or 14, comprising the following steps after step ii and before step iii: - Deposit (82.1) a transition metal layer into the contact hole (35) and onto the insulating layer (30); - To react the transition metal (82.2) to form silicide in the contact hole (35); - Remove the remaining transition metal from (82.3).